WO2011011912A1

WO2011011912A1 - Phase change memory and manufacturing method thereof

Info

Publication number: WO2011011912A1
Application number: PCT/CN2009/072940
Authority: WO
Inventors: Jinshan Li
Original assignee: Beijing Huizhi Fountain Science Co., Ltd
Priority date: 2009-07-28
Filing date: 2009-07-28
Publication date: 2011-02-03

Abstract

A type of phase change memory (PCM) and the process to manufacture it are provided. Said phase change memory comprises a base with a conductive area formed on it, and a wall space (8A,8B,18A,18B), an exposed side wall area formed on the upper part of said wall space (8A,8B,18A,18B) to define the contact pad of the phase change memory, wherein part of the bottom of said wall space (8A,8B,18A,18B) covers the conductive area, and a upper electrode (16A,16B,20A,20B) is located on the contact pad, while said wall space (8A,8B,18A,18B) comprises the phase change material which is sensitive to temperature change. This type of phase change memory can efficiently reduce the area of the contact pad of the phase change memory, thus reduce the power consumption.

Description

PHASE CHANGE MEMORYAND MANUFACTURING

METHOD THEREOF

FIELD OF INVENTION

The invention is related to the semiconductor integrated circuit and the manufacturing method of it, especially to the method forming small contacting area in phase change memory (PCM).

BACKGROUND OF THE INVENTION

The phase of the PCM changes due to the electric current loaded to the PCM, the electric current can make the temperature of phase change material change, and the temperature of phase change material can be risen by imposing voltage. The states of the phase change material include crystalline and amorphous, the changes of phase change material include the part of the amorphous and part of the crystalline changing into each other. The phase change materials possess high resistance as amorphous, while the resistance thereof is low as crystalline, the memorized data is formed by the detected phase changing characterizations. The phase changing characterization includes the variation of resistance. The known phase change materials used in the PCM in the art include sulfur compound material, such as Ge-Sb-Te compound.

PCM takes advantage of dynamic random access memory or static random access memory, such as non-volatile, that is even the power is off the memorized data would be kept intact rather than lost. Beside, the writing rate of PCM is fast, which is shorter than 50ns, and the writing voltage of PCM is low, which is lower than 3 volt, while the writing rate of flash memory is lms and the writing voltage is 8 volt. The PCM obviously takes advantage. On the other hand, PCM is compatible with complementary metal oxide semiconductor (CMOS), and it also possesses the advantages of low power consumption and low cost. One of the aims to produce PCM is to reduce the power consumption by reducing the driven current which is required by phase changing. The driven current depends on the resistance of phase change material and the area of active region. While the values of the resistance and the area of active region depend on the contact pad of phase change material, which is used to transform phase change current. Generally, for a certain type of phase change material and a given driven current, the smaller the area of the contact pad is, the higher the resistance is, thus it may lead to higher resistance heating temperature. Therefore, the smaller the area of the contact pad of PCM is, the smaller the driven current is, and the less the power consumption of the PCM is.

Various ways to reduce the area of contact pad of the PCM have been developed. Generally, the contact pad of relatively small size is manufactured by lithography and etching in the art. Since the methods of lithography and etching are limited by the minimum feature size, the area of contact pad cannot be reduced effectively. The remaining methods also cannot reduce the area of contact pad effectively, due to the high cost and the complexity of use.

Thus, an effective method to reduce the area of contact pad of the PCM then to reduce the power consumption is expected.

SUMMARY OF THE INVENTION

The aims of this invention are to provide a type of PCM, which can reduce the area of contact pad of PCM, thus can reduce the power consumption of the PCM, and the process to manufacture it.

The invention provides a type of PCM, which comprising a base with a conductive region set on it, a wall space with part of side wall region exposed on its upper half, defining the contact pad of PCM, whereas the bottom half of the wall space covers the conductive region, and a upper pole locating on the contact pad. The wall space comprises the phase change material which is sensitive to temperature change. The invention provide the process to manufacture the PCM defined above, which include 3 steps: providing a base with a conductive region formed on it; forming a wall space, part of which cover the conductive region on the bottom; forming a spin coating on this wall space, removing part of the spin coating, thus exposing the upper half of the wall space, thus defining the contact pad of PCM; forming a pole on the contact pad; while the wall space comprise phase change material which is sensitive to temperature change.

To a better understanding of the characterizations, aims and the benefits of this invention, embodiments will be described incorporating the drawing description, to give a more detailed explanation to this invention.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. IA- IF illustrate the cutaway view of the embodiment of the process to manufacture the PCM according to this invention.

Fig.2A and F2B illustrate the cutaway view of the embodiment of the PCM according to this invention.

Fig.3 illustrates the flow chart of the process of manufacturing the PCM according to this invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Although a certain PCM is taken as an example to demonstrate the PCM according to the invention and the process of manufacturing it, the wall space pole and the memory elements which comprise said pole can be adapted on other memory element constructers, exposed side wall pole is defined on the upper half of the wall space as the contact pad of the PCM.

As Fig. 1 shows, the first internal dielectric layer is formed on a base by the way of PECVD, a conductive region, such as the plug 4A formed by the way of mosaic manufacture way, is formed on the first internal dielectric layer. The material of plug 4A as the conductive region can be, but not limited to W, TiN, TiW, TiAl or TiAlN. The material of first internal dielectric layer can be dielectric material, including, but not limited to Silica produced by PECVD, PETEOS, BPTEOS, BTEOS, PIEOS, TEOS, PEOX, suicide, fluoride glass (such as FSG), or other materials with low permittivity (K<2.9). Conductive plug 4A contacts with current drive circuit (not Shown), on which the current drive circuit can be CMOS element.

As Fig. IB shows, a material of dielectric layer 6(dielectric material with a flat top) is formed on the first internal dielectric layer 2 through precipitation, then form dielectric layer 6 by the way of erosion lithography or TiAlN engrave, for example, using PECVD to form silica as dielectric insulation material. Dielectric layer 6 and the dielectric insulation material can be the same with the material of first internal dielectric layer. Dielectric layer 6 can either be partially overlapped with plug 4A, or do not overlap with each other.

As Fig. 1C shows, firstly form a conductive layer on the surface by CVD and PVD method, which have been known by person in the art, then form the wall space 8A which is close to dielectric layer 6 by the ways of conventional dry etching or wet etching to implement etching-back, the wall space 8A partially overlaps the conductive plug 4A. In the preferred embodiment, wall space 8A is wet etched highly conductive material, such as one of W, TiN, TiW, TiAl or TiAlN. The maximum width of wall space 8A is variable, including modification of the wall space width that covers the plug 4A, and modification of the thickness of wall space 8A or the duration for etching-back, thus the resistance value of the wall space(such as contact electrode) can be adjusted.

As Fig. ID shows, a inorganic or organic spin-on-layer 20 is formed through precipitation process, the material of which can be spin-coating glass, spin-coating dielectric material, Benzocyclobutene, Polymids, and so on. Then wet etch it for a period of time to expose the top half of the wall space 8A, namely A region, therefore the exposed region would become electrode contact region(the contact pad of PCM), thus form the upper electrode. For example, since the wall space 8A has the exposed side wall electrode, the etch-back process can be implemented on spin-coating layer, in order to expose the chosen region on top half of the wall space, for example, region A, therefore the adjustable electrode contact pad is formed. Thus the adjustable contact pad of PCM is defined by the etch-back process according to this invention. Comparing to the conventional PCM, the area of the contact pad according to the invention is less than lOOOOnm , the preferred area is less than lOOOnm , the most preferred area is less than 1 OOnm .

As the Fig. IE shows, the phase change (change of structure) material layer which is readily to change according to temperature change is formed by known precipitation method. For example, the sulfur selenium tellurium glass, including Te and Sb. Then the phase change layer is lithographed, and dry etched and/or wet etched, to form phase change memory zone 12 A, and contact with the exposed top half(contact pad), such as the region A of wall space 8A of bottom electrode. The dimension of phase change part 12A is variable, it can equal to, larger or smaller than the width of bottom electrode (conductive plug 4A). In the preferred embodiment, the phase change part 12A can cover the exposed area of the bottom electrode, region A, the area of the exposed predetermined upper part of the wall space 8A is determined by controlling the time of etch-back.

As the Fig IF shows, second internal dielectric layer 14 A, which is made of the same material with the first internal dielectric layer, is formed by precipitation process, and the process for planarization is carried out, thus become insulated with phase change memory part 12A. The flat third internal dielectric layer is formed on the second internal dielectric layer 14 A. Then the conductive plug 16A is formed to form upper electrode, in which the manufacturing process and used material of the third internal dielectric layer 14B and conductive plug 16A are similar with that of first internal dielectric layer 2 and conductive plug 4A. As the Fig. 2A shows, the structure of the PCM according to the process mentioned above has been displayed. The structure mainly comprises the wall space (8A, 8B) of the bottom electrode, which is formed by the conductive plug (4A, 4B) of first internal dielectric layer 2, and the exposed bottom electrode aiming to contact the A region of the phase change element (12A, 12B), in which the contact area is determined mainly by etching the spin-coating layer 20. By using the dielectric layer 6 to partially cover the conductive plug (4A, 4B), a relatively thinner wall space (8A, 8B) is formed. And the phase change memory part is formed to cover the contact area of electrode, such as region A, to form a phase change memory contact area which covers the wall space (8A, 8B). Then the second and third internal dielectric layer (14A, 14B) of the upper electrode (16A, 16B) is formed as mentioned above.

As the Fig. 2B shows, the PCM which is manufactured by the process similar to the process demonstrated in Fig IA- IF, the differences lies in the wall space (18A, 18B) of the PCM. The etch-back is carried out only on spin-coating layer 20 to expose the top half of the wall space, which is displayed as region B, to form a memory element electrode contact area with flat top electrode contact. In this embodiment, dielectric layer 6 does not cover the conductive plug (4A, 4B) which forms the bottom electrode. And the area of the bottom electrode contact area is adjusted by the width (Wl) that the wall space (18A, 18B) covers the conductive plug (4A, 4B).

As the Fig. 2B shows, the material of upper electrode (2OA, 20B) and conductive plug (4A, 4B) can either be the same or not. The precipitation, lithography and dry/wet etch can be applied to form the upper electrode. In this embodiment, the second internal dielectric layer 14A is used to separate the upper electrode and bottom electrode (2OA, 20B). Similar to the first embodiment, the contact area of memory electrode (active area) is less than 10000 nm , preferred is less than 1000 nm , more preferred is less than 100 nm . Therefore, the structure of the phase change memory and the process to manufacture it form the active region whose area is adjustable, thus the drive current needed is reduced. In this invention, the contact area of the memory element electrode (active region) is formed in the chosen region of the upper wall space. In one embodiment, wall space (18A, 18B) is phase material covering the bottom electrode (4A, 4B). In another embodiment, the upper electrode contact area is formed on the exposed upper part of the phase change material wall space. The process of manufacturing according to the invention is easily to implement, low cost and compatible to the method of manufacturing the CMOS element. The inventors reduce the drive current by adjusting the area of the contact region of the memory element electrode, thus reduce the power consumption. The contact region of the memory element electrode can be used to plan the capacity of phase change memory.

The Fig. 3 shows the flow chart of the process of manufacturing these embodiments according to this invention. In the step 301, internal dielectric layer with conductive plug set in it is formed. In the step 302, a flat top dielectric layer is formed on the internal dielectric layer. Then in the step 303, memory element is formed at the position which is close to the flat top dielectric layer, and the wall space of the memory electrode is formed to partially cover the conductive plug. Then in step 304, the upper part of the wall space is covered by SOG layer to form the contact area of the phase change element. Finally, in step 305, dielectric layer and upper electrode is formed as a memory unit, which includes the formation of memory element on the bottom of the wall space electrode or the formation of upper electrode on single wall space.

Although the preferred embodiment has been disclosed here, the aim of which is not to limit this invention, various changes and modifications can be made to the invention as long as it falls into the scope and the spirit of the invention, the scope that is to be protected is defined in the claims.

Claims

1. A process of manufacturing the phase change memory, which comprises following steps:

providing a base on which a conductive area is formed;

forming a wall space, the bottom part of which covers said conductive area;

forming a spin-coating layer on said wall space, remove part of said spin-coating layer, thus the upper part of the said wall space is exposed to define the contact pad of phase change memory;

forming a upper electrode on said contact pad; and

said wall space comprise the phase change material which is sensitive to temperature change.

2. The process of manufacturing the phase change memory according to claim 1, wherein said phase change materials comprise sulfuric compounds.

3. The process of manufacturing the phase change memory according to claim 1 , wherein the material of the upper electrode can be chosen from the group consisting of Tungsten, Titanium nitride, Titanium Tungsten, Titanium aluminum, Titanium aluminum nitride.

4. The process of manufacturing the phase change memory according to claim 1 , wherein the material of said spin-coating layer is chosen from the group consisting of spin-coating glass, Phencynonate butane, poly-acid imide.

5. The process of manufacturing the phase change memory according to claim 1 , wherein said wall space formed is close to the side wall of a dielectric layer, said dielectric layer covers part of the conductive region, and said dielectric layer is separate with the conductive area.

6. A type of phase change memory, which comprise:

a base with a conductive area formed on it, and

a wall space, a exposed side wall area is formed on the upper part of said wall space to define the contact pad of the phase change memory, wherein part of the bottom of said wall space covers the conductive area; a upper electrode located on the contact pad; and

said wall space comprises the phase change material which is sensitive to temperature change.

7. The phase change memory according to claim 6, wherein said phase change materials comprise sulfuric compounds.

8. The phase change memory according to claim 6, wherein the material of the upper electrode can be chosen from the group consisting of Tungsten, Titanium nitride, Titanium Tungsten, Titanium aluminum, Titanium aluminum nitride.

9. The phase change memory according to claim 6, wherein the material of said spin-coating layer is chosen from the group consisting of spin-coating glass, Phencynonate butane, poly-acid imide.

10. The phase change memory according to claim 6, wherein said wall space formed is close to the side wall of a dielectric layer, said dielectric layer covers part of the conductive region, and said dielectric layer is separate with the conductive area.