KR100795908B1 - Semiconductor device having heating structure and methods of forming the same - Google Patents

Abstract

A semiconductor device having a heating structure and a method for forming the same are provided to minimize a contact area by connecting a phase change pattern through a contact window to a sidewall part of an exposed lower electrode. A plurality of lower electrodes(145) include bottom parts and sidewall parts extended from edges of the bottom parts. A heating target pattern(170) is disposed on an upper part of each lower electrode. An insulating layer(160) includes a contact window for exposing partially an upper surface of the sidewall part of the lower electrode and is inserted between the heating target pattern and the lower electrode. The heating target pattern is connected through the contact window to the upper surface of the sidewall part of the lower electrode. The contact window has a width narrower than that of the heating target pattern. A contact area between the heating target pattern and the lower electrode corresponds to a product of the thickness of the sidewall part and the width of the contact window.

Description

Semiconductor device having a heating structure and a method of forming the same {Semiconductor Device Having Heating Structure And Methods Of Forming The Same}

1A is a plan view illustrating a memory cell of a PRAM according to the prior art.

1B is a cross-sectional view illustrating a heat generation structure of a PRAM according to the prior art.

1C is a circuit diagram illustrating a technical problem of a PRAM according to the prior art.

2A through 2C are plan views illustrating a semiconductor device having a heat generating structure according to example embodiments.

3A to 3G are perspective views illustrating a method of manufacturing a semiconductor device having a heat generating structure according to an embodiment of the present invention.

4 is a cross-sectional view illustrating a method of manufacturing a semiconductor device having a heat generating structure according to another embodiment of the present invention.

5A and 5B are perspective views illustrating a method of manufacturing a semiconductor device having a heat generating structure according to another embodiment of the present invention.

6A and 6B are plan views illustrating a semiconductor device including a heat generating structure according to still other embodiments of the inventive concept.

7A to 7D are perspective views illustrating a method of manufacturing a semiconductor device in accordance with still another embodiment of the present invention.

8 is a perspective view illustrating a semiconductor device having a heat generating structure according to still another embodiment of the present invention.

9 is a perspective view illustrating a method of manufacturing a semiconductor device in accordance with still another embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for forming the same, and more particularly to a semiconductor device having a heat generating structure and a method for forming the same.

BACKGROUND With the development of the electronics industry such as mobile communication and computers, semiconductor devices having characteristics such as high read / write operation speed, nonvolatile and low operating voltage are required. However, currently used memory devices such as static random access memory (SRAM), dynamic random access memory (DRAM), and flash memory do not meet all of these characteristics.

For example, since the unit cell of the DRAM includes one capacitor and one transistor for controlling the DRAM, the unit cell has a relatively large unit cell area compared to the NAND flash memory. Also, since DRAM stores information in a capacitor, as is known, it is a volatile memory device that requires a refresh operation. The SRAM has a high operating speed, but is similarly one of volatile memory devices, and since the unit cell is composed of six transistors, the unit cell area is very large. The flash memory is a nonvolatile memory device and provides the highest degree of integration among existing memory devices (particularly in the case of NAND flash memory devices), but has the disadvantage of slow operation speed as is known.

Accordingly, in recent years, research has been conducted on memory devices capable of fast read / write operations, nonvolatile, refresh operations, and low operating voltages, and include phase random access memory; PRAM) is one of the next generation memory devices that are expected to meet these technical requirements. For example, a PRAM can change information more than 10 to ¹³ times, so it has a long product life and has a high speed of about 30 ns.

Information stored in a memory cell of the PRAM can be read by sensing a change in electrical resistance according to a change in a crystal state of a phase change film, and the crystal state of the phase change film is dependent on a heating temperature and a heating time of the phase change film. Accordingly, the PRAM adopts a method of adjusting the current flowing through the phase change film and Joule's heat generated by the current as a method for bringing the phase change film into a desired crystal state. The row-column Q can be represented by the following row law, as is well known.

Q = I ² Rt

In this case, the resistance (R) is a fixed parameter depending on the type of material or the manufacturing process, whereas the time (t) and the current (I) are externally controllable for the operation of the manufactured product. Externally controllable parameters. As a result, in order to heat the phase change film to the required temperature while minimizing the power consumption, it is necessary to increase the resistance of the portion heating the phase change film.

1A is a plan view illustrating a memory cell of a PRAM according to the prior art, and FIG. 1B is a cross-sectional view illustrating a heat generating structure of the PRAM according to the prior art. More specifically, FIG. 1B shows a cross section taken along the dotted line II ′ of FIG. 1A. 1C is a circuit diagram illustrating a technical problem of a PRAM according to the prior art.

1A and 1B, an active region ACT is disposed in a predetermined region of the semiconductor substrate 10, word lines WL are disposed above the active region ACT, and the word lines The source region 12S and the drain region 12D are disposed in the active region ACT at both sides of the WL. A plug 16 and a pad 18 are stacked on the drain region 12D, and an interlayer insulating film having an opening 20 exposing the top surface of the pad 18 on the resultant product on which the pad 18 is formed. 14 is disposed. A lower electrode 24 used as a heating device is disposed in the opening 20, and a phase change pattern GST and an upper electrode contacting the lower electrode 24 are disposed on the interlayer insulating layer 14. 28) are stacked.

On the other hand, as is known, the electrical resistance of a conductive line is proportional to its resistivity and the length of the conductor and inversely proportional to its cross sectional area. Based on this fact, in the prior art, efforts have been made to reduce the cross-sectional area in order to increase the resistance of the lower electrode 24. (For example, the spacer 22 formed on the inner wall of the opening 20, as shown in Fig. 1A.)

However, the method of reducing the cross-sectional area of the lower electrode 24 using the spacer 22 is not only the cross-sectional area of the upper region of the lower electrode 24 (in contact with the phase change pattern GST), but also the The cross-sectional area of the lower region of the lower electrode 24, which does not contribute to the heating of the change pattern GST, is reduced. As a result, as shown in FIG. 1C, the method of reducing the cross-sectional area of the lower electrode 24 by using the spacer 22 may be achieved at the intended position of the resistance (ie, the phase change pattern and the lower electrode interface resistance R4). In addition, it also increases the resistance of the unintentional position (i.e., lower electrode resistance R5 and interface resistance R6 of the lower electrode and the diode). As such, an increase in resistance in a region that does not contribute to heating of the phase change pattern GST causes an increase in power consumption and a decrease in reliability. To overcome this problem, there is a need for a technique capable of selectively increasing only the interface resistance R4 between the phase change pattern GST and the lower electrode 24 while minimizing an increase in other unintended resistances. .

On the other hand, since the opening 20 is formed through a patterning process including a photolithography step, the cross-sectional area of the opening 20 has a process variation associated with the patterning process. In this case, since the cross-sectional area of the opening 20 substantially determines the cross-sectional area of the lower electrode 24, the area spread generated in the opening 20 forming process leads to the area spread of the lower electrode 24. .

More specifically, as described above, although the cross sectional area of the lower electrode 24 may be reduced by the spacer 22, the cross sectional area distribution of the lower electrode 24 is essentially an area spread of the opening 20. Determined by In other words, if the reduction in the cross-sectional area of the lower electrode 24 does not involve a decrease in its cross-sectional area distribution, which is at least in the same proportion, the reduction in the cross-sectional area of the lower electrode 24 rather reduces the uniformity of the memory cells. Let's do it. This uniformity problem is a technical issue that has an important effect on the yield of the PRAM in that it is intensified as the degree of integration of the semiconductor device increases. In conclusion, a technique for reducing not only the cross-sectional area of the lower electrode 24 but also its spread is required.

In addition, according to the prior art, as shown in FIG. 1A, the memory cells of the PRAM have island-shaped phase change patterns GST (not connected to each other). However, the anisotropic etching step for forming the phase change patterns GST involves etching damage that affects the physical properties of the phase change pattern GST. In particular, as shown in FIG. 1A, the island-shaped phase change pattern GST is more vulnerable to such etching damage. In addition, since the island-shaped phase change pattern GST does not have a large contact area with the underlying films (for example, the lower electrode 24 and the interlayer insulating film 14), as the degree of integration of the PRAM increases, It is vulnerable to the problem of lifting which leads to failure. In particular, the phase change pattern (GST) is heated to a high temperature, the problem of lifting due to thermal expansion is a technical problem to be overcome for the commercialization of the PRAM.

An object of the present invention is to provide a semiconductor device capable of selectively increasing only the interface resistance between the phase change film and the lower electrode.

An object of the present invention is to provide a method for manufacturing a semiconductor device that can selectively increase only the interface resistance between the phase change film and the lower electrode.

An object of the present invention is to provide a semiconductor device capable of reducing the contact area and the contact area distribution between the lower electrode and the phase change film.

An object of the present invention is to provide a method of manufacturing a semiconductor device that can reduce the contact area and the contact area distribution between the lower electrode and the phase change film together.

An object of the present invention is to provide a semiconductor device that can minimize the lifting problem of the phase change film.

An object of the present invention is to provide a method of manufacturing a semiconductor device that can minimize the lifting problem of the phase change film.

In order to achieve the above technical problem, the present invention provides a semiconductor device having a heating pattern to contact a portion of the side wall portion of the lower electrode. The apparatus includes a plurality of bottom electrodes having a bottom portion and a side wall portion extending upwardly from an edge of the bottom portion; A heated pattern disposed on the lower electrodes; And an insulating layer interposed between the heating pattern and the lower electrodes while having a contact window exposing a portion of the upper surface of the side wall of the lower electrode. In this case, the heated pattern is connected to a portion of an upper surface of the sidewall portion of the lower electrode through the contact window.

According to an embodiment of the present invention, the contact window has a narrower width than the heating pattern, and the contact area between the heating pattern and the lower electrode is equal to the product of the thickness of the sidewall portion and the width of the contact window. .

According to another embodiment of the present invention, the contact window is formed to expose the upper surface of the side wall portion of the lower electrodes in the direction crossing the heating pattern, the contact area between the heating pattern and the lower electrode is It is equal to the product of the thickness of the side wall portion and the width of the heated pattern.

According to the present invention, the heated pattern is formed to connect the plurality of lower electrodes, and the sidewall portion of the lower electrode may be a closed line having a thickness of 1 to 20 nm. An upper electrode may be further disposed on the heated pattern. In this case, the upper electrode is self-aligned to the heating pattern, thereby electrically connecting the lower electrodes connected to the heating pattern.

According to one embodiment of the present invention, a lower conductive pattern crossing the heated pattern is further disposed below the lower electrodes, and semiconductor patterns constituting a diode are further disposed between the lower conductive pattern and the lower electrodes. Can be. In this case, the lower electrode and the semiconductor pattern are self-aligned to have substantially the same occupied area.

According to the present invention, an inner insulating pattern is further disposed between the bottom portion of the lower electrode and the insulating layer, and an outer insulating pattern is further disposed around the sidewall portion of the lower electrode to electrically separate the lower electrodes. The upper surface of the sidewall portion of the lower electrode may be lower than the upper surfaces of the inner insulation pattern and the outer insulation pattern at least in the contact window.

According to another embodiment of the present invention, a memory transistor may be further disposed under the lower electrode. In this case, the memory transistor includes a gate electrode crossing the heated pattern and source / drain regions formed on both sides of the gate electrode. According to the present invention, the contact window has a depth of 5 kPa to 1000 kPa, and an aspect ratio thereof may be 0.0001 to 2.

In order to achieve the above another technical problem, the present invention comprises the steps of forming an outer insulating pattern having gap regions on a semiconductor substrate; Forming a bottom electrode in the gap region, the bottom electrode having a bottom portion and a sidewall portion extending upwardly from an edge of the bottom portion; Forming an insulating layer on the outer insulating pattern, the insulating layer having a contact window exposing a portion of an upper surface of the sidewall of the lower electrode; And forming a heated pattern on the insulating layer to be connected to an upper surface of the sidewall of the lower electrode exposed through the contact window.

According to an embodiment of the present invention, before forming the lower electrode, the semiconductor patterns constituting the diode may be further formed on the lower regions of the gap regions. In this case, before forming the external insulating pattern, a lower conductive pattern may be further formed below the semiconductor patterns. The lower conductive pattern connects the semiconductor patterns in a direction crossing the heated pattern.

In the forming of the semiconductor pattern, an epitaxial process using the lower conductive pattern as a seed layer is performed to form a semiconductor film filling the gap regions, and the upper sidewall of the gap region is formed by etching the entire surface of the semiconductor layer. After forming the semiconductor pattern to expose, it may include the step of injecting impurities of different conductivity type to the semiconductor substrate.

According to another embodiment of the present invention, before forming the external insulating pattern, a transistor may be further formed. In this case, the transistor includes a gate electrode crossing the heated pattern and source / drain regions formed on both sides of the gate electrode. Subsequently, the method may further include forming a drain plug electrically connecting the drain region of the transistor and the lower electrode.

According to an embodiment of the present invention, the forming of the insulating film having the contact windows may include forming the insulating film on a resultant product on which the lower electrode is formed, and then forming the insulating film so that one contact window exposes one lower electrode. Patterning the;

According to another embodiment of the present invention, the step of forming the insulating film having the contact window is formed after the insulating film formed on the lower electrode formed, the insulating film so that one contact window exposes a plurality of lower electrodes Patterning the; In this case, the contact window is formed to have a long axis in a direction crossing the heated pattern or a long axis parallel to the heated pattern.

The contact window is formed to have a depth of 5 μs to 1000 μs and an aspect ratio of 0.0001 to 2.

The forming of the pattern to be heated may include forming a phase change layer on the insulating layer to contact an upper surface of the sidewall of the lower electrode through the contact window, and then patterning the phase change layer to form the pattern to be heated. It may include. In this case, the heated pattern is formed to connect the plurality of lower electrodes.

Objects, other objects, features and advantages of the present invention will be readily understood through the following preferred embodiments associated with the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the invention to those skilled in the art.

In the present specification, when it is mentioned that a film is on another film or substrate, it means that it may be formed directly on another film or substrate or a third film may be interposed therebetween. In addition, in the drawings, the thicknesses of films and regions are exaggerated for effective explanation of technical contents. In addition, in various embodiments of the present specification, terms such as first, second, and third are used to describe various regions, films, and the like, but these regions and films should not be limited by these terms. . These terms are only used to distinguish any given region or film from other regions or films. Thus, the film quality referred to as the first film quality in one embodiment may be referred to as the second film quality in other embodiments. Each embodiment described and illustrated herein also includes its complementary embodiment.

2A is a plan view illustrating a semiconductor device having a heat generating structure according to an exemplary embodiment of the present invention. 3A to 3G are perspective views illustrating a method of manufacturing a semiconductor device having a heat generating structure according to an embodiment of the present invention.

2A and 3A, lower conductive patterns 110 are formed on the semiconductor substrate 100. The lower conductive pattern 110 may be used as a wire (more specifically, a word line) connecting memory cells of the PRAM in a predetermined direction.

According to an embodiment of the present invention, active regions formed using well-known shallow trench isolation (STI) techniques may be used as the lower conductive patterns 110. More specifically, the forming of the lower conductive pattern 110 may include forming isolation trenches defining active regions in the semiconductor substrate 100, and forming a device isolation layer pattern (not shown) filling the isolation trenches. And forming impurity regions to be used as the lower conductive pattern 110 by implanting impurities in the active regions at a high concentration. In this case, the conductivity type of the impurity is different from that of the semiconductor substrate 100. For example, when the conductivity type of the semiconductor substrate 100 is p-type, the conductivity type of the lower conductive pattern 110 may be n +.

According to another embodiment of the present invention, the lower conductive pattern 110 may include a metallic material (eg, metal silicides and metals). Such an embodiment is disclosed in detail in Korean Application No. 2005-110004, and a description thereof will be omitted.

2A and 3B, a first insulating layer 120 covering the lower conductive patterns 110 is formed on the semiconductor substrate 100. The first insulating layer 120 may be formed of at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a low dielectric film, and may be used as an external insulating pattern surrounding the lower electrode in a subsequent process.

The first insulating layer 120 is patterned to form gap regions 125 exposing upper surfaces of the lower conductive patterns 110. The forming of the gap regions 125 may include forming a first mask pattern (not shown) on the first insulating layer 120 and using the first mask pattern as an etching mask. Anisotropically etching 120. In this case, the etching of the first insulating layer 120 may be performed using an etching recipe having an etching selectivity with respect to the lower conductive pattern 110.

The first mask pattern may be a photoresist pattern formed through a photolithography process. In this case, corners of the gap regions 125 may be rounded. For example, the gap region 125 may be elliptical having a long axis and a short axis. According to an embodiment of the present invention, the long axis of the gap region 125 may reduce the sidewall curvature of the gap region 120 measured in the direction crossing the lower conductive patterns 110. It is preferable to be parallel to the longitudinal direction of the lower conductive pattern 110. According to the present invention, the long axis length or short axis length of the gap region 125 may be 1 to 250 nm.

Also, as shown in FIGS. 2A and 3B, the gap regions 125 are two-dimensionally arranged. That is, a plurality of gap regions 125 are formed on one lower conductive pattern 110.

2A and 3C, the semiconductor pattern 130 is formed in the lower region of the gap region 125. The semiconductor pattern 130 may include an upper impurity region 131 and a lower impurity region 132 that are sequentially stacked to form a diode. The lower impurity region 132 is formed to contact the upper surface of the lower conductive pattern 110. When the lower conductive pattern 110 is formed of polycrystalline silicon containing impurities, the lower impurity region 132 has the same conductivity type as the lower conductive pattern 110, and the upper impurity region 131 may be The lower conductive pattern 110 may have a different conductivity type.

According to the present invention, the forming of the semiconductor pattern 130 may include forming a semiconductor layer filling the gap region 125 and the semiconductor layer until the sidewalls of the upper region of the gap region 125 are exposed. Etching the surface; Since the height of the sidewalls of the gap region 125 exposed by the front side etching determines the height of the lower electrode (to be formed in a subsequent process), the front side etching process is performed in consideration of this.

The semiconductor layer may be formed through an epitaxial process using the lower conductive pattern 110 exposed through the gap region 125 as a seed layer, and among the Group 4 elements and the Group 3-5 elements. It can be one. For example, the semiconductor layer may be an epitaxial germanium-silicon layer or an epitaxial Si layer. The semiconductor layer may be an amorphous Si layer formed using chemical vapor deposition.

The forming of the upper and lower impurity regions 131 and 132 may include implanting impurities having different conductivity types into the semiconductor layer using an ion implantation process. According to another embodiment of the present invention, during the epitaxial process using an in-situ doping technique, impurities of the first conductivity type are implanted into the semiconductor layer, and then the first conductivity is used using an ion implantation technique. Impurities of the second conductivity type may be implanted into the semiconductor layer including impurities of the type.

2A and 3D, a bottom electrode layer 140 is formed on a resultant product on which the semiconductor pattern 130 is formed. That is, the lower electrode layer 140 is formed on the upper surface of the first insulating layer 120 and the inner wall of the gap region 125 (more specifically, the lower electrode layer 140 is formed on the gap region 125). An exposed sidewall of the upper region and an upper surface of the semiconductor pattern 130).

According to the present invention, since the thickness of the lower electrode film 140 determines the contact area between the lower electrode and the heated pattern, which is one of the technical features of the present invention, as described below, precise control of the thickness is possible. It is formed through the methods. For example, the lower electrode layer 140 may be formed using one of atomic layer deposition (ALD), metal organic chemical vapor deposition (MO-CVD), thermal CVD, biased CVD, plasma CVD, and ECR CVD. have. According to this embodiment, the thickness of the lower electrode layer 140 may be approximately 1 nm to 30 nm.

In addition, the lower electrode layer 140 may include nitrides including metal elements, oxynitrides including metal elements, carbon (carbon, C), titanium (Ti), tantalum (Ta), aluminum titanium (TiAl), Zirconium (Zr), hafnium (Hf), molybdenum (Mo), aluminum (Al), aluminum-copper (Al-Cu), aluminum-copper-silicon (Al-Cu-Si), copper (Cu), tungsten (W ), Tungsten titanium (TiW) and tungsten silicide (WSix). In this case, nitrides including the metal element include TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN and TaAlN, and include the metal element. Oxidizing nitrides include TiON, TiAlON, WON, TaON. According to this embodiment, the lower electrode film 140 is formed of a titanium nitride film.

Referring to FIGS. 2A and 3E, after forming a second insulating film filling the upper region of the gap region 125 on the resultant product on which the lower electrode film 140 is formed, the second insulating film and the lower electrode film ( The planarization etch 140 may expose the top surface of the first insulating layer 120. As a result, as shown in FIG. 3E, in the upper region of the gap region 125, a lower electrode 145 having a bottom portion and a sidewall portion and an internal insulation pattern 150 disposed on the bottom portion are formed. .

The second insulating film may be one of a silicon oxide film and a silicon nitride film, and may be formed using a chemical vapor deposition technique. In addition, the planarization etching may be performed using a chemical-mechanical polishing technique.

The bottom portion is formed to be in contact with the top surface of the semiconductor pattern 130, and has the same area as the gap region 125. The side wall portion extends from the bottom portion to the inlet of the gap region 125. The lower electrode 145 forms a closed curve in that the lower electrode 145 is a result of the planarization etching of the lower electrode layer 140 conformally covering the gap region. More specifically, the side wall portion may be formed to have a ring-shaped cross section. An upper surface of the sidewall portion of the lower electrode 145 is exposed at the inlet of the gap region 125.

Meanwhile, according to an embodiment of the present invention, as shown in FIG. 4, the lower electrode 145 is disposed such that an upper surface of the sidewall portion of the lower electrode 145 is lower than an upper surface of the first insulating layer 120. The method may further include etching. In this case, since the sidewalls of the sidewalls of the lower electrode 145 are not exposed, the contact area and the distribution of the contact area between the lower electrode 145 and the phase change film (to be formed thereon) can be minimized. . That is, since only the upper surface of the side wall portion of the lower electrode 145 is exposed, stable management of the contact area is possible.

2A and 3F, a contact window for forming an insulating layer 160 on a resultant product on which the lower electrode 145 is formed, and then patterning the same to expose a portion of the upper surface of the sidewall portion of the lower electrode 145. Form field 165.

The insulating layer 160 may be formed of one of materials having a specific resistance of at least 10 × 10 ⁻³ Ωcm, low thermal conductivity, and good adhesion characteristics with the heated pattern 170 to be formed in a subsequent process. Do. For example, the insulating layer 160 may be formed of an aluminum nitride film (AlN), a silicon nitride film (SiN), a silicon oxynitride film (SiON), a silicon oxide film (SiO ₂ ), amorphous carbon (amorphous carbon) having a thickness of 5 to 1000 kW. ), Titanium oxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), aluminum oxide (AlO _X ), hafnium oxide (HfO _X ), lanthanum oxide (LaO _X ), and yttrium oxide (Y2O _X ). .

The contact window 165 is formed to expose a portion of the sidewall portion of the lower electrode 145. More specifically, the contact window 165 is formed to have a narrower width W ₁ than the bottom of the lower electrode 145, and the center point of the contact window 165 is the center of the gap region 125. It is formed on the edge of the gap region rather than on the axis. According to one embodiment of the present invention, the contact windows 165 may be formed one each on top of the lower electrodes (125). According to the present invention, the contact window 165 is preferably formed to have a depth of 5 kHz to 1000 kHz and an aspect ratio of 0.0001 to 2.

The contact windows 165 may be formed using a photolithography process. In this case, corners of the contact windows 165 may be rounded. For example, the contact window 165 may be elliptical having a long axis and a short axis. According to an embodiment of the present invention, the long axis of the contact window 165 may be reduced so that the sidewall curvature of the contact window 165 measured in a direction parallel to the lower conductive patterns 110 may be reduced. It is preferable to be perpendicular to the longitudinal direction of the conductive pattern 110. The long axis length or short axis length of the contact window 165 may be 1 to 100 nm.

Referring to FIGS. 2A and 3G, the heated pattern 170 and the upper electrode 180 are sequentially stacked on a resultant product in which the contact windows 165 are formed to cross the lower conductive patterns 110. Form. The heated pattern 170 and the upper electrode 180 directly contact the lower electrodes 145 through the contact windows 165.

In the case of PRAM, the heated pattern 170 may be formed of one of chalcogenide compounds including at least one of antimony (Sb), tellurium (Te), and selenium (Se). . For example, the heated pattern 170 may be Ge ₂₂ Sb ₂₂ Te _{56 including} three elements of tellurium (Te), antimony (Sb), and germanium (Ge). In one composition that provides improved electrical switching properties, tellurium (Te) has a concentration of about 80 atomic percent or less, at least about 20 atomic percent, and antimony (Sb) to about 5 atomic percent It has a concentration of 50 atomic percent and the remainder is germanium (Ge). In addition, the heated pattern 170 may be formed of a GeSbTe film including at least one of N, O, C, Bi, In, B, Sn, Si, Ti, Al, Ni, Fe, Dy, and La as impurities. Or GeBiTe, InSb, GeSb, or GaSb.

The upper electrode 180 includes nitrides including metal elements, oxynitrides including metal elements, carbon, titanium (Ti), tantalum (Ta), aluminum titanium (TiAl), zirconium (Zr), and hafnium (Hf). ), Molybdenum (Mo), aluminum (Al), aluminum-copper (Al-Cu), aluminum-copper-silicon (Al-Cu-Si), copper (Cu), tungsten (W), tungsten titanium (TiW) and It may be formed of at least one material selected from tungsten silicide (WSix). In this case, nitrides including the metal element include TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN and TaAlN, and include the metal element. Oxidizing nitrides include TiON, TiAlON, WON, TaON. According to this embodiment, the upper electrode 180 is formed of a titanium nitride film. Bit lines (not shown) that cross the lower conductive patterns 110 (used as word lines) may be disposed on the upper electrode 180.

According to this embodiment, as shown in FIG. 2C, the heated pattern 170 completely covers the contact window 165, so that the width W ₂ of the heated pattern 170 is the contact window ( It is formed wider than the width W ₁ of 165. In this case, the area where the lower electrode 145 contacts the heated pattern 170 is a product of the thickness T of the sidewall of the lower electrode 145 and the width W ₁ of the contact window 165. Same as As described above, when the contact window 165 and the gap region 125 are rounded as a result of the photolithography process, the contact area may vary from T × W because of their sidewall curvature.

Meanwhile, the thickness T of the sidewall portion is determined by the deposition thickness of the lower electrode layer 140, and as described above, the lower electrode layer 140 accurately measures the thickness by an order of angstrom. It is formed through deposition methods that can be controlled. Thus, the thickness and thickness distribution of the sidewall portions are much smaller than the width and width distribution of the pluggable lower electrode, which is formed by a conventional photolithography process. As a result, the contact area between the lower electrode 145 and the heated pattern 170 is smaller than that of the conventional plug type lower electrode. In addition, since the contact area spread between the lower electrode 145 and the heated pattern 170 is mainly determined in one dimension by the spread of the width W ₁ of the contact window 165, the plug Is much smaller than the prior art contact area distribution, such as the two-dimensional cross-sectional area distribution of. That is, according to the present invention, it is possible to simultaneously reduce the contact area and the contact area distribution between the lower electrode 145 and the heated pattern 170.

According to the present invention, the contact area between the lower electrode 145 and the heated pattern 170 is reduced, but between the lower electrode 145 and the lower layer (eg, the semiconductor pattern 130). The contact area of is equal to the cross-sectional area of the gap region 125. In addition, even though only a portion of the sidewall portion of the lower electrode 145 is used for contact with the heated pattern 170, the sidewall portion of the lower electrode 145 is formed of the semiconductor pattern 130 and the heated pattern ( 170 is used as a wiring to connect. As a result, the interface resistance between the lower electrode 145 and the heated pattern 170 increases rapidly, but the bulk resistance of the lower electrode 145 or between the lower electrode 145 and the semiconductor pattern 130 is increased. Its interface resistance does not increase drastically. As described above, the request of selectively increasing only the interface resistance between the phase change film and the lower electrode can be achieved from this fact of the present invention.

In addition, according to the present invention, the pattern to be heated 170 is patterned together with the upper electrode 180 to be self-aligned to the upper electrode 180. Accordingly, the heated pattern 170 is formed to cross a plurality of memory cells (ie, the lower electrodes 145). As a result, problems such as deterioration of product characteristics due to etching damage or lifting of phase change patterns accompanying the conventional island-like phase change patterns can be minimized.

2B is a plan view illustrating a semiconductor device having a heat generating structure according to another exemplary embodiment of the present invention. 5A to 5B are perspective views illustrating a method of manufacturing a semiconductor device having a heat generating structure according to this embodiment. This embodiment is similar to the embodiment described with reference to FIG. 2A, except for the technical differences associated with contact window 165. Therefore, for the sake of brevity of discussion, redundant descriptions are omitted below.

2B and 5A, after forming the insulating layer 160, the insulating layer 160 is patterned to form a contact window 165 exposing a portion of the upper surface of the sidewall of the lower electrode 145. According to this embodiment, the contact window 165 is formed in a direction parallel to the lower conductive pattern 145, and one contact window 165 exposes the plurality of lower electrodes 145. The contact window 165 is formed in a line shape, unlike the embodiment described with reference to FIG. 2A.

Referring to FIGS. 2B and 5B, the contact patterns 165 are sequentially stacked on the resultant product to form the heated pattern 170 and the upper electrode 180 crossing the lower conductive patterns 110. do. The heated pattern 170 and the upper electrode 180 directly contact the lower electrodes 145 through the contact windows 165. According to this embodiment, since the contact window 165 is formed in a line shape, the area where the lower electrode 145 contacts the heated pattern 170 contacts the width W of the heated pattern 170. ₂ ) is equal to the product of the sidewall portion thickness T of the lower electrode 145. In this case, in order to minimize the contact area, the width of the heated pattern 170 is smaller than the width of the gap region 125 (that is, the width of the bottom of the lower electrode 145). As a result, the upper surface of the lower electrode 145 may be partially exposed in the contact window 165 on both sides of the pattern to be heated 170.

Meanwhile, according to another exemplary embodiment, the contact window 165 may be formed in a direction crossing the lower conductive patterns 145, as shown in FIG. 9. In this case, one contact window 165 is formed in a line shape, as in the previous embodiment, to expose the top surfaces of the plurality of lower electrodes 145. In addition, according to this embodiment, the contact window 165 may be formed smaller than the width of the heated pattern 170. In this case, the contact area between the heated pattern 170 and the lower electrode 145 is equal to the product of the thickness of the sidewall portion and the width of the contact window 165.

6A is a plan view illustrating a semiconductor device having a heat generating structure according to still another embodiment of the present invention. 7A to 7D are perspective views illustrating a method of manufacturing a semiconductor device in accordance with still another embodiment of the present invention. This embodiment is similar to the embodiment described with reference to FIG. 2A except that the flow of current between the word line and the bit line is a transistor, not a diode. Therefore, for the sake of brevity of discussion, redundant descriptions are omitted below.

6A and 7A, trenches 105 defining active regions 101 are formed in a predetermined region of the semiconductor substrate 100. The trenches 105 may be formed using well known shallow trench isolation (STI) techniques. According to one embodiment of the invention, the active regions 101 may be arranged in a structure similar to those of the DRAM.

6A and 7B, after forming device isolation layer patterns 210 filling the trenches 105, gate patterns 220 are formed across the active regions 101. The gate patterns 220 (used as word lines) constitute gate electrodes of memory cell transistors. Before forming the gate patterns 220, a step of forming a gate insulating layer (not shown) on upper surfaces of the active regions 101 may be further performed.

Subsequently, an ion implantation process using the gate patterns 220 as a mask is performed to be used as the source region 230S and the drain region 230D in the active region 101 at both sides of the gate patterns 220. Impurity regions are formed. According to the present invention, a pair of gate patterns 220 are formed to cross one active region 101. As a result, the pair of drain regions 230D are formed in the active region 101 outside the pair of gate patterns 220, and the active regions 101 between the gate patterns 220 are formed. The source region 230S is formed therein.

6A and 7C, a source plug 240 and a source line 250 connected to the source region 230S are formed. The source line 250 is parallel to the gate patterns 220, and the source plug 240 electrically connects the source line 250 to the source region 230S. Next, drain plugs 260 connected to the drain regions 230D and pads 270 connected to the drain plugs 260 are formed.

6A and 7D, a first insulating layer 120 having gap regions 125 exposing an upper surface of the pad 270 is formed. Subsequently, a lower electrode 145 and an internal insulating pattern 150 are formed in the gap region 125, and an insulating layer 160 having a contact window 165 is formed on the resultant. Subsequently, the heated pattern 170 and the upper electrode 180 that are connected to the lower electrode 145 through the contact window 165 are sequentially formed. The process from forming the first insulating layer 120 to forming the upper electrode 180 may be the same as that of the embodiment described above with reference to FIGS. 3D to 3G.

6B is a plan view illustrating a semiconductor device having a heat generating structure according to still another embodiment of the present invention. 8 is a perspective view illustrating a semiconductor device including a heat generating structure according to still another embodiment of the present invention. This embodiment is similar to the embodiment described with reference to FIGS. 7A-7D, except for the technical differences associated with contact window 165. Therefore, for the sake of brevity of discussion, redundant descriptions are omitted below.

6B and 8, after forming the insulating layer 160, the insulating layer 160 is patterned to form a contact window 165 exposing a portion of the upper surface of the sidewall of the lower electrode 145. According to this embodiment, the contact window 165 is formed in a direction parallel to the lower conductive pattern 145, and one contact window 165 exposes the plurality of lower electrodes 145. The contact window 165 is formed in a line shape, unlike the embodiment described with reference to FIG. 2A.

Subsequently, the heating pattern 170 and the upper electrode 180 that are connected to the lower electrode 145 through the contact window 165 are formed. The step of forming the heated pattern 170 and the lower electrode 145 is the same as that of the embodiment described with reference to FIG. 7D.

According to the present invention, the phase change pattern of the PRAM is connected to a portion of the sidewall portion of the lower electrode exposed through the contact window. In this case, the contact area of the phase change pattern and the lower electrode is equal to the product of the thickness of the side wall portion and the width of the contact window. In this case, since the lower electrode is formed through a deposition process in which the thickness thereof is strictly controlled by an order of several angstroms, the present invention can minimize not only the contact area but also the distribution of the contact area. This reduction in contact area contributes to the improvement of the electrical properties of the PRAM, and the reduction in the spread of the contact area contributes to improving the uniformity of the memory cells.

In addition, according to the present invention, the lower electrode is formed without reducing the contact area with the lower film. Accordingly, only the interface resistance between the lower electrode and the phase change pattern can be selectively increased, and this selective increase contributes to improving the electrical characteristics of the PRAM.

In addition, according to the present invention, since the phase change pattern is patterned in the form of a line crossing a plurality of memory cells (ie, lower electrodes), deterioration of product characteristics due to etching damage occurring in conventional island-like phase change patterns. Or problems such as lifting of phase change patterns can be minimized.

Claims (32)

delete A plurality of lower electrodes having a bottom portion and a sidewall portion extending upwardly from an edge of the bottom portion; A heated pattern disposed on the lower electrodes; And An insulating film interposed between the heating pattern and the lower electrodes, the contact window exposing a part of the upper surface of the sidewall of the lower electrode; The heating pattern is connected to a part of the upper surface of the side wall portion of the lower electrode through the contact window, The contact window has a narrower width than the heating pattern, And a contact area between the pattern to be heated and the lower electrode is a product of a thickness of the sidewall portion and a width of the contact window. A plurality of lower electrodes having a bottom portion and a sidewall portion extending upwardly from an edge of the bottom portion; A heated pattern disposed on the lower electrodes; And An insulating film interposed between the heating pattern and the lower electrodes, the contact window exposing a part of the upper surface of the sidewall of the lower electrode; The heating pattern is connected to a part of the upper surface of the side wall portion of the lower electrode through the contact window, The contact window is formed to expose upper surfaces of sidewall portions of the lower electrodes in a direction crossing the heated pattern, And a contact area between the heated pattern and the lower electrode is a product of the thickness of the sidewall portion and the width of the heated pattern. A plurality of lower electrodes having a bottom portion and a sidewall portion extending upwardly from an edge of the bottom portion; A heated pattern disposed on the lower electrodes; And An insulating film interposed between the heating pattern and the lower electrodes, the contact window exposing a part of the upper surface of the sidewall of the lower electrode; The heating pattern is connected to a part of the upper surface of the side wall portion of the lower electrode through the contact window, The contact window is formed to expose upper surfaces of sidewall portions of the lower electrodes in a direction parallel to the heating pattern; And a contact area between the pattern to be heated and the lower electrode is a product of a thickness of the sidewall portion and a width of the contact window. The method according to any one of claims 2 to 4, The heating pattern is a semiconductor device having a heating structure, characterized in that for connecting a plurality of lower electrodes. The method according to any one of claims 2 to 4, The heating pattern is a semiconductor device having a heat generating structure, characterized in that formed of a material containing at least one of antimony (Sb), tellurium (Te) and selenium (Selenium, Se). The method according to any one of claims 2 to 4, The lower electrode includes nitrides including metal elements, oxynitrides including metal elements, carbon (carbon), titanium (Ti), tantalum (Ta), aluminum titanium (TiAl), zirconium (Zr), and hafnium. (Hf), molybdenum (Mo), aluminum (Al), aluminum-copper (Al-Cu), aluminum-copper-silicon (Al-Cu-Si), copper (Cu), tungsten (W), tungsten titanium (TiW ) And tungsten silicide (WSix) formed of at least one material, Nitrides including the metal element include TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN and TaAlN, And the oxynitrides containing the metal elements include TiON, TiAlON, WON, and TaON. The method according to any one of claims 2 to 4, And a sidewall portion of the lower electrode is a closed line having a thickness of 1 to 20 nm. The method according to any one of claims 2 to 4, Further comprising an upper electrode disposed on the heating pattern, And the upper electrode is self-aligned to the heating pattern, and electrically connects the lower electrodes connected to the heating pattern. The method of claim 9, The upper electrode includes nitrides including metal elements, oxynitrides including metal elements, titanium (Ti), tantalum (Ta), aluminum titanium (TiAl), zirconium (Zr), hafnium (Hf), and molybdenum (Mo). ), Aluminum (Al), aluminum-copper (Al-Cu), aluminum-copper-silicon (Al-Cu-Si), copper (Cu), tungsten (W), tungsten titanium (TiW) and tungsten silicide (WSix) Formed of at least one material selected from among Nitrides including the metal element include TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN and TaAlN, And the oxynitrides containing the metal elements include TiON, TiAlON, WON, and TaON. The method according to any one of claims 2 to 4, A lower conductive pattern disposed across the lower electrodes while crossing the heated pattern; And And a heating structure interposed between the lower conductive pattern and the lower electrodes to further include semiconductor patterns constituting a diode. The method of claim 11, And the lower electrode and the semiconductor pattern are self-aligned to have the same occupation area. The method of claim 11, And the lower conductive pattern includes at least one of polycrystalline silicon, metal silicides, and metals. The method according to any one of claims 2 to 4, An internal insulating pattern disposed between the bottom portion of the lower electrode and the insulating layer; And Is disposed around the side wall portion of the lower electrode, further comprising an external insulating pattern for electrically separating the lower electrodes, And an upper surface of the sidewall portion of the lower electrode is lower than at least upper surfaces of the inner insulating pattern and the outer insulating pattern in the contact window. The method according to any one of claims 2 to 4, A memory transistor disposed under the lower electrode, The memory transistor includes a gate electrode crossing the heated pattern and source / drain regions formed on both sides of the gate electrode. The method of claim 15, A source line crossing the heated pattern at an upper portion of the source region; A source plug connecting the source region and the source line; And And a heat generating structure further comprising a drain plug connecting the drain region and the lower electrode. The method according to any one of claims 2 to 4, The insulating film is a semiconductor device having a heat generating structure, characterized in that formed of one of the materials having a thickness of 20 ~ 200 Å, at least 10 × 10 ^-3 10cm. The method according to any one of claims 2 to 4, The contact window has a depth of 5 kPa to 1000 kPa, and an aspect ratio of 0.0001 to 2, the semiconductor device having a heat generating structure. Forming an outer insulating pattern having gap regions on the semiconductor substrate; Forming a bottom electrode in the gap region, the bottom electrode having a bottom portion and a sidewall portion extending upwardly from an edge of the bottom portion; Forming an insulating layer on the outer insulating pattern, the insulating layer having a contact window exposing a portion of an upper surface of the sidewall of the lower electrode; And Forming a heating pattern on the insulating layer to be connected to an upper surface of the sidewall of the lower electrode exposed through the contact window; Forming an insulating film having the contact windows Forming the insulating film on a resultant on which the lower electrode is formed; And And patterning the insulating film such that one contact window exposes the plurality of lower electrodes. The method of claim 19, Before forming the lower electrode, further comprising forming semiconductor patterns disposed in the lower regions of the gap regions to form a diode. The method of claim 20, Before forming the external insulating pattern, further comprising forming a lower conductive pattern disposed under the semiconductor patterns, And the lower conductive pattern connects the semiconductor patterns in a direction crossing the heated pattern. The method of claim 20, Forming the semiconductor pattern Performing an epitaxial process using the lower conductive pattern as a seed layer to form a semiconductor film filling the gap regions; Etching the entire semiconductor layer to form the semiconductor pattern to expose the upper sidewall of the gap region; And Forming the diode by sequentially injecting impurities of different conductivity types into the semiconductor substrate. The method of claim 19, Before forming the outer insulation pattern, Forming a transistor having a gate electrode crossing the heated pattern and source / drain regions formed on both sides of the gate electrode; And And forming a drain plug electrically connecting the drain region of the transistor and the lower electrode. The method of claim 19, And forming an inner insulation pattern on the bottom portion of the lower electrode prior to forming the insulating layer to fill the gap region. The method of claim 24, Forming the lower electrode and the internal insulation pattern Forming a lower electrode layer covering a bottom surface and a sidewall of the gap region on the resultant product on which the external insulation pattern is formed; Forming an internal insulating film filling the gap region on the resultant material on which the lower electrode film is formed; And Etching the inner insulating film and the lower electrode film until the upper surface of the outer insulating pattern is exposed. The method of claim 25, The lower electrode layer is formed using one of atomic layer deposition (ALD), metal organic chemical vapor deposition (MO-CVD), thermal CVD, biased CVD, plasma CVD, and ECR CVD. . The method of claim 25, And the lower electrode film conformally covers the bottom and sidewalls of the gap region with a thickness of 1 to 20 nm. Forming an outer insulating pattern having gap regions on the semiconductor substrate; Forming a bottom electrode in the gap region, the bottom electrode having a bottom portion and a sidewall portion extending upwardly from an edge of the bottom portion; Forming an insulating layer on the outer insulating pattern, the insulating layer having a contact window exposing a portion of an upper surface of the sidewall of the lower electrode; And Forming a heating pattern on the insulating layer to be connected to an upper surface of the sidewall of the lower electrode exposed through the contact window; Forming an insulating film having the contact windows Forming the insulating film on a resultant on which the lower electrode is formed; And And patterning the insulating film so that one contact window exposes one lower electrode. The method of claim 19, And the contact window has a long axis in a direction crossing the heated pattern or a long axis parallel to the heated pattern. The method of claim 19, Forming an insulating film having the contact windows Forming the insulating film on a resultant on which the lower electrode is formed; And Patterning the insulating film to form the contact window; And the contact window is formed to have a depth of 5 kV to 1000 kV and an aspect ratio of 0.0001 to 2. The method of claim 19, Forming the heated pattern is Forming a phase change film on the insulating film, the phase change film contacting an upper surface of the sidewall portion of the lower electrode through the contact window; And Patterning the phase change film to form the heated pattern; The heating pattern is a method of manufacturing a semiconductor device, characterized in that for connecting a plurality of lower electrodes. The method of claim 19, The insulating film forms one of materials having a resistivity of at least 10 × 10 ⁻³ Ωcm to a thickness of 5 Å to 1000 ,, The lower electrode is TiN, TaN, WN, MoN, NbN, TiSiN, TiAlN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoSiN, MoAlN, TaSiN, TaAlN, TiON, TiAlON, WON, TaON, Carbon (carbon, C) , Titanium (Ti), tantalum (Ta), aluminum titanium (TiAl), zirconium (Zr), hafnium (Hf), molybdenum (Mo), aluminum (Al), aluminum-copper (Al-Cu), aluminum-copper- It is formed of at least one material selected from silicon (Al-Cu-Si), copper (Cu), tungsten (W), tungsten titanium (TiW) and tungsten silicide (WSix), The heating pattern is a method of manufacturing a semiconductor device, characterized in that formed of a material containing at least one of antimony (Sb), tellurium (Te) and selenium (Selenium, Se).

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