KR100675278B1 - Semiconductor devices having phase change memory cells covered with an oxygen barrier layer, electronic systems employing the same and methods of fabricating the same - Google Patents

Abstract

Semiconductor devices having phase change memory cells covered with an oxygen barrier film are provided. The semiconductor devices have a molding film formed on a semiconductor substrate. The molding film has a protrusion extending in the vertical direction from its upper surface. A phase change material pattern is provided to contact the protrusion. The phase change material pattern is electrically connected to the lower electrode. Semiconductor devices and electronic systems employing the phase change memory cells are provided. Methods of manufacturing the phase change memory cells are also provided.

Description

Semiconductor devices having phase change memory cells covered with an oxygen barrier layer, electronic systems employing the same and methods of fabricating the same}

FIG. 1A is a schematic view for explaining phase change memory devices according to example embodiments. FIG.

FIG. 1B is a plan view illustrating a portion of a phase change memory device according to example embodiments. FIG.

2 through 9 are cross-sectional views taken along line II ′ of FIG. 1B to explain phase change memory devices and a method of manufacturing the same according to embodiments of the present invention.

FIG. 10 is a cross-sectional view illustrating a unit cell and a manufacturing method of a phase change memory device according to another exemplary embodiment of the present invention.

FIG. 11 is a cross-sectional view illustrating a unit cell of a phase change memory device and a method of manufacturing the same according to another embodiment of the present invention.

12 is a cross-sectional view illustrating a unit cell of a phase change memory device and a method of manufacturing the same according to another embodiment of the present invention.

FIG. 13 is a schematic block diagram illustrating a portable electronic device employing phase change memory devices in accordance with embodiments of the present invention.

FIG. 14 is a graph showing contact resistance measurement results between GST films and lower electrodes of phase change memory cells fabricated according to the related art and embodiments of the present invention.

FIG. 15 is a graph illustrating measurement results of set / reset characteristics of phase change memory cells manufactured according to the related art.

FIG. 16 is a graph illustrating measurement results of set / reset characteristics of phase change memory cells manufactured according to an exemplary embodiment of the present invention.

FIG. 17 is a graph illustrating set / reset resistance characteristics according to cell size of phase change memory cells fabricated according to the related art and the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices and methods of manufacturing the same, and more particularly to semiconductor devices having phase change memory cells covered with an oxygen barrier film, electronic systems employing the same, and methods of manufacturing the same.

Nonvolatile memory devices have a feature that data stored therein is not destroyed even if their power supply is cut off. Accordingly, the nonvolatile memory devices are widely adopted in computers, mobile communication systems, and memory cards.

Flash memory devices are widely used as the nonvolatile memory devices. The flash memory device mainly employs memory cells having a stacked gate structure. The stacked gate structure includes a tunnel oxide layer, a floating gate, an inter-gate dielectric layer, and a control gate electrode sequentially stacked on the channel region. In order to improve the reliability and program efficiency of the flash memory cell, the film quality of the tunnel oxide layer should be improved and the coupling ratio of the cell should be increased.

Instead of the flash memory device, new nonvolatile memory devices such as phase change memory devices have recently been proposed. The unit cell of the phase change memory device includes a switching device and a data storage element serially connected to the switching device. The data storage element includes a lower electrode electrically connected to the switching element and a phase change material layer in contact with the lower electrode. In general, the lower electrode acts as a heater. When a write current flows through the switching element and the lower electrode, joule heat is generated at an interface between the phase change material layer and the lower electrode. This joule heat transforms the phase change material film into an amorphous state or crystalline state. The phase change material film having the amorphous state exhibits higher resistance than the phase change material film having the crystalline state. Therefore, the phase change material film is widely used as a data storage element of the phase change memory device.

The switching element should be designed to have sufficient current drivability to provide the write current. However, in order to improve the current driving capability, the area occupied by the switching element must be increased. When the area of the switching element is increased, it is difficult to improve the integration density of the phase change memory device. Accordingly, methods for minimizing the contact area between the lower electrode and the phase change material film instead of increasing the size of the switching device are continuously studied.

The method for minimizing the contact area of the lower electrode is described in US Pat. No. 6,147,395 as "Method for fabricating a small area of contact between electrodes." It has been disclosed by. According to Gilgen, a fine tip serving as a lower electrode (heater) of the phase change memory device is formed by using an isotropic etching process. A phase change material film is formed on the fine tip. As a result, the contact area between the phase change material film and the fine tip (heater) can be minimized.

The uniformity of the contact resistance between the phase change material layers and the heaters may directly affect a writing operation of the phase change memory cells. For example, when the contact resistance of all heaters in the phase change memory device exhibits a variation larger than a specific value, a first write current for writing information corresponding to logic "0" and It may be difficult to set a second write current for writing information corresponding to logic "1". In particular, the interface between the phase change material films and the heaters may be further oxidized during a subsequent process carried out under an oxygen atmosphere. In this case, the variation of the contact resistance of the heaters increases, which causes more difficulty in setting the first write current and the second write current.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide high performance and highly integrated phase change memory cells.

Another technical object of the present invention is to provide semiconductor devices having high performance and highly integrated phase change memory cells.

Another technical object of the present invention is to provide electronic systems employing high performance and highly integrated phase change memory cells.

Another technical problem to be achieved by the present invention is to provide methods for manufacturing high performance and highly integrated phase change memory cells.

According to one aspect of the present invention, semiconductor devices having phase change memory cells are provided. The semiconductor devices include a molding film disposed on a semiconductor substrate. The molding film has a protrusion extending in the vertical direction from an upper surface thereof. A phase change material pattern is provided to contact the protrusion. The phase change material pattern is electrically connected to the lower electrode.

In some embodiments of the present invention, the phase change material pattern may be disposed on the protrusion. In this case, the phase change material pattern may be self-aligned with the protrusion. In addition, the phase change material pattern may have a localized shape extending through the protrusion.

In other embodiments, at least a portion of the sidewall of the phase change material pattern and at least a portion of the sidewall of the protrusion may be covered with an oxygen barrier film.

In still other embodiments, the phase change material pattern may be electrically connected to the upper electrode. The phase change material pattern and the upper electrode may be covered with an oxygen barrier layer.

In still other embodiments, the phase change material pattern may include a chalcogenide material film. The chalcogenide material layer may include a GeSbTe (GST) alloy layer. The GST alloy film may be doped with at least one of silicon and nitrogen.

In still other embodiments, the protrusion may have a thickness of at least 100 mm 3. The thickness may range from 300 kPa to 600 kPa.

According to another aspect of the present invention, the semiconductor devices include a molding film disposed on a semiconductor substrate and a phase change material pattern disposed on the molding film. The molding film has a protrusion extending in a vertical direction from an upper surface thereof, and the phase change material pattern is disposed on the protrusion. An area where the sidewall of the phase change material pattern and the sidewall of the protrusion contact each other is covered with an oxygen barrier layer. The phase change material pattern is electrically connected to the lower electrode. The lower electrode extends to penetrate the protrusion.

In some embodiments of the present invention, the phase change material pattern may have a localized shape extending through the protrusion.

In other embodiments, an upper electrode may be disposed on the phase change material pattern. A hard mask may be provided on the upper electrode. The oxygen barrier layer may cover the upper electrode and the phase change material pattern. The oxygen barrier layer may include a first portion disposed on an upper surface of the upper electrode and a second portion covering sidewalls of the phase change material pattern. In this case, the first portion may be thicker than the second portion. The thickness of the second portion may be equal to or greater than 300 mm 3.

In still other embodiments, the oxygen barrier layer may include a lower oxygen barrier layer and an upper oxygen barrier layer. The lower oxygen barrier film may be a material film formed using a plasma CVD process or an atomic layer deposition (ALD) process at a temperature of 350 ° C. or less, and the upper oxygen barrier film may use a plasma CVD process or a low pressure CVD process at a temperature of 350 ° C. or more. It may be formed of a material film. The lower oxygen barrier layer may include a nitride layer, and the upper oxygen barrier layer may include a nitride layer or a metal oxide layer. The nitride layer may include a silicon nitride layer or a silicon oxynitride layer, and the metal oxide layer may include an aluminum oxide layer, a titanium oxide layer, a zirconium oxide layer, a hafnium oxide layer, or a lanthanum oxide layer. The lower oxygen barrier layer may have a spacer shape covering sidewalls of the protrusion and sidewalls of the phase change material pattern. A stress buffer layer may be provided between the lower oxygen barrier layer and the upper oxygen barrier layer. The stress buffer layer may be a silicon oxide layer.

In still other embodiments, the oxygen barrier film may be a single nitride film. In this case, the oxygen barrier film may be a silicon nitride film or a silicon oxynitride film formed using a plasma CVD process or an atomic layer deposition (ALD) process at a temperature of 350 ° C. or less.

In other embodiments, sidewalls of the phase change material pattern may be self-aligned with the sidewalls of the protrusion.

In still other embodiments, the phase change material pattern may be a chalcogenide material film.

In still other embodiments, a switching transistor may be provided on the semiconductor substrate. In addition, an interlayer insulating film may be disposed on the switching transistor, and a conductive pad may be provided in the interlayer insulating film. The conductive pad may be electrically connected to the switching transistor and the lower electrode. In addition, the protrusion of the molding layer may be positioned on the conductive pad. The switching transistor may include a gate electrode, a source region, and a drain region, and the conductive pad may be electrically connected to the drain region. A common source line may be disposed in the interlayer insulating layer. The common source line may be electrically connected to the source region. A silicide layer may be provided on the source / drain regions and / or the gate electrode.

In other embodiments, the molding layer may be a material layer having a higher thermal conductivity than the silicon oxide layer. The molding layer may be a silicon oxynitride layer or a silicon nitride layer.

In other embodiments, the sidewall of the lower electrode may be surrounded by the contact spacer. The contact spacer may include an inner contact spacer and an outer contact spacer, and the outer contact spacer may surround the inner contact spacer.

According to another aspect of the present invention, the semiconductor devices include a semiconductor substrate having a memory cell region and a peripheral circuit region. A first transistor is provided on the semiconductor substrate in the memory cell region. The first transistor includes a first gate electrode having a first source / drain regions and a first gate electrode having a first width, and a first gate insulating layer between the first gate electrode and the substrate. A molding film is provided on a substrate having the first transistor. The molding film has a protrusion extending in the vertical direction from an upper surface thereof and the protrusion is located in the memory cell area. A phase change material pattern is provided to contact the protrusion. The phase change material pattern is electrically connected to the lower electrode. The phase change material pattern is electrically connected to the upper electrode. Sidewalls of the phase change material pattern and sidewalls of the protrusions are covered with an oxygen barrier film. A second transistor is provided on the semiconductor substrate in the peripheral circuit region. The second transistor includes a second gate electrode between the second gate electrode and the substrate as well as a second gate electrode having second source / drain regions and a second width. The second width is different from the first width.

In some embodiments of the present invention, the second width may be at least 1.5 times greater than the first width.

In other embodiments, the sidewalls of the protrusion may be self-aligned with the sidewalls of the phase change material pattern. The phase change material pattern may have a localized shape extending through the protrusion.

In other embodiments, the second gate insulating layer may be thicker than the first gate insulating layer.

In still other embodiments, the phase change material pattern may include a chalcogenide material film.

In still other embodiments, the oxygen barrier layer may include a lower oxygen barrier layer and an upper oxygen barrier layer. The lower oxygen barrier layer may include a nitride layer, and the upper oxygen barrier layer may include a nitride layer or a metal oxide layer. The nitride layer may include a silicon nitride layer or a silicon oxynitride layer, and the metal oxide layer may include an aluminum oxide layer, a titanium oxide layer, a zirconium oxide layer, a hafnium oxide layer, or a lanthanum oxide layer. The lower oxygen barrier layer may have a spacer shape covering sidewalls of the protrusion and sidewalls of the phase change material pattern. A stress buffer layer may be provided between the lower oxygen barrier layer and the upper oxygen barrier layer. The stress buffer layer may be a silicon oxide layer.

In still other embodiments, the oxygen barrier film may be a single nitride film. In this case, the oxygen barrier film may be a silicon nitride film or a silicon oxynitride film formed using a plasma CVD process or an atomic layer deposition (ALD) process at a temperature of 350 ° C. or less.

In other embodiments, the oxygen barrier layer may include a first portion disposed on an upper surface of the upper electrode and a second portion covering sidewalls of the phase change material pattern. The first portion may be thicker than the second portion.

In still other embodiments, a silicide layer may be provided on the first and second source / drain regions and / or the first and second gate electrodes.

According to another aspect of the present invention, electronic systems are provided that employ phase change memory cells. The electronic systems include a processor, an input / output device for performing data communication with the processor, and a phase change memory device for performing data communication with the processor. The phase change memory device includes a molding film formed on an integrated circuit board. The molding film has a protrusion extending in the vertical direction from its upper surface. A phase change material pattern is provided to contact the protrusion. The phase change material pattern is electrically connected to the lower electrode.

In some embodiments of the present invention, the phase change material pattern may have a localized shape extending through the protrusion.

In other embodiments, an area where the sidewall of the phase change material pattern and the sidewall of the protrusion contact each other may be covered with an oxygen barrier layer.

According to another aspect of the present invention, methods of manufacturing semiconductor devices having phase change memory cells are provided. These methods include forming a molding film on a semiconductor substrate. A lower electrode is formed in the molding film. A phase change material film is formed to contact the lower electrode. The phase change material layer is patterned and an upper portion of the molding layer is etched to form a protrusion extending in a vertical direction from an upper surface of the etched molding layer and a phase change material pattern contacting the protrusion. An oxygen barrier layer is formed to cover the phase change material pattern.

In some embodiments of the present invention, the oxygen barrier film may be formed of a single nitride film. The single nitride film may be formed of a silicon nitride film or a silicon oxynitride film at a temperature lower than 350 ° C. The single nitride film may be formed using a plasma CVD process or an atomic layer deposition process. The single nitride film can be condensed using heat treatment techniques or plasma treatment techniques.

In other embodiments, forming the oxygen barrier layer may include forming a lower oxygen barrier layer on the substrate having the phase change material pattern and forming an upper oxygen barrier layer on the lower oxygen barrier layer. . The lower oxygen barrier layer may be formed of a silicon nitride layer or a silicon oxynitride layer at a temperature lower than 350 ° C. The lower oxygen barrier film may be condensed using heat treatment techniques or plasma treatment techniques.

In example embodiments, the lower oxygen barrier layer may be anisotropically etched to form a lower oxygen barrier layer pattern in the form of a spacer covering the sidewall of the phase change material pattern and the sidewall of the molding layer. The spacer-shaped lower oxygen barrier film pattern may be condensed using a heat treatment technique or a plasma treatment technique. A stress buffer layer may be formed on the substrate having the spacer-shaped lower oxygen barrier layer pattern. The stress buffer layer may be formed of a silicon oxide layer.

In other embodiments, a stress buffer layer may be formed on the substrate having the lower oxygen barrier layer.

In other embodiments, the upper oxygen barrier layer may be formed of a nitride layer or a metal oxide layer. The nitride film may be formed of a silicon nitride film or a silicon oxynitride film, and the metal oxide film may be formed of an aluminum oxide film, a titanium oxide film, a zirconium oxide film, a hafnium oxide film, or a lanthanum oxide film.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

1A is a schematic diagram illustrating phase change memory devices according to example embodiments.

Referring to FIG. 1A, the phase change memory devices include a cell array region CA and a peripheral circuit region PCA. The cell array region CA, that is, the memory cell region includes a plurality of word lines WL, a plurality of bit lines BL orthogonal to the word lines WL, and the word lines WL and A plurality of phase change memory cells 100 are disposed at intersections of the bit lines BL. In addition, the peripheral circuit area PCA includes first and second integrated circuits PCA1 and PCA2 for driving the phase change memory cells 100. The first integrated circuit PCA1 may include a row decoder for selecting one of the word lines WL, and the second integrated circuit PCA2 may include the bit lines BL. It may include a column decoder for selecting any one of the.

Each of the phase change memory cells 100 has a phase change resistor RP electrically connected to any one of the bit lines BL and a switching electrically connected to the phase change resistor RP. It includes an element. The phase change resistor RP may have both terminals, i.e., first and second terminals, and a phase change material interposed between the first and second terminals. It may be an access MOS transistor TA having a gate electrode, a source region, and a drain region. In this case, the first terminal of the phase change resistor RP is electrically connected to a drain region of the access MOS transistor TA, and the second terminal of the phase change resistor RP is connected to the bit line. Is electrically connected to BL). In addition, the gate electrode of the access MOS transistor TA is electrically connected to any one of the word lines WL, and the source region of the access MOS transistor TA is a common source line CSL; Is electrically connected).

To selectively store data in any one of the phase change memory cells 100, the bit connected to the access MOS transistor TA of the selected cell CL and connected to the selected cell CL is turned on. A writing current Iw is forced through the line BL. In this case, the electrical resistance of the phase change resistor RP may change according to the amount of the writing current Iw. For example, when the phase change material is heated by the write current Iw to a temperature between its crystallization temperature and a melting point and the heated phase change material is cooled, The phase change material is transformed into a crystalline state. In contrast, when the phase change material is heated to a temperature higher than the melting point by the write current Iw and the molten phase change material is quenched, the phase change material is changed into an amorphous state. The resistivity of the phase change material having the crystalline state is lower than that of the phase change material having the amorphous state. Accordingly, by detecting the current flowing through the phase change material in the read mode, it is possible to determine whether the information stored in the phase change resistor RP is logic "1" or logic "0".

FIG. 1B is a plan view illustrating a part of the phase change memory device shown in FIG. 1A. 2 to 9 are cross-sectional views taken along line II ′ of FIG. 1B to explain methods of manufacturing phase change memory devices according to example embodiments.

1B and 2, an isolation layer 3 is formed in a predetermined region of an integrated circuit board 1, that is, a semiconductor substrate, thereby enabling cell activation in the cell array area CA and the peripheral circuit area PCA, respectively. The region 3c and the peripheral active region 3p are defined. A gate insulating film is formed on the active regions 3c and 3p. The gate insulating layer may include a cell gate insulating layer 5c and a peripheral gate insulating layer 5p respectively formed on the cell active region 3c and the peripheral active region 3p. The peripheral gate insulating layer 5p may be formed to have the same thickness as the cell gate insulating layer 5c. Alternatively, the peripheral gate insulating layer 5p may be formed to have a thickness different from that of the cell gate insulating layer 5c. For example, the peripheral gate insulating layer 5p may be formed to be thicker than the cell gate insulating layer 5c. A pair of cell gate electrodes 7c crossing the upper portion of the cell active region 3c by forming a gate conductive layer on the substrate having the gate insulating layers 5c and 5p, and patterning the gate conductive layer; A peripheral gate electrode 7p is formed across the upper portion of the peripheral active region 3p. The cell gate electrodes 7c may extend to serve as word lines (WL in FIG. 1A). In addition, the cell gate electrodes 7c may be formed to have a width different from that of the peripheral gate electrode 7p. For example, the width of the peripheral gate electrode 7p may be at least 1.5 times larger than the width of the cell gate electrodes 7c.

1B and 3, N-type impurity ions may be selectively implanted into the cell active region 3c by using the cell gate electrodes 7c as an ion implantation mask. That is, the first low concentration impurity regions 9a are formed. Subsequently, P-type impurity ions are selectively implanted into the peripheral active region 3p by using the peripheral gate electrode 7p as an ion implantation mask, that is, P-type low concentration impurity regions, that is, second low concentration impurity regions ( 9b). Subsequently, gate spacers 11 are formed on the sidewalls of the gate electrodes 7c and 7p using a conventional method. The gate spacers 11 are formed of an insulating film, such as a silicon oxide film or a silicon nitride film.

N-type impurity ions selectively in the cell active region 3c using the cell gate electrodes 7c and the gate spacers 11 on the sidewalls of the cell gate electrodes 7c as ion implantation masks. To form N-type source / drain regions, that is, first source / drain regions 13s 'and 13d'. Specifically, the first source / drain regions 13s ′ and 13d ′ may be formed in addition to the common source region 13s ′ formed in the cell active region 3c between the cell gate electrodes 7c. It is formed to have a pair of drain regions 13d 'formed at both ends of the region 3c.

Subsequently, P-type impurity ions are selectively formed in the peripheral active region 3p using the peripheral gate electrode 7p and the gate spacer 11 on the sidewall of the peripheral gate electrode 7p as ion implantation masks. Implantation to form P-type source / drain regions, that is, second source / drain regions 13s "and 13d". As a result, a pair of access MOS transistors TA formed of the cell gate electrodes 7c and the first source / drain regions 13s 'and 13d' are formed in the cell active region 3c. The peripheral circuit MOS transistor TP including the peripheral gate electrode 7p and the second source / drain regions 13s "and 13d" is formed in the peripheral active region 3p.

When the peripheral circuit MOS transistor TP is an NMOS transistor, the second low concentration impurity regions 9b may be formed simultaneously with the first low concentration impurity regions 9a and the second Source / drain regions 13s "and 13d" may be formed simultaneously with the first source / drain regions 13s 'and 13d'.

Subsequently, the peripheral metal silicide film 15b is formed on at least the second source / drain regions 13s ″, 13d ″ using a conventional salicide (self-aligned silicide) technique. For example, after forming a silicidation blocking layer (not shown) covering the cell array region CA and exposing the peripheral circuit region PCA, the peripheral gate electrode 7p and The peripheral metal silicide layer 15b may be selectively formed on the second source / drain regions 13s ″ and 13d ″. When a capping layer made of an insulating layer is formed on the peripheral gate electrode 7p, the peripheral metal silicide layer 15b may be selectively formed only on the second source / drain regions 13s ″ and 13d ″. . The silicided stop layer may be formed of a silicon nitride layer. According to another embodiment of the present invention, the cell metal silicide layer 15a and the peripheral metal silicide layer 15b are formed on the first and second source / drain regions 13s ', 13d', 13s ", and 13d", respectively. ) May be selectively formed. According to another embodiment of the present invention, as shown in FIG. 3, selective on the gate electrodes 7c and 7p and the source / drain regions 13s ', 13d', 13s ", and 13d". The metal silicide layers 15a and 15b may be formed. In contrast, the silicided stop layer covers the first and second source / drain regions 13s ', 13d', 13s ", and 13d", and covers the cell gate electrodes 7c and the peripheral gate electrode 7p. When formed to expose, the cell metal silicide film 15a and the peripheral metal silicide film 15b may be formed only on the cell gate electrodes 7c and the peripheral gate electrode 7p, respectively. .

The access MOS transistors TA serve as switching elements of phase change memory cells. In other embodiments of the present invention, bipolar transistors may be formed instead of the access MOS transistors TA.

The lower etch stop layer 17 is formed on the substrate including the metal silicide layers 15a and 15b. The lower etch stop layer 17 may be formed of a silicon nitride layer having an etch selectivity with respect to an insulating layer such as a silicon oxide layer.

1B and 4, the planarized lower insulating layer 19 is formed on the lower etch stop layer 17. The lower insulating film 19 may be formed of a silicon oxide film. The lower etch stop layer 17 and the lower insulating layer 19 form a lower interlayer insulating layer 20. The process of forming the lower etch stop layer 17 may be omitted. First source / drain contact holes 19s' and 19d exposing the cell metal silicide layers 15a on the first source / drain regions 13s' and 13d 'by patterning the lower interlayer insulating layer 20. ') And second source / drain contact holes 19s ″ and 19d ″ exposing the peripheral metal silicide films 15b on the second source / drain regions 13s ″ and 13d ″.

First and second source / drain contact plugs 21s', 21s ", respectively, using conventional methods in the first and second source / drain contact holes 19s', 19s ", 19d ', and 19d", respectively. 21d ', 21d "). The contact plugs 21s ', 21s ", 21d', and 21d" may be formed of a tungsten film. An upper interlayer insulating layer 26 is formed on a substrate having the contact plugs 21s ', 21s ", 21d', and 21d". The upper interlayer insulating layer 26 may be formed by sequentially stacking the upper etch stop layer 23 and the upper insulating layer 25. In this case, the upper etch stop layer 23 is preferably formed of an insulating film having an etch selectivity with respect to the upper insulating film 25. For example, when the upper insulating layer 25 is formed of a silicon oxide layer, the upper etch stop layer 23 may be formed of a silicon nitride layer. The process of forming the upper etch stop layer 23 may be omitted. The upper interlayer insulating film 26 and the lower interlayer insulating film 20 constitute an interlayer insulating film 28.

1B and 5, conductive drain pads 27d ′ and a common source line may be formed using a conventional damascene process in the upper interlayer insulating layer 26 in the cell array region CA. common source line (27s'). In addition, the drain pads 27d "and the source pads are also formed in the upper interlayer insulating layer 26 in the peripheral circuit area PCA while the conductive drain pads 27d 'and the common source line 27s' are formed. 27s " can be formed. The conductive drain pads 27d ', the common source line 27s', the drain pad 27d ", and the source pad 27s" may be formed of a metal film such as a tungsten film, and the common source line 27s ') May be formed to be parallel to the cell gate electrodes 7c. The conductive drain pads 27d 'and the common source line 27s' are formed to contact the first drain contact plugs 21d 'and the first source contact plug 21s', respectively, and the drain The pad 27d ″ and the source pad 27s ″ are formed to contact the second drain contact plug 21d ″ and the second source contact plug 21s ″, respectively. As a result, the common source line 27s 'and the conductive drain pads 27d' are electrically connected to the first source region 13s 'and the first drain regions 13d', respectively. The pad 27s ″ and the drain pad 27d ″ are electrically connected to the second source region 13s ″ and the second drain region 13d ″, respectively.

A molding layer 29 is formed on the substrate having the conductive drain pads 27d ', the common source line 27s', the drain pad 27d ", and the source pad 27s". The molding film 29 is preferably formed of an insulating film having a higher thermal conductivity than a silicon oxide film used as a conventional interlayer insulating film. In addition, the molding layer 29 may be formed of an insulating layer serving as an oxygen barrier layer. For example, the molding layer 29 may be formed of a nitride layer such as a silicon oxynitride layer (SiON layer) or a silicon nitride layer. This improves the cooling efficiency, that is, the quenching efficiency, for phase transition of the phase change material film formed in a subsequent process, between the phase change material film and the upper and lower electrodes in contact therewith. This is to prevent the oxygen atoms from penetrating into the interfaces. Subsequently, the molding layer 29 is patterned to form phase change resistor contact holes 29a exposing the conductive drain pads 27d '.

1B and 6, a conformal contact spacer layer 34 is formed on a substrate having the phase change resistor contact holes 29a. The contact spacer film 34 is preferably formed under the use of oxygen gas under vacuum. If the contact spacer layer 34 is formed using a process gas containing oxygen gas, the contact spacer layer 34 is formed at a temperature as low as possible to suppress oxidation of the exposed conductive drain pad 27d '. It is preferably formed.

The contact spacer layer 34 may be formed of a single contact spacer layer or a double contact spacer layer. The double contact spacer layer may be formed by sequentially stacking a lower contact spacer layer 31 and an upper contact spacer layer 33. In this case, the lower contact spacer layer 31 may be formed of a silicon oxynitride layer using a plasma CVD technique performed at a temperature lower than 500 ° C., and the upper contact spacer layer 33 may be higher than 500 ° C. It can be formed into a silicon nitride film using a low pressure CVD technique carried out in. The single contact spacer film may be formed of a silicon nitride film using a low pressure CVD technique or a plasma CVD technique.

1B and 7, the contact spacer layer 34 is anisotropically etched to expose the conductive drain pads 27d ′. As a result, contact spacers 34a are formed on sidewalls of the phase change resistor contact holes 29a. When the contact spacer layer 34 is formed by sequentially stacking the lower contact spacer layer 31 and the upper contact spacer layer 33, each of the contact spacers 34a may be formed as shown in FIG. 7. An outer contact spacer 31a covering the sidewall of the phase change resistor contact hole 29a and an inner contact spacer 33a covering the inner sidewall of the outer contact spacer 31a are formed. In this case, a lower portion of the outer contact spacer 31a may be exposed after the anisotropic etching process. The effective diameter of the phase change resistor contact holes 29a may be smaller than the resolution limit of the photographing process due to the presence of the contact spacer 34a. That is, according to the present exemplary embodiment, the formation of the contact spacers 34a may reduce the size of the initial phase change resistor contact holes 29a and oxidize the conductive drain pads 27d '. May lead to the suppression of.

Subsequently, a lower electrode layer is formed on the substrate including the contact spacers 34a to fill the phase change resistor contact holes 29a. The lower electrode layer may be formed of a conductive layer such as a titanium nitride layer or a titanium aluminum nitride layer (TiAlN). Subsequently, the lower electrode layer is planarized to expose the molding layer 29. As a result, lower electrodes 35 are formed in the phase change resistor contact holes 29a surrounded by the contact spacers 34a. During the planarization of the lower electrode layer, the lower electrode layer may be excessively etched to form recessed lower electrodes in the phase change resistor contact holes 29a.

The phase change material layer 37 and the upper electrode layer 39 are sequentially formed on the substrate having the lower electrodes 35. The phase change material layer 37 may be formed of a chalcogenide layer. For example, the phase change material layer 37 may be made of germanium (Ge), stevidium (Sb), and tellurium (Te). ) Alloy layer, that is, Te _x Sb _y Ge _{(100- (x + y))} alloy film (hereinafter referred to as "GST alloy film"). Here, "x" may be 20 to 80, and "y" may be 5 to 50. In other words, the GST alloy film is composed of tellurium (Te) having a concentration of 20 atomic% to 80 atomic%, stevirium (Sb) having a concentration of 5 atomic% to 50 atomic%, and greater than 0 atomic% and 75 atomic% It may contain germanium (Ge) having a concentration less than or equal to. Furthermore, the phase change material layer 37 may be formed of a GST alloy layer doped with at least one of nitrogen and silicon. In this case, the doped GST alloy layer has a higher resistivity than the undoped GST alloy layer. Accordingly, the doped GST alloy film generates higher joule heat than the undoped GST alloy film at the same current level. As a result, when the phase change material film 37 is formed of the doped GST alloy film, phase transition efficiency of the phase change material film 37 may be improved. The upper electrode film 39 may be formed of a conductive film such as a titanium nitride film.

A hard mask layer 43 may be further formed on the upper electrode layer 39. In this case, it is preferable to further form a glue layer 41 on the upper electrode film 39 before the hard mask film 43 is formed. The glue film 41 is formed to improve the adhesion between the upper electrode film 39 and the hard mask film 43. The hard mask layer 43 may be formed of a silicon oxide layer, and the glue layer 41 may be formed of a silicon nitride layer.

1B and 8, the hard mask layer 43 is patterned to form hard mask patterns 43a positioned on the lower electrodes 35. Subsequently, the glue film (41 in FIG. 7), the upper electrode film (39 in FIG. 7) and the phase change material film (37 in FIG. 7) are successively using the hard mask patterns 43a as etching masks. Etching forms phase change resistors 44a on the lower electrodes 35. As a result, each of the phase change resistors 44a is formed to have the phase change material film pattern 37a, the upper electrode 39a, and the glue film pattern 41a sequentially stacked.

In addition, after the phase change resistors 44a are formed, the molding layer 29 may be partially etched. Accordingly, the neighboring phase change material layer patterns 37a are completely separated, and the molding layer 29 is self-aligned with the phase change material layer patterns 37a. With protrusions 77. That is, the protrusions 77 correspond to portions extending upwardly from the surface 67 of the partially etched molding layer, and sidewalls of the phase change material patterns 37a are formed in the protrusions. Self-aligned with the sidewalls of 77. As a result, after the phase change resistors 44a are formed, the molding layer 29 may have a surface step difference (S). The protrusions 77 may be formed to have a height (thickness) of at least 100 mm. For example, the protrusions 77 may be formed to have a height of 300 kPa to 600 kPa.

An oxygen barrier layer 48 is formed on the substrate having the phase change resistors 44a. The oxygen barrier layer 48 is formed to cover sidewalls of the protrusions 77 as well as upper surfaces and sidewalls of the phase change resistors 44a. In this case, the first portion of the oxygen barrier film 48 formed on the upper electrodes 39a is formed on the sidewalls of the phase change material patterns 37a. It may be formed thicker than the second portion of the. The second portion of the oxygen barrier layer 48 may be formed to have a thickness of at least 300 kPa.

The oxygen barrier layer 48 may include the phase change material layer patterns 37a and the phases together with interfaces between the phase change material layer patterns 37a and the lower electrodes 35 during subsequent processes. It is formed to prevent oxygen atoms from penetrating the interfaces between the upper electrodes 39a. This is because when oxygen atoms penetrate along the interfaces between the phase change material film patterns 37a and the electrodes 35 and 39a, the phase change material film patterns 37a are oxidized or contaminated, and thus their inherent characteristics. (their own property) is lowered. As a result, the oxygen barrier layer 48 completely surrounds the sidewalls and the upper surfaces of the phase change resistors 44a together with the sidewalls of the protrusions 77 of the molding layer 29 and the phase change resistors. The lower surfaces of the 44a may contact the molding layer 29 which serves as an oxygen barrier layer, thereby preventing external oxygen atoms from penetrating into the interfaces of the phase change material layer patterns 37a.

In addition, oxygen atoms must not penetrate along the top / bottom surfaces of the phase change material film patterns 37a even during the formation of the oxygen barrier film 48. Therefore, the oxygen barrier layer 48 may be formed using an in-situ process without a vacuum break after the etching process for forming the phase change resistors 44a.

The oxygen barrier layer 48 may be formed by sequentially stacking a lower oxygen barrier layer 45, a stress buffer layer 46, and an upper oxygen barrier layer 47. The lower oxygen barrier layer 45 may be formed of a nitride film such as a silicon oxynitride film or a silicon nitride film. In addition, the upper oxygen barrier layer 47 may be formed of a silicon oxynitride layer or a silicon nitride layer and a nitride layer, or may include aluminum oxide (AlO), titanium oxide (TiO), zirconium oxide (ZrO), hafnium oxide (HfO), or lanthanum oxide ( Metal oxide film such as LaO). In addition, the stress buffer layer 46 may be formed of a material layer for relieving stress applied to the lower oxygen barrier layer 45 due to the presence of the upper oxygen barrier layer 47. . For example, the stress buffer layer 46 may be formed of a silicon oxide layer using a plasma CVD technique performed at a temperature of about 200 ° C to 400 ° C.

The lower oxygen barrier layer 45 is directly formed on the substrate to which the phase change material layer patterns 37a are exposed. In this case, when the lower oxygen barrier layer 45 is formed at a temperature higher than about 350 ° C., the exposed phase change material film patterns 37a may be oxidized and the exposed phase change material film patterns ( Oxygen atoms can penetrate along the top / bottom surfaces of 37a). As a result, the characteristics of the phase change material layer patterns 37a may be degraded and the contact resistance of the phase change material layer patterns 37a may increase. For example, when the phase change material layer patterns 37a are formed of chalcogenide layers, the chalcogenide layers may be volatilized at a temperature higher than about 350 ° C. to lose their intrinsic properties. Therefore, the lower oxygen barrier layer 45 is preferably formed at a temperature lower than about 350 ℃. In detail, the lower oxygen barrier layer 45 may be formed using plasma chemical vapor deposition or atomic layer deposition (ALD).

When the lower oxygen barrier layer 45 is formed at a temperature lower than 350 ° C. as described above, the lower oxygen barrier layer 45 may be porous. In this case, since the oxygen blocking efficiency of the lower oxygen barrier layer 45 may be lowered, the lower oxygen barrier layer 45 may be condensed. The condensation process may be carried out using an annealing technique or a plasma treatment technique. The heat treatment process may be carried out using nitrogen gas or ammonia gas as an ambient gas at a temperature of about 400 ℃, the plasma treatment process plasma nitrogen gas or ammonia gas at a temperature of about 200 ℃ to 400 ℃ It can proceed using as a source gas.

The upper oxygen barrier layer 47 does not directly contact the phase change material layer patterns 37a. Therefore, the upper oxygen barrier layer 47 may be formed in consideration of oxygen blocking performance rather than damage to the phase change material layer patterns 37a. That is, the upper oxygen barrier layer 47 may be formed at a higher temperature than the lower oxygen barrier layer 47. For example, the upper oxygen barrier layer 47 may be formed using a plasma chemical vapor deposition technique, a low pressure chemical vapor deposition technique, or an atomic layer deposition technique performed at a temperature higher than about 350 ° C.

In one embodiment of the present invention, the upper oxygen barrier film 47 may be formed of an aluminum oxide film using atomic layer deposition technology. In this case, the aluminum oxide film is formed using ozone gas. The ozone gas is a gas having a stronger corrosive property than oxygen gas. Nevertheless, at least the phase change material layer patterns 37a are covered with the lower oxygen barrier layer 45, so that the phase change material layer patterns 37a are formed during the formation of the upper oxygen barrier layer 47. Can minimize damage.

In another embodiment of the present invention, the metal oxide film employed as the upper oxygen barrier film 47 may be formed using a sputtering technique. In this case, the metal oxide film may be formed by depositing a metal film using a sputtering technique and oxidizing the metal film. For example, when the upper oxygen barrier film 47 is formed of an aluminum oxide film, the aluminum oxide film may be formed by depositing an aluminum film and oxidizing the aluminum film using a sputtering technique. When the aluminum oxide film is formed using the sputtering process and the oxidation process as described above, the aluminum oxide film may be formed to have a final thickness corresponding to 150% of the thickness of the aluminum film by the sputtering technique. For example, if the final target thickness of the aluminum oxide film adopted as the upper oxygen barrier film 47 is 150 kPa, the aluminum oxide film is deposited using an sputtering technique to deposit an aluminum film having a thickness of 100 kPa. It can be formed by oxidizing the aluminum film.

The lower oxygen barrier layer 45 may be formed to a thickness of 200 kPa to 1000 kPa, and the upper oxygen barrier film 47 may be formed to a thickness of 10 kPa to 150 kPa. More specifically, the lower oxygen barrier film 45 may be formed to a thickness of 300 kPa to 500 kPa, and the upper oxygen barrier film 47 may be formed to a thickness of 50 kPa to 100 kPa.

In other embodiments of the present invention, at least one of the condensation process of the lower oxygen barrier layer 45, the process of forming the stress buffer layer 46, and the process of forming the upper oxygen barrier layer 47 may be omitted. Can be.

1B and 9, an insulating film, such as a silicon oxide film, is formed on the oxygen barrier film 48. Subsequently, the insulating layer is planarized to form a planarized lower interlayer insulating layer 49 exposing the oxygen barrier layer 48 on the phase change resistors 44a. The oxygen barrier layer 48 prevents oxygen atoms from penetrating along upper and lower surfaces of the phase change material layer patterns 37a while forming the lower interlayer insulating layer 49. In other words, the oxygen barrier layer 48 prevents the interfacial characteristics between the upper and lower electrodes 39a and 35 of the phase change resistors 44a and the phase change material layer patterns 37a from deteriorating. do.

The upper electrodes may be patterned by patterning the lower interlayer insulating layer 49, the exposed oxygen barrier layer 48, the hard mask patterns 43a, the glue layer patterns 41a, and the molding layer 29. The drain wiring contact hole 49d "and the source wiring contact hole 49s" exposing the drain pad 27d "and the source pad 27s", respectively, as well as the contact holes 49a exposing the 39a. Form. Contact plugs 51, drain wiring contact plugs 51d ", and source wiring contact plugs 51s" in the contact holes 49a, drain wiring contact holes 49d ", and source wiring contact holes 49s", respectively. ). The contact plugs 51, 51d ″, and 51s ″ may be formed of a conductive film such as a tungsten film. Bit line pads 53 and a drain wiring line forming a lower metal layer on a substrate having the contact plugs 51, 51d ″, and 51s ″, and patterning the lower metal layer to cover the contact plugs 51. A drain wiring 53d "covering the contact plug 51d" and a source wiring 53s "covering the source wiring contact plug 51s" are formed. The lower metal film may be formed of a metal film such as an aluminum film or an aluminum alloy film.

An upper interlayer insulating film 55 is formed on a substrate having the bit line pad 53, a drain wiring 53d ″, and a source wiring 53s ″, and the upper interlayer insulating film 55 is patterned to form the bit. Bit line contact holes 55a exposing the line pads 53 are formed. An upper metal layer is formed on the substrate having the bit line contact holes 55a, and the upper metal layer is patterned to cover the bit line contact holes 55a to cross the upper portions of the cell gate electrodes 7c. It forms the squeezing bitline 57. The upper metal film may also be formed of a metal film such as an aluminum film or an aluminum alloy film. The passivation film 62 is formed on the substrate having the bit line 57. The passivation film 62 may be formed by sequentially stacking the silicon oxide film 59 and the silicon nitride film 61.

FIG. 10 is a cross-sectional view for describing a method of manufacturing a unit cell of a phase change memory device according to other exemplary embodiments. The present embodiments differ from the embodiment shown in FIG. 8 in the method of forming the lower oxygen barrier film. Therefore, only the method of forming the lower oxygen barrier film in this embodiment is described.

Referring to FIG. 10, the phase change resistors 44a are formed on the semiconductor substrate 1 using the same methods as described with reference to FIGS. 2 to 8. The lower oxygen barrier layer 45 is formed on the substrate having the phase change resistors 44a using the same method as described with reference to FIG. 8. By anisotropically etching the lower oxygen barrier layer 45, lower oxygen barrier layer patterns 45a having a spacer shape are formed on sidewalls of the phase change resistors 44a and sidewalls of the protrusions 77. Form. The spacer-shaped lower oxygen barrier layer patterns 45a may be condensed through a heat treatment process or a plasma treatment process as described with reference to FIG. 8. In addition, the stress buffer layer 46 and the upper oxygen barrier layer 47 may be sequentially formed on the spacer-shaped lower oxygen barrier layer patterns 45a as described with reference to FIG. 8. Can be. As a result, according to the exemplary embodiments, the spacer-shaped lower oxygen barrier layer patterns 45a, the stress buffer layer 46, and the upper oxygen barrier layer 47 may be formed using an oxygen barrier layer ( 44a) can be configured.

In the present embodiments, at least one of the condensation process of the lower oxygen barrier layer patterns 45a, the process of forming the stress buffer layer 46, and the process of forming the upper oxygen barrier layer 47 may also be omitted. have.

11 is a cross-sectional view for describing a method of manufacturing a unit cell of a phase change memory device according to still another embodiment of the present invention. The embodiments are different from the embodiments shown in FIGS. 7 and 8 in the method of forming the phase change material film patterns.

Referring to FIG. 11, the molding layer 29 and the contact spacer layer 34 are formed on the semiconductor substrate 1 using the same methods as those described with reference to FIGS. 2 to 6. Anisotropically etching the contact spacer layer 34 to form contact spacers 34a and a phase change material without forming the lower electrodes 35 shown in FIG. 7 on the substrate having the contact spacers 34a. The film 37 and the upper electrode film 39 are sequentially formed. Then, the phase change resistors 44b and the oxygen barrier film 48 are formed using the same methods as described with reference to FIGS. 7 and 8. As a result, each of the phase change resistors 44b is directly connected to the conductive drain pad 27d 'through the phase change resistor contact hole 29a surrounded by the contact spacer 34a as shown in FIG. It is formed to have a phase change material film pattern 37b in contact. That is, according to the present embodiments, confined phase change memory cells may be formed. In this case, the conductive drain pad 27d 'may serve as a lower electrode of the phase change resistor 44b.

12 is a cross-sectional view for describing a method of manufacturing a unit cell of a phase change memory device according to still other embodiments of the inventive concept. The present embodiments correspond to the combination of the embodiments shown in FIGS. 10 and 11.

Referring to FIG. 12, confined phase change resistors 44b are formed on the semiconductor substrate 1 using the same methods as described with reference to FIG. 11. The oxygen barrier film 48a is formed on the substrate having the localized phase change resistors 44b using the same methods as described with reference to FIG. 10.

Now, a phase change memory device having phase change memory cells according to embodiments of the present invention will be described.

Referring to FIGS. 1B, 9, 10, 11, and 12, the isolation layer 3 may be formed in a predetermined region of the integrated circuit board 1 having the cell array region CA and the peripheral circuit region PCA. Is provided. The device isolation layer 3 defines a cell active region 3c and a peripheral active region 3p respectively positioned in the cell array region CA and the peripheral circuit region PCA. A pair of switching elements is provided in the cell active region 3c. The switching elements may be access MOS transistors or bipolar transistors. When the switching elements are the access MOS transistors, the pair of access MOS transistors include a pair of first drain regions 13d 'formed at both ends of the cell active region 3c and the cell active region ( A pair of cell gate electrodes 7c disposed on the first source region 13s' formed at the center of 3c and the channel regions between the first source / drain regions 13s' and 13d 'are disposed. Include. The cell gate electrodes 7c may extend to cross the cell active region 3c. In this case, the cell gate electrodes 7c may serve as word lines WL. In addition, the first source region 13s ′ corresponds to a common source region of the pair of access MOS transistors.

A peripheral circuit MOS transistor is provided in the peripheral active region 3p. The peripheral circuit MOS transistor is disposed between the second source / drain regions 13s ″ and 13d ″ as well as the second source region 13s ″ and the second drain region 13d ″ formed in the peripheral active region 3p. A peripheral gate electrode 7p disposed on top of the channel region of the substrate. The width of the peripheral gate electrode 7p may be greater than the width of the cell gate electrodes 7c. In addition, a peripheral gate insulating layer (5p in FIG. 3) between the peripheral gate electrode 7p and the peripheral active region 3p may be a cell gate insulating layer between the cell gate electrode 7c and the cell active region 3c. It may be thicker than 5c) of FIG. 3.

Furthermore, gate spacers 11 may be provided on sidewalls of the gate electrodes 7c and 7p. In this case, first low concentration impurity regions 9a extending from the first source / drain regions 13s 'and 13d' are disposed under the gate spacers 11 in the cell array region CA. Second low concentration impurity regions 9b which may be provided and extend from the second source / drain regions 13s ″ and 13d ″ under the gate spacers 11 in the peripheral circuit region PCA. This may be provided.

A peripheral metal silicide film (self-aligned on at least the second source / drain regions 13s ″, 13d ″ of the peripheral gate electrode 7p and the second source / drain regions 13s ″, 13d ″) 15b) can be stacked. For example, the peripheral metal silicide layer 15b may be provided on the peripheral gate electrode 7p and the second source / drain regions 13s ″ and 13d ″. In addition, a cell metal silicide layer is formed on at least the first source / drain regions 13s 'and 13d' of the cell gate electrodes 7c and the first source / drain regions 13s 'and 13d'. 15a may be provided.

The substrate having the access MOS transistor and the peripheral circuit MOS transistor is covered with an interlayer insulating film 28. The interlayer insulating layer 28 may include a lower interlayer insulating layer 20 and an upper interlayer insulating layer 26 that are sequentially stacked. In addition, the lower interlayer insulating layer 20 may include a lower etch stop layer 17 and a lower insulating layer 19 that are sequentially stacked, and the upper interlayer insulating layer 26 may be sequentially stacked upper etch stop layer 23. And an upper insulating layer 25. The etch stop layers 17 and 23 may be insulating layers having an etch selectivity with respect to the insulating layers 19 and 25. For example, when the insulating layers 19 and 25 are silicon oxide layers, the etch stop layers 17 and 23 may be silicon nitride layers. The interlayer insulating film 28 may be formed of only the lower insulating film 19 and the upper insulating film 25.

The first source region 13s' is electrically connected to a first source contact plug 21s' penetrating the lower interlayer insulating layer 20, and the first drain regions 13d 'are connected to the lower interlayer insulating layer. Is electrically connected to the first drain contact plugs 21d ′ penetrating through 20. In addition, the second source region 13s ″ is electrically connected to a second source contact plug 21s ″ penetrating through the lower interlayer insulating layer 20, and the second drain region 13d ″ is connected to the lower interlayer. It is electrically connected to the second drain contact plug 21d ″ penetrating through the insulating film 20. The contact plugs 21s ', 21d', 21s ", 21d" may be tungsten plugs.

The first source contact plug 21s' is electrically connected to a common source line 27s' disposed in the upper interlayer insulating layer 26, and the first drain contact plugs 21d 'are connected to the upper interlayer insulating layer. And electrically connected to conductive drain pads 27d 'disposed in 26. In FIG. The common source line 27s ′ may be disposed to be parallel to the cell gate electrodes 7c. In addition, the second source contact plug 21s ″ may be electrically connected to a source pad 27s ″ disposed in the upper interlayer insulating layer 26, and the second drain contact plug 21d ″ may be connected to the upper portion of the upper interlayer insulating layer 26. It can be electrically connected to the drain pad 27d ″ disposed in the interlayer insulating film 26. The common source line 27s ', the drain pads 27d' and 27d ″, and the source pad 27s ″ may be a metal film such as a tungsten film.

The molding layer 29 is stacked on the common source line 27s ', the drain pads 27d' and 27d ″, the source pad 27s ″, and the interlayer insulating layer 28. The molding layer 29 has a surface step S so as to have protrusions 77 on the drain pads 27d '. The molding layer 29 is preferably an insulating layer having a higher thermal conductivity than the silicon oxide layer. In addition, the molding film 29 is preferably an insulating film that serves as an oxygen barrier film. For example, the molding layer 29 may be a nitride layer such as a silicon oxynitride layer or a silicon nitride layer. The drain pads 27d ′ are electrically connected to the lower electrodes 35 passing through the protrusions 77 of the molding layer 29. The lower electrodes 35 may be plugs formed of a titanium nitride layer. Sidewalls of the lower electrodes 35 may be surrounded by contact spacers 34a.

Each of the contact spacers 34a includes an inner contact spacer 33a surrounding a sidewall of the lower electrode 35 and an outer contact surrounding an outer sidewall of the inner contact spacer 33a. An outer contact spacer 31a. A lower portion of the outer contact spacer 31a may extend to contact the lower electrode 35. The outer contact spacer 31a may be a plasma CVD oxynitride film formed at a temperature lower than 500 ° C., and the inner contact spacer 33a may be a low pressure CVD nitride film formed at a temperature higher than 500 ° C.

Phase change resistors 44a are disposed on the protrusions 77 of the molding layer 29. The phase change resistors 44a may be self-aligned with the protrusions 77. Each of the phase change resistors 44a includes a phase change material film pattern 37a electrically connected to the lower electrode 35 and an upper electrode 39a stacked on the phase change material film pattern 37a. It may include. The phase change material layer pattern 37a may be a chalcogenide layer, such as an alloy layer of germanium (Ge), stevilium (Sb), and tellurium (Te). In addition, the phase change material layer pattern 37a may be a GST alloy layer doped with at least one of nitrogen and silicon. The upper electrodes 39a may be a conductive film such as a titanium nitride film.

Each of the phase change resistors 44a may further include a glue film pattern 41a and a hard mask pattern 43a that are sequentially stacked on the upper electrode 39a. The glue film patterns 41a correspond to a wetting layer for improving adhesion between the hard mask patterns 43a and the upper electrodes 39a. For example, when the hard mask patterns 43a and the upper electrodes 39a are silicon oxide films and titanium nitride films, the glue film patterns 41a may be silicon nitride films.

In other embodiments of the present invention, the drain pads 27d ′ may include phase change material layer patterns passing through the protrusions 77 of the molding layer 29, as shown in FIGS. 11 and 12. Direct contact with (37b). In this case, the phase change material pattern 37b, the upper electrode 39a, the glue film pattern 41a, and the hard mask pattern 43a constitute a confined phase change resistor 44b. do.

The substrate having at least the phase change resistors 44a or 44b is covered with an oxygen barrier film 48. As described above, when the molding layer 29 includes the protrusions 77, the oxygen barrier layer 48 may be formed together with the sidewalls and the upper surfaces of the phase change resistors 44a or 44b. Cover the side walls of the protrusions 77.

The oxygen barrier layer 48 may include the phase change material layer patterns 37a and the phases together with interfaces between the phase change material layer patterns 37a and the lower electrodes 35 during subsequent processes. It serves as an oxygen blocking layer to prevent oxygen atoms from penetrating the interfaces between the upper electrodes 39a. The oxygen barrier layer 48 may include a lower oxygen barrier layer 45, a stress buffer layer 46, and an upper oxygen barrier layer 47 that are sequentially stacked. The lower oxygen barrier layer 45 may include a nitride layer such as a silicon oxynitride layer or a silicon nitride layer, and the upper oxygen barrier layer 47 may include an insulating layer such as an oxide layer, a nitride layer, or a metal oxide layer. The oxide layer may be a silicon oxide layer, and the nitride layer may be a silicon oxynitride layer or a silicon nitride layer. The metal oxide layer may be an aluminum oxide layer (AlO), a titanium oxide layer (TiO), a zirconium oxide layer (ZrO), a hafnium oxide layer (HfO), or a lanthanum oxide layer (LaO). In addition, the stress buffer layer 46 may include a material layer for relieving stress applied to the lower oxygen barrier layer 45 due to the presence of the upper oxygen barrier layer 47. . For example, the stress buffer layer 46 may be a silicon oxide layer formed using a plasma CVD technique that proceeds at a temperature of about 200 ° C to 400 ° C.

The lower oxygen barrier layer 45 may have a thickness of 200 kPa to 1000 kPa, and the upper oxygen barrier film 47 may have a thickness of 10 kPa to 150 kPa. More specifically, the lower oxygen barrier film 45 may have a thickness of 300 kPa to 500 kPa, and the upper oxygen barrier film 47 may have a thickness of 50 kPa to 100 kPa.

In other embodiments of the present invention, the oxygen barrier layer 48 may include at least the lower oxygen barrier layer 45. In other words, the oxygen barrier layer 48 may be a single oxygen barrier layer or a multi-layered oxygen barrier layer. For example, the oxygen barrier layer 48 may be composed of only the lower oxygen barrier layer 45 or the stress buffer layer 46 and the upper oxygen barrier layer 47 in addition to the lower oxygen barrier layer 45. It may include at least one of.

In still other embodiments of the present invention, a lower portion having a spacer shape on sidewalls of the phase change resistors 44a or 44b and sidewalls of the protrusions 77 instead of the lower oxygen barrier layer 45. Oxygen barrier film patterns 45a may be provided (see FIGS. 10 and 12). In this case, the spacer-shaped lower oxygen barrier layer pattern 45a, the stress buffer layer 46 and the upper oxygen barrier layer 47 constitute an oxygen barrier layer 48a.

A lower interlayer insulating film 49 is provided on the oxygen barrier film 48 or 48a. The lower interlayer insulating layer 49 may have a flat upper surface such that the oxygen barrier layer 48 or 48a on the phase change resistors 44a or 44b is exposed. The upper electrodes 39a may be electrically connected to the contact plugs 51 passing through the exposed oxygen barrier layer 48, the hard mask patterns 41a, and the glue layer patterns 41a. In addition, the drain pad 21d ″ and the source pad 21s ″ respectively pass through the lower interlayer insulating layer 49, the oxygen barrier layer 48 or 48a, and the molding layer 29. It can be electrically connected to the plug 51d "and the source wiring contact plug 51s". The contact plugs 51, 51d ″, 51s ″ may be tungsten plugs.

The contact plugs 51 may be covered with bit line pads 53. In addition, the drain wiring contact plug 51d ″ may be covered by the drain wiring 53d ″, and the source wiring contact plug 51s ″ may be covered by the source wiring 53s ″. The bit line pads 53, the drain wiring 53d ″, and the source wiring 53s ″ may be formed of a lower metal film such as an aluminum film or an aluminum alloy film.

The substrate having the bit line pads 53, the drain wiring 53d ″, and the source wiring 53s ″ is covered with an upper interlayer insulating layer 55. The bit line 57 is disposed on the upper interlayer insulating layer 55. The bit line 57 is electrically connected to the bit line pads 53 through bit line contact holes 55a passing through the upper interlayer insulating layer 55. In addition, the bit line 57 is disposed to cross the upper portions of the cell gate electrodes 7c. The substrate having the bit line 57 is covered with a passivation film 62. The passivation layer 62 may include a silicon oxide layer 59 and a silicon nitride layer 61 that are sequentially stacked.

FIG. 13 is a schematic block diagram of a portable electronic device 600 employing phase change memory elements in accordance with embodiments of the present invention.

Referring to FIG. 13, the portable electronic device 600 includes at least one phase change memory device 602 serving as a data storage medium and a processor 604 connected to the phase change memory device 602. ). Here, the phase change memory device 602 may include the phase change memory cells described with reference to FIGS. 2 to 12 along with FIG. 1B. The portable electronic device 600 may correspond to a portable notebook computer, a digital video camera, or a cellular phone. In this case, the processor 604 and the phase change memory device 602 are installed on a board and used as a program memory for storing code and data for execution of the processor 604.

The portable electronic device 600 may exchange data with another electronic product such as a personal computer or a network of computers through the input / output device 606. The input / output device 606 may provide data to a peripheral bus line of a computer, a high speed digital transmission line, or a wireless transmission / reception antenna. The data communication between the processor 604 and the input / output device 606, as well as the data communication between the processor 604 and the phase change memory device 602, may employ conventional computer bus architectures. Can be made using.

Experimental Examples; examples>

Hereinafter, various measurement results of samples manufactured according to the prior art and the embodiments of the present invention will be described.

14 is a graph showing lower electrode contact resistance characteristics of phase change memory cells fabricated according to the related art and embodiments of the present invention. In FIG. 14, the horizontal axis represents split groups for the oxygen barrier film, and the vertical axis represents contact resistance Rc between the GST films and the lower electrodes.

Phase change memory cells showing the measurement results of FIG. 14 were fabricated using the process conditions described in Table 1 below.

  Process parameters Prior art                  The present invention  Sample A    Sample B    Sample C    Sample D      Molding film                 Silicon oxynitride film (SiON) Outer contact spacer          Silicon oxynitride film (SiON; plasma CVD) Internal contact spacer            Silicon Nitride (SiN; Low Pressure CVD)     Bottom electrode          Titanium nitride film (TiN), diameter: 50 nm)    Phase change material film            GST alloy film (GeSbTe alloy film)     Upper electrode             Titanium Nitride (TiN)   Oxygen barrier membrane   None SiON film (200 ℃, PECVD, 200Å) SiN film 200 ° C, PECVD, 200Å) Lower SiN Film (200 ℃, PECVD, 200Å) Upper SiN Film (400 ℃, PECVD, 200Å)

Referring to FIG. 14 and Table 1, phase change memory cells fabricated according to the prior art have a nonuniform lower electrode contact resistance Rc distributed within a range of about 1,000 (ohms / contact) to about 10,000 (ohms / contact). Seemed. In contrast, phase change memory cells fabricated in accordance with embodiments of the present invention exhibited a uniform bottom electrode contact resistance (Rc) distributed within a range of about 500 (ohms / contact) to about 1,200 (ohms / contact). . In particular, phase change memory cells fabricated in accordance with an embodiment of the present invention employing a double oxygen barrier film have a very stable lower electrode contact resistance within the range of about 500 (ohms / contact) to about 600 (ohms / contact). Rc).

FIG. 15 is a graph showing set / reset characteristics of phase change memory cells fabricated according to the prior art, and FIG. 16 is a set / reset characteristics of phase change memory cells fabricated according to an embodiment of the present invention. It is a graph showing. 15 and 16, the horizontal axes represent the number of program cycles (N) of the phase change memory cells, that is, the number of writing cycles, and the vertical axes represent the resistance of the phase change resistor per unit cell. (R _GST ). Here, the conventional phase change memory cells are manufactured using the same process conditions as those of Samples A of [Table 1], and the phase change memory cells according to the present invention are the same processes as Samples C of [Table 1]. Made using the conditions.

The respective program cycles are performed by sequentially applying a single reset pulse and one set pulse to the phase change resistors of the phase change memory cells. Each of the reset pulse and the set pulse was applied for 100 ms. In addition, the reset pulse was generated to have a write current of about 1.5 mA to convert the GST film of the phase change resistor into an amorphous state, and the set pulse was generated in the phase change resistor of the phase change resistor. It was produced to have a write current of about 0.6 mA to change the GST film into a crystalline state. In addition, the reset resistance (R _RESET ) of the phase change resistors was measured using a bit line voltage of 0.2 volt after applying the reset pulse, and the set resistance (R _SET ) of the phase change resistors measured the set pulse. After application it was measured using a bit line voltage of 0.2 volts.

As can be seen from Figs. 15 and 16, both of the conventional technology and the phase change memory cells according to the present invention have a uniform set resistance R _SET of about 1000 (ohms / cell) regardless of the number of the program cycles. Seemed. However, the conventional phase change memory cells exhibited a low reset resistance (R _RESET ) of about 6,000 (ohms / cell) to about 100,000 (ohms / cell) despite about 5,000 cycles of program operations. In contrast, phase change memory cells according to the present invention exhibited a high reset resistance (R _RESET ) of about 300,000 (ohms / cell) to about 3,000,000 (ohms / cell) after about 10 cycles of program operations. This can be understood that the interface characteristics of the phase change material film patterns of the phase change memory cells according to the present invention are superior to those of the phase change material film patterns of the conventional phase change memory cells. That is, the phase transition of the phase change material film patterns of the phase change memory cells according to the present invention is the phase change of the phase change material film patterns of the conventional phase change memory cells. It can be understood that the transition occurred efficiently compared to the phase transition (phase transition from the crystalline state to the amorphous state). The improvement of the interfacial properties of the phase change material film patterns increases the skip probability of the firing test performed before the main test for measuring the electrical properties of the phase change memory devices. Can be. As a result, according to the present invention, the read margin and test efficiency of semiconductor devices employing phase change memory cells can be significantly improved.

FIG. 17 is a graph illustrating set / reset resistance characteristics according to cell size of phase change memory cells fabricated according to the related art and the present invention. In FIG. 17, the horizontal axis represents diameter D of phase change material patterns, and the vertical axis represents resistance R of phase change resistors. In the graph of FIG. 17, the data denoted by reference numerals "NR" and "NS" represent the reset resistance and the set resistance of conventional phase change resistors manufactured without the oxygen barrier film, respectively, and the reference numerals "SR" and SS ". The data indicated by denote the reset resistance and the set resistance of the phase change resistors respectively covered by a single oxygen barrier film, and the data denoted by the reference numerals "DR" and "DS" respectively indicate the phase change covered by a double oxygen barrier film. The reset resistors and the set resistors of the resistors are shown.

  Process parameters  Prior art              The present invention    Single barrier membrane    Double barrier membrane      Molding film             Silicon oxynitride film (SiON)     Bottom electrode         Titanium Nitride Film (TiN), Diameter (50nm)   Phase change material film            GST alloy film (GeSbTe alloy film)     Upper electrode            Titanium Nitride (TiN)   Oxygen barrier membrane    None SiN film, 500Å, PECVD Lower barrier film (SiN film, 500 ,, PECVD) Upper barrier film (AlO film, 50Å, ALD)

Referring to FIG. 17 and Table 2, the difference between the set resistance and the reset resistance of the conventional phase change resistors gradually decreased with decreasing diameter D of the phase change material pattern. For example, when the diameter D of the phase change material patterns is reduced from 0.68 μm to 0.4 μm, the reset / set resistance ratio of the conventional phase change resistors is from about 1.6 × 10 ² to about It drastically decreased to 0.5 × 10. In addition, the conventional phase change resistor having a phase change material pattern having a diameter of 0.4 μm exhibited non-uniform set resistance of about 6 × 10 ⁴ kPa to about 7 × 10 ⁵ kPa.

On the other hand, the reset / set resistance ratio of the phase change resistors covered with the single oxygen barrier film is from about 1.6 × 10 ² to about 1 × 10 ² when the diameter (D) of the phase change material patterns is reduced from 0.68 μm to 0.4 μm. Decreased. Furthermore, the reset / set resistance ratio of the phase change resistors covered with the double oxygen barrier film is from about 2.5 × 10 ² to about 1.3 × 10 ² when the diameter (D) of the phase change material patterns is reduced from 0.68 μm to 0.4 μm. Decreased. In particular, phase change resistors having a phase change material pattern having a diameter of 0.4 μm and covered with a single oxygen barrier film or a double oxygen barrier film may be applied to a conventional phase change resistor having a phase change material pattern having a diameter of 0.4 μm. More uniform set resistance was shown.

As described above, according to the present invention, by forming an oxygen barrier layer covering the phase change resistors, the contact resistance characteristics of the lower electrodes and the set / reset resistance characteristics of the phase change resistors can be significantly improved. In particular, in the case where the phase change resistors are covered with the oxygen barrier film, even if the diameter of the phase change resistors (diameter of the phase change material patterns) is reduced, a sudden decrease in the reset / set resistance ratio of the phase change resistors can be prevented. have. As a result, it is possible to significantly improve the test efficiency as well as the integration and performance of the semiconductor devices employing the phase change memory cells according to the present invention.

Claims (83)

A molding film disposed on the semiconductor substrate, the molding film having a protrusion extending in a vertical direction from an upper surface thereof; A phase change material pattern in contact with the protrusion; And And a lower electrode electrically connected to the phase change material pattern. The method of claim 1, And the phase change material pattern is disposed on the protrusion. The method of claim 2, And the phase change material pattern is self-aligned with the protrusion. The method of claim 3, wherein And the phase change material pattern extends to penetrate the protrusion to have a localized shape. The method of claim 1, And an oxygen barrier layer covering at least a portion of the sidewalls of the phase change material pattern and at least a portion of the sidewalls of the protrusions. The method of claim 1, And a top electrode electrically connected to the phase change material pattern. The method of claim 6, And an oxygen barrier layer covering the phase change material pattern and the upper electrode. The method of claim 1, The phase change material pattern includes a chalcogenide material layer. The method of claim 8, And the chalcogenide material layer comprises a GeSbTe (GST) alloy layer. The method of claim 9, And the GST alloy film is doped with at least one of silicon and nitrogen. The method of claim 1, And the protrusion has a thickness of 100 kPa to 600 kPa. delete A molding film disposed on the semiconductor substrate, the molding film having a protrusion extending in a vertical direction from an upper surface thereof; A phase change material pattern disposed on the protrusions; An oxygen barrier layer covering an area where the sidewalls of the phase change material pattern and the sidewalls of the protrusion contact each other; And And a lower electrode electrically connected to the phase change material pattern, wherein the lower electrode extends through the protrusion. The method of claim 13, And the phase change material pattern extends to penetrate the protrusion to have a localized shape. The method of claim 13, And an upper electrode disposed on the phase change material pattern. The method of claim 15, And a hard mask on the upper electrode. The method of claim 16, And the oxygen barrier layer covers the upper electrode and the phase change material pattern. The method of claim 17, The oxygen barrier layer may include a first portion disposed on an upper surface of the upper electrode and a second portion covering sidewalls of the phase change material pattern, wherein the first portion is thicker than the second portion. Memory element. delete The method of claim 13, The oxygen barrier layer includes a lower oxygen barrier layer and an upper oxygen barrier layer. The method of claim 20, The lower oxygen barrier film is a material film formed using a plasma CVD process or an atomic layer deposition (ALD) process at a temperature of 200 ℃ to 350 ℃, the upper oxygen barrier film is a plasma CVD process or a low pressure at a temperature of 350 ℃ to 800 ℃ A semiconductor memory device, characterized in that it is a material film formed using a CVD process. The method of claim 21, And the lower oxygen barrier film includes a nitride film, and the upper oxygen barrier film includes a nitride film or a metal oxide film. The method of claim 22, The nitride film includes a silicon nitride film or a silicon oxynitride film, and the metal oxide film includes an aluminum oxide film, a titanium oxide film, a zirconium oxide film, a hafnium oxide film, or a lanthanum oxide film. The method of claim 20, And the lower oxygen barrier layer has a spacer shape covering sidewalls of the protrusion and sidewalls of the phase change material pattern. The method of claim 20, And a stress buffer layer between the lower oxygen barrier layer and the upper oxygen barrier layer. The method of claim 25, And said stress buffer film is a silicon oxide film. The method of claim 13, And the oxygen barrier film comprises a single nitride film. The method of claim 27, The oxygen barrier film is a silicon nitride film or a silicon oxynitride film formed using a plasma CVD process or an atomic layer deposition (ALD) process at a temperature of 200 ℃ to 350 ℃. The method of claim 13, And a sidewall of the phase change material pattern is self-aligned with the sidewall of the protrusion. The method of claim 13, The phase change material pattern is a semiconductor memory device, characterized in that the chalcogenide material film. The method of claim 13, A switching transistor formed on the semiconductor substrate; An interlayer insulating film disposed on the switching transistor; And And a conductive pad penetrating the interlayer insulating film and electrically connected to the switching transistor and the lower electrode, wherein the protrusion of the molding film is positioned above the conductive pad. The method of claim 31, wherein And the switching transistor comprises a gate electrode, a source region and a drain region, wherein the conductive pad is electrically connected to the drain region. The method of claim 32, And a common source line disposed in the interlayer insulating film, wherein the common source line is electrically connected to the source region. The method of claim 32, And a silicide layer formed on the source / drain regions and / or the gate electrode. The method of claim 13, And the molding film has a higher thermal conductivity than a silicon oxide film. 36. The method of claim 35 wherein And the molding film is a silicon oxynitride film or a silicon nitride film. The method of claim 13, And a contact spacer surrounding the sidewalls of the lower electrode. The method of claim 37, And the contact spacer includes an inner contact spacer and an outer contact spacer, wherein the outer contact spacer surrounds the inner contact spacer. A semiconductor substrate having a memory cell region and a peripheral circuit region; A first source formed in the semiconductor substrate in the memory cell region, the first source / drain regions, a first gate electrode having a first width, and a first gate insulating layer between the first gate electrode and the substrate transistor; A molding film formed on a substrate having the first transistor, the protrusion having a protrusion extending in a vertical direction from an upper surface thereof, wherein the protrusion is located in the memory cell region; A phase change material pattern in contact with the protrusion; A lower electrode electrically connected to the phase change material pattern; An upper electrode electrically connected to the phase change material pattern; An oxygen barrier layer covering sidewalls of the phase change material pattern and sidewalls of the protrusions; And A second transistor formed on the semiconductor substrate in the peripheral circuit region, wherein the second transistor includes second source / drain regions, a second gate electrode having a second width, and between the second gate electrode and the substrate; And a second gate insulating film, wherein said second width is different from said first width. The method of claim 39, And the second width is larger than the first width. The method of claim 39, And the sidewalls of the protrusions are self-aligned with the sidewalls of the phase change material pattern. 42. The method of claim 41 wherein And the phase change material pattern extends to penetrate the protrusion to have a localized shape. The method of claim 39, And the second gate insulating film is thicker than the first gate insulating film. The method of claim 39, The phase change material pattern includes a chalcogenide material layer. The method of claim 39, The oxygen barrier layer includes a lower oxygen barrier layer and an upper oxygen barrier layer. The method of claim 45, And the lower oxygen barrier film includes a nitride film, and the upper oxygen barrier film includes a nitride film or a metal oxide film. The method of claim 46, The nitride film includes a silicon nitride film or a silicon oxynitride film, and the metal oxide film includes an aluminum oxide film, a titanium oxide film, a zirconium oxide film, a hafnium oxide film, or a lanthanum oxide film. The method of claim 45, And the lower oxygen barrier layer has a spacer shape covering sidewalls of the protrusion and sidewalls of the phase change material pattern. The method of claim 45, And a stress buffer layer between the lower oxygen barrier layer and the upper oxygen barrier layer. The method of claim 49, And said stress buffer film is a silicon oxide film. The method of claim 39, And the oxygen barrier film comprises a single nitride film. The method of claim 51, wherein The oxygen barrier film is a silicon nitride film or a silicon oxynitride film formed using a plasma CVD process or an atomic layer deposition (ALD) process at a temperature of 200 ℃ to 350 ℃. The method of claim 39, The oxygen barrier layer may include a first portion disposed on an upper surface of the upper electrode and a second portion covering sidewalls of the phase change material pattern, wherein the first portion is thicker than the second portion. Memory element. The method of claim 39, And silicide films formed on the first and second source / drain regions and / or the first and second gate electrodes. In an electronic system having a processor, an input / output device for performing data communication with the processor, and a phase change memory device for performing data communication with the processor, A molding film formed on the integrated circuit substrate, the molding film having a protrusion extending in a vertical direction from an upper surface thereof; A phase change material pattern in contact with the protrusion; And And a lower electrode electrically connected to the phase change material pattern. The method of claim 55, And the phase change material pattern extends through the protrusion to have a localized shape. The method of claim 55, And an oxygen barrier layer covering an area where the sidewalls of the phase change material pattern and the sidewalls of the protrusion contact each other. The method of claim 57, The oxygen barrier film includes an lower oxygen barrier film and an upper oxygen barrier film. The method of claim 58, And the lower oxygen barrier layer includes a nitride layer, and the upper oxygen barrier layer includes a nitride layer or a metal oxide layer. The method of claim 59, The nitride film includes a silicon nitride film or a silicon oxynitride film, and the metal oxide film includes an aluminum oxide film, a titanium oxide film, a zirconium oxide film, a hafnium oxide film, or a lanthanum oxide film. The method of claim 58, And the lower oxygen barrier layer has a spacer shape covering sidewalls of the protrusion and sidewalls of the phase change material pattern. The method of claim 58, And a stress buffer layer between the lower oxygen barrier layer and the upper oxygen barrier layer. 63. The method of claim 62, The stress buffer film is an electronic system, characterized in that the silicon oxide film. The method of claim 57, And the oxygen barrier film comprises a single nitride film. The method of claim 64, wherein The oxygen barrier film is a silicon nitride film or silicon oxynitride film formed using a plasma CVD process or an atomic layer deposition (ALD) process at a temperature of 200 ℃ to 350 ℃. The method of claim 55, The phase change material pattern is an electronic system, characterized in that the chalcogenide material film. The method of claim 66, wherein And the chalcogenide material film is a GST (GeSbTe) alloy film. Preparing a semiconductor substrate, Forming a molding film on the semiconductor substrate, Forming a lower electrode in the molding layer, Forming a phase change material film in contact with the lower electrode, Patterning the phase change material film and etching the upper part of the molding film to form a protrusion extending in a vertical direction from an upper surface of the etched molding film and a phase change material pattern in contact with the protrusion, And forming an oxygen barrier film covering the phase change material pattern. The method of claim 68, wherein And the oxygen barrier film is formed of a single nitride film. The method of claim 69, The single nitride film is a silicon nitride film or a silicon oxynitride film formed at a temperature of 200 ℃ to 350 ℃ manufacturing method of a semiconductor memory device. The method of claim 70, And the single nitride film is formed using a plasma CVD process or an atomic layer deposition process. The method of claim 70, And condensing the single nitride film using a heat treatment technique or a plasma treatment technique. 69. The method of claim 68, wherein forming the oxygen barrier film Forming a lower oxygen barrier layer on the substrate having the phase change material pattern; And forming an upper oxygen barrier film on the lower oxygen barrier film. The method of claim 73, wherein The lower oxygen barrier film is a silicon nitride film or a silicon oxynitride film formed at a temperature of 200 ℃ to 350 ℃ manufacturing method of a semiconductor memory device. The method of claim 74, wherein And condensing the lower oxygen barrier layer using a heat treatment technique or a plasma treatment technique. The method of claim 73, wherein And anisotropically etching the lower oxygen barrier layer to form a lower oxygen barrier layer pattern in a spacer shape covering sidewalls of the phase change material pattern and sidewalls of the molding layer. 77. The method of claim 76, And condensing the spacer-shaped lower oxygen barrier layer pattern using a heat treatment technique or a plasma treatment technique. 77. The method of claim 76, And forming a stress buffer film on the substrate having the spacer-shaped lower oxygen barrier film pattern. The method of claim 78, And the stress buffer film is formed of a silicon oxide film. The method of claim 73, wherein And forming a stress buffer film on the substrate having the lower oxygen barrier film. 81. The method of claim 80, And the stress buffer film is formed of a silicon oxide film. The method of claim 73, wherein And the upper oxygen barrier film is formed of a nitride film or a metal oxide film. 83. The method of claim 82, And the nitride film is formed of a silicon nitride film or a silicon oxynitride film, and the metal oxide film is formed of an aluminum oxide film, a titanium oxide film, a zirconium oxide film, a hafnium oxide film, or a lanthanum oxide film.

Images