WO2011007898A1

WO2011007898A1 - Semiconductor device and data transfer method in semiconductor device

Info

Publication number: WO2011007898A1
Application number: PCT/JP2010/062389
Authority: WO
Inventors: 斎藤英彰
Original assignee: 日本電気株式会社
Priority date: 2009-07-17
Filing date: 2010-07-15
Publication date: 2011-01-20
Also published as: JPWO2011007898A1; JP5365693B2

Abstract

In order to suppress the interference between data when the data are transferred between a logic circuit region and a memory circuit region of a semiconductor device such as an SoC chip, specifically disclosed is a semiconductor device comprising a logic circuit region provided with a plurality of logic macros, a first data transfer unit, and a first input/output unit, and a memory circuit region provided with a plurality of memory macros, a second data transfer unit, and a second input/output unit, wherein the first data transfer unit is connected to the plurality of logic macros, the second data transfer unit is connected to the plurality of memory macros, the first data transfer unit transfers first data groups generated in the respective logic macros to the second data transfer unit in different time zones for the respective first data groups via the first input/output unit and the second input/output unit, and the second data transfer unit transfers second data groups stored in the respective memory macros to the first data transfer unit in different time zones for the respective second data groups via the second input/output unit and the first input/output unit.

Description

Semiconductor device and data transfer method in semiconductor device

The present invention relates to a semiconductor device and a data transfer method in the semiconductor device, and more particularly to a semiconductor device having a logic circuit region having a plurality of logic macros and a memory circuit region having a plurality of memory macros, and a data transfer method in the semiconductor device. .

Since information terminal devices such as mobile phones are becoming increasingly multifunctional, such as voice processing functions and image processing functions, it is necessary to mount a large number of logic macros on semiconductor chips used in information terminal devices. In recent years, with the miniaturization of semiconductor processes, it has become possible to integrate many logic macros on a chip, and the number of logic macros is large, exceeding 10. Such a semiconductor chip in which multiple functions are integrated on one chip is called a system on chip (hereinafter referred to as SoC), and an example thereof is described in Patent Document 1.
Many of the logic macros are composed of CMOS (Complementary Metal Oxide Semiconductor) logic circuits. Each logic macro requires a memory for temporarily storing programs and data. Therefore, it is desirable that a memory such as an SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), or an MRAM (Magnetic Resistive Random Access Memory) be arranged near the logic macro.
FIG. 21 shows an example of the configuration of the logic macro and on-chip memory in the SoC chip. In the related SoC chip 800 shown in FIG. 21, an on-chip memory is arranged for each logic macro. The logic macro 810A accesses the memory macro 810a, the logic macro 820B accesses the memory macro 820b, the logic macro 830C accesses the memory macro 830c, and the logic macro 840D accesses the memory macro 840d. The logic macro and the memory macro are connected via an input / output port (I / O port) 850 arranged in the logic macro and the memory macro, respectively, and access to the memory is performed. Further, since it is necessary to exchange data between the logic macros in order to operate in the entire system, the logic macros are also connected by wiring.
Here, when one logic macro in the SoC chip and a corresponding memory macro are connected, the total number of necessary connection wirings increases as the number of logic macros increases. For example, assuming that the memory bit width is 32 bits and the number of words is 1000 words, a total of 76 lines, 32 lines for read data, 32 lines for write data, 10 lines for addresses, and 2 lines for commands Connection wiring is required. When the number of logic macros in the SoC chip is 10, the total number of connection wirings required to connect each logic macro and the corresponding memory macro is 760.
Japanese Patent Laid-Open No. 10-134,022 (paragraphs “0028” to “0034”)

The region where the logic circuit is formed and the region where the memory circuit is formed are desirably arranged separately for the following reason. That is, since an analog circuit configuration is required for the memory, optimized transistors and memory elements are used separately from the logic circuit, and different steps are included in the manufacturing process. Further, the reason is that a different power supply voltage is used for optimizing each circuit performance, and that the memory circuit is less resistant to noise than a digital logic circuit.
In order to arrange the logic circuit area and the memory circuit area separately, for example, a method in which the logic circuit area and the memory circuit area are separately formed on the same semiconductor chip, or the logic circuit and the memory circuit are separated and separated. A method of forming each on the semiconductor chip is conceivable. When the memory circuit is formed on another semiconductor chip, specifically, the semiconductor chip on which the memory circuit is mounted and the semiconductor chip on which the logic circuit is mounted are arranged side by side, and are connected by wiring through the board substrate. There is a method of performing signal transmission on the Internet. There is also a method of stacking semiconductor chips mounted with memory circuits and semiconductor chips mounted with logic circuits vertically, flip-chip stacking so that the surfaces of the respective semiconductor chips face each other, and bump-connecting the semiconductor chips.
However, when the logic circuit area and the memory circuit area are formed separately in the SoC chip, wiring between the logic macro and the memory macro intersects between the logic circuit area and the memory circuit area by the number of logic macros. Become. This complicates the wiring layout and increases the number of layout steps. In addition, in order to avoid an increase in the wiring density, the bypassed wiring is frequently used, and the data transfer speed is lowered. Therefore, it is desirable to reduce the number of wires for data transfer between each logic macro and the memory macro. However, if the number of wirings is reduced, the number of wirings is insufficient to individually connect a large number of logic macros and their memory macro signals. Therefore, there is a problem that a plurality of data transferred from a plurality of logic macros interfere with each other on the wiring between the areas.
In addition, when the logic circuit and memory circuit are mounted on separate semiconductor chips, the wiring within the semiconductor chip is about a sub-micron size compared to several tens to several hundreds of microns, a size that is two orders of magnitude larger The board wiring of the board must be used. Further, since the pad shape of the semiconductor chip is as large as one hundred microns or more, the number of pads on the semiconductor chip for connecting the connection wiring between the semiconductor chips is limited to about several hundred. Therefore, in this case as well, the number of wires is insufficient to connect a large number of logic macros and corresponding memory macros. Therefore, even in this case, there is a problem that a plurality of data transferred from a plurality of logic macros interfere with each other on the wiring between the semiconductor chips.
The object of the present invention is to separate the logic circuit area and the memory circuit area in the semiconductor device such as the SoC chip, which is the problem described above, and the data transferred between the two areas interferes with each other on the wiring between the two areas. To provide a semiconductor device and a data transfer method in the semiconductor device.

A semiconductor device according to the present invention includes a logic circuit region including a plurality of logic macros, a first data transfer unit, and a first input / output unit, a plurality of memory macros, a second data transfer unit, and a second input / output unit. A first data transfer unit connected to a plurality of logic macros, a second data transfer unit connected to a plurality of memory macros, and a first input / output unit The second input / output units are connected to each other, and the first data transfer unit receives the first data group generated in each logic macro via the first input / output unit and the second input / output unit. The data is transferred to the second data transfer unit in a different time zone for each data group, and the second data transfer unit is connected to each memory macro via the second input / output unit and the first input / output unit. The accumulated second data group is transferred to the first data transfer unit in a different time zone for each second data group. To.
In the data transfer method in the semiconductor device of the present invention, data generated in each of a plurality of logic macros constituting the semiconductor device is formed as a first data group for each logic macro, and the first data group is defined as the first data group. In a time zone provided for each data group, the data is transferred to the memory macro constituting the semiconductor device corresponding to the logic macro, and the data stored in each of the plurality of memory macros constituting the semiconductor device is transferred to the second memory macro for each memory macro. The data group is formed as a data group, and the second data group is transferred to a logic macro constituting a semiconductor device corresponding to the memory macro in a different time zone for each second data group.

According to the semiconductor device of the present invention, it is possible to suppress interference between data when data is transferred between the logic circuit area and the memory circuit area constituting the semiconductor device.

FIG. 1 is a plan view showing the configuration of the semiconductor device according to the first embodiment of the present invention.
FIG. 2 is a circuit configuration diagram in the logic circuit region of the semiconductor device according to the first embodiment of the present invention.
FIG. 3 is a circuit configuration diagram in the memory circuit region of the semiconductor device according to the first embodiment of the present invention.
FIG. 4 is another circuit configuration diagram in the logic circuit region of the semiconductor device according to the first embodiment of the present invention.
FIG. 5 is a plan view showing a configuration of another semiconductor device according to the first embodiment of the present invention.
FIG. 6 is a circuit configuration diagram in the logic circuit region of another semiconductor device according to the first embodiment of the present invention.
FIG. 7 is a circuit configuration diagram in the memory circuit area of another semiconductor device according to the first embodiment of the present invention.
FIG. 8 is a plan view showing a configuration of a semiconductor device according to the second embodiment of the present invention.
FIG. 9 is a circuit configuration diagram in a logic circuit region of a semiconductor device for explaining a data transfer method in the semiconductor device according to the third embodiment of the present invention.
FIG. 10 is a circuit configuration diagram in the memory circuit region of the semiconductor device for explaining a data transfer method in the semiconductor device according to the third embodiment of the present invention.
FIG. 11 is a waveform diagram for explaining the data transfer method in the semiconductor device according to the third embodiment of the present invention.
FIG. 12 is a plan view showing a configuration of a semiconductor device for explaining a data transfer method in the semiconductor device according to the third embodiment of the present invention.
FIG. 13 is a plan view showing a configuration of a semiconductor device according to the fourth embodiment of the present invention.
FIG. 14 is a circuit configuration diagram of the sequence control unit in the logic circuit region of the semiconductor device according to the fourth embodiment of the present invention and a table showing its operation.
FIG. 15 is a circuit configuration diagram of the sequence control unit in the memory circuit region of the semiconductor device according to the fourth embodiment of the present invention and a table showing its operation.
FIG. 16 is a plan view showing a configuration of a semiconductor device according to the fifth embodiment of the present invention.
FIG. 17 is a circuit configuration diagram of the input / output control unit in the logic circuit region of the semiconductor device according to the fifth embodiment of the present invention and a table showing its operation.
FIG. 18 is a circuit diagram of the input / output control unit in the memory circuit region of the semiconductor device according to the fifth embodiment of the present invention and a table showing its operation.
19A is a schematic perspective view for explaining a semiconductor device according to a sixth embodiment of the present invention, FIG. 19B is a plan view showing the configuration of a memory circuit board, and FIG. 19C is a diagram of a logic circuit board. It is a top view which shows a structure.
FIG. 20 is a plan view showing another memory macro configuration of the semiconductor device of the present invention.
FIG. 21 is a plan view showing a configuration of a related SoC chip.

Embodiments of the present invention will be described below with reference to the drawings.
[First Embodiment]
FIG. 1 is a plan view showing a configuration of a semiconductor device 100 according to the first embodiment of the present invention. The semiconductor device 100 includes a logic circuit area 110 including a plurality of logic macros 111, a first data transfer unit 112, and a first input / output unit 113, a plurality of memory macros 121 corresponding to the logic macro 111, and a second The memory circuit area 120 includes a data transfer unit 122 and a second input / output unit 123. The first data transfer unit 112 is connected to a plurality of logic macros 111, and the second data transfer unit 122 is connected to a plurality of memory macros 121. The first input / output unit 113 and the second input / output unit 123 are connected to each other by an inter-region connection wiring 130.
The first data transfer unit 112 transmits the first data group generated in each logic macro 111 via the first input / output unit 113 and the second input / output unit 123 for different times for each first data group. The data is transferred to the second data transfer unit 122. Similarly, the second data transfer unit 122 converts the second data group stored in each memory macro 121 to the second data group via the second input / output unit 123 and the first input / output unit 113. The data is transferred to the first data transfer unit 112 at a different time zone every time.
According to the semiconductor device 100 according to the present embodiment, the write data as the first data group is directed from the first input / output unit 113 in the logic circuit region 110 toward the second input / output unit 123 in the memory circuit region 120. The writing data is transferred in a sequential manner at different times in different time zones. Therefore, a plurality of data can be prevented from interfering on the inter-region connection wiring 130 between the logic circuit region 110 and the memory circuit region 120. Similarly, the read data from the memory macro as the second data group is transferred in sequential order while shifting the time in different time zones for each read data. Therefore, even in this case, it is possible to prevent a plurality of data from interfering on the inter-region connection wiring 130.
Here, the first data transfer unit 112 can include a first ring bus 114 to which each logic macro 111 and a first I / O port 115 as the first input / output unit 113 are connected. Further, the second data transfer unit 122 can include a second ring bus 124 to which each memory macro 121 and a second I / O port 125 as the second input / output unit 123 are connected.
When transferring write data from the logic macro 111 to the memory macro 121, the first ring bus 114 transfers the write data from each logic macro 111 to the first I / O port 115 in order. Write data is transferred from the first I / O port 115 in the logic circuit area 110 to the second I / O port 125 in the memory circuit area 120 by the inter-area connection wiring 130. In the memory circuit area 120, write data is transferred in order from the second I / O port 125 to the corresponding memory macro 121 that is the destination of data by the second ring bus 124.
Similarly, when the read data is transferred from the memory macro 121 to the logic macro 111, the second ring bus 124 transfers the read data to the second I / O port 125 in order in the memory circuit area 120. The read data is transferred from the second I / O port 125 to the first I / O port 115 in the logic circuit area 110 by the inter-area connection wiring 130. In the logic circuit area 110, the read data is transferred in order from the first I / O port 115 to the corresponding logic macro 111 as the destination by the first ring bus 114.
Next, the semiconductor device according to the present embodiment will be described in more detail with reference to FIGS.
FIG. 2 is a circuit configuration diagram in the logic circuit region 110 of the semiconductor device 100 according to the present embodiment. The input side of each logic macro 111 is directly connected to the first ring bus 114, and the output side of each logic macro 111 is connected to the first ring bus 114 via the multiplexer 116 and the register 117. The multiplexer 116 receives data from the connected logic macro 111 and output data from the register 117 of the preceding logic circuit block, and selects one of them. Here, the data input from the logic macro to the multiplexer includes, for example, 32 bits of write data transmitted from each logic macro 111 to the

memory macro

121, and 2 bits for the address of the destination memory macro 121 are added thereto. The total data can be 34 bits wide.
When transmitting write data of each logic macro 111 from the logic circuit area 110 to the memory circuit area 120, the multiplexer 116 connected to each logic macro 111 selects the write data from the logic macro 111 at the timing of the first clock, The register 117 holds the data. Thereafter, the multiplexer 116 switches the input to select the data from the register 117 in the previous stage, and the data held in each register 117 at the timing of the next clock is adjacent to the first ring bus 114. 117. In this way, the data is forwarded on the first ring bus 114 in synchronization with the clock and sent to the first I / O port 115. Data is transmitted from the first I / O port 115 to the inter-region connection wiring 130 connected to the memory circuit region 120.
FIG. 3 is a circuit configuration diagram in the memory circuit region 120 of the semiconductor device 100 according to the present embodiment. The input side of each memory macro 121 is directly connected to the second ring bus 124, and the output side of each memory macro 121 is connected to the second ring bus 124 via the multiplexer 126 and the register 127. Write data transmitted from the logic circuit area 110 is received by the second I / O port 125 and held in the register 127 to which the second I / O port 125 is connected. Then, the data is transferred to the register 127 adjacent to the forward transfer by the second ring bus 124. The memory macro 121 connected to each register 127 looks at the address bit designating the memory macro that is the destination of the write data held in each register 127, and if it is addressed to itself, the write data is stored in the memory macro. take in.
As described above, in the semiconductor device 100 according to the present embodiment, the write data generated in each logic macro 111 is transferred sequentially through the register 117 connected to the first ring bus 114. Therefore, the order in which each write data is transferred on the inter-region connection wiring 130 is determined in advance. As a result, the write data of each logic macro is transferred from the first I / O port 115 in the logic circuit area to the second I / O port 125 in the memory circuit area with a time shift, so that a plurality of data are stored in the area. Interference on the inter-connection wiring 130 can be suppressed.
When the read data is transferred from the memory macro 121, the read data is transferred to the second I / O port 125 through the second ring bus 124 in the memory circuit area 120. Thereafter, the data is transferred to the first I / O port 115 in the logic circuit area 110, and in the logic circuit area 110, the data is transferred to the logic macro 111 that receives the read data through the first ring bus 114. Accordingly, even in this case, the read data of each memory macro is transferred from the second I / O port 125 in the memory circuit area to the first I / O port 115 in the logic circuit area at different times. Can be prevented from interfering on the inter-region connection wiring 130.
In the present embodiment, all the logic macros 111 in the logic circuit area 110 simultaneously transmit write data to the first ring bus 114, set the write data from each logic macro 111 in each register 117, and then the first The data is sequentially transferred by the ring bus 114. Therefore, each logical macro 111 does not transmit the next write data until all the write data is transferred from the first I / O port 115 to the memory circuit area 120. Therefore, when there is a logic macro that does not transmit write data at a certain clock time, there is a register to which invalid data that is not write data is input, and invalid data is transferred. Therefore, together with the write data, an identification signal for identifying whether the data is valid or invalid is sent together. When the identification signal indicates invalidity, the subsequent logic macro transmits new write data, and the first data New write data may be transferred by the ring bus 114. Thereby, the data transfer efficiency in inter-region connection wiring can be improved.
In the present embodiment, the ring bus in each area is used to transfer two types of data: write data and read data. However, the present invention is not limited to this, as shown in FIG. A double ring bus structure including a data ring bus 114-1 and a read data ring bus 114-2 may be employed.
In the present embodiment, the first I / O port 115 as the first input / output unit 113 is connected to the first ring bus 114 which is the first data transfer unit 112, and the second input / output unit 123 is used as the second input / output unit 123. The second I / O port 125 is connected to the second ring bus 124 which is the second data transfer unit 122. However, the present invention is not limited to this, and as shown in FIG. 5, the first I / O port 115 as the first input / output unit 113 is connected to one of the logic macros 111, and The second I / O port 125 may be connected to any one of the memory macros 121.
FIG. 6 shows an example of a circuit configuration diagram of the logic circuit region 110 in this case. Write data from the logic macro 111 is transferred to the logic macro 111A connected to the first I / O port 115 through the first ring bus 114. The data is transferred to the first I / O port 115 via the logic macro 111 A and transmitted to the memory circuit area 120. FIG. 7 shows an example of a circuit configuration diagram of the memory circuit region 120. After the write data is received at the second I / O port 125 in the memory circuit area 120, it is transferred to the memory macro 121D connected to the second I / O port 125. Thereafter, data is transferred from the memory macro 121D to the second ring bus 124, and data is transferred in order by the second ring bus 124. The memory macro 121 which is the address destination receives the write data from the second ring bus 124.
As described above, also in the embodiments shown in FIGS. 5 to 7, the write data generated in each logic macro 111 is transferred sequentially through the register 117 connected to the first ring bus 114. Therefore, the order in which each write data is transferred on the inter-region connection wiring 130 is determined in advance. As a result, the write data of each logic macro is transferred from the first I / O port 115 in the logic circuit area to the second I / O port 125 in the memory circuit area with a time shift, so that a plurality of data are stored in the area. Interference on the inter-connection wiring 130 can be suppressed. Similarly, when data read from the memory macro 121 is transferred to the first I / O port 115 of the logic circuit area 110, data interference can be similarly suppressed.
[Second Embodiment]
Next, a second embodiment of the present invention will be described. FIG. 8 is a plan view showing a configuration of a semiconductor device 200 according to the second embodiment of the present invention. The semiconductor device 200 includes a transfer start signal wiring 240 that connects each logic macro 211 and the corresponding memory macro 221 for each pair. Other configurations are the same as those of the semiconductor device 100 according to the first embodiment. A transfer start signal is transmitted from the logic macro 211 to the memory macro 221 using the transfer start signal wiring 240. Since the transfer start signal is used only for informing the start of data transfer between the logic macro 211 and the memory macro 221, a connection wiring having a 1-bit width is sufficient.
The memory macro that has received the transfer start signal transfers a clock cycle for transferring data from the logic macro as the transmission source to the first I / O port 215 and from the second I / O port 225 to its own memory macro. Count the number and receive data when the number of clock cycles is reached. Here, the number of clock cycles required for data transfer is determined by the number of registers that sequentially transmit the first ring bus 214 and the second ring bus 224. Accordingly, the number of clock cycles for data transfer is determined by the number of logic macros 211, the number of memory macros 221, and the arrangement positions of the first I / O port 215 and the second I / O port 225. Become. As described above, by setting the information of the number of clock cycles in the counter of each memory macro 221 in advance, the memory macro 211 selects data addressed to itself from the data flowing through the second ring bus 224. Can be captured.
In the semiconductor device 100 according to the first embodiment, for example, 2 bits are added as an address of a memory macro of a transmission destination to 32 bits of write data, for example, and transferred as a 34 bit signal from the logic macro to the memory macro. Yes. On the other hand, according to the semiconductor device 200 of the present embodiment, the process of transferring the address information of the memory macro that is the destination, collating the address information, and discarding the data becomes unnecessary. The effect that the control in the memory macro 221 becomes easy is obtained.
Similarly, even when the logic macro 211 receives read data transferred from the memory macro 221, a transfer start signal is transmitted from the memory macro 221 to the logic macro 211 via the transfer start signal wiring 240. The logic macro 211 can measure the number of clock cycles required for data transfer with a counter and select and fetch data addressed to itself from data flowing through the first ring bus 214.
[Third Embodiment]
Next, a third embodiment of the present invention will be described. In the data transfer method in the semiconductor device according to the present embodiment, first, data generated in each of a plurality of logic macros constituting the semiconductor device is formed as a first data group for each logic macro. Further, the data stored in each of the plurality of memory macros constituting the semiconductor device is formed as a second data group for each memory macro. Then, the first data group is transferred to a memory macro corresponding to the logic macro in a different time zone for each first data group, and the second data group is transferred to a different time zone for each second data group. And transfer to a logic macro corresponding to the memory macro.
The first data group is connected to the first data transfer unit connected to the logic macro, the first input / output unit connected to the first data transfer unit, and the first input / output unit. The data is transferred to the corresponding memory macro via the second input / output unit. The second data group is connected to a second data transfer unit connected to the memory macro, a second input / output unit connected to the second data transfer unit, and a second input / output unit. It is transferred to the corresponding logic macro via the first input / output unit. At this time, the transfer rate between the first data transfer unit and the second data transfer unit, and the transfer rate between the first input / output unit and the second input / output unit are the logical macro and the first data transfer. Or more than twice the transfer rate between the data transfer unit or the memory macro and the second data transfer unit.
According to the data transfer method in the semiconductor device according to the present embodiment, the same data transfer speed can be obtained as compared with the case where each logic macro and each memory macro are wired independently. Therefore, interference between data during data transfer can be suppressed without causing a decrease in data transfer speed. For example, when the number of logic macros is four, the data transfer speed of the first ring bus as the first data transfer unit and the data transfer speed between the logic circuit area and the memory circuit area are set to the logic macro. And 4 times the transfer rate between the first ring bus and the first ring bus. As a result, when data is transmitted from the four logic macros to the corresponding memory macro, each memory macro receives the data after the same time as when each logic macro and the memory macro are individually wired. Is possible.
Next, the data transfer method in the semiconductor device according to the present embodiment will be described in more detail with reference to FIGS.
FIG. 9 is a circuit configuration diagram in the logic circuit region 310 of the semiconductor device for explaining the data transfer method in the semiconductor device according to the present embodiment. Each logic macro 311 is synchronized with the normal-speed clock CLK1, but the register 317 on the first ring bus 314 is synchronized with the quadruple-speed clock CLK2.
FIG. 10 is a circuit configuration diagram in the memory circuit region 320 of the semiconductor device for explaining the data transfer method in the semiconductor device according to the present embodiment. The memory macro 321 is synchronized with the normal speed clock CLK1, but the register 327 on the second ring bus 324 is synchronized with the quadruple speed clock CLK2.
FIG. 11 is a waveform diagram when data is transferred from the logic macro 311 to the memory macro 321. Here, La to Ld represent each logic macro 311, Ma to Md represent each memory macro 321, LRa to LRd represent each register 317 in the logic circuit area 310, and MRa to MRd represent each register 327 in the memory circuit area 320. To express. Write data a, b, c, d transmitted from the logic macros La, Lb, Lc, Ld in synchronization with CLK1 are taken into the registers LRa, LRb, LRc, LRd in synchronization with the quadruple speed clock CLK2, respectively. It is. In the next clock cycle, the write data a captured in the register LRa is transferred to the second I / O port 325 in the memory circuit area via the first I / O port 315 in the logic circuit area. Then, it is taken into the second ring bus 324 in the memory circuit area. The write data a is transferred on the second ring bus 324 in synchronization with the quadruple speed clock CLK2, and is taken into the memory macro Ma in synchronization with the normal speed clock CLK1. The write data b, c, d are transferred from the logic circuit area to the memory circuit area in different time zones. As can be seen from FIG. 11, each write data is transmitted from the logic macro in one cycle period of the normal-speed clock CLK1, transferred from the logic circuit area to the memory circuit area in two cycle periods, and transferred to the memory macro in three cycle periods. It is captured. Therefore, according to the present embodiment, it is possible to transfer write data with the same number of clock cycles as when each logical macro and each memory macro are wired independently.
Further, as shown in FIG. 12, the present embodiment can be used even for a semiconductor device 300 including a plurality of ring buses. The semiconductor device 300 includes, for example, two first ring buses and two second ring buses, and a part of the logic macro 311 is connected to one first ring bus 314-1 to connect the first I / O. Data is transferred to the O port 315, and the remaining logic macro 311 is connected to the other first ring bus 314-2 to transfer data to the first I / O port 315. At this time, if data is transferred from the first I / O port 315 to the second I / O port 325 at twice the normal speed, the same effect can be obtained. For example, the memory circuit region 320 may include one second ring bus 324-1 and the other second ring bus 324-2.
[Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described. FIG. 13 is a plan view showing a configuration of a semiconductor device 400 according to the fourth embodiment of the present invention. The semiconductor device 400 includes a first order control unit 440 and a second order control unit 450 that connect each logic macro 411 and each memory macro 421, respectively. In the logic circuit area 410, write data as the first data group is collected from the plurality of logic macros 411 to the first sequence control unit 440 through the respective connection wirings. The write data for each logic macro is transferred from the first I / O port 415 in the logic circuit area 410 to the second I / O port 425 in the memory circuit area 420 via the inter-area connection wiring 430. At this time, the first order control unit 440 sequentially transfers the write data according to the order information in which the logical macros 411 are ordered.
FIG. 14 shows an example of the circuit configuration of the first sequence control unit 440 in the logic circuit region 410. The first order control unit 440 includes a selector circuit 441 and a counter circuit 442 that select input of write data from the plurality of logic macros 411 (FIG. 14A). Here, for example, the input ports of the selector circuit 441 that inputs data from four logic macros La, Lb, Lc, and Ld are a, b, c, and d, respectively. At this time, the 2-bit counter value output from the counter circuit 442 is used as a control signal for the selector circuit 441 to select one of the input ports a, b, c, and d (FIG. 14B). Here, the order of the logic macros that are sequentially selected by the selector circuit 441 as the counter value increases can be used as the order information. Output data from the first sequence control unit 440 is transmitted to the memory circuit area 420 via the first I / O port 415.
On the other hand, a second sequence control unit 450 is arranged in the memory circuit region 420. The second sequence control unit 450 distributes the write data input to the second I / O port 425 to each destination memory macro 421 and transfers it. FIG. 15 shows an example of a circuit configuration of the second order control unit 450 in the memory circuit region 420. The second sequence control unit 450 includes a selector circuit 451 and a counter circuit 452 that select an output destination of write data received from the second I / O port 425 (FIG. 15A). Here, for example, the output ports of the selector circuit 451 that outputs data to the four memory macros Ma, Mb, Mc, and Md are a, b, c, and d. At this time, the 2-bit counter value output from the counter circuit 452 is used as a control signal for the selector circuit 451, and any one of the output force ports a, b, c, and d is selected (FIG. 15B). Thereby, the output data to the four memory macros can be sequentially selected.
Here, the first order controller 440 in the logic circuit area 410 and the second order controller 450 in the memory circuit area 420 have common order information, and the

counter circuits

442 and 452 are synchronized with each other. Therefore, write data from the logic macros La, Lb, Lc, and Ld are sequentially transferred to the corresponding memory macros Ma, Mb, Mc, and Md, respectively.
Even when the read data as the second data group is transferred from the memory macro 421 to the logic macro 411, the order control unit having the same circuit configuration is provided by reversing the data transfer direction. Can be used.
As described above, according to the semiconductor device 400 according to the present embodiment, the write data as the first data group is transmitted from the first I / O port 415 in the logic circuit area 410 to the second in the memory circuit area 420. To the I / O port 425, the writing data is transferred in sequential order at different times for each write data. Therefore, interference of a plurality of data on the inter-region connection wiring 430 between the logic circuit region 410 and the memory circuit region 420 can be suppressed. Here, since the semiconductor device 100 according to the first embodiment uses a ring bus, the order in which the write data generated in each logic macro 111 is transferred to the memory circuit area is fixed by the arrangement of the logic macros 111. It had been. On the other hand, according to the semiconductor device 400 according to the present embodiment, by changing the order information in the first order control unit 440 and the second order control unit 450, the order in which the write data is transferred to the memory circuit area is changed. The effect that it can be changed is obtained. That is, it is possible to change the order of the logic macros that transmit the write data or the order of the memory macros that receive the write data. For example, since a normal counter counts up in synchronization with a clock, it is selected in the order of a → b → c → d. However, by inverting the output signal of a 2-bit counter circuit, d → c → b → The order of transfer with a can be reversed. Further, by reversing only the lower bits of the counter value, it is possible to change the transfer order as b → a → d → c.
In the present embodiment, as described above, the write data is transferred from the second order control unit 450 to each memory macro 421 in the memory circuit area 420 by using the common order information and the

counter circuits

442 and 452 are transferred. Control was performed in synchronization with each other. However, the present invention is not limited to this, and control may be performed using addresses. That is, a destination address is assigned for each write data, and the data is sequentially transmitted from the logic circuit area 410. Then, the second order control unit 450 of the memory circuit area 420 may select the memory macro 421 corresponding to the destination based on this address, and output the write data to the selected memory macro.
Further, the data transfer rate in the semiconductor device 400 according to the present embodiment is not particularly limited, but the transfer rate in the first order control unit 440 and the second order control unit 450, the first I / O port 415, and the first transfer rate are not limited. The transfer rate between the I / O port 425 and the second macro is equal to or higher than twice the transfer rate between the logic macro 411 and the first sequence control unit 440 or between the memory macro 421 and the second sequence control unit 450. be able to.
For example, the data output from the first sequence control unit 440 to the first I / O port 415 in the logic circuit area 410 is four times the transfer rate from the logic macro 411 to the first sequence control unit 440 and is the same. Data is transferred from the first I / O port 415 to the second I / O port 425 at a speed. Then, when the second sequence control unit 450 in the memory circuit area 420 is transferred to the memory macro 421, the original transfer speed may be restored. Thus, when data is simultaneously transferred from four logic macros to the corresponding memory macros, each memory macro receives data in the same time as when each logic macro and memory macro are individually wired. It becomes possible.
[Fifth Embodiment]
Next, a fifth embodiment of the present invention will be described. FIG. 16 is a plan view showing a configuration of a semiconductor device 500 according to the fifth embodiment of the present invention. In the semiconductor device 500, a first input / output control unit 560 is connected to each of the logic macros 511, and each first input / output control unit 560 and a first I / O port 515 which is a first input / output unit. The first shared bus 518 to which are respectively connected constitutes a first data transfer unit. On the other hand, a second input / output control unit 570 is connected to each of the memory macros 521, and each second input / output control unit 570 and a second I / O port 525 that is a second input / output unit are connected to each of the memory macros 521. The second shared bus 528 constitutes a second data transfer unit. Each first input / output control unit 560 outputs a first data group to the first shared bus 518 according to the order information in which each logical macro 511 is ordered, and each second input / output control unit 570 follows the order information. The first data group is sequentially received from the second shared bus 528.
FIG. 17 illustrates an example of a circuit configuration of the first input / output control unit 560 included in the logic macro (La). The first input / output control unit 560 can be configured using, for example, a three-state buffer circuit 561, a counter circuit 562, and a comparator circuit 563 (FIG. 17A). The counter circuit 562 outputs a 2-bit counter value to the comparator circuit 563 when the number of logic macros 511 is, for example, four. For example, when the counter value is “00”, the comparator circuit 563 outputs “1” to the 3-state buffer circuit 561. At this time, the 3-state buffer circuit 561 outputs a signal constituting the first data group from the logic macro La to the first shared bus 518, and the data is transferred from the first I / O port 515 to the memory circuit area. . When the counter value is other than “00”, the comparator circuit 563 outputs “0”, and at this time, the output of the three-state buffer circuit 561 becomes high impedance (FIG. 17B). For logic macros (Lb, Lc, Ld) other than La, the comparator circuit 563 is set to output data when the counter value is “01”, “10”, “11”, for example.
On the other hand, in the memory circuit area 520, as shown in FIG. 16, a second input / output control unit 570 is arranged in each memory macro 521. FIG. 18 illustrates an example of a circuit configuration of the second input / output control unit 570 included in the memory macro (Ma). The second input / output control unit 570 can be configured using, for example, a three-state buffer circuit 571, a counter circuit 572, and a comparator circuit 573 (FIG. 18A). The counter circuit 572 outputs a 2-bit counter value to the comparator circuit 573. For example, when the counter value is “00”, the comparator circuit 573 outputs “1” to the 3-state buffer circuit 571. At this time, the 3-state buffer circuit 571 outputs the signal from the second shared bus 528 to the memory macro Ma. When the counter value is other than “00”, the comparator circuit 573 outputs “0”, and at this time, the output of the 3-state buffer circuit 571 becomes high impedance (FIG. 18B). For memory macros (Mb, Mc, Md) other than Ma, the comparator circuit 573 is set to output data when the counter value is “01”, “10”, “11”, for example.
Here, the first input / output control unit 560 in the logic circuit region 510 and the second input / output control unit 570 in the memory circuit region 520 have common order information, and the

counter circuits

562 and 572 are synchronized with each other. . Therefore, write data from the logic macros La, Lb, Lc, and Ld are sequentially transferred to the corresponding memory macros Ma, Mb, Mc, and Md, respectively.
Even when the read data as the second data group is transferred from the memory macro 521 to the logic macro 511, the input / output control having the same circuit configuration is realized by reversing the data transfer direction. Part can be used.
As described above, according to the semiconductor device 500 according to the present embodiment, the write data as the first data group is transmitted from the first I / O port 515 in the logic circuit area 510 to the second in the memory circuit area 520. To the I / O port 525, the writing data is transferred in a sequential manner at different times in different time zones. Therefore, interference of a plurality of data on the inter-region connection wiring 530 between the logic circuit region 510 and the memory circuit region 520 can be suppressed. Furthermore, according to the semiconductor device 500 according to the present embodiment, the order information in the first input / output control unit 560 and the second input / output control unit 570 is changed to change the order in which the write data is transferred to the memory circuit area. The effect that it can be changed is obtained. That is, it is possible to change the order of the logic macros that transmit the write data or the order of the memory macros that receive the write data. For example, since a normal counter counts up in synchronization with a clock, it is selected in the order of a → b → c → d. However, by inverting the output signal of a 2-bit counter circuit, d → c → b → The order of transfer with a can be reversed. Further, by reversing only the lower bits of the counter value, it is possible to change the transfer order as b → a → d → c.
In addition, the data transfer speed in the semiconductor device 500 according to the present embodiment is not particularly limited, but the first input / output control unit 560 and the first shared bus 518, the second input / output control unit 570 and the second shared bus. The transfer rate in each of 528 and the transfer rate between the first I / O port 515 and the second I / O port 525 are the same as the logic macro 511 and the first input / output control unit 560 or the memory macro 521. The transfer rate with the second input / output control unit 570 can be twice or more.
For example, the data output from the first input / output control unit 560 to the first shared bus 518 in the logic circuit area 510 is four times the transfer rate from the logic macro 511 to the first input / output control unit 560, and the same. Data is transferred from the first I / O port 515 to the second I / O port 525 at a speed. Then, when data is taken into the memory macro 521 from the second input / output control unit 570 in the memory circuit area 520, the original speed may be restored. Thus, when data is simultaneously transferred from four logic macros to the corresponding memory macros, each memory macro receives data in the same time as when each logic macro and memory macro are individually wired. It becomes possible.
[Sixth Embodiment]
Next, a sixth embodiment of the present invention will be described. FIG. 19 shows a semiconductor device 600 according to the sixth embodiment of the present invention. 2A is a schematic perspective view for explaining the configuration of the semiconductor device 600, FIG. 1B is a plan view of a memory circuit substrate 602 constituting the semiconductor device 600, and FIG. 2 is a plan view of a logic circuit board 601. FIG. The semiconductor device 600 includes a logic circuit board 601 and a memory circuit board 602. A logic circuit area 610 is formed on the logic circuit board 601 and a memory circuit area 620 is formed on the memory circuit board 602 (FIG. 19B). (C)). Here, as the logic circuit region 610 and the memory circuit region 620, the same ones as those used in the first to fifth embodiments described above can be used.
As shown in FIG. 19A, a semiconductor device 600 is configured in a state where a logic circuit board 601 and a memory circuit board 602 are stacked. In this embodiment, the logic circuit board 601 and the memory circuit board 602 are connected so as to face each other by a flip chip mounting method using the micro bumps 630. Pads are formed on the surface of each substrate with which the microbumps 630 come into contact. The pads and the first I / O port 615 on the logic circuit board 601 and the second I / O port on the memory circuit board 602 are formed. 625 are connected by wiring.
Then, the first data group generated by the logic macro 611 on the logic circuit board 601 is transferred to the second I / O port in a different time zone for each first data group via the first I / O port 615. It is controlled to be transferred to 625. Similarly, the second data group stored in the memory macro 621 on the memory circuit board 602 is transferred to the first I / O in a different time zone for each second data group via the second I / O port 625. It is controlled to be transferred to the O port 615. For the configurations of the logic circuit region 610 and the memory circuit region 620 for performing this control, the configurations in the first to fifth embodiments described above can be used.
As described above, in the semiconductor device 600 according to the present embodiment, each data is transferred between the logic circuit area 610 and the memory circuit area 620 while shifting the time in different time zones. Therefore, interference of a plurality of data between the areas between the logic circuit area 610 and the memory circuit area 620 can be suppressed. Furthermore, in the semiconductor device 600 according to the present embodiment, since the memory circuit area 620 is configured on the memory circuit board 602 different from the logic circuit board 601, a manufacturing process dedicated to the memory circuit is used to form the memory circuit area 620. can do. This makes it possible to optimize the performance of the transistor for the memory circuit. Further, the manufacturing cost can be reduced by omitting the manufacturing process necessary only for forming the logic circuit.
In this embodiment, the micro bumps 630 are used to connect the logic circuit board 601 and the memory circuit board 602. However, the present invention is not limited to this, and a non-contact connection mode such as inductor coupling or capacitive coupling is used. Also good.
The configuration of the memory macro in the first to sixth embodiments described above is not particularly limited, and may be a configuration having a plurality of sub memory macros, for example. For example, as shown in FIG. 20, the memory macro 721 may be composed of a plurality of sub memory macros 722, and the individual sub memory macros 722 may be connected to each other via a connection network 723 in the memory macro. The write data transferred from the second ring bus 724 is transferred to the write destination sub memory macro 722 via the connection network 723. FIG. 20 shows an example in which a two-dimensional mesh configuration is used as the connection network 723. However, the configuration of the connection network 723 is not limited to this, and any of a bus configuration, a ring configuration, a tree configuration, or a crossbar switch configuration can be used. It may be used.
The present invention is not limited to the above-described embodiment, and various modifications are possible within the scope of the invention described in the claims, and it is also included within the scope of the present invention. Not too long.
This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2009-168598 for which it applied on July 17, 2009, and takes in those the indications of all here.

100, 200, 300, 400, 500, 600

Semiconductor device

110, 210, 310, 410, 510, 610

Logic circuit area

111, 211, 311, 411, 511, 611 Logic macro 112 First data transfer unit 113

First

114, 214, 314, 314-1, 314-2 First ring bus 114-1 Write data ring bus 114-2 Read

data ring bus

115, 215, 315, 415, 515, 615 1 I /

O port

116, 126, 316

Multiplexer

117, 127, 317

Register

120, 220, 320, 420, 520, 620

Memory circuit area

121, 221, 321, 421, 521, 621, 721 Memory macro 122 Second Data transfer unit 123 No. Input /

output unit

124, 224, 324, 324-1, 324-2, 724

Second ring bus

125, 225, 325, 425, 525, 625 Second I /

O port

130, 230, 330, 430, 530 Inter-region connection wiring 240 Transfer start signal wiring 440 First sequence control unit 450 Second

sequence control unit

441, 451

Selector circuit

442, 452, 562, 572 Counter circuit 518 First shared bus 528 Second shared bus 560 First input /

output control unit

561, 571 Three-

state buffer circuit

563, 573 Comparator circuit 570 Second input / output control unit 601 Logic circuit board 602 Memory circuit board 630 Micro bump 722 Sub memory macro 723 Connection network 800

Related SoC Chip

810A, 820B, 8 0C,

840D logic macro

810a, 820b, 830c, 840d memory macro 850 output ports (I / O ports)

Claims

A logic circuit region including a plurality of logic macros, a first data transfer unit, and a first input / output unit, and a memory circuit region including a plurality of memory macros, a second data transfer unit, and a second input / output unit Have
The first data transfer unit is connected to the plurality of logic macros, and the second data transfer unit is connected to the plurality of memory macros, and the first input / output unit and the second input / output unit Parts are connected to each other,
The first data transfer unit sends a first data group generated in the individual logic macro to the first data group via the first input / output unit and the second input / output unit. Transfer to the second data transfer unit at different times,
The second data transfer unit transfers the second data group stored in the individual memory macros to the second data group via the second input / output unit and the first input / output unit. A semiconductor device that transfers data to the first data transfer unit at different times.
The semiconductor device according to claim 1,
The first data transfer unit has a first ring bus to which the logic macros are connected,
The second data transfer unit is a semiconductor device having a second ring bus to which the memory macros are connected.
The semiconductor device according to claim 2,
The first input / output unit is connected to the first ring bus;
The second input / output unit is connected to the second ring bus;
The first ring bus sequentially transfers the first data group from the logic macros to the first input / output unit,
The second ring bus is a semiconductor device that sequentially transfers the second data group from the memory macros to the second input / output unit.
The semiconductor device according to claim 2,
The first input / output unit is connected to one of the logic macros;
The second input / output unit is connected to one of the memory macros;
The first ring bus sequentially transfers the first data group from the logic macros to the first input / output unit,
The second ring bus is a semiconductor device that sequentially transfers the second data group from the memory macros to the second input / output unit.
The semiconductor device according to claim 1,
The first data transfer unit includes a first sequence control unit to which the logic macros and the first input / output unit are connected.
The second data transfer unit includes a second sequence control unit to which the memory macros and the second input / output unit are connected.
The first order control unit receives a first data group generated in each individual logic macro from each of the logic macros, and sets the first data group according to order information in which the logic macros are ordered. Sequentially transferring to the second input / output unit via the first input / output unit;
The second sequence control unit sequentially receives the first data group from the second input / output unit, and each of the memories corresponding to each logic macro according to the sequence information. A semiconductor device that sequentially transfers to a macro.
The semiconductor device according to claim 1,
A first input / output control unit connected to the logic macro; and a second input / output control unit connected to the memory macro;
The first data transfer unit includes a first shared bus to which the first input / output control unit and the first input / output unit are connected.
The second data transfer unit has a second shared bus to which the second input / output control unit and the second input / output unit are connected,
Each of the first input / output control units outputs the first data group to the first shared bus according to order information in which the logic macros are ordered.
Each of the second input / output control units sequentially receives the first data group from the second shared bus according to the order information.
The semiconductor device according to any one of claims 1 to 6,
A semiconductor device in which the logic circuit area and the memory circuit area are arranged on the same substrate.
The semiconductor device according to any one of claims 1 to 6,
A semiconductor device in which the logic circuit area and the memory circuit area are arranged on different substrates.
Data generated in each of a plurality of logic macros constituting the semiconductor device is formed as a first data group for each logic macro,
Transferring the first data group to a memory macro constituting the semiconductor device corresponding to the logic macro in a different time zone for each first data group;
Forming each data stored in a plurality of memory macros constituting the semiconductor device as a second data group for each memory macro;
A data transfer method in a semiconductor device, wherein the second data group is transferred to a logic macro constituting the semiconductor device corresponding to the memory macro in a different time zone for each second data group.
In the data transfer method in the semiconductor device according to claim 9,
The first data group includes a first data transfer unit connected to the logic macro, a first input / output unit connected to the first data transfer unit, and the first input / output unit. Transferred to the corresponding memory macro via the connected second input / output unit,
The second data group includes a second data transfer unit connected to the memory macro, a second input / output unit connected to the second data transfer unit, and the second input / output unit. Transferred to the corresponding logic macro via the connected first input / output unit,
The transfer rate in the first data transfer unit and the second data transfer unit, and the transfer rate between the first input / output unit and the second input / output unit are determined by the logic macro and the first data transfer unit. A data transfer method in a semiconductor device that is at least twice the transfer rate between the data transfer unit or the memory macro and the second data transfer unit.