WO2011001818A1 - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Semiconductor device and method for manufacturing semiconductor device Download PDF

Info

Publication number
WO2011001818A1
WO2011001818A1 PCT/JP2010/060105 JP2010060105W WO2011001818A1 WO 2011001818 A1 WO2011001818 A1 WO 2011001818A1 JP 2010060105 W JP2010060105 W JP 2010060105W WO 2011001818 A1 WO2011001818 A1 WO 2011001818A1
Authority
WO
WIPO (PCT)
Prior art keywords
solder
semiconductor device
semiconductor element
connection
mass
Prior art date
Application number
PCT/JP2010/060105
Other languages
French (fr)
Japanese (ja)
Inventor
靖 池田
芹沢　弘二
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Publication of WO2011001818A1 publication Critical patent/WO2011001818A1/en

Links

Images

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B23K35/262—Sn as the principal constituent
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B23K35/264—Bi as the principal constituent
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00—Layered products comprising a layer of metal
    • B32B15/01—Layered products comprising a layer of metal all layers being exclusively metallic
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C12/00—Alloys based on antimony or bismuth
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C13/00—Alloys based on tin
    • C22C13/02—Alloys based on tin with antimony or bismuth as the next major constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Definitions

  • the present invention relates to a semiconductor device, and more particularly to flash prevention when a semiconductor element is connected on a frame using solder.
  • FIG. 12 is a configuration diagram showing a configuration of a conventional semiconductor device.
  • the semiconductor element 1 is die-bonded on the frame 2 with solder 3, and wire bonding is performed between the electrode on the upper surface of the semiconductor element 1 and the terminal 5 of the frame with a wire 4, and then sealed with a potting resin 6. Stopped.
  • the semiconductor device 7 is reflow soldered to a printed circuit board (not shown) with Sn-Ag-Cu-based medium temperature lead-free solder.
  • the melting point of Sn—Ag—Cu-based lead-free solder is as high as about 220 ° C., and it is assumed that the connection portion is heated up to 260 ° C. during reflow soldering.
  • high lead solder having a melting point of 290 ° C. or more has been used for the die bonding solder 3 of the semiconductor element 1 inside the semiconductor device 7 for the purpose of the temperature hierarchy.
  • High lead solder has 85 wt. Compared with Sn-Pb eutectic solder prohibited by the RoHS Directive that has been in force since July 2006, it contains a large amount of lead.
  • solders have a melting point of 260 ° C. or lower, so when used for die bonding of the semiconductor element 1, the solder is used during reflow soldering (maximum temperature 260 ° C.). Will melt.
  • the periphery of the connecting portion is resin-molded, when the internal solder 3 melts, the solder 3 leaks from the interface between the potting resin 6 and the frame 2 as shown in FIG. 13 due to volume expansion at the time of melting.
  • the solder 3 leaks from the interface between the potting resin 6 and the frame 2 as shown in FIG. 13 due to volume expansion at the time of melting.
  • FIG. 13 is a view showing a state after reflow soldering in a conventional semiconductor device.
  • Au-based solders such as Au-Sn, Au-Si, Au-Ge, Zn, Zn-Al solders, and solders such as Bi, Bi-Cu, Bi-Ag, etc. are reported in terms of melting point. Although being studied all over the world, there are problems in using it for general purposes.
  • Au-based solder is 80wt. % Or more, and there is difficulty in versatility in terms of cost.
  • Bi-based solder has a thermal conductivity of about 9 W / mK, which is lower than that of current high-lead solder, and it can be estimated that it is difficult to apply it to semiconductor devices that require high heat dissipation.
  • Zn and Zn—Al solder have a high thermal conductivity of about 100 W / mK, but they are difficult to wet (especially Zn—Al solder).
  • the solder is hard and the semiconductor element is destroyed by thermal stress during cooling after connection. There are problems such as easy.
  • a conductive adhesive is mentioned in addition to a metal material. This is a mixture of a resin and an Ag filler, and is most commonly used as an alternative material for high lead solder.
  • the thermal conductivity is about 10 W / mK, which is less than the thermal conductivity of high lead solder of about 30 W / mK.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2007-181880
  • Bi-0.01 to 57 mass% Sn is used to prevent volume shrinkage during solidification of the solder, and to the interface between the inner surface electrode of the through-type ceramic capacitor and the hole inner wall of the structure or the inside of the structure. This is to prevent cracks.
  • Patent Document 1 has the following problems when applied to a semiconductor device.
  • Bi-0.01 to 57 mass% Sn has high reactivity with the Ni layer used for the electrode of the semiconductor element.
  • a Ni electrode having a thickness of 0.5 ⁇ m to 1 ⁇ m is used as the back electrode of the semiconductor element. This Ni electrode is a layer necessary for maintaining the connection between the solder and the semiconductor element.
  • Ni metallization disappears due to reaction with solder at the time of connection, and the interface strength may be reduced, and the semiconductor element may be peeled off.
  • Bi-0.01 to 57 mass% Sn is weak in the strength of the base material because Bi is a brittle material, and cracks easily develop in the solder connection portion. .
  • an object of the present invention is to connect a semiconductor element with a Sn-37 to 60 mass% Bi-2 to 7 mass% Cu solder, and to reduce the volume change when the solder is melted within 0.5%, and to perform reflow soldering.
  • An object of the present invention is to provide a semiconductor device capable of preventing flashing of time, ensuring stability of a semiconductor element connection interface, and improving connection reliability against thermal stress.
  • a typical outline is that a semiconductor element having a Ni electrode is connected to a frame plated with Ni with Sn—Bi—Cu based lead-free solder, and the periphery thereof is sealed with resin.
  • the effect obtained by a typical one can suppress flashing during reflow soldering by applying Sn-37 to 60 mass% Bi-2 to 7 mass% Cu to the connection of the semiconductor element.
  • the addition of 2 to 7% by mass of Cu ensures the stability of the semiconductor element connection interface during connection and reflow soldering, and improves connection reliability against thermal stress.
  • connection part by the side of the semiconductor element of the semiconductor device which concerns on one embodiment of this invention. It is sectional drawing of the connection part by the side of the frame of the semiconductor device which concerns on one embodiment of this invention. It is sectional drawing of the connection part by the side of a semiconductor element at the time of using Sn-Bi type lead free solder which does not contain Cu used as the comparative example of the semiconductor device concerning one embodiment of the present invention. It is sectional drawing of the connection part by the side of a flame
  • FIGS. 1 is a cross-sectional view of a connection portion on the semiconductor element side of a semiconductor device according to an embodiment of the present invention
  • FIG. 2 is a cross-sectional view of a connection portion on the frame side of the semiconductor device according to the embodiment of the present invention
  • 3 is a cross-sectional view of the connection portion on the semiconductor element side when Sn—Bi based lead-free solder not containing Cu is used as a comparative example of the semiconductor device according to one embodiment of the present invention
  • FIG. 5 is a cross-sectional view of a connection portion on the frame side when Sn—Bi-based lead-free solder not containing Cu is used as a comparative example of the semiconductor device according to the embodiment, and FIG. 5 relates to the embodiment of the present invention.
  • FIG. 6 is a diagram showing the relationship between the temperature of the semiconductor device and the volume expansion of solder, and FIG. 6 is a diagram showing the relationship between the Cu content of the semiconductor device according to one embodiment of the present invention and the Ni electrode disappearance thickness of the semiconductor element.
  • the Ni electrode 14 and the frame 2 of the semiconductor element 1 are connected as shown in FIGS.
  • An intermetallic compound layer 11 containing (Cu, Ni) 6 Sn 5 can be formed on the Ni plating 12.
  • the intermetallic compound 11 ′ containing (Cu, Ni) 6 Sn 5 precipitated inside the solder reinforces Sn—Bi that is the parent phase.
  • the Ni electrode of the semiconductor element 1 disappears at the connection interface on the semiconductor element 1 side at the time of connection. As shown in FIG. 4, the interface of the connection interface may be peeled off. Further, the Ni 3 Sn 4 compound 13 is formed at the interface on the frame 2 side shown in FIG. Will be formed.
  • the volume change at the time of melting the solder can be made smaller than that of Sn-rich lead-free solder such as Sn-3Ag-0.5Cu.
  • the volume expansion at 260 ° C. in which reflow soldering is performed can be reduced as compared with Sn-rich lead-free solder.
  • FIG. 5 is a diagram showing the relationship between the temperature and volume expansion of Sn-48Bi-5Cu, Sn-rich solder, and Sn-58Bi.
  • Sn-rich solder the volume expansion of about 3% is caused by melting, whereas in the case of Sn-48Bi-5Cu and Sn-58Bi, the volume expansion is less than 1%.
  • the volume expansion of Sn-rich solder from room temperature is about 4.5%, while that of Sn-48Bi-5Cu and Sn-58Bi is about 2%.
  • FIG. 6 shows that the semiconductor element 1 having a Ni electrode 14 thickness of 0.5 ⁇ m is connected at 350 ° C. for 1 min. It is the graph which showed the loss
  • the horizontal axis represents the Cu content of the Sn—Bi—Cu alloy. When the Cu content is 2% by mass or more, the 0.5 ⁇ m Ni electrode 14 can be connected without disappearing.
  • the liquidus temperature of the solder is 400 ° C. or higher, and the wettability is reduced at 350 ° C. where the solder connection of the semiconductor device is performed, and the solder non-wetting portion is likely to occur. .
  • the volume change at the time of melting can be made within 5%.
  • the Cu content is 5% by mass or more.
  • the liquidus temperature of the solder is 400 ° C. or higher, and the wettability is reduced at 350 ° C. where the solder connection of the semiconductor device is performed, and the solder non-wetting portion is likely to occur. .
  • Ni, Ni—P, Ni—B or the like is plated as Ni-based plating, or at least one of Au, Ag, and Pd is applied thereon.
  • Ni-based plating can ensure sufficient wetting with respect to Sn-based solder, and a barrier layer mainly composed of (Cu, Ni) -Sn compound is formed on the Ni-based plating.
  • wetting can be improved by applying Au plating or Ag plating on the plating of Ni, Ni—P, Ni—B or the like.
  • a plating layer such as Au or Ag is diffused in the solder at the time of connection, so that a barrier layer mainly composed of (Cu, Ni) -Sn compound can be formed on the underlying Ni-based plating.
  • solder supply form can be strengthened by the solder flash and the stability of the semiconductor element connection interface, and the Sn—Bi matrix phase compound, regardless of the supply form of foil, wire, or paste. It is possible to select a supply method according to the connection environment.
  • the connected state can be maintained even when the resin is cured at a temperature higher than the solidus temperature of the solder.
  • FIG. 7 is a diagram showing the relationship between the solder composition and the connection reliability in the example of the semiconductor device according to the embodiment of the present invention and the comparative example
  • FIG. 8 is the implementation of the semiconductor device according to the embodiment of the present invention.
  • FIG. 9 is a diagram illustrating a connection state in an example
  • FIG. 9 is a diagram illustrating a crack state of a semiconductor device according to an embodiment of the present invention
  • FIG. 10 is a comparative example of a semiconductor device according to an embodiment of the present invention.
  • FIG. 11 is a diagram showing a state of cracks
  • FIG. 11 is a diagram showing generation of voids in a comparative example of a semiconductor device according to an embodiment of the present invention.
  • Examples 1 to 9 shown in FIG. 7 the semiconductor device 7 shown in FIG. 12 was manufactured, and the presence / absence of flash at the time of reflow soldering and the connection reliability based on crack progress were determined.
  • the semiconductor device 7 was produced as follows.
  • a semiconductor element 1 having a size of 3 mm ⁇ 3 mm having a metallization of Ti / Ni (0.5 ⁇ m) / flash Au from the Si side is applied to a N 2 + 4% H 2 atmosphere using solder 3 having a solder composition shown in FIG. Medium, 350 ° C. for 1 min.
  • the Ni-plated frame 2 was connected under the following conditions.
  • wire bonding was performed between the electrode on the upper surface of the semiconductor element 1 and the terminal 5 of the frame 2 with a wire 4. Further, after wire bonding, the periphery was surrounded by a metal mold, and a potting resin 6 was poured in, and the resin was cured in the atmosphere at 150 ° C. for 2 hours.
  • the potting resin 6 may be another resin such as a mold resin.
  • ribbon bonding may be used for connection between the upper surface of the semiconductor element 1 and the inter-terminal 5.
  • FIG. 8 shows a cross section of the connection part after the reflow test of Sn-48Bi-5Cu. It can be confirmed that the connection of the semiconductor element 1 is maintained without the solder 3 flowing out.
  • ⁇ indicates that the connection is maintained at 80% or more of the original connection area after 1000 cycles, and x indicates that the connection area is less than 80%. In any of Examples 1 to 9, the connection area did not change before and after the test.
  • the crack 23 linearly propagated along the semiconductor element 1 and the solder connection portion. This is because the Cu content is low, and the intermetallic compound layer 11 containing (Cu, Ni) 6 Sn 5 is not formed at the connection interface as in Examples 1 to 9, so the solder matrix (Cu, Ni) is not formed. This is because 6 Sn 5 is not precipitated.
  • Comparative Example 1 since the crack 23 linearly propagates along the semiconductor element 1 and the solder connection portion, problems such as peeling easily occur and the connectivity is deteriorated.
  • FIG. 11 shows a connection portion made of Sn-3Ag-0.5Cu after the reflow test. It can be confirmed that voids are generated by melting and flowing out of the solder.
  • the present invention is widely applicable to semiconductor devices in which a semiconductor element is connected on a frame using solder.

Abstract

Disclosed is a semiconductor device wherein flash is suppressed when reflow soldering is performed, stability of a semiconductor element connecting interface is ensured, and connection reliability with respect to thermal stress is improved. The semiconductor device is provided with: a semiconductor element (1) having an Ni electrode (14); an Ni-plated frame; an Sn-Bi-Cu lead-free solder (3) which connects the Ni electrode (14) of the semiconductor element (1) to the Ni-plated frame; and a resin which seals the periphery of the semiconductor element (1).

Description

半導体装置および半導体装置の製造方法Semiconductor device and manufacturing method of semiconductor device
　本発明は、半導体装置に関し、特に、はんだを使用して半導体素子をフレーム上に接続する場合のフラッシュ防止に関するものである。 The present invention relates to a semiconductor device, and more particularly to flash prevention when a semiconductor element is connected on a frame using solder.
　従来、はんだを使用して半導体素子をフレーム上に接続した半導体装置は、図１２に示すような構成である。図１２は従来の半導体装置の構成を示す構成図である。 Conventionally, a semiconductor device in which semiconductor elements are connected on a frame using solder has a configuration as shown in FIG. FIG. 12 is a configuration diagram showing a configuration of a conventional semiconductor device.
　図１２において、半導体素子１はフレーム２上に、はんだ３によりダイボンディングされ、半導体素子１の上面の電極と、フレームの端子５との間をワイヤ４でワイヤボンディングした後、ポッティングレジン６で封止される。 In FIG. 12, the semiconductor element 1 is die-bonded on the frame 2 with solder 3, and wire bonding is performed between the electrode on the upper surface of the semiconductor element 1 and the terminal 5 of the frame with a wire 4, and then sealed with a potting resin 6. Stopped.
　その後、半導体装置７は、Ｓｎ－Ａｇ－Ｃｕ系の中温の鉛フリーはんだにより、プリント基板（図示せず）にリフローはんだ付けされる。Ｓｎ－Ａｇ－Ｃｕ系鉛フリーはんだの融点は約２２０℃と高く、リフローはんだ付けの際に接続部が最高２６０℃まで加熱されることが想定される。 Thereafter, the semiconductor device 7 is reflow soldered to a printed circuit board (not shown) with Sn-Ag-Cu-based medium temperature lead-free solder. The melting point of Sn—Ag—Cu-based lead-free solder is as high as about 220 ° C., and it is assumed that the connection portion is heated up to 260 ° C. during reflow soldering.
　そのため、温度階層を目的として半導体装置７内部の半導体素子１のダイボンディングのはんだ３には、２９０℃以上の融点を有する高鉛はんだが使用されていた。高鉛はんだは、構成成分として８５ｗｔ．％以上の鉛を含有しており、２００６年７月より施行されているＲｏＨＳ指令で禁止されているＳｎ－Ｐｂ共晶はんだに比べて環境負荷が大きい。 Therefore, high lead solder having a melting point of 290 ° C. or more has been used for the die bonding solder 3 of the semiconductor element 1 inside the semiconductor device 7 for the purpose of the temperature hierarchy. High lead solder has 85 wt. Compared with Sn-Pb eutectic solder prohibited by the RoHS Directive that has been in force since July 2006, it contains a large amount of lead.
　よって、高鉛はんだに替わる代替接続材の開発が切望されている。 Therefore, development of an alternative connection material to replace high lead solder is eagerly desired.
　現在、既に開発されているＳｎ－Ａｇ－Ｃｕ系等のはんだは融点が２６０℃以下であるため、半導体素子１のダイボンディングに使用した場合、リフローはんだ付け（最高温度２６０℃）の際にはんだが溶融してしまう。接続部周りが樹脂モールドされている場合、内部のはんだ３が溶融すると、溶融時の体積膨張により、図１３に示すような、フラッシュといってポッティングレジン６とフレーム２界面からはんだ３が漏れ出すことがある。 Currently developed Sn—Ag—Cu solders have a melting point of 260 ° C. or lower, so when used for die bonding of the semiconductor element 1, the solder is used during reflow soldering (maximum temperature 260 ° C.). Will melt. When the periphery of the connecting portion is resin-molded, when the internal solder 3 melts, the solder 3 leaks from the interface between the potting resin 6 and the frame 2 as shown in FIG. 13 due to volume expansion at the time of melting. Sometimes.
　図１３は従来の半導体装置でのリフローはんだ付け後の状態を示す図である。 FIG. 13 is a view showing a state after reflow soldering in a conventional semiconductor device.
　また、漏れ出さないまでも、漏れ出そうと作用し、その結果、図１３に示すように、凝固後にはんだの中に大きなボイド８が形成され不良品となる。 Moreover, even if it does not leak, it acts to leak, and as a result, as shown in FIG. 13, a large void 8 is formed in the solder after solidification, resulting in a defective product.
　代替材料候補としては、融点の面からＡｕ－Ｓｎ、Ａｕ－Ｓｉ、Ａｕ－Ｇｅ等のＡｕ系はんだ、Ｚｎ、Ｚｎ－Ａｌ系のはんだおよびＢｉ、Ｂｉ－Ｃｕ、Ｂｉ－Ａｇ等のはんだが報告されており、世界中で検討が進められているが、汎用的に使用するには課題がある。 As alternative material candidates, Au-based solders such as Au-Sn, Au-Si, Au-Ge, Zn, Zn-Al solders, and solders such as Bi, Bi-Cu, Bi-Ag, etc. are reported in terms of melting point. Although being studied all over the world, there are problems in using it for general purposes.
　Ａｕ系のはんだは構成成分としてＡｕを８０ｗｔ．％以上含有しており、コストの面で汎用性に難がある。Ｂｉ系はんだは、熱伝導率が約９Ｗ／ｍＫと現行の高鉛はんだより低く、高放熱性が要求される半導体装置への適用は難しいと推定できる。 Au-based solder is 80wt. % Or more, and there is difficulty in versatility in terms of cost. Bi-based solder has a thermal conductivity of about 9 W / mK, which is lower than that of current high-lead solder, and it can be estimated that it is difficult to apply it to semiconductor devices that require high heat dissipation.
　また、ＺｎおよびＺｎ－Ａｌ系はんだは、約１００Ｗ／ｍＫと高い熱伝導率を有するが、濡れにくい（特にＺｎ－Ａｌ系はんだ）、はんだが硬く接続後冷却時に熱応力によって半導体素子が破壊しやすい等の問題がある。 Zn and Zn—Al solder have a high thermal conductivity of about 100 W / mK, but they are difficult to wet (especially Zn—Al solder). The solder is hard and the semiconductor element is destroyed by thermal stress during cooling after connection. There are problems such as easy.
　高鉛はんだ代替材として、金属材料の他に導電性接着剤が挙げられる。これは樹脂とＡｇフィラーの混合物であり、高鉛はんだの代替材料としては、最も汎用的に使用されている。 As a high lead solder substitute material, a conductive adhesive is mentioned in addition to a metal material. This is a mixture of a resin and an Ag filler, and is most commonly used as an alternative material for high lead solder.
　ただし、金属接合ではなく、フィラー間の接触により熱伝導するため、高い熱伝導率を得るためには、Ａｇフィラー含有量を高くする必要がある。その場合、接着を担う樹脂の量を減らさなければならなくなり、十分な接着強度を得ることが難しくなる。また、Ａｇの含有率を９０％以上に高めたとしても熱伝導率を約１０Ｗ／ｍＫ程度であり、高鉛はんだの熱伝導率約３０Ｗ／ｍＫには及ばない。 However, since heat conduction is performed not by metal bonding but by contact between fillers, it is necessary to increase the Ag filler content in order to obtain high thermal conductivity. In that case, the amount of resin responsible for adhesion must be reduced, making it difficult to obtain sufficient adhesion strength. Further, even if the Ag content is increased to 90% or more, the thermal conductivity is about 10 W / mK, which is less than the thermal conductivity of high lead solder of about 30 W / mK.
　このような問題点を解決するための、従来では、例えば、特開２００７－１８１８８０号公報（特許文献１）に記載されたものがあった。これは、Ｂｉ－０．０１～５７質量％Ｓｎを用いることで、はんだ凝固時の体積収縮を防止し、貫通型セラミックコンデンサの内面電極と構造体の孔内壁との界面や構造体の内部へのクラックを抑止するものである。 Conventionally, for solving such problems, there has been one described in, for example, Japanese Patent Application Laid-Open No. 2007-181880 (Patent Document 1). This is because Bi-0.01 to 57 mass% Sn is used to prevent volume shrinkage during solidification of the solder, and to the interface between the inner surface electrode of the through-type ceramic capacitor and the hole inner wall of the structure or the inside of the structure. This is to prevent cracks.
特開２００７－１８１８８０号公報JP 2007-181880 A
　しかしながら、特許文献１に記載のものは、半導体装置に適用するには、以下の問題がある。 However, the one described in Patent Document 1 has the following problems when applied to a semiconductor device.
　Ｂｉ－０．０１～５７質量％Ｓｎは、半導体素子の電極に用いられるＮｉ層との反応性が高い。通常、半導体素子の裏面電極に厚さ０．５μｍから１μｍのＮｉ電極が使用される。このＮｉ電極は、はんだと半導体素子の接続を維持するために必要な層である。 Bi-0.01 to 57 mass% Sn has high reactivity with the Ni layer used for the electrode of the semiconductor element. Usually, a Ni electrode having a thickness of 0.5 μm to 1 μm is used as the back electrode of the semiconductor element. This Ni electrode is a layer necessary for maintaining the connection between the solder and the semiconductor element.
　特許文献１のＢｉ－０．０１～５７質量％Ｓｎで接続した場合、接続時にはんだと反応してＮｉメタライズが消失して界面強度が低下し、半導体素子が剥離するおそれがある。 When connecting with Bi-0.01 to 57 mass% Sn of Patent Document 1, Ni metallization disappears due to reaction with solder at the time of connection, and the interface strength may be reduced, and the semiconductor element may be peeled off.
　また、接続した半導体装置に熱衝撃が生じた場合、Ｂｉ－０．０１～５７質量％Ｓｎは、Ｂｉが脆性材料であるため、母材の強度が弱く、はんだ接続部にクラックが進展しやすい。 Further, when a thermal shock occurs in the connected semiconductor device, Bi-0.01 to 57 mass% Sn is weak in the strength of the base material because Bi is a brittle material, and cracks easily develop in the solder connection portion. .
　更に、特許文献１の場合、凝固時の体積膨張について考慮がなされていない。Ｂｉの含有率が高い場合、凝固時に体積膨張する。はんだの最終凝固部で体積膨張するため、リフローはんだ付けの加熱によって、はんだが溶融して体積収縮し、それが凝固して膨張した際に、元の形状に戻らない場合、半導体装置のモールド樹脂部、半導体素子等が破損するおそれがある。 Furthermore, in the case of Patent Document 1, no consideration is given to volume expansion during solidification. When the Bi content is high, volume expansion occurs during solidification. Since the solder expands in volume at the final solidified part of the solder, the solder melts and shrinks in volume due to the heat of reflow soldering. When it solidifies and expands, it does not return to its original shape. There is a risk of damage to parts, semiconductor elements, and the like.
　そこで、本発明の目的は、Ｓｎ－３７～６０質量％Ｂｉ－２～７質量％Ｃｕのはんだで半導体素子を接続し、はんだ溶融時の体積変化を０．５％以内にして、リフローはんだ付け時のフラッシュを抑止し、半導体素子接続界面の安定性を確保し、熱応力に対する接続信頼性を向上することができる半導体装置を提供することにある。 Accordingly, an object of the present invention is to connect a semiconductor element with a Sn-37 to 60 mass% Bi-2 to 7 mass% Cu solder, and to reduce the volume change when the solder is melted within 0.5%, and to perform reflow soldering. An object of the present invention is to provide a semiconductor device capable of preventing flashing of time, ensuring stability of a semiconductor element connection interface, and improving connection reliability against thermal stress.
　本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。 The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
　本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、次の通りである。 The outline of a representative one of the inventions disclosed in the present application will be briefly described as follows.
　すなわち、代表的なものの概要は、Ｎｉ電極を有する半導体素子を、Ｓｎ－Ｂｉ－Ｃｕ系鉛フリーはんだでＮｉ系めっきを施したフレームに接続し、その周囲を樹脂で封止したものである。 That is, a typical outline is that a semiconductor element having a Ni electrode is connected to a frame plated with Ni with Sn—Bi—Cu based lead-free solder, and the periphery thereof is sealed with resin.
　本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば以下の通りである。 Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
　すなわち、代表的なものによって得られる効果は、Ｓｎ－３７～６０質量％Ｂｉ－２～７質量％Ｃｕを半導体素子の接続に適用することにより、リフローはんだ付け時のフラッシュを抑止できる。また、２～７質量％Ｃｕの添加により、接続時およびリフローはんだ付け時の半導体素子接続界面の安定性を確保、熱応力に対する接続信頼性を向上ができる。 That is, the effect obtained by a typical one can suppress flashing during reflow soldering by applying Sn-37 to 60 mass% Bi-2 to 7 mass% Cu to the connection of the semiconductor element. In addition, the addition of 2 to 7% by mass of Cu ensures the stability of the semiconductor element connection interface during connection and reflow soldering, and improves connection reliability against thermal stress.
本発明の一実施の形態に係る半導体装置の半導体素子側の接続部の断面図である。It is sectional drawing of the connection part by the side of the semiconductor element of the semiconductor device which concerns on one embodiment of this invention. 本発明の一実施の形態に係る半導体装置のフレーム側の接続部の断面図である。It is sectional drawing of the connection part by the side of the frame of the semiconductor device which concerns on one embodiment of this invention. 本発明の一実施の形態に係る半導体装置の比較例となるＣｕを含まないＳｎ－Ｂｉ系鉛フリーはんだを使用した場合の半導体素子側の接続部の断面図である。It is sectional drawing of the connection part by the side of a semiconductor element at the time of using Sn-Bi type lead free solder which does not contain Cu used as the comparative example of the semiconductor device concerning one embodiment of the present invention. 本発明の一実施の形態に係る半導体装置の比較例となるＣｕを含まないＳｎ－Ｂｉ系鉛フリーはんだを使用した場合のフレーム側の接続部の断面図である。It is sectional drawing of the connection part by the side of a flame | frame at the time of using the Sn-Bi type | system | group lead free solder which does not contain Cu used as the comparative example of the semiconductor device which concerns on one embodiment of this invention. 本発明の一実施の形態に係る半導体装置の温度とはんだの体積膨張の関係を示す図である。It is a figure which shows the relationship between the temperature of the semiconductor device which concerns on one embodiment of this invention, and the volume expansion of a solder. 本発明の一実施の形態に係る半導体装置のＣｕ含有率と半導体素子のＮｉ電極消失厚さの関係を示す図である。It is a figure which shows the relationship between Cu content rate of the semiconductor device which concerns on one embodiment of this invention, and Ni electrode loss | disappearance thickness of a semiconductor element. 本発明の一実施の形態に係る半導体装置の実施例および比較例のはんだの組成と接続信頼性の関係を示す図である。It is a figure which shows the relationship between the solder composition and connection reliability of the Example of a semiconductor device which concerns on one embodiment of this invention, and a comparative example. 本発明の一実施の形態に係る半導体装置の実施例での接続状態を示す図である。It is a figure which shows the connection state in the Example of the semiconductor device which concerns on one embodiment of this invention. 本発明の一実施の形態に係る半導体装置のクラックの状態を示す図である。It is a figure which shows the state of the crack of the semiconductor device which concerns on one embodiment of this invention. 本発明の一実施の形態に係る半導体装置の比較例でのクラックの状態を示す図である。It is a figure which shows the state of the crack in the comparative example of the semiconductor device which concerns on one embodiment of this invention. 本発明の一実施の形態に係る半導体装置の比較例でのボイドの発生を示す図である。It is a figure which shows generation | occurrence | production of the void in the comparative example of the semiconductor device which concerns on one embodiment of this invention. 従来の半導体装置の構成を示す構成図である。It is a block diagram which shows the structure of the conventional semiconductor device. 従来の半導体装置でのリフローはんだ付け後の状態を示す図である。It is a figure which shows the state after reflow soldering in the conventional semiconductor device.
　以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の部材には原則として同一の符号を付し、その繰り返しの説明は省略する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.
　図１～図６により、本発明の一実施の形態に係る半導体装置の構成について説明する。図１は本発明の一実施の形態に係る半導体装置の半導体素子側の接続部の断面図、図２は本発明の一実施の形態に係る半導体装置のフレーム側の接続部の断面図、図３は本発明の一実施の形態に係る半導体装置の比較例となるＣｕを含まないＳｎ－Ｂｉ系鉛フリーはんだを使用した場合の半導体素子側の接続部の断面図、図４は本発明の一実施の形態に係る半導体装置の比較例となるＣｕを含まないＳｎ－Ｂｉ系鉛フリーはんだを使用した場合のフレーム側の接続部の断面図、図５は本発明の一実施の形態に係る半導体装置の温度とはんだの体積膨張の関係を示す図、図６は本発明の一実施の形態に係る半導体装置のＣｕ含有率と半導体素子のＮｉ電極消失厚さの関係を示す図である。 A configuration of a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 is a cross-sectional view of a connection portion on the semiconductor element side of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a connection portion on the frame side of the semiconductor device according to the embodiment of the present invention. 3 is a cross-sectional view of the connection portion on the semiconductor element side when Sn—Bi based lead-free solder not containing Cu is used as a comparative example of the semiconductor device according to one embodiment of the present invention, and FIG. FIG. 5 is a cross-sectional view of a connection portion on the frame side when Sn—Bi-based lead-free solder not containing Cu is used as a comparative example of the semiconductor device according to the embodiment, and FIG. 5 relates to the embodiment of the present invention. FIG. 6 is a diagram showing the relationship between the temperature of the semiconductor device and the volume expansion of solder, and FIG. 6 is a diagram showing the relationship between the Cu content of the semiconductor device according to one embodiment of the present invention and the Ni electrode disappearance thickness of the semiconductor element.
　本実施の形態では、Ｓｎ系鉛フリーはんだを使用しても、上記の図１３に示すようなフラッシュを防止できないかと考え、フラッシュは、Ｓｎ－Ａｇ－Ｃｕ等の鉛フリーはんだがリフローはんだ付けの際に溶融して、約３％の体積膨張を起こすことによって発生するので、溶融する際の体積変化が小さなＳｎ－Ｂｉ－Ｃｕはんだで半導体素子１を接続することによって、フラッシュを抑制するようにしたものである。 In this embodiment, it is thought that even if Sn-based lead-free solder is used, flash as shown in FIG. 13 can be prevented, and lead-free solder such as Sn-Ag-Cu is reflow soldered. When the semiconductor element 1 is connected with Sn—Bi—Cu solder, the volume change upon melting is suppressed, so that flash is suppressed. It is a thing.
　上記の図１２に示すような半導体装置において、Ｓｎ－Ｂｉ－Ｃｕ系鉛フリーはんだで半導体素子を接続することによって、図１および図２に示すように、半導体素子１のＮｉ電極１４とフレーム２のＮｉめっき１２上に（Ｃｕ，Ｎｉ）６Ｓｎ５を含む金属間化合物層１１を形成することができる。 In the semiconductor device as shown in FIG. 12, by connecting the semiconductor elements with Sn—Bi—Cu based lead-free solder, the Ni electrode 14 and the frame 2 of the semiconductor element 1 are connected as shown in FIGS. An intermetallic compound layer 11 containing (Cu, Ni) 6 Sn 5 can be formed on the Ni plating 12.
　これが、半導体素子１のＮｉ電極１４およびＮｉめっき１２の消失を防ぐバリア層として機能する。また、はんだ内部に析出した（Ｃｕ，Ｎｉ）６Ｓｎ５を含む金属間化合物１１’は、母相であるＳｎ－Ｂｉを強化している。 This functions as a barrier layer that prevents disappearance of the Ni electrode 14 and the Ni plating 12 of the semiconductor element 1. In addition, the intermetallic compound 11 ′ containing (Cu, Ni) 6 Sn 5 precipitated inside the solder reinforces Sn—Bi that is the parent phase.
　一方、比較例として、従来のＣｕを含まないＳｎ－Ｂｉ系鉛フリーはんだで接続した場合、半導体素子１側の接続界面において、接続時に半導体素子１のＮｉ電極が消失したために、図３の２１に示すような接続界面の剥離が発生するおそれがあり、また、図４に示すフレーム２側界面においては、Ｎｉ３Ｓｎ４化合物１３を形成しており、Ｃｕを添加した場合と異なる化合物層が形成されてしまう。 On the other hand, as a comparative example, when connecting with conventional Sn-Bi lead-free solder not containing Cu, the Ni electrode of the semiconductor element 1 disappears at the connection interface on the semiconductor element 1 side at the time of connection. As shown in FIG. 4, the interface of the connection interface may be peeled off. Further, the Ni 3 Sn 4 compound 13 is formed at the interface on the frame 2 side shown in FIG. Will be formed.
　本実施の形態では、Ｓｎ－Ｂｉが母合金であるため、はんだ溶融時の体積変化をＳｎ－３Ａｇ－０．５Ｃｕ等のＳｎ－ｒｉｃｈな鉛フリーはんだに比べて、小さくすることができる。また、リフローはんだ付けを行う２６０℃における体積膨張もＳｎ－ｒｉｃｈな鉛フリーはんだに比べて小さくすることができる。 In this embodiment, since Sn—Bi is a mother alloy, the volume change at the time of melting the solder can be made smaller than that of Sn-rich lead-free solder such as Sn-3Ag-0.5Cu. In addition, the volume expansion at 260 ° C. in which reflow soldering is performed can be reduced as compared with Sn-rich lead-free solder.
　図５は、Ｓｎ－４８Ｂｉ－５Ｃｕと、Ｓｎ－ｒｉｃｈなはんだと、Ｓｎ－５８Ｂｉの温度と体積膨張の関係を示した図である。Ｓｎ－ｒｉｃｈなはんだの場合、溶融により約３％の体積膨張が生じるのに対し、Ｓｎ－４８Ｂｉ－５ＣｕおよびＳｎ－５８Ｂｉの場合、１％未満の体積膨張となる。また、リフローはんだ付けを行う２６０℃において、Ｓｎ－ｒｉｃｈなはんだの室温からの体積膨張が約４．５％であるのに対し、Ｓｎ－４８Ｂｉ－５ＣｕおよびＳｎ－５８Ｂｉでは約２％となる。 FIG. 5 is a diagram showing the relationship between the temperature and volume expansion of Sn-48Bi-5Cu, Sn-rich solder, and Sn-58Bi. In the case of Sn-rich solder, the volume expansion of about 3% is caused by melting, whereas in the case of Sn-48Bi-5Cu and Sn-58Bi, the volume expansion is less than 1%. Further, at 260 ° C. in which reflow soldering is performed, the volume expansion of Sn-rich solder from room temperature is about 4.5%, while that of Sn-48Bi-5Cu and Sn-58Bi is about 2%.
　以上のことから、Ｎｉ電極１４を有する半導体素子１がＳｎ－Ｂｉ－Ｃｕ系鉛フリーはんだでＮｉ系めっきを施したフレーム２に接続することにより、接続界面の安定性、接続部の母相強化するのと同時に、はんだフラッシュを抑制できる。 From the above, when the semiconductor element 1 having the Ni electrode 14 is connected to the frame 2 plated with Ni with Sn—Bi—Cu-based lead-free solder, the stability of the connection interface and the strengthening of the mother phase of the connection portion are achieved. At the same time, solder flash can be suppressed.
　図６は、Ｎｉ電極１４の厚さが０．５μｍの半導体素子１を接続条件３５０℃１ｍｉｎ．で接続したときのＮｉ電極１４の消失量を示したグラフである。横軸は、Ｓｎ－Ｂｉ－Ｃｕ合金のＣｕ含有率を示している。Ｃｕ含有率が２質量％以上の場合、０．５μｍのＮｉ電極１４が消失することなく接続できる。 FIG. 6 shows that the semiconductor element 1 having a Ni electrode 14 thickness of 0.5 μm is connected at 350 ° C. for 1 min. It is the graph which showed the loss | disappearance amount of the Ni electrode 14 when it connects by. The horizontal axis represents the Cu content of the Sn—Bi—Cu alloy. When the Cu content is 2% by mass or more, the 0.5 μm Ni electrode 14 can be connected without disappearing.
　ただし、Ｃｕ含有率が７質量％以上になると、はんだの液相線温度が４００℃以上となり、半導体装置のはんだ接続を行う３５０℃で濡れ性が低下してはんだ未濡れ部が発生しやすくなる。 However, when the Cu content is 7% by mass or more, the liquidus temperature of the solder is 400 ° C. or higher, and the wettability is reduced at 350 ° C. where the solder connection of the semiconductor device is performed, and the solder non-wetting portion is likely to occur. .
　また、Ｓｎ－Ｂｉ－Ｃｕ合金の組成をＳｎ－３７～６０質量％Ｂｉ－２～７質量％Ｃｕとすることにより、溶融時の体積変化を５％以内にすることができる。 In addition, when the composition of the Sn—Bi—Cu alloy is Sn-37 to 60 mass% Bi-2 to 7 mass% Cu, the volume change at the time of melting can be made within 5%.
　したがって、Ｓｎ－３７～６０質量％Ｂｉ－２～７質量％Ｃｕのはんだ使用することにより、Ｎｉ層の消失を抑制し、リフローはんだ付け時のフラッシュを抑止することができる。 Therefore, by using Sn-37 to 60 mass% Bi-2 to 7 mass% Cu solder, disappearance of the Ni layer can be suppressed and flashing during reflow soldering can be suppressed.
　また、図６に示すＳｎ－Ｂｉ－Ｃｕ合金のＣｕ含有率とＮｉ電極消失厚さの関係を見ると、Ｃｕ含有率が５質量％以上になると、Ｎｉ電極消失抑制効果が大きく向上することが分かる。 Further, when the relationship between the Cu content of the Sn—Bi—Cu alloy and the Ni electrode disappearance thickness shown in FIG. 6 is seen, when the Cu content is 5% by mass or more, the Ni electrode disappearance suppression effect is greatly improved. I understand.
　このことから、Ｃｕ含有率５質量％以上にすることが望ましい。ただし、Ｃｕ含有率が７質量％以上になると、はんだの液相線温度が４００℃以上となり、半導体装置のはんだ接続を行う３５０℃で濡れ性が低下してはんだ未濡れ部が発生しやすくなる。 Therefore, it is desirable that the Cu content is 5% by mass or more. However, when the Cu content is 7% by mass or more, the liquidus temperature of the solder is 400 ° C. or higher, and the wettability is reduced at 350 ° C. where the solder connection of the semiconductor device is performed, and the solder non-wetting portion is likely to occur. .
　したがって、Ｓｎ－３７～６０質量％Ｂｉ－５～７質量％Ｃｕのはんだ使用することにより、Ｎｉ層の消失をより抑制し、リフローはんだ付け時のフラッシュを抑止することができる。 Therefore, by using Sn-37 to 60 mass% Bi-5 to 7 mass% Cu solder, disappearance of the Ni layer can be further suppressed, and flashing during reflow soldering can be suppressed.
　また、本実施の形態では、Ｎｉ系めっきとしてＮｉ、Ｎｉ－Ｐ、Ｎｉ－Ｂ等のめっき、あるいはその上にＡｕ、Ａｇ、Ｐｄのうちの少なくとも１つのめっきを施すようになっている。 In the present embodiment, Ni, Ni—P, Ni—B or the like is plated as Ni-based plating, or at least one of Au, Ag, and Pd is applied thereon.
　Ｎｉ系めっきは、Ｓｎ系はんだに対して十分な濡れを確保することができ、Ｎｉ系めっき上に（Ｃｕ，Ｎｉ）－Ｓｎ化合物主体のバリア層が形成される。また、Ｎｉ、Ｎｉ－Ｐ、Ｎｉ－Ｂ等のめっき上にＡｕめっき、Ａｇめっきを施すことにより、濡れを向上させることも可能である。 Ni-based plating can ensure sufficient wetting with respect to Sn-based solder, and a barrier layer mainly composed of (Cu, Ni) -Sn compound is formed on the Ni-based plating. In addition, wetting can be improved by applying Au plating or Ag plating on the plating of Ni, Ni—P, Ni—B or the like.
　その場合、Ａｕ、Ａｇといっためっき層は接続時にはんだ内部に全て拡散させることにより、下地のＮｉ系めっき上に（Ｃｕ，Ｎｉ）－Ｓｎ化合物主体のバリア層を形成することができる。 In this case, a plating layer such as Au or Ag is diffused in the solder at the time of connection, so that a barrier layer mainly composed of (Cu, Ni) -Sn compound can be formed on the underlying Ni-based plating.
　また、はんだの供給形態は、箔、ワイヤ、ペーストのいずれの形状で供給した場合でも、はんだフラッシュおよび半導体素子接続界面の安定性、Ｓｎ－Ｂｉ母相の化合物による強化ができる。接続環境に応じた供給方法を選択することが可能である。 Also, the solder supply form can be strengthened by the solder flash and the stability of the semiconductor element connection interface, and the Sn—Bi matrix phase compound, regardless of the supply form of foil, wire, or paste. It is possible to select a supply method according to the connection environment.
　また、封止にポッティングレジンを用いることで、レジンをはんだの固相線温度以上で硬化させた場合にも、接続状態を維持することができる。 Also, by using a potting resin for sealing, the connected state can be maintained even when the resin is cured at a temperature higher than the solidus temperature of the solder.
　次に、図７～図１１により、本発明の一実施の形態に係る半導体装置の実施例について説明する。図７は本発明の一実施の形態に係る半導体装置の実施例および比較例のはんだの組成と接続信頼性の関係を示す図、図８は本発明の一実施の形態に係る半導体装置の実施例での接続状態を示す図、図９は本発明の一実施の形態に係る半導体装置のクラックの状態を示す図、図１０は本発明の一実施の形態に係る半導体装置の比較例でのクラックの状態を示す図、図１１は本発明の一実施の形態に係る半導体装置の比較例でのボイドの発生を示す図である。 Next, examples of the semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. FIG. 7 is a diagram showing the relationship between the solder composition and the connection reliability in the example of the semiconductor device according to the embodiment of the present invention and the comparative example, and FIG. 8 is the implementation of the semiconductor device according to the embodiment of the present invention. FIG. 9 is a diagram illustrating a connection state in an example, FIG. 9 is a diagram illustrating a crack state of a semiconductor device according to an embodiment of the present invention, and FIG. 10 is a comparative example of a semiconductor device according to an embodiment of the present invention. FIG. 11 is a diagram showing a state of cracks, and FIG. 11 is a diagram showing generation of voids in a comparative example of a semiconductor device according to an embodiment of the present invention.
　図７に示す実施例１～９は、上記の図１２に示す半導体装置７を作製し、リフローはんだ付け時のフラッシュの有無およびクラック進展による接続信頼性の判定を行った。半導体装置７は、以下のように作製した。 In Examples 1 to 9 shown in FIG. 7, the semiconductor device 7 shown in FIG. 12 was manufactured, and the presence / absence of flash at the time of reflow soldering and the connection reliability based on crack progress were determined. The semiconductor device 7 was produced as follows.
　まず、Ｓｉ側からＴｉ／Ｎｉ（０．５μｍ）／フラッシュＡｕのメタライズを有するサイズ３ｍｍ×３ｍｍの半導体素子１を、図７に示すはんだ組成のはんだ３を用いて、Ｎ２＋４％Ｈ２雰囲気中、３５０℃１ｍｉｎ．の条件で、Ｎｉめっきのフレーム２に接続した。 First, a semiconductor element 1 having a size of 3 mm × 3 mm having a metallization of Ti / Ni (0.5 μm) / flash Au from the Si side is applied to a N 2 + 4% H 2 atmosphere using solder 3 having a solder composition shown in FIG. Medium, 350 ° C. for 1 min. The Ni-plated frame 2 was connected under the following conditions.
　その後、半導体素子１の上面の電極とフレーム２の端子５の間をワイヤ４でワイヤボンディングした。更に、ワイヤボンディングをした後、周囲を金属製の型で囲み、ポッティングレジン６を流し込み、大気中、１５０℃２ｈの条件でレジンを硬化させた。 Thereafter, wire bonding was performed between the electrode on the upper surface of the semiconductor element 1 and the terminal 5 of the frame 2 with a wire 4. Further, after wire bonding, the periphery was surrounded by a metal mold, and a potting resin 6 was poured in, and the resin was cured in the atmosphere at 150 ° C. for 2 hours.
　なお、ポッティングレジン６は、モールド樹脂などの他のレジンを用いてもよい。 The potting resin 6 may be another resin such as a mold resin.
　また、半導体素子１の上面と端子間５との接続はリボンボンディングを使用してもよい。 Further, ribbon bonding may be used for connection between the upper surface of the semiconductor element 1 and the inter-terminal 5.
　実施例１～９について、最高温度２６０℃以上でリフロープロセスを３回行い、はんだフラッシュ発生の有無を評価した結果を図７に示す。 For Examples 1 to 9, the reflow process was performed three times at a maximum temperature of 260 ° C. or higher, and the results of evaluating the presence or absence of solder flash are shown in FIG.
　実施例１～９のいずれにおいても、フラッシュは発生しなかった。図８に、Ｓｎ－４８Ｂｉ－５Ｃｕのリフロー試験後の接続部断面を示す。はんだ３が流出することなく、半導体素子１の接続を維持していることを確認できる。 In any of Examples 1 to 9, no flash occurred. FIG. 8 shows a cross section of the connection part after the reflow test of Sn-48Bi-5Cu. It can be confirmed that the connection of the semiconductor element 1 is maintained without the solder 3 flowing out.
　実施例１～９について、－４０℃⇔１２５℃の条件で温度サイクル試験を１０００サイクル行った結果をクラック接続信頼性として図７に示す。 For Examples 1 to 9, the results of 1000 cycles of the temperature cycle test under the condition of −40 ° C. to 125 ° C. are shown as crack connection reliability in FIG.
　１０００サイクル後に元の接続面積の８０％以上で接続を維持したものを○、接続面積が８０％未満になった場合を×とした。実施例１～９いずれの場合も試験前後で接続面積は変化しなかった。 ◯ indicates that the connection is maintained at 80% or more of the original connection area after 1000 cycles, and x indicates that the connection area is less than 80%. In any of Examples 1 to 9, the connection area did not change before and after the test.
　このとき、いずれも図９に示すように、半導体素子１とはんだ接続部端部からクラック２３が入り、はんだ３内部を進展した。このようにクラック２３ははんだ３の内部を進展するので、剥離などの問題は発生しない。 At this time, as shown in FIG. 9, cracks 23 entered from the end portions of the semiconductor element 1 and the solder connection portion, and the inside of the solder 3 progressed. As described above, since the crack 23 propagates inside the solder 3, problems such as peeling do not occur.
　一方、比較例１の場合、リフロー試験ではフラッシュは発生しなかった。ただし、半導体素子１とはんだ３の接続界面において、図３に示すような剥離２１が局所的に発生した。これを温度サイクル試験したところ、１０００サイクル後の接続面積が元の面積の約６０％となり、高い接続信頼性が得られなかった。 On the other hand, in the case of Comparative Example 1, flash did not occur in the reflow test. However, peeling 21 as shown in FIG. 3 locally occurred at the connection interface between the semiconductor element 1 and the solder 3. When this was subjected to a temperature cycle test, the connection area after 1000 cycles was about 60% of the original area, and high connection reliability was not obtained.
　このとき、図１０に示すように、クラック２３は半導体素子１とはんだ接続部を伝うように直線的に進展した。これは、Ｃｕの含有率が低いため、実施例１～９のように接続界面に（Ｃｕ，Ｎｉ）６Ｓｎ５を含む金属間化合物層１１を形成しないため、はんだ母相（Ｃｕ，Ｎｉ）６Ｓｎ５が析出していないためである。このように比較例１では、クラック２３は半導体素子１とはんだ接続部を伝うように直線的に進展してしまうので、剥離などの問題は発生しやすくなり、接続性が悪くなってしまう。 At this time, as shown in FIG. 10, the crack 23 linearly propagated along the semiconductor element 1 and the solder connection portion. This is because the Cu content is low, and the intermetallic compound layer 11 containing (Cu, Ni) 6 Sn 5 is not formed at the connection interface as in Examples 1 to 9, so the solder matrix (Cu, Ni) is not formed. This is because 6 Sn 5 is not precipitated. As described above, in Comparative Example 1, since the crack 23 linearly propagates along the semiconductor element 1 and the solder connection portion, problems such as peeling easily occur and the connectivity is deteriorated.
　また、比較例２～４については、いずれもリフロー試験において、フラッシュが発生した。図１１にリフロー試験後のＳｎ－３Ａｇ－０．５Ｃｕによる接続部を示す。はんだが溶融して流出したことにより、ボイドが生成していることを確認できる。 Further, in Comparative Examples 2 to 4, flashing occurred in the reflow test. FIG. 11 shows a connection portion made of Sn-3Ag-0.5Cu after the reflow test. It can be confirmed that voids are generated by melting and flowing out of the solder.
　以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。 As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
　本発明は、はんだを使用して半導体素子をフレーム上に接続する半導体装置に広く適用可能である。 The present invention is widely applicable to semiconductor devices in which a semiconductor element is connected on a frame using solder.
　１…半導体素子、２…フレーム、３…はんだ、４…ワイヤ、５…端子、６…ポッティングレジン、７…半導体装置、８…ボイド、１１…（Ｃｕ，Ｎｉ）６Ｓｎ５を含む金属間化合物層、１２…Ｎｉめっき、１３…Ｎｉ３Ｓｎ４化合物、１４…Ｎｉ電極、２１…剥離、２３…クラック。 1 ... semiconductor device, 2 ... frame, 3 ... solder, 4 ... wire, 5 ... terminal, 6 ... potting resin, 7 ... semiconductor device, 8 ... void, 11 ... (Cu, Ni) intermetallic compounds containing 6 Sn 5 Layer, 12 ... Ni plating, 13 ... Ni 3 Sn 4 compound, 14 ... Ni electrode, 21 ... peeling, 23 ... crack.

Claims (11)

  1. 　第１の部材と、
    　第２の部材と、
    　前記第１の部材と前記第２の部材とを接続するはんだと、
    　前記はんだの周囲を封止するレジンとを備えた半導体装置において、
    　前記第１の部材は、前記はんだに接続される表面がＮｉであり、
    　前記はんだは、Ｓｎ－Ｂｉ－Ｃｕ系鉛フリーはんだであることを特徴とする半導体装置。     A first member;
    A second member;
    Solder for connecting the first member and the second member;
    In a semiconductor device comprising a resin for sealing the periphery of the solder,
    In the first member, the surface connected to the solder is Ni,
    The semiconductor device is characterized in that the solder is Sn—Bi—Cu based lead-free solder.
  2. 　請求項１に記載の半導体装置において、
    　前記第１の部材表面のＮｉ上に（Ｃｕ，Ｎｉ）６Ｓｎ５化合物が形成されていることを特徴とする半導体装置。     The semiconductor device according to claim 1,
    A semiconductor device characterized in that a (Cu, Ni) 6 Sn 5 compound is formed on Ni on the surface of the first member.
  3. 　請求項１または２に記載の半導体装置において、
    　前記第２の部材は、前記はんだに接続される表面がＮｉであり、
    　当該Ｎｉ上に（Ｃｕ，Ｎｉ）６Ｓｎ５化合物が形成されていることを特徴とする半導体装置。     The semiconductor device according to claim 1 or 2,
    The surface of the second member connected to the solder is Ni,
    A semiconductor device, wherein a (Cu, Ni) 6 Sn 5 compound is formed on the Ni.
  4. 　請求項１乃至３のいずれか１項に記載の半導体装置において、
    　前記Ｓｎ－Ｂｉ－Ｃｕ系鉛フリーはんだは、Ｂｉを３７～６０質量％含むはんだであることを特徴とする半導体装置。     The semiconductor device according to any one of claims 1 to 3,
    The Sn—Bi—Cu-based lead-free solder is a solder containing 37 to 60% by mass of Bi.
  5. 　請求項２または３に記載の半導体装置において、
    　前記Ｓｎ－Ｂｉ－Ｃｕ系鉛フリーはんだは、Ｂｉを３７～６０質量％含むはんだであり、
    　前記第１の部材または第２の部材は、前記（Ｃｕ，Ｎｉ）６Ｓｎ５化合物を介して前記Ｓｎ－Ｂｉ－Ｃｕ系鉛フリーはんだに接続されていることを特徴とする半導体装置。     The semiconductor device according to claim 2 or 3,
    The Sn—Bi—Cu-based lead-free solder is a solder containing 37 to 60% by mass of Bi,
    The semiconductor device, wherein the first member or the second member is connected to the Sn—Bi—Cu-based lead-free solder via the (Cu, Ni) 6 Sn 5 compound.
  6. 　請求項１に記載の半導体装置において、
    　前記表面がＮｉの第１の部材及び第２の部材は、半導体素子、電極のいずれかであり、その材質がＮｉである、またはＮｉめっきを有することを特徴とする半導体装置。     The semiconductor device according to claim 1,
    The first member and the second member whose surfaces are Ni are either a semiconductor element or an electrode, and the material thereof is Ni or Ni plating.
  7. 　請求項１に記載の半導体装置において、
    　前記Ｎｉ系めっきは、Ｎｉ、Ｎｉ－Ｐ、Ｎｉ－Ｂのめっきのいずれかであり、その上にＡｕ、Ａｇ、Ｐｄのうちの少なくとも１つのめっきを有することを特徴とする半導体装置。     The semiconductor device according to claim 1,
    The Ni-based plating is any one of Ni, Ni—P, and Ni—B, and has at least one of Au, Ag, and Pd thereon.
  8. 　第１の部材と第２の部材とをはんだにより接続する接続工程と、
    　前記接続後に、レジンにより前記はんだの周囲を封止する封止工程とを含む半導体装置の製造方法において、
    　前記第１の部材は、前記はんだに接続される表面がＮｉであり、
    　前記はんだは、Ｓｎ－Ｂｉ－Ｃｕ系鉛フリーはんだであることを特徴とする半導体装置の製造方法。     A connecting step of connecting the first member and the second member by solder;
    In the manufacturing method of a semiconductor device including a sealing step of sealing the periphery of the solder with a resin after the connection,
    In the first member, the surface connected to the solder is Ni,
    The method of manufacturing a semiconductor device, wherein the solder is Sn—Bi—Cu based lead-free solder.
  9. 　請求項８に記載の半導体装置の製造方法において、
    　前記接続工程では、前記第１の部材表面のＮｉ上に、（Ｃｕ，Ｎｉ）６Ｓｎ５化合物が析出して当該表面のＮｉを覆うことを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 8,
    In the connecting step, a (Cu, Ni) 6 Sn 5 compound is deposited on Ni on the surface of the first member to cover Ni on the surface.
  10. 　請求項８または９に記載の半導体装置の製造方法において、
    　前記Ｓｎ－Ｂｉ－Ｃｕ系鉛フリーはんだは、Ｂｉを３７～６０質量％、Ｃｕを２～７質量％含むはんだであることを特徴とする半導体装置の製造方法。     In the manufacturing method of the semiconductor device according to claim 8 or 9,
    The method of manufacturing a semiconductor device, wherein the Sn—Bi—Cu-based lead-free solder is a solder containing 37 to 60% by mass of Bi and 2 to 7% by mass of Cu.
  11. 　請求項１０に記載の半導体装置の製造方法において、
    　前記Ｓｎ－Ｂｉ－Ｃｕ系鉛フリーはんだは、Ｃｕを５～７質量％含むはんだであることを特徴とする半導体装置の製造方法。
          In the manufacturing method of the semiconductor device according to claim 10,
    The semiconductor device manufacturing method, wherein the Sn—Bi—Cu-based lead-free solder is a solder containing 5 to 7 mass% of Cu.
PCT/JP2010/060105 2009-07-01 2010-06-15 Semiconductor device and method for manufacturing semiconductor device WO2011001818A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009-157248 2009-07-01
JP2009157248A JP2011014705A (en) 2009-07-01 2009-07-01 Semiconductor device and method of manufacturing the same

Publications (1)

Publication Number Publication Date
WO2011001818A1 true WO2011001818A1 (en) 2011-01-06

Family

ID=43410897

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2010/060105 WO2011001818A1 (en) 2009-07-01 2010-06-15 Semiconductor device and method for manufacturing semiconductor device

Country Status (2)

Country Link
JP (1) JP2011014705A (en)
WO (1) WO2011001818A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6543890B2 (en) * 2014-04-14 2019-07-17 富士電機株式会社 High temperature solder alloy
CN111630646A (en) * 2018-12-28 2020-09-04 Ｊｘ金属株式会社 Solder joint

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH071179A (en) * 1993-06-16 1995-01-06 Internatl Business Mach Corp <Ibm> Lead-free tin - bismuth solder
JP2001284792A (en) * 2000-03-30 2001-10-12 Tanaka Electronics Ind Co Ltd Solder material and method for manufacturing semiconductor device using the same
JP2004533327A (en) * 2001-05-28 2004-11-04 ハネウエル・インターナシヨナル・インコーポレーテツド High temperature lead-free solder compositions, methods and devices
JP2007123566A (en) * 2005-10-28 2007-05-17 Fuji Electric Holdings Co Ltd Semiconductor device and its manufacturing method
JP2009060101A (en) * 2000-12-21 2009-03-19 Hitachi Ltd Electronic device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH071179A (en) * 1993-06-16 1995-01-06 Internatl Business Mach Corp <Ibm> Lead-free tin - bismuth solder
JP2001284792A (en) * 2000-03-30 2001-10-12 Tanaka Electronics Ind Co Ltd Solder material and method for manufacturing semiconductor device using the same
JP2009060101A (en) * 2000-12-21 2009-03-19 Hitachi Ltd Electronic device
JP2004533327A (en) * 2001-05-28 2004-11-04 ハネウエル・インターナシヨナル・インコーポレーテツド High temperature lead-free solder compositions, methods and devices
JP2007123566A (en) * 2005-10-28 2007-05-17 Fuji Electric Holdings Co Ltd Semiconductor device and its manufacturing method

Also Published As

Publication number Publication date
JP2011014705A (en) 2011-01-20

Similar Documents

Publication Publication Date Title
JP5045673B2 (en) Functional component lid and manufacturing method thereof
JP5280520B2 (en) Solder material and electronic component assembly
JP5463845B2 (en) Power semiconductor device and manufacturing method thereof
JP5943066B2 (en) Bonding method and manufacturing method of bonded structure
JP5278616B2 (en) Bi-Sn high temperature solder alloy
JP2002307188A (en) PRODUCT USING Zn-Al BASED SOLDER
JP2007123395A (en) Semiconductor device and method of manufacturing the same
JP2001230360A (en) Semiconductor integrated circuit device and method of manufacturing the same
KR20180130002A (en) Method for soldering surface-mount component and surface-mount component
JP2012209402A (en) Lead component, manufacturing method of the lead component, and semiconductor package
JP2006269903A (en) Lead frame for semiconductor device
JP5152125B2 (en) Connection material, method for manufacturing connection material, and semiconductor device
JP2005340268A (en) Transistor package
WO2011001818A1 (en) Semiconductor device and method for manufacturing semiconductor device
JP5723523B2 (en) Connecting material, manufacturing method of connecting material, semiconductor device, manufacturing method of semiconductor device, power module
JP2002185130A (en) Electronic circuit device and electronic part
JP2004034134A (en) Line-solder and process of producing electronic equipment
JP5738523B2 (en) Connection material, connection method, and manufacturing method of semiconductor device
JP2008034514A (en) Semiconductor device
JP2009158725A (en) Semiconductor device and die bonding material
WO2011030517A1 (en) Connecting material, semiconductor device and method for manufacturing semiconductor device
JP2012253242A (en) Joint structure
JP6543890B2 (en) High temperature solder alloy
JP2006352175A (en) Semiconductor integrated circuit device
WO2024038665A1 (en) Electronic device and method for manufacturing electronic device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10793988

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10793988

Country of ref document: EP

Kind code of ref document: A1