WO2010146752A1 - Shift resister, display-driving circuit, displaying panel, and displaying device - Google Patents
Shift resister, display-driving circuit, displaying panel, and displaying device Download PDFInfo
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- WO2010146752A1 WO2010146752A1 PCT/JP2010/001962 JP2010001962W WO2010146752A1 WO 2010146752 A1 WO2010146752 A1 WO 2010146752A1 JP 2010001962 W JP2010001962 W JP 2010001962W WO 2010146752 A1 WO2010146752 A1 WO 2010146752A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/06—Details of flat display driving waveforms
- G09G2310/061—Details of flat display driving waveforms for resetting or blanking
- G09G2310/063—Waveforms for resetting the whole screen at once
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
Definitions
- the present invention relates to a shift register and various display drivers.
- Patent Document 1 an output of each stage of a shift register included in a gate driver is input to a NAND circuit, a DCG signal is input to the NAND circuit, and an output of the NAND circuit is supplied to a scanning signal line.
- the structure to perform is disclosed. In this configuration, if the DCG signal is activated when the power of the liquid crystal display device is turned on / off, all scanning signal lines can be simultaneously selected and Vcom (common electrode potential) can be written to all pixels.
- Vcom common electrode potential
- Patent Document 2 a set-reset flip-flop and a gate circuit including an analog switch 43 and an N-channel transistor 45 are provided at each stage of a shift register included in a gate driver.
- a configuration is disclosed in which the clock signal CK is input to 43, the source of the N-channel transistor 44 is connected to VSS, and the output of each stage is supplied to the scanning signal line.
- Vcom common electrode potential
- Japanese Patent Publication Japanese Patent Laid-Open No. 2000-347627 (Publication Date: December 15, 2000)”
- An object of the present invention is to provide a shift register and various drivers capable of quickly selecting a plurality of signal lines simultaneously and initializing the shift register.
- This shift register is a shift register used in a display drive circuit that simultaneously selects a plurality of signal lines at a predetermined timing, for example, and a set / reset type flip-flop and a simultaneous selection signal are input to each stage, And a signal generation circuit that generates an output signal of its own stage using the output of the flip-flop.
- the output signal of each stage becomes active by the activation of the simultaneous selection signal and is active during the simultaneous selection.
- the output of the flip-flop is inactive during a period in which both the set signal and the reset signal are active.
- both the set signal and the reset signal input to each flip-flop are active.
- the flip-flops in each stage are initialized (inactive) during the simultaneous selection period. ) That is, the shift register is initialized during the simultaneous selection, and the simultaneous selection and the initialization of the shift register can be completed quickly. Further, the configuration for generating and transmitting the initialization signal for the shift register is not necessary, and various drivers including the shift register can be downsized.
- simultaneous selection of a plurality of signal lines and initialization of the shift register can be performed quickly.
- FIG. 1 is a schematic diagram illustrating a configuration of a liquid crystal display device according to a first embodiment.
- FIG. 2 is a circuit diagram showing a part of a shift register of the liquid crystal display device shown in FIG. 1.
- FIG. 3 is a circuit diagram (a) and a truth table (b) of a flip-flop of the shift register shown in FIG. 2.
- 3 is a timing chart illustrating a method for driving the liquid crystal display device of FIG. 1.
- FIG. 6 is a schematic diagram illustrating another configuration of the liquid crystal display device according to the first embodiment.
- FIG. 6 is a schematic diagram illustrating still another configuration of the liquid crystal display device according to the first embodiment.
- FIG. 7 is a circuit diagram showing each stage of the shift register of the liquid crystal display device shown in FIG. 6.
- FIG. 7 is a timing chart showing a method for driving the liquid crystal display device of FIG. 6.
- FIG. 7 is a circuit diagram showing each stage of the shift register of the liquid crystal display device shown in FIG. 6.
- FIG. 6 is a schematic diagram illustrating a configuration of a liquid crystal display device according to a second embodiment.
- FIG. 11 is a circuit diagram showing a part of a shift register of the liquid crystal display device shown in FIG. 10.
- FIG. 12A is a circuit diagram of a flip-flop of the shift register shown in FIG. 11 and a truth table (b).
- 11 is a timing chart showing a method for driving the liquid crystal display device of FIG. 10.
- FIG. 10 is a schematic diagram illustrating another configuration of the liquid crystal display device according to the second embodiment.
- FIG. 15 is a circuit diagram showing a part of a shift register of the liquid crystal display device shown in FIG. 14. 15 is a timing chart showing a method for driving the liquid crystal display device of FIG.
- FIG. 16 is a circuit diagram showing a specific configuration of the NAND of FIG. 15.
- FIG. 15A is another circuit diagram (a) of the flip-flop included in the shift register of FIGS. 10 and 14 and a truth table (b).
- FIG. 15A is another circuit diagram (a) of the flip-flop included in the shift register of FIGS. 10 and 14 and a truth table (b).
- FIG. 15A is another circuit diagram (a) of the flip-flop included in the shift register of FIGS. 10 and 14 and a truth table (b).
- FIG. 15A is another circuit diagram (a) of the flip-flop included in the shift register of FIGS. 10 and 14 and a truth table (b).
- FIG. 10 is a schematic diagram illustrating still another configuration of the liquid crystal display device according to the second embodiment.
- FIG. 22 is a circuit diagram showing a part of a shift register of the liquid crystal display device shown in FIG. 21. It is a timing chart which shows the drive method of the liquid crystal display device of FIG. It is a circuit diagram which shows the specific structure of NOR of FIG. It is a schematic diagram which shows the structure of the liquid crystal display device concerning this Embodiment 3.
- FIG. 26 is a circuit diagram showing each stage of the shift register of the liquid crystal display device shown in FIG. 25.
- FIG. 26 is a circuit diagram showing a D latch circuit of a G-CS driver of the liquid crystal display device shown in FIG. 25.
- FIG. 22 is a circuit diagram showing a part of a shift register of the liquid crystal display device shown in FIG. 21. It is a timing chart which shows the drive method of the liquid crystal display device of FIG. It is a circuit diagram which shows the specific structure of NOR of FIG. It is a schematic diagram
- FIG. 26 is a timing chart illustrating a driving method of the liquid crystal display device of FIG. 25.
- FIG. 26 is a timing chart illustrating a driving method of the liquid crystal display device of FIG. 25.
- It is a schematic diagram which shows the structure of the liquid crystal display device concerning this Embodiment 4.
- 31 is a timing chart showing a method for driving the liquid crystal display device of FIG. 30.
- 31 is a timing chart showing a method for driving the liquid crystal display device of FIG. 30.
- FIG. 16 is a circuit diagram showing each stage of the shift register of the liquid crystal display device shown in FIG. 15. It is a circuit diagram which shows the structure of the conventional shift register. It is a circuit diagram which shows the structure of the conventional shift register.
- a set signal (S signal or SB signal) is input to a set terminal (S terminal or SB terminal) of a set-reset type flip-flop (hereinafter abbreviated as FF as appropriate), and a reset terminal (R
- the reset signal (R signal or RB signal) is input to the terminal or RB terminal, the Q signal is output from the output terminal (Q terminal), and the QB signal is output from the inverted output terminal (QB terminal).
- FF set-reset type flip-flop
- VDD high potential side power supply
- VSS low potential side power supply
- S signal set signal
- R signal reset signal
- Q signal output signal
- SB set bar signal
- RB signal reset bar signal
- QB QB signal
- FIG. 1 is a circuit diagram showing a configuration of a liquid crystal display device 3a according to the present invention.
- the liquid crystal display device 3a includes a display unit DAR, a gate driver GD, a source driver SD, and a display control circuit DCC.
- the display control circuit DCC supplies the gate driver GD with an AONB signal (all ON signal), a gate start pulse GSP, a gate on enable signal GOE, and gate clock signals GCK1B and GCK2B.
- the display control circuit DCC supplies a source start pulse SSP, digital data DAT, a polarity signal POL, and a source clock signal SCK to the source driver SD.
- the gate driver GD includes a shift register SR having a plurality of stages.
- the output signal (OUT signal) from the i-stage SRi of the shift register is supplied to the scanning signal line Gi of the display unit DAR via the buffer.
- the OUT signal of the n stage SRn is supplied to the scanning signal line Gn via the buffer.
- the scanning signal line Gn is connected to the gate of a transistor connected to the pixel electrode in PIXn, and a storage capacitor (auxiliary capacitor) is formed between the pixel electrode in PIXn and the storage capacitor line CSn.
- one analog switch asw and an inverter are provided corresponding to one data signal line, the input of this inverter is connected to the AONB signal line, and the end of the data signal line is one of the continuity of the analog switch asw.
- the other conduction terminal of the analog switch asw is connected to the Vcom (common electrode potential) power source, the N channel side gate of the analog switch asw is connected to the output of the inverter, and the P channel side gate of the analog switch asw is Connected to AONB signal line.
- FIG. 2 is a circuit diagram showing a specific configuration of part of the shift register SR. As shown in the figure, each stage of the shift register includes a set / reset type flip-flop FF having an SB terminal and an R terminal, two analog switches ASW1 and ASW2, NAND, two inverters, and a CKB terminal.
- the OUT terminal of its own stage is connected to the SB terminal of the next stage via an inverter, and the OUT terminal of the next stage is connected to the R terminal of its own stage.
- the OUT terminal of the n stage SRn is connected to the SB terminal of the (n + 1) stage SRn + 1 via the inverter, and the OUT terminal of the (n + 1) stage SRn + 1 is connected to the R terminal of the n stage SRn.
- the GSPB signal is input to the SB terminal of the first stage SR1 of the shift register SR.
- odd-numbered CKB terminals and even-numbered CKB terminals are connected to different GCK lines (lines for supplying GCK).
- the CKB terminal of the n stage SRn is connected to the GCK2B signal line
- the CKB terminal of the (n + 1) stage SRn + 1 is connected to the GCK1B signal line.
- the flip-flop FF1 shown in FIG. 3 is used for the flip-flop FF of FIG.
- the flip-flop FF1 includes a P-channel transistor p84 and an N-channel transistor n84 that constitute a CMOS circuit, a P-channel transistor p85 and an N-channel transistor n85 that constitute a CMOS circuit, and P-channel transistors p81 and p82.
- N-channel transistors n82, n83, SB terminal, R terminal, Q terminal, QB terminal, p84 gate, n84 gate, p85 drain, n85 drain, and QB terminal are connected
- the drain of p84, the drain of n84, the drain of p81, the drain of n82, the gate of p85, the gate of n85, and the Q terminal are connected
- the source of n84 and the drain of n83 are connected
- the source of p84 And p83 drain connected The source of p81 and the drain of p82 are connected
- the SB terminal is connected to the gate of p82 and the gate of n83
- the R terminal is connected to the gate of n82, the gate of p81, and the gate of p83
- the source is connected to VSS
- the sources of p82, p83, and p85 are connected to VDD
- the sources of n82 and n83 are connected to VSS.
- p84, n84, p85 and n85 constitute a latch circuit LC
- p82 functions as a set transistor ST
- n82 functions as a reset transistor RT
- p83 and n83 function as a latch release transistor LRT
- p81 functions as a priority determination transistor PDT.
- FIG. 3B is a truth table of FF1.
- the Q signal of FF1 is low (inactive) during the period when the SB signal is high (inactive) and the R signal is high (active), and the SB signal is high (inactive).
- the SB signal is High (active)
- the SB signal is Low (active)
- the flip-flop FF1 when both the SB signal and the R signal become active, n82 is turned ON, the Q signal becomes Vss (Low), and the R signal (reset) has priority.
- FIG. 4 is a timing chart showing a driving method of the liquid crystal display device 3a.
- AONB is an AONB signal (all ON signal)
- GSPB is a gate start pulse bar signal
- GCK1B is a GCK1B signal
- GCK2B is a GCK2B signal
- the following display preparation operation is performed before the first frame (vertical scanning period) of the display image.
- the AONB signal is active (Low) for a predetermined period, and at each stage of the shift register SR, one input of the NAND becomes Low and the output of the NAND becomes High.
- the OUT signals at all stages become active (High), and all scanning signal lines are selected.
- Vcom is supplied to all the data signal lines.
- the SB signal input to the FF in each stage is active (Low) and the R signal is also active (High)
- the Q signal of the FF becomes inactive (Low).
- the liquid crystal display device 3a for example, all scanning signal lines are simultaneously selected before the display is started and the same potential (for example, Vcom) can be written to all the pixels, so that the screen disturbance before the display start and after the display ends can be eliminated.
- the initialization of the shift register initialization of flip-flops in each stage
- the conventional simultaneous selection of all the scanning signal lines and the initialization of the shift register are performed separately.
- the preparatory operation before the start of display can be performed promptly.
- the structure for generating and transmitting the initialization signal for the shift register is not necessary, and the gate driver can be downsized.
- FIG. 5 is a circuit diagram showing a configuration of a liquid crystal display device 3b using the shift register SR of FIG. 1 on the source driver side.
- the source start pulse SSP is input to the first stage of the shift register SR
- the source clock bar signal SCK1B or SCK2B is input to the CKB terminal of each stage.
- the OUT signal output from the i stage SRi is supplied to the sampling circuit SAC, and the data sampled by the OUT signal is supplied to the data signal line SLi of the display unit DAR through the DAC.
- the OUT signal of the n stage SRn is supplied to the sampling circuit SAC, and the data sampled by this OUT signal is supplied to the data signal line SLn of the display unit DAR through the DAC.
- the data signal line SLn is connected to the source of a transistor connected to the pixel electrode in PIXn.
- FIG. 6 is a circuit diagram showing a configuration of a liquid crystal display device 3c obtained by modifying the liquid crystal display device 3a.
- the output signal (OUTB signal) from the i-stage SRi of the shift register is supplied to the scanning signal line Gi of the display unit DAR via the inverter.
- the OUTB signal of the n stage SRn is supplied to the scanning signal line Gn via the inverter.
- the scanning signal line Gn is connected to the gate of a transistor connected to the pixel electrode in PIXn, and a storage capacitor (auxiliary capacitor) is formed between the pixel electrode in PIXn and the storage capacitor line CSn. .
- FIG. 7 is a circuit diagram showing the configuration of the i-stage SRi of the shift register SR.
- the i-stage SRi includes a set / reset type flip-flop FF having an SB terminal and an R terminal, two analog switches ASW3 and ASW4, an AND, an inverter, a CKB terminal, and an ONB terminal. , OUTB terminal, and the Q terminal of the flip-flop FF is connected to the P channel side gate of the analog switch ASW3, the N channel side gate of the analog switch ASW4, and the input of the inverter, and the output of the inverter is connected to the analog switch ASW3.
- one conduction electrode of the analog switch ASW3 is connected to VDD, and one conduction electrode of the analog switch ASW4 is connected to the CKB terminal, The other side of analog switch ASW3
- the conduction electrode, the other conduction electrode of the analog switch ASW4, and one input of the AND are connected, the other input of the AND and the ONB terminal are connected, and the output of the AND and the OUTB terminal that is the output terminal of this stage And are connected.
- the OUTB terminal of its own stage is connected to the SB terminal of the next stage, and the OUTB terminal of the next stage is connected to the R terminal of its own stage via an inverter.
- the OUTB terminal of the n stage SRn is connected to the SB terminal of the (n + 1) stage SRn + 1
- the OUTB terminal of the (n + 1) stage SRn + 1 is connected to the R terminal of the n stage SRn via the inverter.
- the GSPB signal is input to the SB terminal of the first stage SR1 of the shift register SR.
- odd-numbered CKB terminals and even-numbered CKB terminals are connected to different GCK lines (lines for supplying GCK).
- the CKB terminal of the n stage SRn is connected to the GCK2B signal line
- the CKB terminal of the (n + 1) stage SRn + 1 is connected to the GCK1B signal line.
- FIG. 8 is a timing chart showing a driving method of the liquid crystal display device 3c.
- the following display preparation operation is performed before the first frame (vertical scanning period) of the display image.
- the AONB signal is active (Low) for a predetermined period, and at each stage of the shift register SR, one input of AND is Low and the output of AND is Low.
- the OUTB signals at all stages become active (Low), and all scanning signal lines are selected.
- Vcom is supplied to all the data signal lines.
- the FF Q signal is inactive (Low). This is because in the flip-flop FF, when the SB signal and the R signal are simultaneously activated, the R signal (reset) is given priority and the Q signal is deactivated. After the above display preparation operation is completed (after the AONB signal becomes inactive), Vcom is written to all PIX of the display unit DAR, and the Q outputs of the FFs provided in the respective stages of the shift register are inactive ( Low).
- the FF at its own stage is reset, the Q signal becomes Low (inactive), and the analog switch ASW3 is turned ON.
- the AON signal is High
- the inputs of the AND of the own stage are both High and the output is High.
- the OUTB signal of its own stage becomes High (inactive).
- the liquid crystal display device 3c has the following effects in addition to the same effects as the liquid crystal display device 3a. That is, when the AOB signal returns to inactive (when returning from simultaneous selection of all scanning signal lines), both the SB signal and R signal input to the flip-flop FF return to inactive, but the OUTB terminal and the R terminal The return of the R signal is delayed from the return of the SB signal due to the intervening inverter. As a result, when the AOB signal returns to inactive (because the return of the SB signal is delayed from the return of the R signal), the flip-flop FFa is prevented from being activated due to unintentional setting. Can do.
- the i-stage SRi of the shift register SR of the liquid crystal display device 3c can also be configured as shown in FIG.
- the i-stage SRi of the shift register includes a flip-flop FF having an SB terminal and an R terminal, analog switches ASW5 and ASW6, an ONB terminal, a CKB terminal, and an OUTB terminal.
- the QB terminal of the flip-flop FF is connected to the N channel side gate of the analog switch ASW5 and the P channel side gate of the analog switch ASW6, and the Q terminal of the FF is connected to the P channel side gate of the analog switch ASW5 and the N channel of the analog switch ASW6.
- the output terminal of this stage is connected to the OUTB terminal, one conduction electrode of the analog switch ASW5 and one conduction electrode of the analog switch ASW6, and the other conduction electrode of the analog switch ASW5 and the ONB terminal.
- the analog switch AS 6 other conductive electrode of and the CKB terminal for the clock signal input is connected.
- the AONB signal becomes active (Low) for a predetermined period
- the AON signal is output from the OUTB terminal via the ASW5 in each stage of the shift register SR.
- the signal becomes Low (active).
- all the scanning signal lines are selected.
- Vcom is supplied to all the data signal lines.
- the SB signal input to each stage is active (Low) and the R signal is also active (High)
- the FF Q signal is inactive (Low) (therefore, ASW5 remains ON).
- Vcom is written to all PIX of the display unit DAR, and the Q outputs of the FFs provided in the respective stages of the shift register are inactive ( Low).
- each stage of the shift register as shown in FIG. 9, it is possible to achieve downsizing while obtaining the same effect as the shift register of FIG.
- FIG. 10 is a circuit diagram showing a configuration of a liquid crystal display device 3d according to the present invention.
- the liquid crystal display device 3d includes a display unit DAR, a gate driver GD, a source driver SD, and a display control circuit DCC.
- the display control circuit DCC supplies the gate driver GD with an AONB signal (all ON signal), a gate start pulse GSP, a gate on enable signal GOE, and gate clock signals GCK1B and GCK2B.
- the display control circuit DCC supplies a source start pulse SSP, digital data DAT, a polarity signal POL, and a source clock signal SCK to the source driver SD.
- the gate driver GD includes a shift register SR having a plurality of stages.
- the output signal (OUT signal) from the i-stage SRi of the shift register is supplied to the scanning signal line Gi of the display unit DAR via the buffer.
- the OUTB signal of the n stage SRn is supplied to the scanning signal line Gn via the buffer.
- the scanning signal line Gn is connected to the gate of a transistor connected to the pixel electrode in PIXn, and a storage capacitor (auxiliary capacitor) is formed between the pixel electrode in PIXn and the storage capacitor line CSn.
- one analog switch asw and an inverter are provided corresponding to one data signal line, the input of this inverter is connected to the AONB signal line, and the end of the data signal line is one of the continuity of the analog switch asw.
- the other conduction terminal of the analog switch asw is connected to the Vcom (common electrode potential) power source, the N channel side gate of the analog switch asw is connected to the output of the inverter, and the P channel side gate of the analog switch asw is Connected to AONB signal line.
- FIG. 11 is a circuit diagram showing a specific configuration of part of the shift register SR. As shown in the figure, each stage of the shift register includes a flip-flop FF having an SB terminal and an RB terminal, two analog switches ASW7 and ASW8 (gate circuit), NAND1 (logic circuit), and NAND2 (output).
- ASW7 and ASW8 gate circuit
- NAND1 logic circuit
- NAND2 output
- the first and second inverters, the CKB terminal, the ONB terminal, and the OUT terminal, the QB terminal of the flip-flop FF is connected to one input of the NAND1, and the output of the NAND1 is
- the input of one inverter is connected to the P channel side gate of the analog switch ASW7 and the N channel side gate of the analog switch ASW8, and the output of the first inverter is the N channel side gate of the analog switch ASW7 and the P channel side of the analog switch ASW8 Is connected to the gate and one of the conductive switches of the analog switch ASW7.
- one conduction electrode of the analog switch ASW8 is connected to the CKB terminal, the other conduction electrode of the analog switch ASW7, the other conduction electrode of the analog switch ASW8, and one input of the NAND2 Connected, the other input of the NAND2 and the ONB terminal are connected, the output of the NAND2, the input of the second inverter, and the OUTB terminal which is the output terminal of this stage are connected, the output of the second inverter, Are connected to the other input of the NAND1.
- the analog switches ASW7 and ASW8 gate circuits), NAND1 (logic circuit), and NAND2 (output circuit) constitute a signal generation circuit that generates an OUT signal.
- the OUTB terminal of its own stage is connected to the SB terminal of the next stage.
- the OUTB terminal of the n stage SRn is connected to the SB terminal of the (n + 1) stage SRn + 1.
- the GSPB signal is input to the SB terminal of the first stage SR1 of the shift register SR.
- odd-numbered CKB terminals and even-numbered CKB terminals are connected to different GCK lines (lines for supplying GCK).
- the CKB terminal of the n stage SRn is connected to the GCK2B signal line
- the CKB terminal of the (n + 1) stage SRn + 1 is connected to the GCK1B signal line.
- the FF2 shown in FIG. 12 is used for the flip-flop FF of FIG.
- the FF 2 includes a P-channel transistor p32 and an N-channel transistor n31 constituting a CMOS circuit, a P-channel transistor p34 and an N-channel transistor n32 constituting a CMOS circuit, P-channel transistors p31 and p33, An SB terminal, an RB terminal, and a Q terminal and a QB terminal, and the gate of p32, the gate of n31, the drain of p34, the drain of n32, the drain of p33, and the QB terminal are connected to each other;
- the drain of n31, the gate of p34, the gate of n32, the drain of p31, and the Q terminal are connected, the SB terminal is connected to the gate of p31, the RB terminal is connected to the source of p31 and the gate of p33, p32,
- the sources of p33 and p34 are connected to V
- Fig. 12 (b) is a truth table of FF2.
- the Q signal of FF2 is low (inactive), SB signal is low (active), and RB during the period when the SB signal is low (active) and the RB signal is low (active).
- SB signal is high (inactive) and RB
- the signal is held during a period when the signal is High (inactive).
- FIG. 13 is a timing chart showing a driving method of the liquid crystal display device 3d.
- AONB is an AONB signal (all ON signal)
- GSPB is a gate start pulse bar signal
- GCK1B is a GCK1B signal
- GCK2B is a GCK2B signal
- the following display preparation operation is performed before the first frame (vertical scanning period) of the display image.
- the AONB signal is active (Low) for a predetermined period, and each GCKB signal is fixed to active (Low) while the AONB signal is active.
- the AONB signal becomes active (Low)
- the AONB signal is input to the NAND 2 via the ASW 7 and the OUT signal becomes active (High), and all scanning signal lines are selected.
- Vcom is supplied to all the data signal lines.
- the SB signal and the RB signal input to each stage are active (Low), the FF QB signal is inactive (High). Note that once the OUT signal of each stage of the shift register becomes active, the feedback signal to NAND1 becomes Low, so ASW7 is turned off and ASW8 is turned on (GCK1B or GCK2B is taken in).
- Vcom is written to all PIX of the display unit DAR, and the QB output of the FF provided in each stage of the shift register is inactive ( High).
- the following operation is performed during each vertical scanning period (when each frame is displayed). That is, when the SB signal input to the own stage of the shift register SR becomes active (Low), the output of the own stage FF is set and activated, and the own stage takes in the GCKB signal.
- the self-stage GCKB signal becomes active (Low)
- the self-stage OUT signal becomes active (High)
- the next-stage SB signal becomes active
- the self-stage FF is reset so that the QB signal becomes High ( Inactive).
- the OUT signal of the own stage is High (that is, the input of NAND1 is Low and ASW8 is ON)
- the GCKB signal is continuously taken into the own stage, and the GCKB signal becomes High (inactive).
- the OUT signal of the own stage becomes Low and the input of NAND1 becomes High (ASW7 is ON). Thereafter, Vdd (High) and the AONB signal (High) are input to NAND2, and the OUT signal becomes Low (inactive). It becomes.
- the liquid crystal display device 3d for example, all scanning signal lines are simultaneously selected before the display is started and the same potential (for example, Vcom) can be written to all the pixels, so that screen disturbance before the start of display and after the end of display can be eliminated.
- the initialization of the shift register initialization of flip-flops in each stage
- the conventional simultaneous selection of all the scanning signal lines and the initialization of the shift register are performed separately.
- the preparatory operation before the start of display can be performed promptly.
- the self-reset at each stage is possible, the connection relationship between the stages can be simplified. Further, the structure for generating and transmitting the initialization signal for the shift register is not required, and the gate driver can be downsized.
- the GD of the liquid crystal display device 3d can be configured as shown in FIG.
- the output signal (OUTB signal) from the i-stage SRi of the shift register is supplied to the scanning signal line Gi of the display unit DAR via the inverter.
- the OUTB signal of the n stage SRn is supplied to the scanning signal line Gn via the inverter.
- the scanning signal line Gn is connected to the gate of a transistor connected to the pixel electrode in PIXn, and a storage capacitor (auxiliary capacitor) is formed between the pixel electrode in PIXn and the storage capacitor line CSn.
- FIG. 15 is a circuit diagram showing a specific configuration of part of the shift register SR.
- each stage of the shift register includes a flip-flop FF having an SB terminal and an RB terminal, two analog switches ASW9 and ASW10 (gate circuit), a NAND (logic circuit), an inverter, A CKB terminal, an ONB terminal, and an OUTB terminal are included, the QB terminal of the flip-flop FF is connected to one input of the NAND, and the output of the NAND is connected to the input of the inverter and the P channel side gate of the analog switch ASW9.
- the output of the inverter is connected to the N channel side gate of the analog switch ASW9 and the P channel side gate of the analog switch ASW10, and one conduction electrode of the analog switch ASW9 is ONB Connected to the terminal and One conductive electrode of the switch ASW10 is connected to the CKB terminal, the other conductive electrode of the analog switch ASW9, the other conductive electrode of the analog switch ASW10, the OUTB terminal which is the output terminal of this stage, and the other of the NAND
- the analog switch ASW9 / ASW10 (gate circuit) and NAND (logic circuit) constitute a signal generation circuit that generates the OUTB signal.
- the OUTB terminal of its own stage is connected to the SB terminal of the next stage.
- the gate driver GD odd-numbered CKB terminals and even-numbered CKB terminals are connected to different GCK lines (lines for supplying GCK).
- FIG. 16 is a timing chart showing a driving method of the liquid crystal display device 3e.
- the following display preparation operation is performed before the first frame (vertical scanning period) of the display image.
- the AONB signal is active (Low) for a predetermined period, and each GCKB signal is fixed to active (Low) while the AONB signal is active.
- the AONB signal becomes active (Low)
- the ASW 9 is ON
- the OUTB signal becomes active (Low)
- all scanning signal lines are selected.
- Vcom is supplied to all the data signal lines.
- the SB signal and the RB signal input to each stage are active (Low), the FF QB signal is inactive (High). Note that once the OUTB signal of each stage of the shift register becomes active, the feedback signal to the NAND becomes Low, so ASW 9 is turned off and ASW 10 is turned on (in each stage, GCK1B or GCK2B is captured).
- Vcom is written to all PIX of the display unit DAR, and the QB output of the FF provided in each stage of the shift register is inactive ( High).
- the OUTB signal of the own stage is Low (that is, the output of the NAND is High)
- the GCKB signal is continuously taken into the own stage, and when the GCKB signal becomes High (inactive), The OUTB signal becomes High and the NAND output becomes Low. Thereafter, the AONB signal is output from the OUTB terminal, and the OUTB signal becomes High (inactive).
- the liquid crystal display device 3e for example, all scanning signal lines are simultaneously selected before the display is started and the same potential (for example, Vcom) can be written to all the pixels, so that it is possible to eliminate screen disturbance before the display is started and after the display is ended.
- the initialization of the shift register initialization of flip-flops in each stage
- the conventional simultaneous selection of all the scanning signal lines and the initialization of the shift register are performed separately.
- the preparatory operation before the start of display can be performed promptly.
- the connection relationship between the stages can be simplified.
- the NAND 2 (output circuit) of the liquid crystal display device 3d (see FIG. 11) can be eliminated, and the size can be reduced. Further, the structure for generating and transmitting the initialization signal for the shift register is not required, and the gate driver can be downsized.
- the source of the P-channel transistor p40 is connected to VDD
- the gate is the input X of the NAND
- the drain is the output M of the NAND
- the source of the P-channel transistor p41 is connected to VDD
- the gate is the input Y of the NAND
- the drain is connected to the source of the N-channel transistor n40
- the gate of the N-channel transistor n40 is connected to the input Y
- the drain is connected to the source of the N-channel transistor n41
- the gate of the N-channel transistor n41 is connected to the input X
- the drain is connected to VSS
- the drive capability of the P-channel transistors p40 and 41 is made larger than that of the N-channel transistors n40 and 41.
- each stage of the shift register in the liquid crystal display device 3e can be changed as shown in FIG. That is, the ASW 9 in FIG. 15 is a single channel (P channel) transistor TR. In this way, the shift register can be further reduced in size.
- the FF3 shown in FIG. 18 may be used for the flip-flop FF shown in FIGS.
- the FF 3 includes a P-channel transistor p6 and an N-channel transistor n5 that constitute a CMOS circuit, a P-channel transistor p8 and an N-channel transistor n7 that constitute a CMOS circuit, and P-channel transistors p5 and p7.
- N channel transistors n6 and n8, SB terminal, RB terminal, Q terminal and QB terminal are provided, and the gate of p6, the gate of n5, the drain of p7, the drain of p8, the drain of n7, and the QB terminal are connected
- the drain of p6, the drain of n5, the drain of p5, the gate of p8, the gate of n7, and the Q terminal are connected
- the source of n5 and the drain of n6 are connected
- the source of n7 and the drain of n8 Are connected
- the SB terminal is connected to the gate of p5 and the gate of n6, and the RB terminal is 5 source and is connected to the gates of the n8 of p7
- the source of p6 and p7 and p8 are connected to VDD, a structure in which the source of n6 and n8 is connected to VSS.
- p6, n5, p8 and n7 constitute a latch circuit LC
- p5 functions as a set transistor ST
- p7 functions as a reset transistor RT
- n6 and n8 function as a latch release transistor (release transistor) LRT.
- FIG. 18B is a timing chart showing the operation of FF3
- FIG. 18C is a truth table of FF3.
- the Q signal of FF3 is low (inactive) during the period when the SB signal is low (active) and the RB signal is low (active), and the SB signal is low (active).
- the RB signal is High (inactive)
- the SB signal is High (inactive) and the RB signal is Low (active)
- the SB signal is High (inactive).
- the RB signal is held (High) (inactive).
- Vdd of the RB terminal is output to the Q terminal, n7 is turned ON, and Vss (Low) is output to the QB terminal.
- the SB signal becomes High
- p5 is turned off and n6 is turned on
- the state of t1 is maintained.
- the RB signal becomes Low
- p7 is turned on and Vdd (High) is outputted to the QB terminal
- n5 is turned on and Vss is outputted to the Q terminal.
- both the SB signal and the RB signal are low (active)
- p7 is turned on, Vdd (High) is output to the QB terminal, and Vss + Vth (p5 threshold voltage via p5) to the Q terminal.
- the FF4 shown in FIG. 19 may be used for the flip-flop FF shown in FIGS.
- the FF 4 includes a P channel transistor p22 and an N channel transistor n21 that constitute a CMOS circuit, a P channel transistor p23 and an N channel transistor n22 that constitute a CMOS circuit, a P channel transistor p21, and an SB terminal.
- an RB terminal, a Q terminal and a QB terminal, the gate of p22, the gate of n21, the drain of p23, the drain of n22, the drain of p21, and the Q terminal are connected, and the drain of p22 and the n21
- the SB terminal is connected to the gate of p21
- the RB terminal is connected to the source of p21 and the source of p23
- the sources of n21 and n22 are set to VSS. It is a connected configuration.
- p22, n21, p23 and n22 form a latch circuit LC
- p21 functions as a set transistor ST.
- FIG. 19B is a timing chart showing the operation of FF4, and FIG. 19C is a truth table of FF4.
- the Q signal of FF4 is low (inactive) during the period when the SB signal is low (active) and the RB signal is low (active), and the SB signal is low (active).
- the RB signal is High (inactive)
- the SB signal is High (inactive) and the RB signal is Low (active)
- the SB signal is High (inactive).
- the RB signal is held (High) (inactive).
- Vdd (High) of the RB terminal is output to the Q terminal, n21 is turned ON, and Vss (Low) is output to the QB terminal.
- SB signal since the SB signal becomes High and p21 is turned off, the state of t1 is maintained.
- Vss + Vth is once output to the Q terminal via p23, and thereby p22 is turned ON and Vdd (High) is output to the QB terminal.
- the QB terminal becomes Vdd, n22 is turned ON and Vss is output to the Q terminal.
- Vss + Vth is once output to the Q terminal via p21, whereby p22 is turned ON and Vdd (High) is output to the QB terminal.
- p22 is turned ON and Vdd (High) is output to the QB terminal.
- n22 is turned ON and Vss is output to the Q terminal.
- the FF5 shown in FIG. 20 may be used for the flip-flop FF shown in FIGS.
- the FF 5 includes a P channel transistor p44 and an N channel transistor n43 constituting a CMOS circuit, a P channel transistor p45 and an N channel transistor n44 constituting a CMOS circuit, a P channel transistor p43, and an N channel.
- the drain of p44, the drain of n43, the gate of p45, the gate of n44, and the QB terminal are connected, the source of n44 and the drain of n45 are connected, and the SB terminal is connected to the gate of p43 and the gate of n45, RB terminal is source of p43 and source of p45 Is connected, the source of n43 is connected to VSS, the source of p44 is connected to VDD, a structure in which the source of n45 is connected to VSS.
- p44, n43, p45 and n44 constitute a latch circuit LC, p43 functions as a set transistor ST, and n45 functions as a latch release circuit transistor LRT.
- FIG. 20B is a truth table of FF5.
- the Q signal of the FF 5 is low (inactive), SB signal is low (active), and RB during the period when the SB signal is low (active) and the RB signal is low (active).
- SB signal is high (inactive) and RB
- the signal is held during a period when the signal is High (inactive).
- the GD of the liquid crystal display device 3e can be configured as shown in FIG.
- the output signal (OUTB signal) from the i-stage SRi of the shift register is supplied to the scanning signal line Gi of the display unit DAR via the inverter.
- the OUTB signal of the n stage SRn is supplied to the scanning signal line Gn via the inverter.
- the scanning signal line Gn is connected to the gate of a transistor connected to the pixel electrode in PIXn, and a storage capacitor (auxiliary capacitor) is formed between the pixel electrode in PIXn and the storage capacitor line CSn.
- FIG. 22 is a circuit diagram showing the configuration of the i-stage SRi of the shift register SR.
- each stage of the shift register includes a flip-flop FF having an SB terminal and an RB terminal, two analog switches ASW11 and ASW12 (gate circuit), NOR (logic circuit), first and A second inverter, a CKB terminal, an ONB terminal, and an OUTB terminal are included, the Q terminal of the flip-flop FF is connected to one input of NOR, and the output of NOR is connected to the input of the first inverter and an analog switch
- the ASW11 is connected to the N channel side gate of the ASW11 and the P channel side gate of the analog switch ASW12, and the output of the first inverter is connected to the P channel side gate of the analog switch ASW11 and the N channel side gate of the analog switch ASW12.
- One conductive electrode of switch ASW11 is connected to the ONB terminal
- one conductive electrode of the analog switch ASW12 is connected to the CKB terminal
- the input of the inverter is connected, and the output of the second inverter, the other input of NOR, and the R terminal of the FF are connected.
- a signal generation circuit for generating an OUTB signal is configured by the analog switches ASW11 and ASW12 (gate circuit) and NOR (logic circuit).
- the OUTB terminal of its own stage is connected to the SB terminal of the next stage.
- the gate driver GD odd-numbered CKB terminals and even-numbered CKB terminals are connected to different GCK lines (lines for supplying GCK).
- FIG. 23 is a timing chart showing a driving method of the liquid crystal display device 3f.
- the following display preparation operation is performed before the first frame (vertical scanning period) of the display image.
- the AONB signal is active (Low) for a predetermined period, and each GCKB signal is fixed to active (Low) while the AONB signal is active.
- the AONB signal becomes active (Low)
- the ASW 11 is ON
- the OUTB signal becomes active (Low)
- all scanning signal lines are selected.
- Vcom is supplied to all the data signal lines.
- the FF QB signal is inactive (High). Note that once the OUTB signal of each stage of the shift register becomes active, the feedback signal to NOR becomes High, so ASW11 is turned off and ASW12 is turned on (in each stage, GCK1B or GCK2B is taken in).
- Vcom is written to all PIX of the display unit DAR, and the QB output of the FF provided in each stage of the shift register is inactive ( High).
- the OUTB signal of the own stage is Low (that is, the output of NOR is Low)
- the GCKB signal is continuously taken into the own stage, and when the GCKB signal becomes High (inactive), The OUTB signal becomes High and the output of NOR becomes High. Thereafter, the AONB signal is output from the OUTB terminal, and the OUTB signal becomes High (inactive).
- the liquid crystal display device 3f for example, all scanning signal lines are simultaneously selected before the display is started and the same potential (for example, Vcom) can be written to all the pixels, so that it is possible to eliminate screen disturbance before the display is started and after the display is ended.
- the initialization of the shift register initialization of flip-flops in each stage
- the conventional simultaneous selection of all the scanning signal lines and the initialization of the shift register are performed separately.
- the preparatory operation before the start of display can be performed promptly.
- the connection relationship between the stages can be simplified.
- the NAND 2 (output circuit) of the liquid crystal display device 3d can be eliminated, and the size can be reduced. Further, the structure for generating and transmitting the initialization signal for the shift register is not required, and the gate driver can be downsized.
- the NOR in FIG. 22 is preferably configured as shown in FIG.
- the source of the P-channel transistor p50 is connected to VDD
- the gate is connected to the NOR input X and the gate of the N-channel transistor n51
- the drain is connected to the source of the P-channel transistor p51
- the gate of the P-channel transistor p51 Is connected to the NOR input Y and the gate of the N-channel transistor n50
- the drain is connected to the source of n50, the source of n51 and the output M of the NOR
- the drains of n50 and n51 are connected to VSS, and the drive capability of the N-channel transistors n50 and 51 is made larger than that of the P-channel transistors p50 and 51.
- FIG. 25 is a circuit diagram showing a configuration of a liquid crystal display device 3g according to the present invention.
- the liquid crystal display device 3g is a so-called CC (charge coupled) drive liquid crystal display device, and includes a display unit DAR, a gate / Cs driver G-CsD, a source driver SD, and a display control circuit DCC.
- the display control circuit DCC supplies the gate driver GD with a gate start pulse GSP, a gate on enable signal GOE, an AONB signal (all ON signal), CS inversion signals CMI1 and CMI2, and gate clock signals GCK1B and GCK2B.
- the display control circuit DCC supplies a source start pulse SSP, digital data DAT, a polarity signal POL, and a source clock signal SCK to the source driver SD.
- the gate / Cs driver G-CsD includes a shift register SR composed of a plurality of stages and a plurality of D latch circuits CSL, and corresponds to one stage of the shift register, one inverter, one OR circuit, One D latch circuit CSL is provided.
- a D latch circuit CSLi is provided corresponding to the i-stage SRi of the shift register.
- the output signal (OUTB signal) from the i stage SRi of the shift register is supplied to the scanning signal line Gi of the display unit DAR via an inverter and a buffer. Further, an output signal (out signal, CS signal) from the D latch circuit CSLi corresponding to the i-stage SRi is supplied to the storage capacitor line CSi of the display unit DAR.
- the OUTB signal of the n stage SRn is supplied to the scanning signal line Gn via the inverter and the buffer, and the output signal (out signal, CS signal) from the D latch circuit CSLn corresponding to the n stage SRn is displayed on the display unit DAR.
- the scanning signal line Gn is connected to the gate of a transistor connected to the pixel electrode in PIXn, and a storage capacitor (auxiliary capacitor) is formed between the pixel electrode in PIXn and the storage capacitor line CSn. .
- one analog switch asw and an inverter are provided corresponding to one data signal line, the input of this inverter is connected to the AONB signal line, and the end of the data signal line is one of the continuity of the analog switch asw.
- the other conduction terminal of the analog switch asw is connected to the Vcom (common electrode potential) power source, the N channel side gate of the analog switch asw is connected to the output of the inverter, and the P channel side gate of the analog switch asw is Connected to AONB signal line.
- FIG. 26 is a circuit diagram showing a configuration of i-stage SRi of shift register SR shown in FIG.
- each stage of the shift register includes a flip-flop FF having the SB terminal and the RB terminal (the above-described flip-flops FF1 to FF5), two analog switches ASW13 and ASW14, NAND, an inverter, , CKB terminal, and ONB terminal, the QB terminal of the flip-flop FF is connected to one input of the NAND, and the output (M) of the NAND is connected to the input of the inverter and the P-channel side gate of the analog switch ASW13.
- the output of the inverter is connected to the N channel side gate of the analog switch ASW13 and the P channel side gate of the analog switch ASW14, and one conduction electrode of the analog switch ASW13 is connected to Connected to the ONB terminal
- the one conducting electrode of the analog switch ASW14 is connected to the CKB terminal, the other conducting electrode of the analog switch ASW13, the other conducting electrode of the analog switch ASW14, the OUTB terminal that is the output terminal of this stage, and the other of the NAND Is connected to the RB terminal of the FF.
- the i-stage SRi In the i-stage SRi, during the period when the QB signal (NAND input X) of the flip-flop FF is High (inactive), if the OUTB signal (NAND other input Y) is High (inactive), the NAND output ( M) becomes Low (analog switch ASW13 is ON and ASW14 is OFF), and AONB signal (inactive and Vdd) is output to OUTB terminal, while OUTB signal (the other input Y of NAND) is Low (active) If so, the output (M) of the NAND becomes High (the analog switch ASW1 is OFF and ASW2 is ON), and the GCKB signal is captured and output from the OUTB terminal.
- the NAND input (M) is High because the one input X of the NAND is Low and the other input Y of the NAND is Low (the analog switch ASW13 is When ASW14 is turned OFF, the GCKB signal is captured and output from the OUTB terminal. That is, the NAND, the inverter, and the analog switches ASW1 and ASW2 (gate circuits) constitute a signal generation circuit that generates the OUTB signal.
- the analog switches ASW13 and ASW14 receive the AONB signal or the clock signal according to the output M of the NAND. Configure the gate circuit to capture.
- FIG. 27 is a circuit diagram showing a configuration of the D latch circuit CSLi corresponding to the i-stage SRi of the shift register SR shown in FIG.
- the D latch circuit CSLi includes three CMOS circuits 5 to 7, analog switches ASW15 and ASW16, an inverter, a CK terminal, a D terminal, and an out terminal.
- the CMOS circuits 5 and 6 the gates of one P-channel transistor and one N-channel transistor are connected to each other, the drains are connected to each other, and the source of the P-channel transistor is connected to VDD. Is connected to VSS.
- the gates of one P-channel transistor and one N-channel transistor are connected to each other, the drains are connected to each other, the source of the P-channel transistor is connected to the power source VCSH, and the source of the N-channel transistor is the power source This is a configuration connected to the VCSL.
- the CK terminal, the input of the inverter, the N channel side gate of the analog switch ASW16, and the P channel side gate of the analog switch ASW15 are connected, and the output of the inverter, the P channel side gate of the analog switch ASW16, and the N channel of the analog switch ASW15 Is connected to the drain side of the CMOS circuit 5 and one conduction terminal of the analog switch ASW15, the other conduction terminal of the analog switch ASW15, one conduction terminal of the analog switch ASW16, and the gate of the CMOS circuit 6.
- the other conduction terminal of the analog switch ASW 16 is connected to the D terminal
- the gate side of the CMOS circuit 5 is connected to the drain side of the CMOS circuit 6
- the drain side of the CMOS circuit 6 is connected to the CMOS circuit 7.
- the gate side of the It is continued, and the drain side and the out terminal of the CMOS circuit 7 is connected.
- the D latch circuit CSLi takes in the D signal (signal input to the D terminal) and latches it while the CK signal (signal input to the CK terminal) is active (High). That is, if the D signal changes from Low to High during the active period of the CK signal, the out signal (signal output from the out terminal) is raised from the potential of the power supply VCSL to the potential of the power supply VCSH, and then the potential of the power supply VCSH is increased. If the D signal changes from High to Low while the CK signal is active, the out signal (the signal output from the out terminal) drops from the potential of the power supply VCSH to the potential of the power supply VCSL, and then the power supply VCSL The potential will be maintained.
- the own OUTB terminal is connected to the next SB terminal.
- the OUTB terminal of the own stage is connected to one input terminal of the OR circuit corresponding to the own stage via an inverter, and the other OUTB terminal corresponding to the own stage is connected to the OUTB terminal of the next stage via the inverter.
- the output of the OR circuit corresponding to the own stage is connected to the CK terminal of the D latch circuit corresponding to the own stage.
- the OUTB terminal of the n-stage SRn is connected to the SB terminal of the (n + 1) -stage SRn + 1, and the OUTB terminal of the n-stage SRn is connected to one input terminal of the OR circuit corresponding to the n-stage SRn via the inverter.
- the OUTB terminal of the (n + 1) stage SRn + 1 is connected to the other input terminal of the OR circuit corresponding to the n stage SRn stage via an inverter, and the output of the OR circuit corresponding to the n stage SRn is D corresponding to the n stage SRn. It is connected to the CK terminal of the latch circuit CSLn.
- the GSPB signal is input to the first stage SB terminal of the shift register SR.
- odd-numbered CKB terminals and even-numbered CKB terminals are connected to different GCK lines (lines for supplying GCK), and the ONB terminals of the respective stages are connected to a common AONB line ( A line for supplying an AON signal).
- the CKB terminal of the n stage SRn is connected to the GCK2B signal line
- the CKB terminal of the (n + 1) stage SRn + 1 is connected to the GCK1B signal line
- the ONB terminals of the n stage SRn and the (n + 1) stage SRn + 1 are the same AONB signal. Connected to the line.
- the D terminal is connected to a different CMI line (a line for supplying a CMI signal) for each of two D latch circuits corresponding to two consecutive stages.
- the D terminal of the D latch circuit CSLn corresponding to the n stage SRn is connected to the CMI2 signal line
- the D terminal of the D latch circuit CSLn + 1 corresponding to the (n + 1) stage SRn + 1 is connected to the CMI2 signal line
- the D terminal of the D latch circuit CSLn + 2 corresponding to SRn + 2 is connected to the CMI1 signal line
- the D terminal of the D latch circuit CSLn + 3 corresponding to the (n + 3) stage SRn + 3 is connected to the CMI1 signal line.
- FIG. 28 is a timing chart showing a driving method of the liquid crystal display device 3g.
- AONB is an AON signal
- GSPB is a gate start pulse bar signal
- GCK1B is a GCK1B signal
- GCK2B is a GCK2B signal
- CMI1 is a CMI1 signal
- CMI2 is a CMI2 signal
- the cycle of the polarity signal POL is set to one horizontal scanning period 1H (that is, the polarity of the data signal supplied to the same data signal line is inverted every 1H), and CMI1 and CMI2 are in phase.
- the following display preparation operation is performed before the first frame (vertical scanning period) of the display image.
- the AONB signal is active (Low) for a predetermined period, and while the AONB signal is active, each GCKB signal is fixed to active (Low) and each CMI signal is High (or Low).
- the OUTB signals in all stages become active (Low), and all scanning signal lines are selected.
- Vcom is supplied to all the data signal lines.
- each D latch circuit latches the CMI1 signal (Low) or the CMI2 signal (Low), and the out signal supplied to the storage capacitor wiring (CS signal) is the potential of the power supply VCSL.
- Vcom is written to all PIX of the display unit DAR, the QB output of the FF provided in each stage of the shift register is made inactive (High), and the out of each D latch circuit is output.
- the signal (the potential of the storage capacitor wiring) is set to the potential of the power supply VCSL.
- the OUTB signal of the own stage is Low (that is, the output of the NAND is High)
- the GCKB signal is continuously taken into the own stage, and when the GCKB signal becomes High (inactive), The OUTB signal becomes High and the NAND output becomes Low. Thereafter, the AONB signal is output from the OUTB terminal, and the OUTB signal becomes High (inactive).
- the D latch circuit corresponding to the own stage latches the CMI1 signal or the CMI2 signal, and further the next stage
- the D latch circuit corresponding to the own stage again latches the CMI1 signal or the CMI2 signal.
- the out signal of the D latch circuit corresponding to the self-stage (the potential of the storage capacitor wiring corresponding to the self-stage) is deactivated by the OUTB signal of the self-stage (the scanning signal line corresponding to the self-stage is OFF)
- the potential of the power supply VCSL is increased to the potential of the power supply VCSH (when a positive polarity data signal is written to the pixel corresponding to the self-stage) or the potential of the power supply VCSH is decreased to the potential of the power supply VCSL. (When a negative polarity data signal is written to the pixel corresponding to the own stage).
- the D latch circuit CSLn corresponding to the n stage SRn latches the CMI2 signal, and (n + 1) )
- D latch circuit CSLn latches the CMI2 signal again.
- the OUT signal of the D-stage latch circuit CSLn corresponding to the n-stage SRn (the potential of the storage capacitor line CSn corresponding to the n-stage SRn) becomes inactive (the corresponding to the n-stage SRn).
- the potential of the power supply VCSH is lowered to the potential of the power supply VCSL.
- a negative polarity data signal is written in the pixel PIXn corresponding to the n-stage SRn, as shown by POL, and the effective potential is lowered below the potential of the data signal by pushing down the storage capacitor wiring CSn. (The luminance of the pixel PIXn can be increased).
- the D latch circuit CSLn + 1 corresponding to the (n + 1) stage SRn + 1 latches the CMI2 signal
- the D latch Circuit CSLn + 2 again latches the CMI2 signal.
- the out signal (potential of the storage capacitor wiring CSn + 1) of the D latch circuit CSLn + 1 corresponding to the (n + 1) stage SRn + 1 is deactivated (the scanning signal line Gn + 1 is turned ON / OFF). After turning off), the potential of the power supply VCSL is pushed up to the potential of the power supply VCSH.
- a positive polarity data signal is written in the pixel PIXn + 1 corresponding to the (n + 1) stage SRn + 1 as shown by POL, and the effective potential is made higher than the potential of the data signal by pushing up the storage capacitor wiring CSn + 1.
- the luminance can be increased (the luminance of the pixel PIXn + 1 is increased).
- the D latch circuit CSLn + 2 corresponding to the (n + 2) stage SRn + 2 latches the CMI1 signal
- the D latch Circuit CSLn + 2 again latches the CMI1 signal.
- the OUT signal of the D latch circuit CSLn + 2 corresponding to the (n + 2) stage SRn + 2 (potential of the storage capacitor line CSn + 2) is deactivated (the scanning signal line Gn + 2 is turned ON / OFF). After turning off, the potential of the power supply VCSH is pushed down to the potential of the power supply VCSL.
- a negative polarity data signal is written to the pixel PIXn + 2 corresponding to the (n + 2) stage SRn + 2 as shown by POL, and the effective potential is made to be lower than the potential of the data signal by pushing down the storage capacitor line CSn + 2. (The luminance of the pixel PIXn + 2 can be increased).
- the second and subsequent frames are displayed in the same manner as the first frame.
- the POL phase is shifted by a half cycle every frame, the polarity of the data signal supplied to the same pixel is inverted every frame.
- the push-up and push-down of the out signal (the potential of the storage capacitor wiring CSi) of the D latch circuit CSLi is also switched every frame.
- the liquid crystal display device 3g for example, all scanning signal lines are simultaneously selected before the display is started and the same potential (for example, Vcom) can be written to all the pixels, so that it is possible to eliminate screen disturbance before the display is started and after the display is ended.
- the initialization of the shift register initialization of flip-flops in each stage
- the conventional simultaneous selection of all the scanning signal lines and the initialization of the shift register are performed separately.
- the preparatory operation before the start of display can be performed promptly.
- the structure for generating and transmitting the initialization signal for the shift register is not necessary, and the G-CS driver can be downsized.
- the connection relationship between the stages can be simplified. Further, since the AONB signal is input to the ASW 13, the NAND 2 (output circuit) of the liquid crystal display device 3d (see FIG. 11) can be eliminated, and the size can be reduced. In addition, since each pixel row can be appropriately CC-driven from the first frame, it is possible to eliminate screen distortion (horizontal stripe-like unevenness) of the first frame, which has been a problem with conventional CC driving.
- the phase of the polarity signal POL is set to 2H (supplied to the same data signal line) only by shifting the phase of the CMI2 signal by a half cycle (from FIG. 28).
- the polarity of the data signal is inverted every 2H), and each pixel row can be appropriately CC-driven from the first frame. That is, in the liquid crystal display device 3g, the period of the polarity signal POL can be switched from 1H to 2H only by controlling the phases of the CS inversion signals CMI1 and CMI2 signals, and screen disturbance at that time can be eliminated.
- FIG. 30 is a circuit diagram showing a configuration of a liquid crystal display device 3h according to the present invention.
- the liquid crystal display device 3h is a so-called CC (charge coupled) drive liquid crystal display device, and includes a display unit DAR, a gate / Cs driver G-CsD, a source driver SD, and a display control circuit DCC.
- the display control circuit DCC supplies the gate driver GD with a gate start pulse GSP, a gate on enable signal GOE, an AONB signal (all ON signal), CS inversion signals CMI1 and CMI2, and gate clock signals GCK1B and GCK2B.
- the display control circuit DCC supplies a source start pulse SSP, digital data DAT, a polarity signal POL, and a source clock signal SCK to the source driver SD.
- the gate / Cs driver G-CsD includes a shift register SR having a plurality of stages and a plurality of D latch circuits CSL.
- One inverter and one D latch circuit CSL are provided corresponding to one stage of the shift register. And one buffer.
- a D latch circuit CSLi is provided corresponding to the i stage SRi of the shift register.
- the output signal (OUTB signal) from the i stage SRi of the shift register is supplied to the scanning signal line Gi of the display unit DAR via an inverter and a buffer.
- the output signal (out signal, CS signal) from the D latch circuit CSLi corresponding to the i-stage SRi is supplied to the storage capacitor line CSi-1 of the display unit DAR.
- the OUTB signal of the n stage SRn is supplied to the scanning signal line Gn via the inverter and the buffer, and the output signal (out signal, CS signal) from the D latch circuit CSLn corresponding to the n stage SRn is displayed on the display unit DAR. Is supplied to the storage capacitor line CSn-1.
- the scanning signal line Gn is connected to the gate of a transistor connected to the pixel electrode in PIXn, and a storage capacitor (auxiliary capacitor) is formed between the pixel electrode in PIXn and the storage capacitor line CSn.
- the scanning signal line Gn-1 is connected to the gate of a transistor connected to the pixel electrode in PIXn-1, and a storage capacitor (between the pixel electrode in PIXn-1 and the storage capacitor line CSn-1). Auxiliary capacity) is formed.
- one analog switch asw and an inverter are provided corresponding to one data signal line, the input of this inverter is connected to the AONB signal line, and the end of the data signal line is one of the continuity of the analog switch asw.
- the other conduction terminal of the analog switch asw is connected to the Vcom (common electrode potential) power source, the N channel side gate of the analog switch asw is connected to the output of the inverter, and the P channel side gate of the analog switch asw is Connected to AONB signal line.
- the configuration of the i-stage SRi of the shift register SR shown in FIG. 30 is as shown in FIG. 26, and the configuration of the D latch circuit CSLi is as shown in FIG.
- the OUTB terminal of its own stage is connected to the SB terminal of the next stage. Further, the M terminal of the own stage is connected to the CK terminal of the D latch circuit corresponding to the own stage.
- the OUTB terminal of the n stage SRn is connected to the SB terminal of the (n + 1) stage SRn + 1
- the M terminal of the n stage SRn is connected to the CK terminal of the D latch circuit CSLn corresponding to the n stage SRn.
- the GSPB signal is input to the first stage SB terminal of the shift register SR.
- odd-numbered CKB terminals and even-numbered CKB terminals are connected to different GCK lines (lines supplying GCK), and the ONB terminals of the respective stages supply a common AONB line (supply AON signal). Line).
- the CKB terminal of the n stage SRn is connected to the GCK2B signal line
- the CKB terminal of the (n + 1) stage SRn + 1 is connected to the GCK1B signal line
- the ONB terminals of the n stage SRn and the (n + 1) stage SRn + 1 are the same AONB signal. Connected to the line.
- the D terminal is connected to a different CMI line (a line for supplying a CMI signal) for each of two D latch circuits corresponding to two consecutive stages.
- the D terminal of the D latch circuit CSLn-1 corresponding to the (n-1) stage SRn-1 is connected to the CMI1 signal line
- the D terminal of the D latch circuit CSLn corresponding to the n stage SRn is connected to the CMI1 signal line.
- the D terminal of the D latch circuit CSLn + 1 corresponding to the (n + 1) stage SRn + 1 is connected to the CMI2 signal line
- the D terminal of the D latch circuit CSLn + 2 corresponding to the (n + 2) stage SRn + 2 is connected to the CMI2 signal line.
- FIG. 31 is a timing chart showing a driving method of the liquid crystal display device 3h.
- AONB is an AON signal
- GSPB is a gate start pulse bar signal
- GCK1B is a GCK1B signal
- GCK2B is a GCK2B signal
- CMI1 is a CMI1 signal
- CMI2 is a CMI2 signal
- the cycle of the polarity signal POL is set to one horizontal scanning period 1H (that is, the polarity of the data signal supplied to the same data signal line is inverted every 1H), and CMI1 and CMI2 are in phase.
- the following display preparation operation is performed before the first frame (vertical scanning period) of the display image.
- the AONB signal is active (Low) for a predetermined period. While the AONB signal is active, each GCKB signal is fixed to active (Low) and each CMI is The signal is fixed to High (or Low).
- the OUTB signal in all stages becomes active (Low), and all scanning signal lines are selected.
- Vcom is supplied to all the data signal lines.
- each D latch circuit latches the CMI1 signal (Low) or the CMI2 signal (Low) and applies it to the storage capacitor wiring.
- the supplied out signal (CS signal) becomes the potential of the power supply VCSL.
- Vcom is written to all PIX of the display unit DAR, the QB outputs of the flip-flops provided in each stage of the shift register are inactive (High), and each D latch circuit
- the out signal (the potential of the storage capacitor wiring) is set to the potential of the power supply VCSL.
- the OUTB signal of the own stage is Low (that is, the output of the NAND is High)
- the GCKB signal is continuously taken into the own stage, and when the GCKB signal becomes High (inactive), The OUTB signal becomes High and the NAND output becomes Low. Thereafter, the AONB signal is output from the OUTB terminal, and the OUTB signal becomes High (inactive).
- the D latch circuit corresponding to the next stage latches the CMI1 signal or the CMI2 signal.
- the out signal of the D latch circuit corresponding to the self-stage (the potential of the storage capacitor wiring corresponding to the self-stage) is deactivated by the OUTB signal of the self-stage (the scanning signal line corresponding to the self-stage is OFF)
- the potential of the power supply VCSL is increased to the potential of the power supply VCSH (when a positive polarity data signal is written to the pixel corresponding to the self-stage) or the potential of the power supply VCSH is decreased to the potential of the power supply VCSL. (When a negative polarity data signal is written to the pixel corresponding to the own stage).
- the D latch circuit CSLn corresponding to the n stage SRn latches the CMI1 signal.
- the out signal of the D latch circuit CSLn (the potential of the storage capacitor line CSn-1) becomes inactive when the OUT signal of the (n-1) stage SRn-1 is turned on (the scanning signal line Gn-1 is turned ON After turning off), the potential of the power supply VCSL is pushed up to the potential of the power supply VCSH.
- a positive polarity data signal is written in the pixel PIXn ⁇ 1 corresponding to the (n ⁇ 1) stage SRn ⁇ 1, as shown by POL.
- the potential can be made higher than the potential of the data signal (the luminance of the pixel PIXn-1 can be increased).
- the D latch circuit CSLn + 1 corresponding to the (n + 1) stage SRn + 1 latches the CMI2 signal.
- the out signal (the potential of the storage capacitor line CSn) of the D latch circuit CSLn + 1 becomes after the OUT signal of the n-stage SRn becomes inactive (the scanning signal line Gn corresponding to the n-stage SRn is turned ON / OFF). Then, the potential of the power supply VCSH is pushed down to the potential of the power supply VCSL.
- a negative polarity data signal is written in the pixel PIXn corresponding to the n-stage SRn, as shown by POL, and the effective potential is lowered below the potential of the data signal by pushing down the storage capacitor wiring CSn. (The luminance of the pixel PIXn can be increased).
- the D latch circuit CSLn + 2 corresponding to the (n + 2) stage SRn + 2 latches the CMI2 signal.
- the out signal of the D latch circuit CSLn + 2 (the potential of the storage capacitor line CSn + 1) is not supplied to the power supply VCSL after the OUT signal of the (n + 1) stage SRn + 1 becomes inactive (the scanning signal line Gn + 1 is turned ON / OFF). The potential is pushed up from the potential to the potential of the power supply VCSH.
- a positive polarity data signal is written in the pixel PIXn + 1 corresponding to the (n + 1) stage SRn + 1 as shown by POL, and the effective potential is made higher than the potential of the data signal by pushing up the storage capacitor wiring CSn + 1.
- the luminance can be increased (the luminance of the pixel PIXn + 1 is increased).
- the second and subsequent frames are displayed in the same manner as the first frame.
- the POL phase is shifted by a half cycle every frame, the polarity of the data signal supplied to the same pixel electrode PIXi is inverted every frame.
- the push-up and push-down of the out signal (the potential of the storage capacitor wiring CSi) of the D latch circuit CSLi is also switched every frame.
- the liquid crystal display device 3e uses the flip-flop described in the above embodiment, the G-Cs driver can be reduced in size.
- the liquid crystal display device 3h for example, all scanning signal lines are simultaneously selected before the display is started and the same potential (for example, Vcom) can be written to all the pixels, so that it is possible to eliminate screen disturbance before the display is started and after the display is ended.
- the initialization of the shift register initialization of flip-flops in each stage
- the conventional simultaneous selection of all the scanning signal lines and the initialization of the shift register are performed separately.
- the preparatory operation before the start of display can be performed promptly.
- the structure for generating and transmitting the initialization signal for the shift register is not necessary, and the G-CS driver can be downsized.
- the connection relationship between the stages can be simplified.
- the NAND 2 (output circuit) of the liquid crystal display device 3d can be eliminated, and the size can be reduced.
- M signal the internal signal of the shift register
- a NOR circuit and an OR circuit are not required in the G-Cs driver, and further miniaturization is possible.
- each pixel row can be appropriately CC-driven from the first frame, it is possible to eliminate screen distortion (horizontal stripe-like unevenness) of the first frame, which has been a problem with conventional CC driving.
- the phase of the polarity signal POL is set to 2H (supplied to the same data signal line) only by shifting the phase of the CMI2 signal by a half cycle (from FIG. 31).
- the polarity of the data signal is inverted every 2H), and each pixel row can be appropriately CC-driven from the first frame. That is, in the liquid crystal display device 3h, the period of the polarity signal POL can be switched from 1H to 2H only by controlling the phases of the CS inversion signals CMI1 and CMI2 signals, and the screen disturbance at that time is greatly reduced. Can do.
- gate driver source driver, or gate-CS driver and the pixel circuit of the display unit may be formed monolithically (on the same substrate).
- the preparatory operation before the display start (for example, when the power is turned on or when the display image is switched) has been described as an example.
- the same operation simultaneous selection of scanning signal lines and (Initialization of the shift register) may be performed.
- the output side of the two conductive electrodes of the transistor (P channel or N channel) is called a drain terminal.
- This shift register is a shift register used in a display drive circuit that simultaneously selects a plurality of signal lines at a predetermined timing, for example, and a set / reset type flip-flop and a simultaneous selection signal are input to each stage, And a signal generation circuit that generates an output signal of its own stage using the output of the flip-flop.
- the output signal of each stage becomes active by the activation of the simultaneous selection signal and is active during the simultaneous selection.
- the output of the flip-flop is inactive during a period in which both the set signal and the reset signal are active.
- both the set signal and the reset signal input to each flip-flop are active.
- the flip-flops in each stage are initialized (inactive) during the simultaneous selection period. ) That is, the shift register is initialized during the simultaneous selection, and the simultaneous selection and the initialization of the shift register can be completed quickly. Further, the configuration for generating and transmitting the initialization signal for the shift register is not necessary, and various drivers including the shift register can be downsized.
- the signal generation circuit may include a gate circuit that selectively captures and outputs a signal corresponding to an input switching signal.
- This shift register may be configured such that the output of the flip-flop is input to the gate circuit as the switching signal.
- the signal generation circuit further includes a logic circuit, the output of the flip-flop is input to the logic circuit, the output of the logic circuit is input to the gate circuit as the switching signal, and the output signal of its own stage is A configuration in which feedback is provided to the logic circuit and the reset terminal of the flip-flop may be employed.
- This shift register can be configured such that the output signal of its own stage is the output of the gate circuit.
- the signal generation circuit may include an output circuit that outputs its own output signal in accordance with the output of the gate circuit and the simultaneous selection signal.
- the gate circuit may be configured to selectively capture the simultaneous selection signal or the clock signal.
- the gate circuit may be configured to selectively capture a constant potential signal or a clock signal equal to the power supply potential.
- the logic circuit may include NAND or NOR.
- the NAND includes a plurality of P-channel transistors and a plurality of N-channel transistors.
- the driving capability of each P-channel transistor is higher than the driving capability of each N-channel transistor. It can also be configured.
- the NOR is composed of a plurality of P-channel transistors and a plurality of N-channel transistors.
- the drive capability of each N-channel transistor is higher than the drive capability of each P-channel transistor. It can also be configured.
- both the set signal and the reset signal are active before the end of the simultaneous selection, and the set signal is deactivated before the reset signal after the simultaneous selection ends. You can also.
- the flip-flop can be configured to have no input terminal other than the set terminal and the reset terminal.
- the flip-flop includes a first CMOS circuit in which gate terminals and drain terminals of a P-channel first transistor and an N-channel second transistor are connected to each other, a P-channel third transistor and an N-channel transistor.
- a gate side of the first CMOS circuit comprising a second CMOS circuit in which the gate terminals and drain terminals of the fourth transistor are connected to each other, a set transistor, a set terminal and a reset terminal, and first and second output terminals.
- drain side of the second CMOS circuit and the first output terminal are connected, the gate side of the second CMOS circuit, the drain side of the first CMOS circuit and the second output terminal are connected, and the set transistor has a gate terminal Connected to the set terminal and the source terminal to the reset terminal It is connected to, and drain terminal may be a configuration that is connected to the first output terminal.
- the set transistor is a P-channel, and the set signal may be configured to have a first potential when inactive and a second potential lower than the first potential when active.
- the shift register may include a reset transistor having a gate terminal connected to the reset terminal, a source terminal connected to the first power supply line, and a drain terminal connected to the second output terminal.
- the gate terminal is connected to the reset terminal, the source terminal is connected to the second power supply line, the drain terminal is connected to the source terminal of the second transistor, and the gate terminal is for setting. It may be configured to include at least one of a release transistor connected to the terminal, a source terminal connected to the second power supply line, and a drain terminal connected to the source terminal of the fourth transistor.
- This display drive circuit includes the shift register.
- the display drive circuit includes the shift register (self-reset type), and fixes the clock signal to active while simultaneous selection is performed.
- This display panel is characterized in that the display driving circuit and the pixel circuit are monolithically formed.
- This display device includes the shift register.
- the display driving circuit includes a pixel electrode connected to the data signal line and the scanning signal line through a switching element, and a signal potential written to the pixel electrode in a storage capacitor wiring that forms a capacitance with the pixel electrode. It is used for a display device that supplies a modulation signal corresponding to the polarity of the above, and includes the shift register.
- one holding circuit is provided corresponding to each stage of the shift register, and a holding target signal is input to each holding circuit, and when the control signal generated in the own stage becomes active,
- the holding circuit corresponding to the stage captures and holds the above holding target signal, supplies the output signal of the own stage to the scanning signal line connected to the pixel corresponding to the own stage, and the holding circuit corresponding to the own stage.
- one holding circuit is provided corresponding to each stage of the shift register, and when a holding target signal is input to each holding circuit and a control signal generated in one stage is activated.
- the holding circuit corresponding to this stage takes in the holding target signal and holds it, supplies the output of one holding circuit as the modulation signal to the holding capacitor wiring, and the control signal generated at each stage is displayed. It is also possible to adopt a configuration that becomes active before the first vertical scanning period of the image.
- This display drive circuit may be configured to invert the polarity of the signal potential supplied to the data signal line every plural horizontal scanning periods.
- one holding circuit is provided corresponding to each stage of the shift register, and a holding target signal is input to each holding circuit, and the output signal of the own stage and the output of the subsequent stage of the own stage are output.
- Signal is input to the logic circuit, and when the output of the logic circuit becomes active, the holding circuit corresponding to the own stage takes in the holding target signal and holds it, and the output signal of the own stage is sent to the own stage.
- the output of the holding circuit corresponding to the own stage is supplied as the modulation signal to the holding capacitor wiring forming the capacitor and the pixel electrode of the pixel corresponding to the own stage.
- the phase of the holding target signal input to the plurality of holding circuits may be different from the phase of the holding target signal input to another plurality of holding circuits.
- one holding circuit is provided corresponding to each stage of the shift register, and a holding target signal is input to each holding circuit, and when the control signal generated in the own stage becomes active,
- the holding circuit corresponding to the stage captures and holds the above holding target signal, supplies the output signal of the own stage to the scanning signal line connected to the pixel corresponding to the own stage, and the holding circuit corresponding to the own stage.
- the polarity of the signal potential supplied to the data signal line is inverted every n horizontal scanning periods (n is a natural number) and the polarity of the signal potential supplied to the data signal line is m horizontal scanning. It can also be set as the structure which switches the mode reversed every period (m is a natural number different from n).
- the phase of the holding target signal input to each holding circuit belonging to the first group and the phase of the holding target signal input to each holding circuit belonging to the second group are determined according to each mode. It can also be set as the structure to set.
- the present invention is not limited to the above-described embodiments, and those obtained by appropriately modifying the above-described embodiments based on known techniques and common general knowledge or combinations thereof are also included in the embodiments of the present invention. It is. In addition, the operational effects described in each embodiment are merely examples.
- the shift register of the present invention is suitable for various drivers, particularly for liquid crystal display devices.
- Liquid crystal display device ASW1 to ASW12 asw Analog switch SR Shift register SRi i stage of shift register DCC display control circuit GD gate driver SD source driver G-CsD gate-Cs driver DAR display unit Gn scanning signal line CSn holding capacitor wiring PIXn D-slot circuit corresponding to i stage of pixel CSLi SR FF flip-flop ST set transistor (input transistor) RT reset transistor (input transistor) LRT Latch release transistor LC Latch circuit POL (Data) polarity signal CMI1 CMI2 CS inversion signal
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Abstract
Description
図1は本発明にかかる液晶表示装置3aの構成を示す回路図である。液晶表示装置3aは、表示部DAR、ゲートドライバGD、ソースドライバSD、および表示制御回路DCCを備える。表示制御回路DCCは、ゲートドライバGDに、AONB信号(全ON信号)、ゲートスタートパルスGSP、ゲートオンイネーブル信号GOE、およびゲートクロック信号GCK1B・GCK2Bを供給する。また、表示制御回路DCCは、ソースドライバSDに、ソーススタートパルスSSP、デジタルデータDAT、極性信号POL、およびソースクロック信号SCKを供給する。ゲートドライバGDには、複数段からなるシフトレジスタSRが含まれている。以下適宜、シフトレジスタのi段(i=1・・・n-1・n・n+1・・・)をi段SRiと略記する。 [Embodiment 1]
FIG. 1 is a circuit diagram showing a configuration of a liquid
図10は本発明にかかる液晶表示装置3dの構成を示す回路図である。液晶表示装置3dは、表示部DAR、ゲートドライバGD、ソースドライバSD、および表示制御回路DCCを備える。表示制御回路DCCは、ゲートドライバGDに、AONB信号(全ON信号)、ゲートスタートパルスGSP、ゲートオンイネーブル信号GOE、およびゲートクロック信号GCK1B・GCK2Bを供給する。また、表示制御回路DCCは、ソースドライバSDに、ソーススタートパルスSSP、デジタルデータDAT、極性信号POL、およびソースクロック信号SCKを供給する。ゲートドライバGDには、複数段からなるシフトレジスタSRが含まれている。以下適宜、シフトレジスタのi段(i=1・・・n-1・n・n+1・・・)をi段SRiと略記する。 [Embodiment 2]
FIG. 10 is a circuit diagram showing a configuration of a liquid
n50およびn51それぞれのドレインをVSSに接続しておき、Nチャネルトランジスタn50・51の駆動能力を、Pチャネルトランジスタp50・51のそれよりも大きくしておく。こうすれば、QB信号が十分に非アクティブ(High)になるまで、OUTB信号がアクティブ(=Low)を保つようになり、FFのR端子へのフィードバックがNORへのフィードバックよりも先立ってしまうことを防止することができる。 Note that in the configuration of FIG. 22 (FF is a reset priority and each stage of the shift register is a self-reset type), the feedback of the OUTB signal to the R terminal of the flip-flop may precede the feedback to the NOR. There is. Therefore, the NOR in FIG. 22 is preferably configured as shown in FIG. That is, the source of the P-channel transistor p50 is connected to VDD, the gate is connected to the NOR input X and the gate of the N-channel transistor n51, the drain is connected to the source of the P-channel transistor p51, and the gate of the P-channel transistor p51 Is connected to the NOR input Y and the gate of the N-channel transistor n50, and the drain is connected to the source of n50, the source of n51 and the output M of the NOR,
The drains of n50 and n51 are connected to VSS, and the drive capability of the N-channel transistors n50 and 51 is made larger than that of the P-channel transistors p50 and 51. By doing so, the OUTB signal remains active (= Low) until the QB signal becomes sufficiently inactive (High), and the feedback to the R terminal of the FF precedes the feedback to the NOR. Can be prevented.
図25は本発明にかかる液晶表示装置3gの構成を示す回路図である。液晶表示装置3gはいわゆるCC(charge coupled)駆動の液晶表示装置であり、表示部DAR、ゲート・CsドライバG-CsD、ソースドライバSD、および表示制御回路DCCを備える。表示制御回路DCCは、ゲートドライバGDに、ゲートスタートパルスGSP、ゲートオンイネーブル信号GOE、AONB信号(全ON信号)、CS反転信号CMI1・CMI2、およびゲートクロック信号GCK1B・GCK2Bを供給する。また、表示制御回路DCCは、ソースドライバSDに、ソーススタートパルスSSP、デジタルデータDAT、極性信号POL、およびソースクロック信号SCKを供給する。ゲート・CsドライバG-CsDには、複数段からなるシフトレジスタSRと、複数のDラッチ回路CSLが含まれ、シフトレジスタの1段に対応して、1つのインバータと、1つのOR回路と、1つのDラッチ回路CSLとが設けられている。以下適宜、シフトレジスタのi段(i=1・・・n-1・n・n+1・・・)をi段SRiと略記する。また、シフトレジスタのi段SRiに対応して、Dラッチ回路CSLiが設けられている。 [Embodiment 3]
FIG. 25 is a circuit diagram showing a configuration of a liquid
図30は本発明にかかる液晶表示装置3hの構成を示す回路図である。液晶表示装置3hはいわゆるCC(charge coupled)駆動の液晶表示装置であり、表示部DAR、ゲート・CsドライバG-CsD、ソースドライバSD、および表示制御回路DCCを備える。表示制御回路DCCは、ゲートドライバGDに、ゲートスタートパルスGSP、ゲートオンイネーブル信号GOE、AONB信号(全ON信号)、CS反転信号CMI1・CMI2、およびゲートクロック信号GCK1B・GCK2Bを供給する。また、表示制御回路DCCは、ソースドライバSDに、ソーススタートパルスSSP、デジタルデータDAT、極性信号POL、およびソースクロック信号SCKを供給する。ゲート・CsドライバG-CsDには、複数段からなるシフトレジスタSRと、複数のDラッチ回路CSLが含まれ、シフトレジスタの1段に対応して、1つのインバータと、1つのDラッチ回路CSLと、1つのバッファとが設けられている。以下適宜、シフトレジスタのi段(i=1・・・n-1・n・n+1・・・)をi段SRiと略記する。また、シフトレジスタのi段SRiに対応して、Dラッチ回路CSLiが設けられている。 [Embodiment 4]
FIG. 30 is a circuit diagram showing a configuration of a liquid
ASW1~ASW12 asw アナログスイッチ
SR シフトレジスタ
SRi シフトレジスタのi段
DCC 表示制御回路
GD ゲートドライバ
SD ソースドライバ
G-CsD ゲート-Csドライバ
DAR 表示部
Gn 走査信号線
CSn 保持容量配線
PIXn 画素
CSLi SRのi段に対応するDラッチ回路
FF フリップフロップ
ST セットトランジスタ(入力トランジスタ)
RT リセットトランジスタ(入力トランジスタ)
LRT ラッチ解除トランジスタ
LC ラッチ回路
POL (データ)極性信号
CMI1 CMI2 CS反転信号 3a to 3h Liquid crystal display device ASW1 to ASW12 asw Analog switch SR Shift register SRi i stage of shift register DCC display control circuit GD gate driver SD source driver G-CsD gate-Cs driver DAR display unit Gn scanning signal line CSn holding capacitor wiring PIXn D-slot circuit corresponding to i stage of pixel CSLi SR FF flip-flop ST set transistor (input transistor)
RT reset transistor (input transistor)
LRT Latch release transistor LC Latch circuit POL (Data) polarity signal CMI1 CMI2 CS inversion signal
Claims (29)
- 所定のタイミングで複数の信号線の同時選択を行う表示駆動回路に用いられるシフトレジスタであって、
各段に、セットリセット型のフリップフロップと、同時選択信号が入力され、上記フリップフロップの出力を用いて自段の出力信号を生成する信号生成回路とを含み、
各段の出力信号は、上記同時選択信号のアクティブ化によりアクティブとなって上記同時選択が行われる間アクティブとされ、
上記フリップフロップの出力は、セット用信号およびリセット用信号がともにアクティブである期間に非アクティブとなることを特徴とするシフトレジスタ。 A shift register used in a display driving circuit that simultaneously selects a plurality of signal lines at a predetermined timing,
Each stage includes a set-reset type flip-flop and a signal generation circuit that receives a simultaneous selection signal and generates an output signal of the own stage using the output of the flip-flop.
The output signal of each stage is activated by the activation of the simultaneous selection signal, and is active during the simultaneous selection.
The output of the flip-flop is inactive during a period in which both the set signal and the reset signal are active. - 上記信号生成回路は、入力される切り替え信号に応じた信号を選択的に取り込んで出力するゲート回路を備えることを特徴とする請求項1記載のシフトレジスタ。 The shift register according to claim 1, wherein the signal generation circuit includes a gate circuit that selectively takes in and outputs a signal corresponding to an input switching signal.
- フリップフロップの出力が上記切り替え信号としてゲート回路に入力されていることを特徴とする請求項2記載のシフトレジスタ。 The shift register according to claim 2, wherein the output of the flip-flop is input to the gate circuit as the switching signal.
- 上記信号生成回路はさらに論理回路を備え、
上記フリップフロップの出力が論理回路に入力され、該論理回路の出力が上記切り替え信号としてゲート回路に入力され、自段の出力信号が該論理回路と上記フリップフロップのリセット用端子とにフィードバックされていることを特徴とする請求項2記載のシフトレジスタ。 The signal generation circuit further includes a logic circuit,
The output of the flip-flop is input to the logic circuit, the output of the logic circuit is input to the gate circuit as the switching signal, and the output signal of its own stage is fed back to the logic circuit and the reset terminal of the flip-flop. 3. The shift register according to claim 2, wherein: - 自段の出力信号はゲート回路の出力であることを特徴とする請求項3または4記載のシフトレジスタ。 5. The shift register according to claim 3, wherein the output signal of the own stage is an output of a gate circuit.
- 上記信号生成回路は、ゲート回路の出力と同時選択信号とに応じて自段の出力信号を出力する出力回路を備えることを特徴とする請求項3または4記載のシフトレジスタ。 5. The shift register according to claim 3, wherein the signal generation circuit includes an output circuit that outputs an output signal of its own stage according to the output of the gate circuit and the simultaneous selection signal.
- 上記ゲート回路は、上記同時選択信号またはクロック信号を選択的に取り込むことを特徴とする請求項5記載のシフトレジスタ。 6. The shift register according to claim 5, wherein the gate circuit selectively takes in the simultaneous selection signal or the clock signal.
- 上記ゲート回路は、電源電位に等しい定電位信号またはクロック信号を選択的に取り込むことを特徴とする請求項6記載のシフトレジスタ。 The shift register according to claim 6, wherein the gate circuit selectively takes in a constant potential signal or a clock signal equal to a power supply potential.
- 上記論理回路に、NANDあるいはNORが含まれていることを特徴とする請求項4記載のシフトレジスタ。 5. The shift register according to claim 4, wherein the logic circuit includes NAND or NOR.
- 上記NANDは複数のPチャネルのトランジスタと複数のNチャネルのトランジスタとからなり、該NANDでは、Pチャネルの各トランジスタの駆動能力が、Nチャネルの各トランジスタの駆動能力よりも高いことを特徴とする請求項9記載のシフトレジスタ。 The NAND is composed of a plurality of P-channel transistors and a plurality of N-channel transistors, and in the NAND, the drive capability of each P-channel transistor is higher than the drive capability of each N-channel transistor. The shift register according to claim 9.
- 上記NORは複数のPチャネルのトランジスタと複数のNチャネルのトランジスタとからなり、該NANDでは、Nチャネルの各トランジスタの駆動能力が、Pチャネルの各トランジスタの駆動能力よりも高いことを特徴とする請求項9記載のシフトレジスタ。 The NOR includes a plurality of P-channel transistors and a plurality of N-channel transistors. In the NAND, the drive capability of each N-channel transistor is higher than the drive capability of each P-channel transistor. The shift register according to claim 9.
- 上記同時選択の終了前はセット用信号およびリセット用信号がともにアクティブであり、同時選択の終了後は、リセット用信号よりもセット用信号が先に非アクティブ化することを特徴とする請求項1記載のシフトレジスタ。 2. The set signal and the reset signal are both active before the end of the simultaneous selection, and the set signal is deactivated prior to the reset signal after the simultaneous selection ends. The shift register described.
- 上記フリップフロップは、セット用端子およびリセット用端子以外の入力端子を持たないことを特徴とする請求項1記載のシフトレジスタ。 The shift register according to claim 1, wherein the flip-flop does not have an input terminal other than a set terminal and a reset terminal.
- 上記フリップフロップは、Pチャネルの第1トランジスタとNチャネルの第2トランジスタのゲート端子同士およびドレイン端子同士が接続された第1CMOS回路と、Pチャネルの第3トランジスタとNチャネルの第4トランジスタのゲート端子同士およびドレイン端子同士が接続された第2CMOS回路と、セットトランジスタと、セット用端子およびリセット用端子と、第1および第2出力端子とを備え、
第1CMOS回路のゲート側と第2CMOS回路のドレイン側と第1出力端子とが接続されるとともに、第2CMOS回路のゲート側と第1CMOS回路のドレイン側と第2出力端子とが接続され、
上記セットトランジスタは、ゲート端子がセット用端子に接続されるとともにソース端子がリセット用端子に接続され、かつドレイン端子が第1出力端子に接続されていることを特徴とする請求項1記載のシフトレジスタ。 The flip-flop includes a first CMOS circuit in which gate terminals and drain terminals of a P-channel first transistor and an N-channel second transistor are connected to each other; a gate of a P-channel third transistor and an N-channel fourth transistor; A second CMOS circuit in which terminals and drain terminals are connected, a set transistor, a set terminal and a reset terminal, and first and second output terminals;
The gate side of the first CMOS circuit, the drain side of the second CMOS circuit, and the first output terminal are connected, and the gate side of the second CMOS circuit, the drain side of the first CMOS circuit, and the second output terminal are connected,
2. The shift according to claim 1, wherein the set transistor has a gate terminal connected to the set terminal, a source terminal connected to the reset terminal, and a drain terminal connected to the first output terminal. register. - 上記セットトランジスタはPチャネルであって、セット用信号は、非アクティブ時に第1電位でアクティブ時に第1電位よりも低い第2電位となることを特徴とする請求項14記載のシフトレジスタ。 15. The shift register according to claim 14, wherein the set transistor is a P-channel, and the set signal has a first potential when inactive and a second potential lower than the first potential when active.
- ゲート端子がリセット用端子に接続されるとともにソース端子が第1電源ラインに接続され、かつドレイン端子が第2出力端子に接続されたリセットトランジスタを備えることを特徴とする請求項14記載のシフトレジスタ。 15. The shift register according to claim 14, further comprising a reset transistor having a gate terminal connected to the reset terminal, a source terminal connected to the first power supply line, and a drain terminal connected to the second output terminal. .
- ゲート端子がリセット用端子に接続されるとともにソース端子が第2電源ラインに接続され、かつドレイン端子が第2トランジスタのソース端子に接続されたリリーストランジスタと、ゲート端子がセット用端子に接続されるとともにソース端子が第2電源ラインに接続され、かつドレイン端子が第4トランジスタのソース端子に接続されたリリーストランジスタとの少なくとも一方を備えることを特徴とする請求項14記載のシフトレジスタ。 A release transistor having a gate terminal connected to the reset terminal, a source terminal connected to the second power supply line, a drain terminal connected to the source terminal of the second transistor, and a gate terminal connected to the set terminal. The shift register according to claim 14, further comprising at least one of a release transistor having a source terminal connected to the second power supply line and a drain terminal connected to the source terminal of the fourth transistor.
- 請求項1~17のいずれか1項に記載のシフトレジスタを備えることを特徴とする表示駆動回路。 A display drive circuit comprising the shift register according to any one of claims 1 to 17.
- 請求項7または8に記載のシフトレジスタを備え、
同時選択が行われる間は上記クロック信号をアクティブに固定することを特徴とする表示駆動回路。 A shift register according to claim 7 or 8,
A display driving circuit, wherein the clock signal is fixed to be active while simultaneous selection is performed. - 請求項18または19記載の表示駆動回路と画素回路とがモノリシックに形成されていることを特徴とする表示パネル。 20. A display panel, wherein the display drive circuit and the pixel circuit according to claim 18 or 19 are monolithically formed.
- 請求項1~17のいずれか1項に記載のシフトレジスタを備えることを特徴とする表示装置。 A display device comprising the shift register according to any one of claims 1 to 17.
- スイッチング素子を介してデータ信号線および走査信号線に接続される画素電極を備えるとともに、該画素電極と容量を形成する保持容量配線に、該画素電極に書き込まれた信号電位の極性に応じた変調信号を供給する表示装置に用いられ、請求項1~17のいずれか1項に記載のシフトレジスタを備えることを特徴とする表示駆動回路。 A pixel electrode connected to the data signal line and the scanning signal line via the switching element is provided, and the storage capacitor wiring that forms a capacitance with the pixel electrode is modulated according to the polarity of the signal potential written to the pixel electrode A display driving circuit, comprising a shift register according to any one of claims 1 to 17, which is used in a display device that supplies a signal.
- 上記シフトレジスタの各段に対応して保持回路が1つずつ設けられるとともに、各保持回路に保持対象信号が入力され、自段で生成された制御信号がアクティブになると自段に対応する保持回路が上記保持対象信号を取り込んでこれを保持し、
自段の出力信号を、自段に対応する画素と接続する走査信号線に供給するとともに、自段に対応する保持回路の出力を、自段よりも前の段に対応する画素の画素電極と容量を形成する保持容量配線に、上記変調信号として供給することを特徴とする請求項22記載の表示駆動回路。 One holding circuit is provided corresponding to each stage of the shift register, and when a holding target signal is input to each holding circuit and the control signal generated in the own stage becomes active, the holding circuit corresponding to the own stage Captures the signal to be held and holds it,
The output signal of the own stage is supplied to the scanning signal line connected to the pixel corresponding to the own stage, and the output of the holding circuit corresponding to the own stage is supplied to the pixel electrode of the pixel corresponding to the stage before the own stage. The display drive circuit according to claim 22, wherein the modulation signal is supplied to a storage capacitor line forming a capacitor. - 上記シフトレジスタの各段に対応して保持回路が1つずつ設けられるとともに、各保持回路に保持対象信号が入力され、
1つの段で生成された制御信号がアクティブになるとこの段に対応する保持回路が上記保持対象信号を取り込んでこれを保持し、
1つの保持回路の出力を、上記変調信号として保持容量配線に供給し、
各段で生成される制御信号が、表示映像の最初の垂直走査期間よりも前にアクティブとなることを特徴とする請求項22記載の表示駆動回路。 A holding circuit is provided for each stage of the shift register, and a holding target signal is input to each holding circuit.
When the control signal generated in one stage becomes active, the holding circuit corresponding to this stage takes in the holding target signal and holds it,
The output of one holding circuit is supplied to the holding capacitor wiring as the modulation signal,
23. The display driving circuit according to claim 22, wherein the control signal generated at each stage becomes active before the first vertical scanning period of the display image. - 上記データ信号線に供給される信号電位の極性を複数水平走査期間ごとに反転させることを特徴とする請求項22記載の表示駆動回路。 23. The display driving circuit according to claim 22, wherein the polarity of the signal potential supplied to the data signal line is inverted every a plurality of horizontal scanning periods.
- 上記シフトレジスタの各段に対応して保持回路が1つずつ設けられるとともに、各保持回路に保持対象信号が入力され、
自段の出力信号と自段よりも後段の出力信号とが論理回路に入力されるとともに、該論理回路の出力がアクティブになると自段に対応する保持回路が上記保持対象信号を取り込んでこれを保持し、
自段の出力信号を、自段に対応する画素と接続する走査信号線に供給するとともに、自段に対応する保持回路の出力を、自段に対応する画素の画素電極と容量を形成する保持容量配線に、上記変調信号として供給し、
複数の保持回路に入力される保持対象信号の位相と、別の複数の保持回路に入力される保持対象信号の位相とを異ならせていることを特徴とする請求項25記載の表示駆動回路。 A holding circuit is provided for each stage of the shift register, and a holding target signal is input to each holding circuit.
The output signal of the own stage and the output signal of the subsequent stage from the own stage are input to the logic circuit, and when the output of the logic circuit becomes active, the holding circuit corresponding to the own stage takes in the hold target signal and outputs it. Hold and
The output signal of the own stage is supplied to the scanning signal line connected to the pixel corresponding to the own stage, and the output of the holding circuit corresponding to the own stage is held to form the pixel electrode and the capacitor of the pixel corresponding to the own stage. Supply to the capacitance wiring as the modulation signal,
26. The display driving circuit according to claim 25, wherein the phase of the holding target signal input to the plurality of holding circuits is different from the phase of the holding target signal input to another plurality of holding circuits. - 上記シフトレジスタの各段に対応して保持回路が1つずつ設けられるとともに、各保持回路に保持対象信号が入力され、自段で生成された制御信号がアクティブになると自段に対応する保持回路が上記保持対象信号を取り込んでこれを保持し、
自段の出力信号を、自段に対応する画素と接続する走査信号線に供給するとともに、自段に対応する保持回路の出力を、自段よりも前の段に対応する画素の画素電極と容量を形成する保持容量配線に、上記変調信号として供給し、
複数の保持回路に入力される保持対象信号の位相と、別の複数の保持回路に入力される保持対象信号の位相とを異ならせていることを特徴とする請求項25記載の表示駆動回路。 One holding circuit is provided corresponding to each stage of the shift register, and when a holding target signal is input to each holding circuit and the control signal generated in the own stage becomes active, the holding circuit corresponding to the own stage Captures the signal to be held and holds it,
The output signal of the own stage is supplied to the scanning signal line connected to the pixel corresponding to the own stage, and the output of the holding circuit corresponding to the own stage is supplied to the pixel electrode of the pixel corresponding to the stage before the own stage. Supply the modulation signal to the storage capacitor wiring that forms the capacitor,
26. The display driving circuit according to claim 25, wherein the phase of the holding target signal input to the plurality of holding circuits is different from the phase of the holding target signal input to another plurality of holding circuits. - 上記データ信号線に供給される信号電位の極性をn水平走査期間(nは自然数)ごとに反転させるモードと、データ信号線に供給される信号電位の極性をm水平走査期間(mはnと異なる自然数)ごとに反転させるモードとを切り替えることを特徴とする請求項26または27記載の表示駆動回路。 A mode in which the polarity of the signal potential supplied to the data signal line is inverted every n horizontal scanning periods (n is a natural number), and the polarity of the signal potential supplied to the data signal line is changed to m horizontal scanning period (m is n 28. The display driving circuit according to claim 26, wherein the mode to be inverted is switched every different natural number).
- 第1グループに属する各保持回路に入力される保持対象信号の位相と、第2グループに属する各保持回路に入力される保持対象信号の位相とを、各モードに応じて設定することを特徴とする請求項28記載の表示駆動回路。 The phase of the holding target signal input to each holding circuit belonging to the first group and the phase of the holding target signal input to each holding circuit belonging to the second group are set according to each mode. The display drive circuit according to claim 28.
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- 2010-03-18 US US13/377,838 patent/US9070471B2/en not_active Expired - Fee Related
- 2010-03-18 CN CN201080026970.9A patent/CN102804253B/en not_active Expired - Fee Related
- 2010-03-18 WO PCT/JP2010/001962 patent/WO2010146752A1/en active Application Filing
- 2010-03-18 JP JP2011519491A patent/JP5575764B2/en not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
CN102804253A (en) | 2012-11-28 |
EP2444958B1 (en) | 2017-09-20 |
JPWO2010146752A1 (en) | 2012-11-29 |
RU2510953C2 (en) | 2014-04-10 |
US20120081346A1 (en) | 2012-04-05 |
RU2012100268A (en) | 2013-07-20 |
EP2444958A4 (en) | 2014-11-05 |
US9070471B2 (en) | 2015-06-30 |
CN102804253B (en) | 2015-11-25 |
BRPI1012072A2 (en) | 2016-03-22 |
JP5575764B2 (en) | 2014-08-20 |
EP2444958A1 (en) | 2012-04-25 |
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