GB2452278A - A scan pulse shift register for an active matrix LCD display - Google Patents

A scan pulse shift register for an active matrix LCD display Download PDF

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Publication number
GB2452278A
GB2452278A GB0716753A GB0716753A GB2452278A GB 2452278 A GB2452278 A GB 2452278A GB 0716753 A GB0716753 A GB 0716753A GB 0716753 A GB0716753 A GB 0716753A GB 2452278 A GB2452278 A GB 2452278A
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Prior art keywords
stage
output
shift register
stages
connected
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GB0716753A
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GB0716753D0 (en
Inventor
Gareth John
Patrick Zebedee
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Sharp Corp
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Sharp Corp
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Priority to GB0716753A priority Critical patent/GB2452278A/en
Publication of GB0716753D0 publication Critical patent/GB0716753D0/en
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Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3674Details of drivers for scan electrodes
    • G09G3/3677Details of drivers for scan electrodes suitable for active matrices only
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores
    • G11C19/28Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores using semiconductor elements
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202Addressing of scan or signal lines
    • G09G2310/0205Simultaneous scanning of several lines in flat panels
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/0291Details of output amplifiers or buffers arranged for use in a driving circuit
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/04Partial updating of the display screen

Abstract

The stages of a scan pulse shift register are activated in sequence during normal operation to output a high level via transistor 56 on one stage output GL in turn. Each stage comprises a logic circuit 34 controlling the output transistors 56,58. The transistor 58, which is conventionally connected to a low logic level, is connected to a signal ALLON which is low in normal operation but which may be placed at a high level so that the output GL of any stage to which ALLON is connected is made high instead of low. This simple adaptation allows all rows in the display, or all rows in a portion of the display, to be activated simultaneously, for example to remove charge from the pixels and prevent noise on the display. The logic circuit may comprise a reset-over-set flip-flop. The bootstrap capacitors 64,74 improve the output high level.

Description

Shift Register, Display Driver and Display The present invention relates to a shift register and to a display driver and a display including such a shift register. Such a shift register may be used, for example, as or in a clock generator for driving the rows andlor columns of an active matrix display.

Figure 1 of the accompanying drawings shows a typical active matrix display. Such a display is made up of a matrix 2 of picture elements (pixels), arranged in M rows and N columns. Each row and column is connected to an electrode, with the column electrodes being connected to the N outputs of a data driver 4 and the row electrodes being connected to the M outputs of a scan driver 6.

The pixels are addressed one row at a time. The scan driver includes an M-phase clock generator, which produces a series of clock pulses as shown in Figure 2 of the accompanying drawings. Each clock pulse OUT1 controls the activation of row i. It is usual for the pulses to be non-overlapping, such that no two pulses are high at the same time.

However, it is common to activate all rows simultaneously (all-on'). This typically occurs at the start and end of operation to remove electric charge from the pixels and prevent noise on the display.

All the pixels of one row may be addressed simultaneously, or they may be addressed in B blocks of b pixels, where bB = N. In the latter case, the data driver may also include a B-phase clock generator of the type described, such that, each clock pulse OUT1 activates block i.

It is also a common requirement for small displays to have a mode where only a portion of the display is refreshed. This is often used to give low power, for example when the display is showing a stand-by image on a limited number of rows. In this case, only the rows corresponding to the partial image are refreshed during every scan. The full screen is refreshed less frequently. Figure 3 of the accompanying drawings shows the outputs of the scan driver during a frame when only the partial image is being refreshed. Rows X to Y are activated in turn whereas other rows are not activated, in this case, the partial image would cover row X to row Y. A full screen refresh requires all rows to be activated in turn. The time taken for a partial image refresh is the same for a full screen refresh. Rows X to Y in Figure 3 can therefore each be charged for longer than each row in a full screen refresh. This reduces power consumption. A full screen refresh requires each row to be activated at a higher rate.

Scan drivers of the type described may be formed directly on the display substrate, reducing the number of connections required to the display. This is advantageous, since it reduces the area occupied by the connector and leads to a display which is more mechanically robust. In such cases, it is common to use a single type of transistor for the clock generator circuit (single-channel'). For example, the circuit may be composed of only n-type transistors rather than a mixture of n-and p-type transistors as commonly used in CMOS circuits. The use of a single type of transistor is advantageous for manufacturing cost. However, it is difficult to design low-power, high-speed logic, such as OR gates and inverters, using a single type of transistor.

A clock generator for use in a scan driver may be formed from a shift register.

US7 145545 describes such a shift register. In this case, all rows are activated simultaneously to pre-charge all data lines to some intermediate data value, as shown in Figure 4 of the accompanying drawings. A start pulse and the simultaneous rise of three clock signals, CK1-CK3, initiate all-on.

An example of a single-channel scan driver is disclosed in US7038653, as shown in Figures 5 and 6 of the accompanying drawings. The scan driver comprises of a number of stages, 32. Each stage has three inputs: R, S and CK. The CK inputs of odd-number stages are connected to a first clock, CK1; the CK inputs of even-number stages are connected to a second clock, CK2.

Figure 6 shows the composition of two stages, 32, in Figure 5. The circuit is composed of only n-type transistors. Each shift register stage is composed of a control logic block, 14, and output stage, 15.

Figure 7 of the accompanying drawings illustrates the operation of the scan driver of Figure 6. QN represents the Q output of the logic block, 14, of stage N; GOUTN represents the output of the output stage, 15, of stage N, which also forms the output of the scan driver. When stage N is set, QN rises to a high logic level, and its output stage, 15, passes the clock to the output. When the clock rises, GOUTN rises, and this sets stage N+ 1 and resets stage N-i, such that QN+1 rises to a high logic level and QN-I falls to a low logic level. Stage N+1 is conFigured to pass the complement of the clock to its output, so the output initially remains low. When the clock falls, the output of stage N falls, and the output of stage N+ 1 rises. This resets stage N, preventing subsequent clock pulses from being passed to its output, and sets stage N+2.

The output stage used is common in such circuits: it is composed of two transistors, 10 and 12, and a bootstrap capacitor, 13. The transistors are controlled by the logic, such that exactly one transistor is activated at any time. The first transistor, 10, passes the clock directly to the output, with no additional logic or buffering; the second, 12, pulls the output to a low supply voltage.

The voltage at the source of an n-type transistor is normally no higher than VG -VTH, where VG is the gate voltage of the transistor and VTH is the threshold of the transistor.

The output of the logic, which supplies VG to the output switches is, in turn, no higher that Von, the high supply voltage, and is commonly no higher than Von -VTH, for similar reasons (it is generated by a transistor whose gate is no higher than VON). It is preferable to pass the full voltage of the clock to the output (otherwise, it would be necessary to increase the voltage of the clock, which leads to higher power consumption). This requires a gate voltage of at least V1-1 + VTH, where VCKH is the clock high voltage (commonly equal to Von).

The bootstrap capacitor, 13, acts to increase the gate voltage of the first transistor when the clock rises. Its operation is as follows: the gate of transistor 10 is raised by the logic to a point where it conducts; when the clock rises, the rise is conducted to the output; this rise is coupled to the gate of transistor 10 by the capacitor 13, increasing the gate voltage, and ensuring that transistor 10 continues to conduct until its source and drain voltages are substantially equal.

A disadvantage of the circuit in Figure 6 is that stages will attempt to set and reset simultaneously when all outputs are activated. In this case, the logic will fail.

Another composition of two stages, 32, in Figure 5 is disclosed in US6300928, as shown in Figure 8 of the accompanying drawings. The circuit is composed of only n-type transistors. Each shift register stage is composed of a control logic block, 14, and output stage, 15. Operation is as previously described for Figure 6, with an additional transistor, 16, allowing the stages to be set only when CK1 or CK2 is active.

Some scan drivers incorporate all-on using logic gates at the shift register outputs. A common arrangement is shown in Figure 9 of the accompanying drawings. The output of each stage of the shift register, 28, is connected to an OR gate, 30. The other input of the OR gate is connected to an all-on signal, ALLON. The output of each OR gate forms one output of the scan driver, GL. The OR gates will therefore pass ALLON to the outputs of the scan driver while all stages are inactive, as shown in Figure 10 of the accompanying drawings.

The scan driver output may be connected to a substantial capacitive load. It is difficult to design low power single-channel OR gates capable of driving such loads at sufficient speed.

It is a requirement of liquid crystal displays to periodically alternate the drive voltage across the liquid crystal. This helps avoid degradation of the liquid crystal and image sticking, where previous images remain visible.

According to a first aspect of the invention, there is provided a shift register as defined in the appended claim 1.

According to a second aspect of the invention, there is provided a display driver as defined in the appended claim 26.

According to a third aspect of the invention, there is provided a display as defined in the appended claim 27.

Embodiments of the invention are defined in the other appended claims.

It is thus possible to provide an arrangement which provides an "all-on" or "partial all-on" function in a relatively simple and elegant way. For example, an existing arrangement may be used with minimal alteration to its circuit, resulting in minimal change in production yield and cost.

The invention will be further described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a block diagram illustrating a known type of active matrix display; Figure 2 is a waveform diagram illustrating output pulses of a typical scan driver of the display in Figure 1; Figure 3 is a waveform diagram illustrating scan driver output pulses in a partial mode of operation; Figure 4 is a waveform diagram illustrating known scan driver output pulses during pre-charge; Figures 5 and 6 are block schematic diagrams of known types of scan driver; Figure 7 is a waveform diagram illustrating the operation of the circuit in Figure 6; Figures 8 and 9 are block schematic diagrams of known types of scan driver; Figure 10 is a waveform diagram illustrating the operation of the circuit in Figure 9 during all-on operation; Figure 11 is a block schematic diagram of a multiple-stage scan driver constituting an embodiment of the invention; Figure 12 is a block schematic diagram of one of the stages of Figure 11; Figure 13 is a waveform diagram illustrating the operation of the circuit in Figure 12 during all-on operation; Figure 14 is a block schematic diagram of one of the stages of Figure 11, constituting another embodiment of the invention; Figure 15 is a block schematic diagram of one of the stages of Figure 11, constituting another embodiment of the invention; Figure 16 is a block schematic diagram of a multiple-stage scan driver constituting another embodiment of the invention; Figure 17 is a block schematic diagram of one of the stages of Figure 16; Figure 18 is a block schematic diagram of one of the stages of Figure 16, constituting another embodiment of the invention; Figure 19 is a waveform diagram illustrating the operation of the circuit in Figure 18 during all-on operation; Figure 20 is a block schematic diagram of a multiple-stage scan driver constituting another embodiment of the invention; Figure 21 is a block schematic diagram of one of the stages of Figure 20, constituting another embodiment of the invention; Figure 22 is a waveform diagram illustrating the operation of the circuit in Figure 21 during all-on operation; Figure 23 is a block schematic diagram of one of the stages of Figure 20, constituting another embodiment of the invention; Figure 24 is a block schematic diagram of a multiple-stage scan driver constituting another embodiment of the invention; Figure 25 is a waveform diagram illustrating the operation of the circuit in Figure 24 during a partial mode of operation; Figures 26 and 27 are block schematic diagrams of the stages of Figure 24, constituting another embodiment of the invention; Figure 28 is a block schematic diagram of a multiple-stage scan driver constituting another embodiment of the invention; Figure 29 is a waveform diagram illustrating the operation of the circuit in Figure 28; Figure 30 is a block schematic diagram of a multiple-stage scan driver constituting another embodiment of the invention; Figure 31 is a waveform diagram illustrating the operation of the circuit in Figure 30 during a partial mode of operation; and.

Figure 32 is a waveform diagram illustrating the operation of the circuit in Figure 30 during a partial mode of operation.

The first embodiment is shown in Figures 11 to 14. The scan driver is composed of a number of stages, 42. Each stage has four inputs: R, S, CK and ALLON. The CK inputs of odd-number stages are connected to a first clock, CK1; the CK inputs of even- number stages are connected to a second clock, CK2. The clocks are preferably non-overlapping, such that the scan driver outputs are non-overlapping. However, the clocks may also be complementary, such that the scan driver outputs have coincident edges.

The ALLON inputs of all stages are connected to a signal ALLON.

Each stage has an output GL. The GL output of each stage forms an output of the driver, GL1, and is connected to the S input of the succeeding stage and the R input of the preceding stage.

Figure 12 shows the composition of one stage, 42, of Figure 11. Each stage is composed of a logic block, 34, and two switches 36, 38. The logic has two inputs, S and R, which are connected to the S and R inputs of the stage, respectively, and two outputs Q and QB. The Q output is high when the logic is activated and low when it is deactivated; the QB output is the complement of Q. The logic may be embodied as a reset-over-set flip-flop (an RS flip-flop in which the logic will reset when set, S, and reset, R, inputs are active simultaneously).

The Q output of the logic is connected to the control terminal of switch 36; the QB output is connected to the control terminal of switch 38. Switch 36 is connected such that its principal conduction path is between the CK input and the GL output; switch 38 is connected such that its principal conduction path is between the ALLON input and the GL output.

The operation of the circuit is similar to that disclosed in US7038653. However, the GL outputs are now pulled down to ALLON instead of a low supply voltage. When all stages in Figure 11 are deactivated, for example during a global reset, all GL outputs are pulled down to ALLON, as shown in Figure 13. In normal mode, ALLON is inactive and held at a low voltage. When ALLON is active, all GL outputs are active simultaneously.

Figure 14 shows a transistor-level embodiment of the stage of Figure 12. The connections between the stages are as shown in Figure 11.

The scan driver is composed of n-type transistors only. Each stage is composed of a logic block, 44, two transistors 56, 58, and two bootstrap capacitors 64, 74. The logic has two inputs, S and R, which are connected to the S and R inputs of the stage, respectively, and two outputs Q and QB. The Q output is high when the logic is activated and low when it is deactivated; the QB output is the complement of Q. The logic may be of the form, 14, shown in Figure 8.

The Q output of the logic is connected to the control terminal of transistor 56; the QB output is connected to the control terminal of transistor 58. Transistor 56 is connected such that its principal conduction path is between the CK input and the GL output; transistor 58 is connected such that its principal conduction path is between the ALLON input and the GL output.

The bootstrap capacitor 64 is connected between the GL output and the Q output of the logic, and serves to ensure the voltage on the control electrode of the transistor 56 is boosted to a level sufficient for the high level of the CK input to conduct fully to GL.

The bootstrap capacitor 74 is connected between the GL output and the QB output of the logic. As before, this serves to ensure the voltage on the control electrode of transistor 58 is boosted to a level sufficient for the high level of ALLON to conduct fully to the GL output. However, it is also possible to connect the bootstrap capacitor between the ALLON input and the QB output of the logic, as shown in Figure 15.

The second and third embodiments concern isolating the GL outputs from the logic of the succeeding and preceding stages when ALLON is active.

The second embodiment is shown in Figures 16 and 17. The scan driver is composed of a number of stages, 52. Each stage has five inputs: R, S, CK, ALLON and ALLONB.

The CK inputs of odd-number stages are connected to a first clock, CK1; the CK inputs of even-number stages are connected to a second clock, CK2. The ALLON and ALLONB inputs of all stages are connected to the ALLON and ALLONB inputs of the scan driver respectively.

Each stage has two outputs: OUT and GL. The GL output of each stage forms an output of the driver, GL1; the OUT output of each stage is connected to the S input of the succeeding stage and the R input of the preceding stage.

Figure 17 shows the composition of one stage, 52, of Figure 16. Each stage is similar to that shown in Figure 12 and only the differences will be described. The ALLON input is connected to the control terminal of switch 42; the complement of ALLON, ALLONB, is connected to the control terminal of switch 40. Switch 40 is connected such that its principal conduction path is between the GL output and the OUT output; switch 42 is connected such that its principal conduction path is between the OUT output and a low supply voltage Vss. Switches 40, 42 are connected such that the OUT output is pulled down to a low supply voltage Vss when ALLON is active.

Figure 18 shows a transistor-level embodiment of the stage of Figure 17. Each stage is similar to that shown in Figure 14 and only the differences will be described. The logic may be of the form, 14, shown in Figure 6. The ALLON input is connected to the control terminal of transistor 22; the complement of ALLON, ALLONB, is connected to the control terminal of transistor 50. Transistor 50 is connected such that its principal conduction path *is between the GL output and the OUT output; transistor 22 is connected such that its principal conduction path is between the OUT output and the low supply voltage Vss. Transistors 56 and 58 therefore form the output switches; transistors 50 and 22 form the logic switches. The bootstrap capacitor, 54, is connected between the ALLONB input and the OUT output and operates as previously described.

Figure 19 shows the timing for the signals in Figure 18. The OUT output is pulled down to a low supply voltage when ALLON is active. When ALLON is inactive, ALLONB active, the GL and OUT outputs are connected. in this way, the OUT output is maintained inactive.

Figures 20 and 21 show an embodiment with the CK input connected to the control terminal of transistor 50. The scan driver is composed of a number of stages, 62. Each stage has four inputs: R, 5, CK and ALLON. The CK inputs of odd-number stages are connected to a first clock, CK1; the CK inputs of even-number stages are connected to a second clock, CK2. The ALLON inputs of all stages are connected to the ALLON input of the scan driver.

Figure 22 shows the timing for the signals in Figure 21. When ALLON is active, CK1 and CK2 are both inactive, and the OUT output is pulled down to a low supply voltage.

When ALLON is inactive, the GL and OUT outputs are connected when the CK input is active. In this way, the OUT output is maintained inactive.

*(The co-pending application is GBO7 16754.7) Our co-pending British patent application (filed on the same day as the present application and having Marks & Clerk reference number P54556GB) discloses a scan driver with dual output stages. This may be combined with the techniques disclosed herein to give a driver where activating all rows simultaneously does not affect the operation of the logic of succeeding and preceding stages. This is a third embodiment, as shown in Figure 23, which represents another composition of one stage, 62, of Figure 20.

The arrangement shown in Figure 23 differs from that shown in Figure 21 in that the transistors 50 and 22 are replaced by transistors 80 and 82, whose main conduction paths are connected in series between the clock input CK and the low or "negative" power supply line Vss. The gates of the transistors 80 and 82 are connected to the Q and QB outputs, respectively, of the logic block 44. The source of the transistor 80 and the drain of the transistor 82 are connected to the output OUT, which is connected via a bootstrap capacitor 84 to the gate of the transistor 80.

The stage shown in Figure 23 thus has a first output arrangement including the transistors 46 and 48 for providing the stage output GL and a second output arrangement including the transistors 80 and 82 for providing the output OUT, which is used to reset the preceding stage and to set the succeeding stage. The load presented, for example by each scan line and the pixels connected to it, to the stage output GL is typically relatively capacitive and this affects the rising and falling edges of the stage output signals at the stage output GL. The presence of the second output arrangement prevents the resetting of the preceding stage and the setting of the succeeding stage from being affected by the capacitive load.

Fourth and fifth embodiments allow only some, for example nearly all, of the outputs of a scan driver to be activated simultaneously (partial-on'), for example when the display is in partial mode and showing a stand-by image on a limited number of rows. Figure 24 shows a scan driver with PARTIALON and pulse width control, PWC, input signals.

The scan driver is composed of two types of stage; stages connected to the rows of the partial image (rows X to Y), 32, and all other stages, 72. Stages 32 have three inputs: R, S and CK; stages 72 have five inputs: R, S, CK, PARTIALON and PWC. The CK inputs of odd-number stages are connected to a first clock, CK1; the CK inputs of even-number stages are connected to a second clock, CK2. The PARTIALON and PWC inputs of stages are connected to the PARTIALON and PWC inputs of the scan driver, respectively. Figure 25 shows that all rows except rows X to Y are activated simultaneously when PARTIALON is activated.

The fourth embodiment is shown in Figures 26 and 27. Figure 26 shows a transistor-level embodiment of a stage, 72, in Figure 24. This stage is similar to that shown in Figure 23. Transistor 58 is connected such that its principal conduction path is between the GL output and the PARTIALON input signal; transistor 56 is connected such that its principal conduction path is between the PWC input and the GL output. Figure 27 shows a stage, 32, in Figure 24. This stage is similar to that shown in Figure 14, except transistor 58 is connected such that its principal conduction path is between the GL output and the low supply rail Vss.

The fifth embodiment is shown in Figures 28 and 29. Figure 28 shows a scan driver similar to Figure 24 and only the differences will be described. Stages 62 have four inputs: R, 5, CK and ALLON. The ALLON inputs of stages are connected to the ALLON input of the scan driver. Figures 23 and 26 show transistor-level embodiments of stages 62 and 72 respectively.

Figure 29 shows the waveforms for signals in Figure 28. This is similar to Figure 25; an all-on capability has been added by simultaneously activating ALLON and PARTIALON.

Sixth and seventh embodiments concern partial activation during alternation of the polarity of the liquid crystal drive voltage. Figure 30 shows a scan driver similar to Figure 28 and only the differences will be explained. The PARTIALON of odd-number stages outside rows X to Y are connected to a first PARTIALON signal, PARTIALON 1; the PARTIALON inputs of even-number stages outside rows X to Y are connected to a second PARTIALON signal, PARTIALON2.

Operation of the sixth embodiment is illustrated in Figure 31. This shows the waveforms of signals in Figure 30. The polarity of the liquid crystal drive voltage corresponds to an alternating voltage, VCOM. Odd rows outside rows X to Y are activated in one frame; even rows are activated in the next frame when VCOM is reversed. In this way, the polarity of the drive voltage for each row is reversed during alternate frames.

Alternatively, operation of a seventh embodiment is illustrated in Figure 32. This shows the waveforms for signals in Figure 30. Odd and even rows outside rows X to Y are activated in each frame during opposite VCOM states. In this way, the polarity of the drive voltage for each row is reversed during each frame.

The advantage of the sixth and seventh embodiments is that a full refresh is no longer required, thus reducing power consumption.

Claims (28)

  1. CLAIMS: 1. A shift register comprising a plurality of stages arranged to be activated in sequence during a first mode of operation, each stage comprising a logic circuit controlling a first output circuit, each of the first output circuits of at least some of the stages comprising a first switch, which connects an output of the stage to an active signal first input of the stage when the stage is active, and a second switch, which, when the stage is inactive, connects the stage output to a second input of the stage for receiving an inactive signal level during the first mode and the active signal level during a second mode of operation for activating the stage outputs of the at least some stages simultaneously.
  2. 2. A shift register as claimed in claim 1, in which the first and second switches comprise first and second transistors, respectively.
  3. 3. A shift register as claimed in claim 2, in which at least one of the first and second transistors is provided with a bootstrap capacitor.
  4. 4. A shift register as claimed in any one of the preceding claims, in which each of the logic circuits comprises a reset-set flip-flop.
  5. 5. A shift register as claimed in claim 4, in which each of the flip-flops comprises a reset-over-set flip-flop.
  6. 6. A shift register as claimed in claim 4 or 5, in which the stage output of each stage is connected to a reset or set input of at least one adjacent stage.
  7. 7. A shift register as claimed in claim 4 or 5, in which each of the at least some stages has a second output circuit for supplying a reset or set signal at a further output connected to a reset or set input of at least one adjacent stage.
  8. 8. A shift register as claimed in claim 7, in which each second output circuit is connected between the stage output and the further output.
  9. 9. A shift register as claimed in claim 8, in which each second output circuit comprises a third switch connected between the stage output and the further output and arranged to be switched on during the first mode and switched off during the second mode.
  10. 10. A shift register as claimed in claim 9, in which the third switch comprises a third transistor.
  11. 11. A shift register as claimed in claim 10, in which the third transistor is provided with a further bootstrap capacitor.
  12. 12. A shift register as claimed in any one of claims 9 to 11, in which each second output circuit comprises a fourth switch arranged to connect the further output to receive the inactive signal level during the second mode.
  13. 13. A shift register as claimed in claim 12, in which the fourth switch comprises a fourth transistor.
  14. 14. A shift register as claimed in claim 7, in which each second output circuit comprises a third switch arranged to connect the further output to an active signal third input of the stage when the stage is active.
  15. 15. A shift register as claimed in claim 14, in which the third switch comprises a third transistor.
  16. 16. A shift register as claimed in claim 15, in which the third transistor is provided with a further bootstrap capacitor.
  17. 17. A shift register as claimed in any one of claims 14 to 16, in which each second output circuit comprises a fourth switch arranged to connect the further output to receive the inactive signal level when the stage is inactive.
  18. 18. A shift register as claimed in claim 17, in which the fourth switch comprises a fourth transistor.
  19. 19. A shift register as claimed in any one of the preceding claims, in which the first inputs of at least some of the stages are connected to at least one clock input of the register.
  20. 20. A shift register as claimed in any one of the preceding claims, in which the first inputs of at least some of the stages are connected to at least one pulse width control input of the register for receiving at least one pulse width control signal for detennining which of the stages is enabled.
  21. 21. A shift register as claimed in any one of the preceding claims, in which the at least some stages are consecutive.
  22. 22. A shift register as claimed in any one of the preceding claims, comprising a control circuit for supplying to the second inputs the inactive signal level during the first mode and the active signal level during the second mode.
  23. 23. A shift register as claimed in any one of the preceding claims, in which each of the first output circuits of at least some others of the stages comprises a first switch, which connects an output of the stage to an active signal first input of the stage when the stage is active, and a second switch, which, when the stage is inactive, connects the stage output to a further input of the stage for receiving an inactive signal level during the first mode and the active signal level during a third mode of operation for activating the stage outputs of the at least some other stages simultaneously.
  24. 24. A shift register as claimed in claim 23, in which the second and third modes are selectable simultaneously.
  25. 25. A shift register as claimed in claim 23 or 24, comprising a further control circuit for supplying to the further inputs the inactive signal level during the first mode and the active signal level during the third mode.
  26. 26. A display driver comprising a shift register as claimed in any one of the preceding claims.
  27. 27. An active matrix display including a display driver as claimed in claim 26.
  28. 28. A display as claimed in claim 27, comprising a liquid crystal display.
GB0716753A 2007-08-30 2007-08-30 A scan pulse shift register for an active matrix LCD display Withdrawn GB2452278A (en)

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GB0716753A GB2452278A (en) 2007-08-30 2007-08-30 A scan pulse shift register for an active matrix LCD display

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GB0716753A GB2452278A (en) 2007-08-30 2007-08-30 A scan pulse shift register for an active matrix LCD display
PCT/JP2008/064763 WO2009028353A1 (en) 2007-08-30 2008-08-13 Shift register, display driver and display

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WO2017049687A1 (en) * 2015-09-23 2017-03-30 深圳市华星光电技术有限公司 Goa circuit, display device, and driving method for goa circuit
US10204579B2 (en) 2015-09-23 2019-02-12 Shenzhen China Star Optoelectronics Technology Co., Ltd GOA circuits, display devices and the driving methods of the GOA circuits

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