WO2010146692A1 - Semiconductor device and method for manufacturing semiconductor device - Google Patents
Semiconductor device and method for manufacturing semiconductor device Download PDFInfo
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- WO2010146692A1 WO2010146692A1 PCT/JP2009/061118 JP2009061118W WO2010146692A1 WO 2010146692 A1 WO2010146692 A1 WO 2010146692A1 JP 2009061118 W JP2009061118 W JP 2009061118W WO 2010146692 A1 WO2010146692 A1 WO 2010146692A1
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- 125000006617 triphenylamine group Chemical class 0.000 description 1
- 150000004961 triphenylmethanes Chemical class 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/80—Constructional details
- H10K10/82—Electrodes
- H10K10/84—Ohmic electrodes, e.g. source or drain electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
- H10K10/471—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising only organic materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
- H10K85/30—Coordination compounds
Definitions
- the present invention relates to a semiconductor device, and more particularly to a method for forming an electrode of an organic thin film transistor using an electroless plating method.
- organic TFT Thin Film Transistor
- Organic TFT is a kind of field effect transistor (FET), which is basically a three-terminal element consisting of a drain, a source and a gate.
- FET field effect transistor
- a plating method is used to form metal wirings that function as the drain, source, and gate terminals of the organic TFT.
- As a patterning method in the case of forming a metal wiring by using a plating method there are the following methods.
- a gate electrode, a gate insulating layer, and a photocatalytic material are sequentially formed on a light-transmitting substrate, and then the substrate is selectively exposed in a state where the substrate is immersed in a solution containing a plating catalyst material.
- a plating catalyst material By depositing a plating catalyst material on the photocatalyst material of the exposed portion by this, and further immersing this substrate in a plating solution containing the metal material to be plated, a metal film is formed on the plating catalyst material to form a drain electrode and a source electrode Is described.
- Patent Document 2 a resist film having an opening in a region where a source electrode and a drain electrode are to be formed on a substrate is formed, and after pretreatment of the substrate exposed in the opening of the resist film, It is described that a metal film is deposited on a substrate exposed at an opening of a resist film to form a source electrode and a drain electrode by immersing the substrate after these treatments in a plating bath by adsorbing a catalyst on the substrate. ing.
- a method for forming a metal wiring of a semiconductor element there are a sputtering method and a vapor deposition method. However, since these methods require processing under high vacuum, the scale of the apparatus is increased and the cost is increased. On the other hand, according to the plating method, since a vacuum process is not required, the apparatus scale can be made relatively small.
- a plating method for forming a metal wiring of a semiconductor element an electroplating method and an electroless plating method are known.
- Electroplating uses an electrochemical reaction in which metal ions are discharged and deposited on the surface of the cathode (material to be plated) by energizing the material to be plated as a cathode in an electrolytic solution containing the metal ions to be plated. It is a thing. As described above, in the electroplating method, since it is necessary to energize the portion to be plated, in the case of a wiring pattern in which an electrically independent portion is generated, it is difficult to perform plating on the wiring. There is. For example, the wiring of an organic EL drive circuit has an electrically independent portion, so that it is often difficult to form the wiring by an electroplating method.
- the electroless plating method does not need to be energized, and after a catalyst is adsorbed to a material to be plated containing an organic material, a uniform film can be obtained by immersing it in a plating solution. it can. For this reason, it can be said that the electroless plating method is a process suitable for forming wiring of a drive circuit such as an organic EL.
- a p-type semiconductor material such as pentacene or P3HT (poly (3-hexylthiophene)
- P3HT poly (3-hexylthiophene)
- these materials have a relatively high ionization potential, it is preferable to select a material having a relatively high work function as the source / drain electrode wiring in accordance with the ionization potential of the organic semiconductor material. This is because when the gap between the ionization potential of the organic semiconductor material and the work function of the electrode material is increased, a Schottky barrier is formed at these interfaces.
- the manufacturing cost is significantly increased.
- the area of the wiring portion usually reaches 10% or more of the substrate area. Will be used, resulting in a significant increase in manufacturing costs.
- the amount of Au used is increased, the replenishment / replacement cycle of the plating solution is shortened and the running cost is increased.
- the present invention has been made in view of the above points, and a specific metal (mainly a noble metal) introduced into the source / drain electrode in order to control the electrical contact between the source / drain electrode and the organic semiconductor material.
- An object of the present invention is to provide a semiconductor device capable of suppressing the amount of the specific metal used and a method for manufacturing the same when forming the film by electroless plating.
- a semiconductor device includes an organic thin film transistor having a pair of source / drain electrodes arranged at positions facing a gate electrode through a gate insulating film, and an organic semiconductor layer in contact with the pair of source / drain electrodes.
- the source / drain electrodes have a plating treatment part formed by electroless plating only at a part including a part in contact with the organic semiconductor layer.
- a semiconductor device includes a gate electrode formed on a substrate, a gate insulating film formed so as to cover the gate electrode, and an upper portion of the gate electrode through the gate insulating film from above the substrate.
- a pair of source / drain electrodes extending and having a separation portion above the gate electrode, and an organic layer provided in contact with the gate insulating film and the pair of source / drain electrodes exposed in the separation portion
- a first electrode layer extending from an upper part of the gate electrode to an upper part of the substrate, and the plating process part provided at the first end part. And a corresponding second electrode layer.
- a semiconductor device includes a pair of source / drain electrodes provided on a substrate so as to be separated from each other, and an organic semiconductor layer provided on the substrate so as to cover the pair of source / drain electrodes.
- the second electrode layer includes a portion in contact with the channel region of the organic semiconductor layer.
- the contact between the second electrode layer and the organic semiconductor layer is preferably ohmic contact.
- the second electrode layer can be formed using displacement plating and reduction plating in combination.
- the second electrode layer is preferably made of a material having a smaller ionization tendency than the constituent material of the first electrode layer.
- the second electrode layer can be formed of a noble metal or an alloy containing a noble metal, for example, gold or an alloy containing gold.
- the method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device including an organic thin film transistor, wherein a step of forming a gate electrode on a substrate and a gate insulating film so as to cover the gate electrode are formed. Forming a pair of source / drain electrodes having a separation portion on the gate electrode on the gate insulating film; and exposing the gate insulation film and the pair of source / drain exposed in the separation portion Forming a pair of source / drain electrodes extending from the upper part of the gate electrode to the upper part of the substrate on the gate insulating film.
- Forming a first electrode layer and having an opening in a region including a portion where the pair of source / drain electrodes are in contact with the organic semiconductor layer Forming a resist mask on the first electrode layer, and forming a second electrode layer on the part of the first electrode layer exposed at the opening of the resist mask by electroless plating. It is characterized by including.
- FIG. 1 is a cross-sectional view showing the structure of an organic TFT 1 which is an embodiment of the present invention.
- the organic TFT 1 is formed on the substrate 10 and has a so-called bottom contact structure.
- the substrate 10 is made of a light transmissive material such as a glass substrate or a flexible plastic film.
- a gate electrode 11 made of, for example, nickel phosphorus (Ni—P) is provided on the substrate 10.
- a gate insulating film 12 made of a polymer material in which, for example, PVP (Poly (4-vinylphenol)) and melamine are mixed is provided so as to cover the gate electrode 11.
- PVP Poly (4-vinylphenol)
- the pair of source / drain electrodes 15 includes a first electrode layer 13 made of, for example, nickel phosphorus (Ni—P) extending from the gate electrode 11 to the substrate 10 through the gate insulating film 12, and a first electrode layer 13. And a second electrode layer 14 corresponding to the plating portion of the present invention made of, for example, Au formed on a part of the electrode layer 13 by using an electroless plating method.
- the pair of source / drain electrodes 15 are separated from each other in the upper part of the gate electrode 11, and one functions as a source electrode and the other functions as a drain electrode.
- the organic semiconductor layer 16 is made of, for example, an organic semiconductor material such as tetrabenzoporphyrin, and the gate insulating film 12 exposed in the separated portion of the pair of source / drain electrodes 15 on the gate electrode 11, the source / drain electrodes 15, and the like. It is provided so that both may be touched. A region sandwiched between the pair of source / drain electrodes 15 in the organic semiconductor layer 16 becomes a channel region 17.
- the second electrode layer 14 made of Au is not formed over the entire surface of the first electrode layer 13, but the source / drain electrode 15 is connected to the organic semiconductor layer 16. Only part of the first electrode layer 13 including the contact portion is formed by electroless plating.
- the second electrode layer 14 is introduced to control the contact between the organic semiconductor 16 and the source / drain electrode 15, and the source / drain electrode 15 is in contact with the organic semiconductor layer 16. If it is formed only in the part, its function is fully exhibited. Therefore, in the organic TFT 1 according to the present embodiment, the usage amount of Au is suppressed by providing the second electrode layer 14 only on a part of the first electrode layer 13 including the portion in contact with the organic semiconductor layer 16. It was decided.
- 2A to 2F are cross-sectional views for each process step showing a manufacturing process of the organic TFT 1 which is an embodiment of the present invention.
- a substrate 10 made of a glass substrate or a flexible plastic film is prepared. Before forming the organic TFT 1 on the substrate 10, it may be cleaned with a cleaning liquid containing pure water, a surfactant or the like to remove oils and fats attached to the surface of the substrate 10.
- the surface of the substrate 10 is roughened to improve the adhesion between the substrate 10 and the gate electrode 11 by the anchor effect. Specifically, fine irregularities are formed on the surface of the substrate 10 by etching the substrate 10 using an etching solution such as a chromic acid / sulfuric acid mixed solution. Thereafter, the chromium compound remaining on the surface of the substrate 10 is removed using hydrochloric acid or the like.
- a catalyst serving as a nucleus of electroless plating for forming the gate electrode 11 is adsorbed on the substrate 10.
- a Pd—Sn complex can be used as the catalyst.
- substrate 10 is immersed in an acid solution, a tin salt is dissolved, and metal palladium is produced
- the substrate 10 is immersed in a plating bath containing nickel sulfate and sodium hypophosphite to form a plating film made of nickel phosphorus (Ni—P) on the surface of the substrate 10.
- the gate electrode 11 is formed by patterning the plating film formed on the substrate 10 using a known photolithography technique (FIG. 2A).
- a roughening process is performed by performing a roughening process on the substrate 10 using a mask corresponding to the pattern of the gate electrode 11.
- the gate electrode 11 may be patterned by causing the catalyst to be adsorbed only on the broken portion and selectively forming a plating film on this portion.
- a silane coupling agent having a catalytic function is applied to the entire surface of the substrate 10 and the surface of the substrate 10 is irradiated with ultraviolet rays through a mask corresponding to the pattern of the gate electrode 11, thereby adsorbing the catalyst.
- the gate electrode 11 it is also possible to pattern the gate electrode 11 by performing a surface modification process that lowers the thickness of the catalyst, adsorbing the catalyst only on the portion that is not irradiated with ultraviolet rays, and selectively forming a plating film on this portion. Further, the gate electrode 11 is patterned by drawing a silane coupling agent having a catalytic function by a printing method such as flexographic printing or an ink jet method, and selectively forming a plating film only on a portion where the silane coupling agent exists. It may be done.
- a gate insulating film 12 is formed so as to cover the gate electrode 11.
- a polymer material in which melamine is mixed with PVP Poly (4-vinylphenol)
- PVP Poly (4-vinylphenol
- a first electrode layer 13 made of nickel phosphorus (Ni—P) constituting the source / drain electrode 15 is formed on the gate insulating film 12 by an electroless plating method.
- the process of forming the nickel phosphorus (Ni—P) plating film by the electroless plating method is the same as the process of forming the gate electrode 11 described above. That is, the gate insulating film 12 is roughened as necessary, a catalyst made of a Pd—Sn complex is adsorbed on the gate insulating film 12, an accelerator treatment with an acid solution is performed, and then the substrate 10 is nickel sulfate. And soak in a plating bath containing sodium hypophosphite.
- a plating film made of nickel phosphorus (Ni—P) is formed on the substrate 10 and the gate electrode 11 via the gate insulating film 12.
- the first electrode layer 13 is patterned by a known photolithography technique.
- an opening (spacer) 13 a for forming the channel region 17 of the organic TFT is provided in the nickel phosphorus (Ni—P) plating film formed on the gate electrode 11, and the source / drain electrode 15 The wiring pattern is formed.
- the first electrode layer 13 As a method for patterning the first electrode layer 13, in addition to the above-described method, for example, a roughening process of the gate insulating film 12 is performed using a mask corresponding to the pattern of the first electrode layer 13.
- the first electrode layer 13 may be patterned by adsorbing the catalyst only on the roughened portion and selectively forming a plating film on this portion.
- a silane coupling agent having a catalytic function is applied to the entire surface of the gate insulating film 12, and the surface of the gate insulating film 12 is irradiated with ultraviolet rays through a mask corresponding to the pattern of the first electrode layer 13.
- the first electrode layer is formed by subjecting the surface modification treatment to reduce the adsorptive power to the catalyst, adsorbing the catalyst only to a portion not irradiated with ultraviolet rays, and selectively forming a plating film on this portion. 13 patterning may be performed. Further, the first electrode layer 13 is formed by drawing a silane coupling agent having a catalytic function by a printing method such as flexographic printing or an ink jet method, and selectively forming a plating film only on a portion where the silane coupling agent is present. The patterning may be performed.
- a resist mask 20 is formed at a position sandwiching the gate electrode 11 on the first electrode layer 13. That is, the resist mask 20 has an opening 20 a at the position where the gate electrode 11 is formed. The first electrode layer 13 is exposed at the opening 20a (FIG. 2D).
- the second electrode layer 14 made of Au is selectively formed only on a part of the first electrode layer 13 exposed in the opening 20a of the resist mask 20 by electroless plating.
- the second electrode layer is formed by using, for example, a substitution Au plating method and a reduction Au plating method in combination.
- the displacement Au plating method utilizes the difference between the ionization tendency of the base metal to be plated and the ionization tendency of Au as the plating material, and the first electrode layer 13 made of nickel phosphorus (Ni—P) is formed.
- the Au substrate is formed on the first electrode layer 13 by immersing the substrate 10 thus obtained in a cyan or non-cyan substitution gold plating bath.
- the underlying nickel phosphorus (Ni—P) which has a relatively high ionization tendency, dissolves, and a reaction occurs in which Au precipitates on the nickel phosphorus (Ni—P).
- the reaction stops when the underlying nickel phosphorus (Ni—P) is coated with Au, so that the deposited Au film becomes thin. Therefore, in this embodiment, the reduced Au plating process is performed subsequent to the replacement Au plating process to secure the film thickness of the Au plating film.
- the reduced Au plating method is a plating method in which electrons released by oxidation of a reducing agent contained in a plating bath are transferred to Au ions to form an Au film on a material to be plated.
- the first electrode layer in which the substituted Au plating film is formed by immersing the substrate 10 in a plating bath using potassium tetrahydroborate (KBH 4 ) or the like as a reducing agent and KAu (CN) 2 as a gold salt.
- KH 4 potassium tetrahydroborate
- KAu (CN) 2 as a gold salt.
- a reduced Au plating film is further formed on 13.
- the first electrode layer 13 is exposed only at the opening 20a of the resist mask 20 formed in the previous step. Therefore, only the exposed portion of the first electrode layer 13 is exposed to the plating solution in the replacement Au plating step and the reduced Au plating step, and the second electrode layer 14 is formed only on the exposed portion. In this way, the second electrode layer 14 is formed on the first electrode layer 13, and the source / drain electrode 15 is completed (FIG. 2E).
- the source / drain electrode 15 formed on the gate electrode 11 and the gate insulating film 12 exposed in the opening 13a that divides the source / drain electrode 15 are formed by, for example, an inkjet method.
- An organic semiconductor layer 16 made of, for example, tetrabenzoporphyrin or the like is formed so as to be in contact therewith.
- the ink jet method is a printing method in which a solution containing an organic semiconductor material is discharged from a nozzle to form a pattern, and can be formed in a non-contact manner with respect to the substrate 10 and can be printed over a wide area.
- the organic TFT 1 is completed through the above steps.
- the first resist mask 20 is used.
- the electrode layer 13 is partially exposed, and the second electrode layer 14 is selectively formed only in the exposed portion of the resist opening, so that the metal constituting the second electrode layer 14 (mainly In addition, the amount of noble metal) used can be reduced, and the manufacturing cost can be reduced.
- the organic TFT according to the present embodiment is formed in an array on a substrate to form a driving circuit for a display panel such as an organic EL display, the amount of Au used can be suppressed to about several percent of the conventional case. It becomes possible, and it becomes possible to bring about a significant cost reduction effect. Moreover, since the exchange cycle of a plating bath can be lengthened by this, a running cost can also be suppressed.
- the second electrode layer 14 is introduced for the purpose of controlling electrical contact between the source / drain electrodes and the organic semiconductor layer, and is formed at least in a portion in contact with the channel region of the organic semiconductor layer. If so, the function is exhibited, and there is no adverse effect on the electrical characteristics due to the restriction of the formation region of the second electrode layer 14.
- FIG. 3 is a cross-sectional view showing the structure of the organic TFT when the formation region of the second electrode layer 14 is further limited.
- the work function of the second electrode layer 14 is close to the ionization potential of the organic semiconductor, whereas the work function of the first electrode layer 13 has a distant value. Therefore, a portion where a part of the organic semiconductor layer 16 is in contact with the first electrode layer 13 may exist.
- charge injection into the organic semiconductor layer 16 is performed from the end of the source / drain electrode, as shown in FIG. 3, charge injection from the organic semiconductor layer 16 occurs in the formation region of the second electrode layer 14. It is desirable to be an end portion of the first electrode layer 13 to be performed.
- the second electrode layer 14 is desirably provided at the tip of the source / drain electrode that sandwiches the channel region 17.
- Such a structure can be realized by making the opening width of the resist mask 20 for selectively forming the second electrode narrower than the case shown in FIG. With such a structure, the amount of Au used can be further suppressed.
- the first electrode layer 13 is formed by sputtering, and then patterned into a desired line with a photoresist, and substitution / reduction plating is performed while leaving the photoresist. Can be mentioned.
- the second electrode layer 14 is used as the second electrode layer 14, but is not limited to this.
- a noble metal such as (Cu) or an alloy thereof.
- the second electrode layer 14 is formed by using both displacement plating and reduction plating.
- the displacement plating is performed. Only the second electrode layer 14 may be formed.
- the displacement plating and the reduction plating are each performed once.
- the plurality of layers may be formed by repeating the displacement plating and the reduction plating.
- the present invention is not limited to this, and any plating material having a higher ionization tendency than the second electrode layer 14 may be used.
- the first electrode layer 13 is not limited to the electroless plating method, but is formed by performing desired patterning using, for example, a photolithography technique after forming an electrode material by a sputtering method, a CVD method, a vacuum deposition method, or the like. May be.
- the first electrode layer 13 may be formed by ejecting metal nano-ink in a line shape by an inkjet method. Further, the same modification can be made for the material and the formation method of the gate electrode 11.
- tetrabenzoporphyrin is used as the material of the organic semiconductor layer 16, but the present invention is not limited to this, and other organic semiconductor materials can also be used.
- organic semiconductor materials for low molecular weight materials, phthalocyanine derivatives, naphthalocyanine derivatives, azo compound derivatives, perylene derivatives, indigo derivatives, quinacridone derivatives, polycyclic quinone derivatives such as anthraquinones, cyanine derivatives, fullerene derivatives Or nitrogen-containing cyclic compound derivatives such as indole, carbazole, oxazole, inoxazole, thiazole, imidazole, pyrazole, oxadiazole, pyrazoline, thiathiazole, triazole, hydrazine derivative, triphenylamine derivative, triphenylmethane derivative, stilbene Quinone compound derivatives such as anthraquinone diphenoquinone, and polycyclic aromatic compound derivatives
- the structure of the low molecular compound mentioned above is pendant as an object or side chain used in the polymer main chain such as polyethylene chain, polysiloxane chain, polyether chain, polyester chain, polyamide chain, polyimide chain, etc.
- Aromatic conjugated polymers such as polyparaphenylene, aliphatic conjugated polymers such as polyacetylene, heterocyclic conjugated polymers with polypinol and polythiophene ratios, polyanilines and polyphenylene sulfide, etc.
- Hetero-atom conjugated polymers of this type complex type conjugated systems having a structure in which structural units of conjugated polymers such as poly (phenylene vinylene), poly (annelen vinylene) and poly (chenylene vinylene) are alternately bonded Carbon-based conjugated polymers such as molecules can be used.
- polymers containing oligosilanes and carbon-based conjugated structures such as polysilanes, disilanylene-arylene polymers, and disilanylene carbon-based conjugated polymer structures such as (disilanylene) ethynylene polymers Can be used.
- polymer chains made of inorganic elements such as phosphorus and nitrogen may be used, and polymers having aromatic chain ligands such as phthalocyanate polysiloxane coordinated, perylenetetracarboxylic Polymers in which perylenes such as acids are heat-treated and condensed, ladder-type polymers obtained by heat-treating polyethylene derivatives having a cyano group such as polyacrylonitrile, and organic compounds intercalated in perovskites
- the composite material may be used.
- a polymer material in which PVP and melamine are mixed is used as the material of the gate insulating film 12.
- the present invention is not limited to this, and any insulating film of an inorganic material or an organic material can be used as the gate insulating film.
- the gate insulating film may be formed by anodizing the gate electrode.
- simple substances such as Ta, Al, Mg, Ti, Nb, Zr, or alloys thereof are effective.
- polymer materials such as polyimide, polyamide, polyester, polyacrylate, epoxy resin, phenol resin, and polyvinyl alcohol.
- the surface of the gate insulating film may be subjected to water repellent treatment using OTS, HMDS, or the like.
- the present invention is applied to the organic TFT having the bottom contact structure.
- the present invention can also be applied to the organic TFT having the top gate structure shown in FIG.
- the top gate structure is a structure in which a source / drain electrode 15 is formed on a substrate 10, and a gate electrode 11 is formed on the outermost surface via an organic semiconductor layer 16 and a gate insulating film 12.
- the organic TFT 3 having a top gate structure includes a pair of source / drain electrodes 15 provided on the substrate 10 so as to be separated from each other, and an organic semiconductor layer 16 provided on the substrate 10 so as to cover the source / drain electrodes 15. And a gate insulating film 12 provided on the organic semiconductor layer 16 and a gate electrode 11 provided on the gate insulating film 12.
- the source / drain electrode 15 is provided so as to cover the first electrode layer 13 made of, for example, nickel phosphorus (Ni—P) extending on the substrate 10 and a part on the first electrode layer 13.
- the second electrode layer 14 is made of Au.
- the second electrode layer 14 is provided at the end of the first electrode layer 13 where charge injection from the organic semiconductor layer 16 is performed, for example.
Landscapes
- Thin Film Transistor (AREA)
Abstract
Disclosed is a semiconductor device comprising a gate electrode formed on a substrate; a gate insulating film so formed as to cover the gate electrode; a pair of source/drain electrodes extending, through the gate insulating film, from the position above the gate electrode to the position above the substrate, while being separated at the position above the gate electrode; and an organic semiconductor layer so formed as to be in contact with the pair of source/drain electrodes and the gate insulating film exposed from the space between the pair of source/drain electrodes. The source/drain electrodes contains a first electrode layer extending from the position above the gate electrode to the position above the substrate, and a second electrode layer so formed as to cover a part of the first electrode layer and corresponding to a plated portion.
Description
本発明は半導体装置に関し、特に無電解めっき法を使用した有機薄膜トランジスタの電極形成方法に関する。
The present invention relates to a semiconductor device, and more particularly to a method for forming an electrode of an organic thin film transistor using an electroless plating method.
現在、有機半導体を使った有機薄膜トランジスタ（以下、有機ＴＦＴ（Thin Film Transistor）と称する）の開発が活発化している。有機ＴＦＴは、デバイス特性においてはシリコン等の無機材料と比べて劣るものの、軽量、フレキシブル、低温プロセスが可能である、印刷による形成が可能であるといった特徴を有していることから電子ペーパやフレキシブルディスプレイ等のユニークな用途が拓けるものと期待されている。
Currently, the development of organic thin film transistors using organic semiconductors (hereinafter referred to as organic TFT (Thin Film Transistor)) has become active. Although organic TFT is inferior to inorganic materials such as silicon in device characteristics, it has features such as light weight, flexibility, low temperature process, and formation by printing. It is expected to open up unique uses such as displays.
有機ＴＦＴは電界効果トランジスタ（ＦＥＴ）の一種であり、基本的にはドレイン、ソース、ゲートからなる三端子素子である。有機ＴＦＴのドレイン、ソース、ゲート端子として機能する金属配線の形成にはめっき法が用いられる場合がある。めっき法を用いて金属配線を形成する場合のパターニング方法としては、以下のようなものがある。
Organic TFT is a kind of field effect transistor (FET), which is basically a three-terminal element consisting of a drain, a source and a gate. In some cases, a plating method is used to form metal wirings that function as the drain, source, and gate terminals of the organic TFT. As a patterning method in the case of forming a metal wiring by using a plating method, there are the following methods.
特許文献１には、透光性基板上にゲート電極、ゲート絶縁層および光触媒物質を順次形成した後、この基板をめっき触媒物質を含む溶液中に浸漬した状態で選択的に基板を露光することにより露光部分の光触媒物質上にめっき触媒物質を析出させ、さらにこの基板をめっきしようとする金属材料を含むめっき液に浸漬することによりめっき触媒物質上に金属膜を形成してドレイン電極およびソース電極を形成することが記載されている。
In Patent Document 1, a gate electrode, a gate insulating layer, and a photocatalytic material are sequentially formed on a light-transmitting substrate, and then the substrate is selectively exposed in a state where the substrate is immersed in a solution containing a plating catalyst material. By depositing a plating catalyst material on the photocatalyst material of the exposed portion by this, and further immersing this substrate in a plating solution containing the metal material to be plated, a metal film is formed on the plating catalyst material to form a drain electrode and a source electrode Is described.
特許文献２には、基板上のソース電極およびドレイン電極を形成すべき領域において開口部を有するレジスト膜を形成し、このレジスト膜の開口部において露出した基板の前処理を行った後、この部位に触媒を吸着させ、これらの処理を経た基板をめっき浴中に浸漬することによりレジスト膜の開口部において露出した基板上に金属膜を析出させてソース電極およびドレイン電極を形成することが記載されている。
In Patent Document 2, a resist film having an opening in a region where a source electrode and a drain electrode are to be formed on a substrate is formed, and after pretreatment of the substrate exposed in the opening of the resist film, It is described that a metal film is deposited on a substrate exposed at an opening of a resist film to form a source electrode and a drain electrode by immersing the substrate after these treatments in a plating bath by adsorbing a catalyst on the substrate. ing.
半導体素子の金属配線を形成する手法としては、従来からスパッタ法や蒸着法等がある。しかしながら、これらの手法は高真空下での処理を要するため装置規模が大きくなり、コストがかかる。一方、めっき法によれば、真空プロセスを要しないため装置規模を比較的小さくできる。半導体素子の金属配線を形成すためのめっき法としては、電気めっき法および無電解めっき法が知られている。電気めっきは、めっきしようとする金属イオンを含む電解溶液中で、被めっき材を陰極として通電することにより、金属イオンが陰極(被めっき材)の表面で放電して析出する電気化学反応を利用したものである。このように、電気めっき法においては、めっきしようとする部分を通電する必要があることから、電気的に独立した部分が生じる配線パターンの場合、当該配線にめっき処理を施すことが困難となる場合がある。例えば有機ＥＬの駆動回路の配線は、電気的に独立した部分が生じるため、電気めっき法で形成することは困難となることが多い。
Conventionally, as a method for forming a metal wiring of a semiconductor element, there are a sputtering method and a vapor deposition method. However, since these methods require processing under high vacuum, the scale of the apparatus is increased and the cost is increased. On the other hand, according to the plating method, since a vacuum process is not required, the apparatus scale can be made relatively small. As a plating method for forming a metal wiring of a semiconductor element, an electroplating method and an electroless plating method are known. Electroplating uses an electrochemical reaction in which metal ions are discharged and deposited on the surface of the cathode (material to be plated) by energizing the material to be plated as a cathode in an electrolytic solution containing the metal ions to be plated. It is a thing. As described above, in the electroplating method, since it is necessary to energize the portion to be plated, in the case of a wiring pattern in which an electrically independent portion is generated, it is difficult to perform plating on the wiring. There is. For example, the wiring of an organic EL drive circuit has an electrically independent portion, so that it is often difficult to form the wiring by an electroplating method.
一方、無電解めっき法は、電気めっき法と異なり、通電する必要はなく、有機材料を含む被めっき材に触媒を吸着させた後、これをめっき液に浸漬すれば均一な皮膜を得ることができる。このため、無電解めっき法は、有機ＥＬ等の駆動回路の配線の形成に適したプロセスであるといえる。
On the other hand, unlike the electroplating method, the electroless plating method does not need to be energized, and after a catalyst is adsorbed to a material to be plated containing an organic material, a uniform film can be obtained by immersing it in a plating solution. it can. For this reason, it can be said that the electroless plating method is a process suitable for forming wiring of a drive circuit such as an organic EL.
有機ＴＦＴを構成する有機半導体層の材料としては、一般的にペンタセンやＰ３ＨＴ（ポリ（３－ヘキシルチオフェン））等のｐ型半導体材料が用いられる。これらの材料はイオン化ポテンシャルが比較的大きいため、ソース／ドレイン電極配線としては、有機半導体材料のイオン化ポテンシャルに応じて比較的仕事関数の高い材料を選択することが好ましい。これは、有機半導体材料のイオン化ポテンシャルと電極材料の仕事関数のギャップが大きくなると、これらの界面においてショットキー障壁が形成されてしまうからである。有機ＴＦＴの構成材料となり得る既存の有機半導体材料のイオン化ポテンシャルを考慮すると、ソース／ドレイン電極配線の材料としては、化学特性および電気特性にも優れるＡｕ（仕事関数４．７ｅＶ）が候補の１つとして挙げられる。
As a material for the organic semiconductor layer constituting the organic TFT, a p-type semiconductor material such as pentacene or P3HT (poly (3-hexylthiophene)) is generally used. Since these materials have a relatively high ionization potential, it is preferable to select a material having a relatively high work function as the source / drain electrode wiring in accordance with the ionization potential of the organic semiconductor material. This is because when the gap between the ionization potential of the organic semiconductor material and the work function of the electrode material is increased, a Schottky barrier is formed at these interfaces. Considering the ionization potential of the existing organic semiconductor material that can be a constituent material of the organic TFT, Au (work function 4.7 eV) having excellent chemical characteristics and electrical characteristics is one of the candidates as a material of the source / drain electrode wiring. As mentioned.
しかしながら、Ａｕは非常に高価であり、配線材料に多量のＡｕを使用すると製造コストの著しい上昇を招く。回路構成にもよるが、例えば、有機ＥＬ表示パネルの駆動回路の場合、通常、配線部分の面積は基板面積の１０％以上にも及ぶため、従来の製造プロセスによれば、相当な量のＡｕが使用されることとなり、製造コストの著しい上昇を招く。また、Ａｕの使用量が多くなると、めっき液の補充／交換サイクルが短くなりランニングコストも高くなる。
However, Au is very expensive, and if a large amount of Au is used as the wiring material, the manufacturing cost is significantly increased. Depending on the circuit configuration, for example, in the case of a drive circuit for an organic EL display panel, the area of the wiring portion usually reaches 10% or more of the substrate area. Will be used, resulting in a significant increase in manufacturing costs. Further, when the amount of Au used is increased, the replenishment / replacement cycle of the plating solution is shortened and the running cost is increased.
本発明は上記した点に鑑みてなされたものであり、ソース／ドレイン電極と有機半導体材料との電気的接触性をコントロールするためにソース／ドレイン電極に導入される特定の金属（主に貴金属）を無電解めっき法により形成する場合において、当該特定の金属の使用量を抑制することが可能な半導体装置およびその製造方法を提供することを目的とする。
The present invention has been made in view of the above points, and a specific metal (mainly a noble metal) introduced into the source / drain electrode in order to control the electrical contact between the source / drain electrode and the organic semiconductor material. An object of the present invention is to provide a semiconductor device capable of suppressing the amount of the specific metal used and a method for manufacturing the same when forming the film by electroless plating.
本発明に係る半導体装置は、ゲート絶縁膜を介してゲート電極と対向する位置に配された一対のソース／ドレイン電極と、前記一対のソース／ドレイン電極と接する有機半導体層を有する有機薄膜トランジスタを含む半導体装置であって、前記ソース／ドレイン電極は、前記有機半導体層と接する部分を含む一部にのみ無電解めっきにより形成されためっき処理部を有することを特徴としている。
A semiconductor device according to the present invention includes an organic thin film transistor having a pair of source / drain electrodes arranged at positions facing a gate electrode through a gate insulating film, and an organic semiconductor layer in contact with the pair of source / drain electrodes. In the semiconductor device, the source / drain electrodes have a plating treatment part formed by electroless plating only at a part including a part in contact with the organic semiconductor layer.
本発明に係る半導体装置は、基板上に形成されたゲート電極と、前記ゲート電極を覆うように形成されたゲート絶縁膜と、前記ゲート絶縁膜を介して前記ゲート電極の上部から前記基板上まで延在し、前記ゲート電極の上部において離間部を有する一対のソース／ドレイン電極と、前記離間部において露出している前記ゲート絶縁膜および前記一対のソース／ドレイン電極と接するように設けられた有機半導体層と、を含み、前記ソース／ドレイン電極が、前記ゲート電極上部から前記基板上部まで延在している第１の電極層と、前記第１の端部に設けられた前記めっき処理部に相当する第２の電極層と、を含むように構成することができる。
A semiconductor device according to the present invention includes a gate electrode formed on a substrate, a gate insulating film formed so as to cover the gate electrode, and an upper portion of the gate electrode through the gate insulating film from above the substrate. A pair of source / drain electrodes extending and having a separation portion above the gate electrode, and an organic layer provided in contact with the gate insulating film and the pair of source / drain electrodes exposed in the separation portion A first electrode layer extending from an upper part of the gate electrode to an upper part of the substrate, and the plating process part provided at the first end part. And a corresponding second electrode layer.
また、本発明に係る半導体装置は、基板上に互いに離間して設けられた一対のソース／ドレイン電極と、前記基板上に前記一対のソース／ドレイン電極を覆うように設けられた有機半導体層と、前記有機半導体層の上に設けられたゲート絶縁膜と、前記ゲート絶縁膜の上に設けられたゲート電極と、を含み、前記ソース／ドレイン電極が、前記基板上に延在する第１の電極層と、前記第１の電極層の端部に設けられた前記めっき処理部に相当する第２の電極層と、を含むように構成することができる。
In addition, a semiconductor device according to the present invention includes a pair of source / drain electrodes provided on a substrate so as to be separated from each other, and an organic semiconductor layer provided on the substrate so as to cover the pair of source / drain electrodes. A gate insulating film provided on the organic semiconductor layer, and a gate electrode provided on the gate insulating film, wherein the source / drain electrodes extend on the substrate. It can comprise so that an electrode layer and the 2nd electrode layer corresponded to the said plating process part provided in the edge part of the said 1st electrode layer may be included.
上記各構成の半導体装置において、前記第２の電極層は、前記有機半導体層のチャネル領域と接する部分を含んでいることが好ましい。また、前記第２の電極層と前記有機半導体層との接触は、オーミック性接触であることが好ましい。また、前記第２の電極層は、置換めっきおよび還元めっきを併用して形成することができる。また、前記第２の電極層は、前記第１の電極層の構成材料よりもイオン化傾向の小さい材料からなることが好ましい。前記第２の電極層は、貴金属または貴金属を含む合金によって形成することができ、例えば、金または金を含む合金によって形成することができる。
In the semiconductor device having each configuration described above, it is preferable that the second electrode layer includes a portion in contact with the channel region of the organic semiconductor layer. The contact between the second electrode layer and the organic semiconductor layer is preferably ohmic contact. The second electrode layer can be formed using displacement plating and reduction plating in combination. The second electrode layer is preferably made of a material having a smaller ionization tendency than the constituent material of the first electrode layer. The second electrode layer can be formed of a noble metal or an alloy containing a noble metal, for example, gold or an alloy containing gold.
また、本発明に係る半導体装置の製造方法は、有機薄膜トランジスタを含む半導体装置の製造方法であって、基板上にゲート電極を形成する工程と、前記ゲート電極を覆うようにゲート絶縁膜を形成する工程と、前記ゲート電極の上部において離間部を有する一対のソース／ドレイン電極を前記ゲート絶縁膜上に形成する工程と、前記離間部において露出している前記ゲート絶縁膜および前記一対のソース／ドレイン電極と接するように有機半導体層を形成する工程と、を含み、前記一対のソース／ドレイン電極を形成する工程は、前記ゲート絶縁膜上に前記ゲート電極上部から前記基板上部まで延在している第１の電極層を形成する工程と、前記一対のソース／ドレイン電極が前記有機半導体層と接する部分を含む領域に開口部を有するレジストマスクを前記第１の電極層の上に形成する工程と、前記レジストマスクの開口部において露出した前記第１の電極層の一部に無電解めっき法により第２の電極層を形成す工程と、を含むことを特徴としている。
The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including an organic thin film transistor, wherein a step of forming a gate electrode on a substrate and a gate insulating film so as to cover the gate electrode are formed. Forming a pair of source / drain electrodes having a separation portion on the gate electrode on the gate insulating film; and exposing the gate insulation film and the pair of source / drain exposed in the separation portion Forming a pair of source / drain electrodes extending from the upper part of the gate electrode to the upper part of the substrate on the gate insulating film. Forming a first electrode layer and having an opening in a region including a portion where the pair of source / drain electrodes are in contact with the organic semiconductor layer Forming a resist mask on the first electrode layer, and forming a second electrode layer on the part of the first electrode layer exposed at the opening of the resist mask by electroless plating. It is characterized by including.
本発明の半導体装置および半導体装置の製造方法によれば、有機半導体層とソース／ドレイン電極との電気的接触性をコントロールするためにソース／ドレイン電極に導入される主に貴金属からなるめっき処理部を、ソース／ドレイン電極が有機半導体層と接触する部分を含む一部にのみ形成することとしたので、当該貴金属の使用量を抑制することが可能となり製造コストおよびランニングコストを抑えることが可能となる。
According to the semiconductor device and the method of manufacturing a semiconductor device of the present invention, a plating treatment unit mainly made of a noble metal introduced into the source / drain electrode in order to control electrical contact between the organic semiconductor layer and the source / drain electrode. Since the source / drain electrode is formed only on a part including the part in contact with the organic semiconductor layer, the amount of the noble metal used can be suppressed, and the manufacturing cost and the running cost can be suppressed. Become.
以下、本発明の実施例について図面を参照しつつ説明する。尚、以下に示す図において、実質的に同一又は等価な構成要素、部分には同一の参照符を付している。
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings shown below, substantially the same or equivalent components and parts are denoted by the same reference numerals.
図１は、本発明の実施例である有機ＴＦＴ１の構造を示す断面図である。有機ＴＦＴ１は、基板１０上に形成され、所謂ボトムコンタクト構造を有している。有機ＴＦＴ１を有機ＥＬディスプレイ等の表示パネルの駆動回路に用いる場合には、基板１０は、例えばガラス基板や可撓性プラスチックフィルム等の光透過性材料が用いられる。基板１０上には例えばニッケルリン（Ｎｉ－Ｐ）からなるゲート電極１１が設けられる。ゲート電極１１上には、これを覆うように例えばＰＶＰ（Poly（4-vinylphenol））とメラミンとを混合したポリマー材料からなるゲート絶縁膜１２が設けられる。
FIG. 1 is a cross-sectional view showing the structure of an organic TFT 1 which is an embodiment of the present invention. The organic TFT 1 is formed on the substrate 10 and has a so-called bottom contact structure. When the organic TFT 1 is used in a drive circuit for a display panel such as an organic EL display, the substrate 10 is made of a light transmissive material such as a glass substrate or a flexible plastic film. A gate electrode 11 made of, for example, nickel phosphorus (Ni—P) is provided on the substrate 10. On the gate electrode 11, a gate insulating film 12 made of a polymer material in which, for example, PVP (Poly (4-vinylphenol)) and melamine are mixed is provided so as to cover the gate electrode 11.
一対のソース／ドレイン電極１５は、ゲート絶縁膜１２を介してゲート電極１１上から基板１０上に延在している例えばニッケルリン（Ｎｉ－Ｐ）からなる第１の電極層１３と、第１の電極層１３上の一部に無電解めっき法を用いて形成された例えばＡｕからなる本発明のめっき処理部に相当する第２の電極層１４とによって構成される。一対のソース／ドレイン電極１５は、ゲート電極１１の上部において互いに離間しており、一方がソース電極、他方がドレイン電極として機能する。
The pair of source / drain electrodes 15 includes a first electrode layer 13 made of, for example, nickel phosphorus (Ni—P) extending from the gate electrode 11 to the substrate 10 through the gate insulating film 12, and a first electrode layer 13. And a second electrode layer 14 corresponding to the plating portion of the present invention made of, for example, Au formed on a part of the electrode layer 13 by using an electroless plating method. The pair of source / drain electrodes 15 are separated from each other in the upper part of the gate electrode 11, and one functions as a source electrode and the other functions as a drain electrode.
有機半導体層１６は、例えばテトラベンゾポルフィリン等の有機半導体材料からなり、一対のソース／ドレイン電極１５のゲート電極１１上の離間部において露出しているゲート絶縁膜１２と、ソース／ドレイン電極１５との双方に接するように設けられる。有機半導体層１６内の一対のソース／ドレイン電極１５の間に挟まれた領域がチャネル領域１７となる。
The organic semiconductor layer 16 is made of, for example, an organic semiconductor material such as tetrabenzoporphyrin, and the gate insulating film 12 exposed in the separated portion of the pair of source / drain electrodes 15 on the gate electrode 11, the source / drain electrodes 15, and the like. It is provided so that both may be touched. A region sandwiched between the pair of source / drain electrodes 15 in the organic semiconductor layer 16 becomes a channel region 17.
本実施例に係る有機ＴＦＴ１においては、Ａｕからなる第２の電極層１４は、第１の電極層１３の全面に亘って形成されるのではなく、ソース／ドレイン電極１５が有機半導体層１６と接する部分を含む第１の電極層１３上の一部にのみ無電解めっき法により形成される。
In the organic TFT 1 according to the present embodiment, the second electrode layer 14 made of Au is not formed over the entire surface of the first electrode layer 13, but the source / drain electrode 15 is connected to the organic semiconductor layer 16. Only part of the first electrode layer 13 including the contact portion is formed by electroless plating.
有機半導体１６のイオン化ポテンシャルの値と近似した仕事関数を持つＡｕを第２の電極層１４の材料として使用することにより、有機半導体層１６とソース／ドレイン電極１５との間でオーミック性接触を形成することが可能となり、良好な電気特性を得ることが可能となる。このように第２の電極層１４は、有機半導体１６とソース／ドレイン電極１５との間の接触性をコントロールするために導入されるものであり、ソース／ドレイン電極１５が有機半導体層１６と接する部分にのみ形成されていればその機能は十分に発揮される。そこで、本実施例に係る有機ＴＦＴ１においては、有機半導体層１６と接する部分を含む第１の電極層１３上の一部にのみ第２電極層１４を設けることにより、Ａｕの使用量を抑制することとした。
By using Au having a work function approximate to the value of the ionization potential of the organic semiconductor 16 as the material of the second electrode layer 14, an ohmic contact is formed between the organic semiconductor layer 16 and the source / drain electrode 15. This makes it possible to obtain good electrical characteristics. Thus, the second electrode layer 14 is introduced to control the contact between the organic semiconductor 16 and the source / drain electrode 15, and the source / drain electrode 15 is in contact with the organic semiconductor layer 16. If it is formed only in the part, its function is fully exhibited. Therefore, in the organic TFT 1 according to the present embodiment, the usage amount of Au is suppressed by providing the second electrode layer 14 only on a part of the first electrode layer 13 including the portion in contact with the organic semiconductor layer 16. It was decided.
次に、上記した構造を有する有機ＴＦＴ１の製造方法について図面を参照しつつ説明する。図２（ａ）～（ｆ）は、本発明の実施例である有機ＴＦＴ１の製造工程を示す各プロセスステップ毎の断面図である。
Next, a method for manufacturing the organic TFT 1 having the above structure will be described with reference to the drawings. 2A to 2F are cross-sectional views for each process step showing a manufacturing process of the organic TFT 1 which is an embodiment of the present invention.
はじめに、ガラス基板や可撓性プラスチックフィルム等からなる基板１０を用意する。基板１０上に有機ＴＦＴ１を形成する前に純水や界面活性剤等を含む洗浄液で洗浄し、基板１０の表面に付着した油脂等を除去することとしてもよい。
First, a substrate 10 made of a glass substrate or a flexible plastic film is prepared. Before forming the organic TFT 1 on the substrate 10, it may be cleaned with a cleaning liquid containing pure water, a surfactant or the like to remove oils and fats attached to the surface of the substrate 10.
次に、アンカー効果によって、基板１０とゲート電極１１との密着性を向上させるため、基板１０表面の粗面化処理を行う。具体的には基板１０をクロム酸／硫酸混合液等のエッチング液を用いてエッチングすることにより、基板１０の表面に微細な凹凸を形成する。その後、基板１０の表面に残ったクロム化合物を塩酸等を用いて除去する。次に、ゲート電極１１を形成するための無電解めっきの核となる触媒を基板１０上に吸着させる。触媒としては、例えばＰｄ－Ｓｎ錯体を用いることができる。次に、基板１０を酸溶液に浸漬し、スズ塩を溶解させ、酸化還元反応により基板１０上に金属パラジウムを生成する。次に、基板１０を硫酸ニッケルおよび次亜リン酸ナトリウムを含むめっき浴に浸漬し、基板１０表面にニッケルリン（Ｎｉ－Ｐ）からなるめっき膜を形成する。次に、基板１０上に形成されためっき膜に公知のフォトリソ技術を用いてパターニングを行って、ゲート電極１１を形成する（図２（ａ））。
Next, the surface of the substrate 10 is roughened to improve the adhesion between the substrate 10 and the gate electrode 11 by the anchor effect. Specifically, fine irregularities are formed on the surface of the substrate 10 by etching the substrate 10 using an etching solution such as a chromic acid / sulfuric acid mixed solution. Thereafter, the chromium compound remaining on the surface of the substrate 10 is removed using hydrochloric acid or the like. Next, a catalyst serving as a nucleus of electroless plating for forming the gate electrode 11 is adsorbed on the substrate 10. As the catalyst, for example, a Pd—Sn complex can be used. Next, the board | substrate 10 is immersed in an acid solution, a tin salt is dissolved, and metal palladium is produced | generated on the board | substrate 10 by oxidation-reduction reaction. Next, the substrate 10 is immersed in a plating bath containing nickel sulfate and sodium hypophosphite to form a plating film made of nickel phosphorus (Ni—P) on the surface of the substrate 10. Next, the gate electrode 11 is formed by patterning the plating film formed on the substrate 10 using a known photolithography technique (FIG. 2A).
尚、ゲート電極１１のパターニングを行う方法としては、上記した方法以外に、例えば、ゲート電極１１のパターンに対応したマスクを用いて基板１０の粗面化処理を行って、粗面化処理が行われた部分にのみ触媒を吸着させ、この部分に選択的にめっき膜を形成することによりゲート電極１１のパターニングを行うこととしてもよい。また、触媒機能を持つシランカップリング剤を基板１０の成膜面に全面塗布し、ゲート電極１１のパターンに対応したマスクを介して基板１０の表面に紫外線照射を行うことにより、触媒に対する吸着力を低下させるような表面改質処理を行って、紫外線が照射されない部分にのみ触媒を吸着させ、この部分に選択的にめっき膜を形成することによりゲート電極１１のパターニングを行うこととしてもよい。また、触媒機能を持つシランカップリング剤をフレキソ印刷やインクジェット法などの印刷法により描画し、シランカップリング剤が存在する部分にのみ選択的にめっき膜を形成することによりゲート電極１１のパターニングを行うこととしてもよい。
As a method for patterning the gate electrode 11, in addition to the above-described method, for example, a roughening process is performed by performing a roughening process on the substrate 10 using a mask corresponding to the pattern of the gate electrode 11. The gate electrode 11 may be patterned by causing the catalyst to be adsorbed only on the broken portion and selectively forming a plating film on this portion. In addition, a silane coupling agent having a catalytic function is applied to the entire surface of the substrate 10 and the surface of the substrate 10 is irradiated with ultraviolet rays through a mask corresponding to the pattern of the gate electrode 11, thereby adsorbing the catalyst. It is also possible to pattern the gate electrode 11 by performing a surface modification process that lowers the thickness of the catalyst, adsorbing the catalyst only on the portion that is not irradiated with ultraviolet rays, and selectively forming a plating film on this portion. Further, the gate electrode 11 is patterned by drawing a silane coupling agent having a catalytic function by a printing method such as flexographic printing or an ink jet method, and selectively forming a plating film only on a portion where the silane coupling agent exists. It may be done.
次に、ゲート電極１１を覆うようにゲート絶縁膜１２を形成する。例えば、ＰＶＰ（Poly（4-vinylphenol））にメラミンを混合したポリマー材料をゲート電極上に適量滴下してスピンコート法により成膜し、これに熱処理を施して硬化させることによりゲート絶縁膜１２を形成する（図２（ｂ））。
Next, a gate insulating film 12 is formed so as to cover the gate electrode 11. For example, an appropriate amount of a polymer material in which melamine is mixed with PVP (Poly (4-vinylphenol)) is dropped onto the gate electrode, a film is formed by a spin coating method, and the gate insulating film 12 is formed by subjecting it to heat treatment and curing. It forms (FIG.2 (b)).
次に、ゲート絶縁膜１２上にソース／ドレイン電極１５を構成するニッケルリン（Ｎｉ－Ｐ）からなる第１の電極層１３を無電解めっき法により形成する。無電解めっき法によりニッケルリン（Ｎｉ－Ｐ）めっき膜を形成するプロセスは、上記したゲート電極１１を形成するプロセスと同様である。すなわち、必要に応じてゲート絶縁膜１２の粗面化処理を行い、Ｐｄ－Ｓｎ錯体からなる触媒をゲート絶縁膜１２上に吸着させ、酸溶液によるアクセレータ処理を行った後、基板１０を硫酸ニッケルおよび次亜リン酸ナトリウムを含むめっき浴に浸漬する。これにより、基板１０およびゲート電極１１上にゲート絶縁膜１２を介してニッケルリン（Ｎｉ－Ｐ）からなるめっき膜が形成される。その後、公知のフォトリソ技術によって第１の電極層１３のパターニングを行う。かかるパターニング工程において、ゲート電極１１上に形成されたニッケルリン（Ｎｉ－Ｐ）めっき膜に有機ＴＦＴのチャネル領域１７を形成するための開口部（離間部）１３ａが設けられ、ソース／ドレイン電極１５の配線パターンが形成される。
Next, a first electrode layer 13 made of nickel phosphorus (Ni—P) constituting the source / drain electrode 15 is formed on the gate insulating film 12 by an electroless plating method. The process of forming the nickel phosphorus (Ni—P) plating film by the electroless plating method is the same as the process of forming the gate electrode 11 described above. That is, the gate insulating film 12 is roughened as necessary, a catalyst made of a Pd—Sn complex is adsorbed on the gate insulating film 12, an accelerator treatment with an acid solution is performed, and then the substrate 10 is nickel sulfate. And soak in a plating bath containing sodium hypophosphite. As a result, a plating film made of nickel phosphorus (Ni—P) is formed on the substrate 10 and the gate electrode 11 via the gate insulating film 12. Thereafter, the first electrode layer 13 is patterned by a known photolithography technique. In this patterning step, an opening (spacer) 13 a for forming the channel region 17 of the organic TFT is provided in the nickel phosphorus (Ni—P) plating film formed on the gate electrode 11, and the source / drain electrode 15 The wiring pattern is formed.
尚、第１の電極層１３のパターニングを行う方法としては、上記した方法以外に、例えば、第１の電極層１３のパターンに対応したマスクを用いてゲート絶縁膜１２の粗面化処理を行って、粗面化処理が行われた部分にのみ触媒を吸着させ、この部分に選択的にめっき膜を形成することにより第１の電極層１３のパターニングを行うこととしてもよい。また、触媒機能を持つシランカップリング剤をゲート絶縁膜１２の成膜面に全面塗布し、第１の電極層１３のパターンに対応したマスクを介してゲート絶縁膜１２の表面に紫外線照射を行うことにより、触媒に対する吸着力を低下させるような表面改質処理を行って、紫外線が照射されない部分にのみ触媒を吸着させ、この部分に選択的にめっき膜を形成することにより第１の電極層１３のパターニングを行うこととしてもよい。また、触媒機能を持つシランカップリング剤をフレキソ印刷やインクジェット法などの印刷法により描画し、シランカップリング剤が存在する部分にのみ選択的にめっき膜を形成することにより第１の電極層１３のパターニングを行うこととしてもよい。
As a method for patterning the first electrode layer 13, in addition to the above-described method, for example, a roughening process of the gate insulating film 12 is performed using a mask corresponding to the pattern of the first electrode layer 13. Thus, the first electrode layer 13 may be patterned by adsorbing the catalyst only on the roughened portion and selectively forming a plating film on this portion. Further, a silane coupling agent having a catalytic function is applied to the entire surface of the gate insulating film 12, and the surface of the gate insulating film 12 is irradiated with ultraviolet rays through a mask corresponding to the pattern of the first electrode layer 13. Thus, the first electrode layer is formed by subjecting the surface modification treatment to reduce the adsorptive power to the catalyst, adsorbing the catalyst only to a portion not irradiated with ultraviolet rays, and selectively forming a plating film on this portion. 13 patterning may be performed. Further, the first electrode layer 13 is formed by drawing a silane coupling agent having a catalytic function by a printing method such as flexographic printing or an ink jet method, and selectively forming a plating film only on a portion where the silane coupling agent is present. The patterning may be performed.
次に、第１の電極層１３上のゲート電極１１を挟む位置にレジストマスク２０を形成する。すなわち、レジストマスク２０は、ゲート電極１１の形成位置に開口部２０ａを有する。第１の電極層１３は、この開口部２０ａにおいて露出している（図２（ｄ））。
Next, a resist mask 20 is formed at a position sandwiching the gate electrode 11 on the first electrode layer 13. That is, the resist mask 20 has an opening 20 a at the position where the gate electrode 11 is formed. The first electrode layer 13 is exposed at the opening 20a (FIG. 2D).
次に、無電解めっき法により、レジストマスク２０の開口部２０ａにおいて露出している第１の電極層１３の一部にのみ選択的にＡｕからなる第２の電極層１４を形成する。第２の電極層は、例えば、置換Ａｕめっき法および還元Ａｕめっき法を併用して形成される。
Next, the second electrode layer 14 made of Au is selectively formed only on a part of the first electrode layer 13 exposed in the opening 20a of the resist mask 20 by electroless plating. The second electrode layer is formed by using, for example, a substitution Au plating method and a reduction Au plating method in combination.
置換Ａｕめっき法は、めっき処理される下地金属のイオン化傾向とめっき材料であるＡｕのイオン化傾向の差を利用するものであり、ニッケルリン（Ｎｉ－Ｐ）からなる第１の電極層１３が形成された基板１０をシアン系又は非シアン系の置換金めっき浴に浸漬することにより、第１の電極層１３上にＡｕめっき膜を形成する。めっき浴中では、比較的イオン化傾向の大きい下地のニッケルリン（Ｎｉ－Ｐ）が溶解し、ニッケルリン（Ｎｉ－Ｐ）上にＡｕが析出する反応が起る。置換Ａｕめっき法においては、下地のニッケルリン（Ｎｉ－Ｐ）がＡｕで被覆された時点で反応が停止するため、析出するＡｕの膜厚は薄くなってしまう。そこで、本実施例においては、置換Ａｕめっき処理に引き続き還元Ａｕめっき処理を行い、Ａｕめっき膜の膜厚を確保することとした。
The displacement Au plating method utilizes the difference between the ionization tendency of the base metal to be plated and the ionization tendency of Au as the plating material, and the first electrode layer 13 made of nickel phosphorus (Ni—P) is formed. The Au substrate is formed on the first electrode layer 13 by immersing the substrate 10 thus obtained in a cyan or non-cyan substitution gold plating bath. In the plating bath, the underlying nickel phosphorus (Ni—P), which has a relatively high ionization tendency, dissolves, and a reaction occurs in which Au precipitates on the nickel phosphorus (Ni—P). In the substitutional Au plating method, the reaction stops when the underlying nickel phosphorus (Ni—P) is coated with Au, so that the deposited Au film becomes thin. Therefore, in this embodiment, the reduced Au plating process is performed subsequent to the replacement Au plating process to secure the film thickness of the Au plating film.
還元Ａｕめっき法は、めっき浴中に含まれる還元剤の酸化によって放出される電子がＡｕイオンに転位して被めっき材にＡｕ皮膜を形成するめっき法である。例えばテトラヒドロほう酸カリウム（ＫＢＨ4）等を還元剤とし、ＫＡｕ（ＣＮ）2を金塩として用いためっき浴中に基板１０を浸漬することにより、置換Ａｕめっき膜が形成された第１の電極層１３上に更に還元Ａｕめっき膜が形成される。
The reduced Au plating method is a plating method in which electrons released by oxidation of a reducing agent contained in a plating bath are transferred to Au ions to form an Au film on a material to be plated. For example, the first electrode layer in which the substituted Au plating film is formed by immersing the substrate 10 in a plating bath using potassium tetrahydroborate (KBH 4 ) or the like as a reducing agent and KAu (CN) 2 as a gold salt. A reduced Au plating film is further formed on 13.
第１の電極層１３は、先の工程で形成したレジストマスク２０の開口部２０ａにおいてのみ露出している。このため、第１の電極層１３は、置換Ａｕめっき工程および還元Ａｕめっき工程において、この露出部分のみがめっき液に曝されて、この露出部分にのみ第２の電極層１４が形成される。このようにして、第１の電極層１３上に第２の電極層１４が形成され、ソース／ドレイン電極１５が完成する（図２（ｅ））。
The first electrode layer 13 is exposed only at the opening 20a of the resist mask 20 formed in the previous step. Therefore, only the exposed portion of the first electrode layer 13 is exposed to the plating solution in the replacement Au plating step and the reduced Au plating step, and the second electrode layer 14 is formed only on the exposed portion. In this way, the second electrode layer 14 is formed on the first electrode layer 13, and the source / drain electrode 15 is completed (FIG. 2E).
次に、レジストマスク２０を除去した後、例えばインクジェット法等により、ゲート電極１１上に形成されたソース／ドレイン電極１５およびソース／ドレイン電極１５を分断する開口部１３ａにおいて露出したゲート絶縁膜１２と接するように、例えばテトラベンゾポルフィリン等からなる有機半導体層１６を形成する。インクジェット法は、有機半導体材料含む溶液をノズルより吐出してパターンを形成する印刷法であり、基板１０に対して非接触で成膜することができる、広面積に印刷することができる、使用する材料の量を最小限に抑えることできる、高い吐出位置精度を確保することができるといった利点を有することから、有機半導体の成膜に好適な手法である。その後、有機半導体材料の塗膜に対し、必要に応じて加熱処理等の後処理を行う（図２（ｆ））。
Next, after the resist mask 20 is removed, the source / drain electrode 15 formed on the gate electrode 11 and the gate insulating film 12 exposed in the opening 13a that divides the source / drain electrode 15 are formed by, for example, an inkjet method. An organic semiconductor layer 16 made of, for example, tetrabenzoporphyrin or the like is formed so as to be in contact therewith. The ink jet method is a printing method in which a solution containing an organic semiconductor material is discharged from a nozzle to form a pattern, and can be formed in a non-contact manner with respect to the substrate 10 and can be printed over a wide area. Since it has an advantage that the amount of material can be minimized and high discharge position accuracy can be secured, it is a method suitable for film formation of an organic semiconductor. Thereafter, post-treatment such as heat treatment is performed on the coating film of the organic semiconductor material as necessary (FIG. 2F).
以上の各工程を経ることにより有機ＴＦＴ１が完成する。このように、本発明の半導体装置の製造方法によれば、第１の電極層１３の上に無電解めっき法により第２の電極層１４を形成する場合において、レジストマスク２０を用いて第１の電極層１３を部分的に露出させるようにし、レジスト開口部における露出部分にのみ選択的に第２の電極層１４を形成することとしたので、第２の電極層１４を構成する金属（主に貴金属）の使用量を抑制することができ製造コストを抑えることが可能となる。例えば、基板上に本実施例に係る有機ＴＦＴをアレイ状に形成して、有機ＥＬディスプレイ等の表示パネルの駆動回路を形成する場合、Ａｕの使用量を従来の数％程度にまで抑えることが可能となり、大幅なコスト削減効果をもたらすことが可能となる。また、これにより、めっき浴の交換サイクルを長くすることができるので、ランニングコストも抑えることが可能となる。
The organic TFT 1 is completed through the above steps. As described above, according to the method of manufacturing a semiconductor device of the present invention, when the second electrode layer 14 is formed on the first electrode layer 13 by the electroless plating method, the first resist mask 20 is used. The electrode layer 13 is partially exposed, and the second electrode layer 14 is selectively formed only in the exposed portion of the resist opening, so that the metal constituting the second electrode layer 14 (mainly In addition, the amount of noble metal) used can be reduced, and the manufacturing cost can be reduced. For example, when the organic TFT according to the present embodiment is formed in an array on a substrate to form a driving circuit for a display panel such as an organic EL display, the amount of Au used can be suppressed to about several percent of the conventional case. It becomes possible, and it becomes possible to bring about a significant cost reduction effect. Moreover, since the exchange cycle of a plating bath can be lengthened by this, a running cost can also be suppressed.
ここで、第２の電極層１４は、ソース／ドレイン電極と有機半導体層との電気的接触性をコントロールすることを目的として導入されるところ、少なくとも有機半導体層のチャネル領域と接する部分に形成されていればその機能は発揮されるので、第２の電極層１４の形成領域を制限したことによる電気的特性への悪影響はない。
Here, the second electrode layer 14 is introduced for the purpose of controlling electrical contact between the source / drain electrodes and the organic semiconductor layer, and is formed at least in a portion in contact with the channel region of the organic semiconductor layer. If so, the function is exhibited, and there is no adverse effect on the electrical characteristics due to the restriction of the formation region of the second electrode layer 14.
本実施例に示す方法により作製した有機ＴＦＴの特性を確認したところ、移動度：０．４ｃｍ2／Ｖｓ、ＯＮ／ＯＦＦ比：１０6、閾値電圧Ｖｔｈ：－８Ｖが得られた。比較例として、第２の電極層１４を設けず、他の構造は上記した本実施例のものと同一である有機ＴＦＴを作製し、特性確認を行ったところ、移動度：０．１ｃｍ2／Ｖｓ、ＯＮ／ＯＦＦ比：１０6、閾値電圧Ｖｔｈ：－１０Ｖであった。以上の結果より、ソース／ドレイン電極に部分的なＡｕめっきを施した場合であっても、第２の電極層１４は有機半導体層１６との接触性を改善させる機能を十分に発揮し、良好な動作特性を示すことが確認された。
When the characteristics of the organic TFT manufactured by the method shown in this example were confirmed, mobility: 0.4 cm 2 / Vs, ON / OFF ratio: 10 6 , and threshold voltage Vth: −8 V were obtained. As a comparative example, when the second electrode layer 14 was not provided and an organic TFT having the other structure identical to that of the above-described embodiment was fabricated and characteristics were confirmed, mobility: 0.1 cm 2 / Vs, ON / OFF ratio: 10 6 , threshold voltage Vth: −10V. From the above results, even when the partial Au plating is applied to the source / drain electrodes, the second electrode layer 14 sufficiently exhibits the function of improving the contact with the organic semiconductor layer 16 and is good. It was confirmed that it showed a good operating characteristic.
図３は、第２の電極層１４の形成領域を更に制限した場合の有機ＴＦＴの構造を示す断面図である。第２の電極層１４の仕事関数は有機半導体のイオン化ポテンシャルに近いものであるのに対し、第１の電極層１３の仕事関数は離れた値を持っている。そのため、有機半導体層１６の一部が第１の電極層１３と接触する部分が存在していても構わない。また、有機半導体層１６への電荷注入は、ソース/ドレイン電極の端部から行われるため、図３に示すように、第２の電極層１４の形成領域は、有機半導体層１６から電荷注入が行われる第1の電極層１３の端部であることが望ましい。すなわち、第２の電極層１４は、チャネル領域１７を挟むソース／ドレイン電極の先端部分に設けられることが望ましい。かかる構造は、第２電極を選択的に形成するためのレジストマスク２０の開口幅を図２（ｄ）に示す場合よりも狭くすることにより実現することができる。かかる構造とすることにより、Ａｕの使用量を更に抑制することが可能となる。また、他の具体的な形成方法としては、第１の電極層１３をスパッタ法で成膜した後にフォトレジストで所望のラインにパターニングし、フォトレジストを残したまま置換/還元めっきを行うことが挙げられる。
FIG. 3 is a cross-sectional view showing the structure of the organic TFT when the formation region of the second electrode layer 14 is further limited. The work function of the second electrode layer 14 is close to the ionization potential of the organic semiconductor, whereas the work function of the first electrode layer 13 has a distant value. Therefore, a portion where a part of the organic semiconductor layer 16 is in contact with the first electrode layer 13 may exist. In addition, since charge injection into the organic semiconductor layer 16 is performed from the end of the source / drain electrode, as shown in FIG. 3, charge injection from the organic semiconductor layer 16 occurs in the formation region of the second electrode layer 14. It is desirable to be an end portion of the first electrode layer 13 to be performed. That is, the second electrode layer 14 is desirably provided at the tip of the source / drain electrode that sandwiches the channel region 17. Such a structure can be realized by making the opening width of the resist mask 20 for selectively forming the second electrode narrower than the case shown in FIG. With such a structure, the amount of Au used can be further suppressed. As another specific formation method, the first electrode layer 13 is formed by sputtering, and then patterned into a desired line with a photoresist, and substitution / reduction plating is performed while leaving the photoresist. Can be mentioned.
上記した本発明に係る有機ＴＦＴの構造および製法は例示にすぎず、種々の改変を行うことが可能である。上記の実施例では、第２の電極層１４としてＡｕを使用することとしたが、これに限定されず、例えばパラジウム（Ｐｄ）、ロジウム（Ｒｈ）、イリジウム（Ｉｒ）、銀（Ａｇ）、銅（Ｃｕ）等の貴金属、若しくはこれらの合金を用いることが可能である。この場合、有機半導体層１６のイオン化ポテンシャルに近似した仕事関数を持つ材料を選定することが好ましい。また、上記の実施例では、置換めっきおよび還元めっきを併用して第２の電極層１４を形成することとしたが、第２の電極層１４の膜厚を薄くできる場合等においては、置換めっきのみで第２の電極層１４を形成することとしてもよい。また、上記の実施例では、置換めっきおよび還元めっきをそれぞれ１回ずつ行うこととしたが、置換めっきおよび還元めっきを繰り返して複数の層を形成するようにしてもよい。
The structure and manufacturing method of the organic TFT according to the present invention described above are merely examples, and various modifications can be made. In the above embodiment, Au is used as the second electrode layer 14, but is not limited to this. For example, palladium (Pd), rhodium (Rh), iridium (Ir), silver (Ag), copper It is possible to use a noble metal such as (Cu) or an alloy thereof. In this case, it is preferable to select a material having a work function approximate to the ionization potential of the organic semiconductor layer 16. In the above embodiment, the second electrode layer 14 is formed by using both displacement plating and reduction plating. However, in the case where the thickness of the second electrode layer 14 can be reduced, the displacement plating is performed. Only the second electrode layer 14 may be formed. In the above embodiment, the displacement plating and the reduction plating are each performed once. However, the plurality of layers may be formed by repeating the displacement plating and the reduction plating.
また、上記の実施例では、第１の電極層１３としてニッケルリン（Ｎｉ－Ｐ）を用いることとしたが、これに限定されず、第２電極層１４よりもイオン化傾向が大きいめっき材料であれば、単体、合金いずれの材料も用いることが可能である。また、第１の電極層１３は、無電解めっき法に限らず、スパッタ法、ＣＶＤ法、真空蒸着法等により電極材料を成膜した後、例えばフォトリソ技術等によって所望のパターニングを行うことにより形成してもよい。また、インクジェット法により金属のナノインクをライン状に吐出することにより第１電極層１３を形成することとしてもよい。また、ゲート電極１１の材料および形成方法についてもこれと同様の改変を行うことが可能である。
In the above embodiment, nickel phosphorus (Ni—P) is used as the first electrode layer 13. However, the present invention is not limited to this, and any plating material having a higher ionization tendency than the second electrode layer 14 may be used. For example, it is possible to use either a simple substance or an alloy material. The first electrode layer 13 is not limited to the electroless plating method, but is formed by performing desired patterning using, for example, a photolithography technique after forming an electrode material by a sputtering method, a CVD method, a vacuum deposition method, or the like. May be. Alternatively, the first electrode layer 13 may be formed by ejecting metal nano-ink in a line shape by an inkjet method. Further, the same modification can be made for the material and the formation method of the gate electrode 11.
また、上記の実施例では、有機半導体層１６の材料としてテトラベンゾポルフィリンを用いることとしたが、これに限定されず、他の有機半導体材料を使用することも可能である。例えば、低分子系材料ではフタロシアニン系誘導体、ナフタロシアニン系誘導体、アゾ化合物系誘導体、ペリレン系誘導体、インジゴ系誘導体、キナクリドン系誘導体、アントラキノン類などの多環キノン系誘導体、シアニン系誘導体、フラーレン類誘導体、あるいはインドール、カルバゾール、オキサゾール、インオキサゾール、チアゾール、イミダゾール、ピラゾール、オキサアジアゾール、ピラゾリン、チアチアゾール、トリアゾールなどの含窒素環式化合物誘導体、ヒドラジン誘導体、トリフェニルアミン誘導体、トリフェニルメタン誘導体、スチルベン類、アントラキノンジフェノキノン等のキノン化合物誘導体、ペンタセン、アントラセン、ビレン、フェナントレン、コロネンなどの多環芳香族化合物誘導体などである。高分子材料では、上述した低分子化合物の構造がポリエチレン鎖、ポリシロキサン鎖、ポリエーテル鎖、ポリエステル鎖、ポリアミド鎖、ポリイミド鎖等の高分子の主鎖中に用いられた物あるいは側鎖としてペンダント状に結合したもの、もしくはポリパラフェニレン等の芳香族系共役性高分子、ポリアセチレン等の脂肪族系共役性高分子、ポリピノールやポリチオフェン率の複素環式共役性高分子、ポリアニリン類やポリフェニレンサルファイド等の含ヘテロ原子共役性高分子、ポリ（フェニレンビニレン）やポリ（アニーレンビニレン）やポリ（チェニレンビニレン）等の共役性高分子の構成単位が交互に結合した構造を有する複合型共役系高分子等の炭素系共役高分子を用いることができる。また、ポリシラン類やジシラニレンアリレンポリマー類、（ジシラニレン）エチニレンポリマー類のようなジシラニレン炭素系共役性ポリマー構造などのオリゴシラン類と炭素系共役性構造が交互に連鎖した高分子類などを用いることができる。他にもリン系、窒素系等の無機元素からなる高分子鎖でも良く、さらにフタロシアナートポリシロキサンのような高分子鎖の芳香族系配位子が配位した高分子類、ペリレンテトラカルボン酸のようなペリレン類を熱処理して縮環させた高分子類、ポリアクリロニトリルなどのシアノ基を有するポリエチレン誘導体を熱処理して得られるラダー型高分子類、さらにペロブスカイト類に有機化合物がインターカレートした複合材料を用いてもよい。
In the above embodiment, tetrabenzoporphyrin is used as the material of the organic semiconductor layer 16, but the present invention is not limited to this, and other organic semiconductor materials can also be used. For example, for low molecular weight materials, phthalocyanine derivatives, naphthalocyanine derivatives, azo compound derivatives, perylene derivatives, indigo derivatives, quinacridone derivatives, polycyclic quinone derivatives such as anthraquinones, cyanine derivatives, fullerene derivatives Or nitrogen-containing cyclic compound derivatives such as indole, carbazole, oxazole, inoxazole, thiazole, imidazole, pyrazole, oxadiazole, pyrazoline, thiathiazole, triazole, hydrazine derivative, triphenylamine derivative, triphenylmethane derivative, stilbene Quinone compound derivatives such as anthraquinone diphenoquinone, and polycyclic aromatic compound derivatives such as pentacene, anthracene, bilene, phenanthrene, and coronene. In the polymer material, the structure of the low molecular compound mentioned above is pendant as an object or side chain used in the polymer main chain such as polyethylene chain, polysiloxane chain, polyether chain, polyester chain, polyamide chain, polyimide chain, etc. Aromatic conjugated polymers such as polyparaphenylene, aliphatic conjugated polymers such as polyacetylene, heterocyclic conjugated polymers with polypinol and polythiophene ratios, polyanilines and polyphenylene sulfide, etc. Hetero-atom conjugated polymers of this type, complex type conjugated systems having a structure in which structural units of conjugated polymers such as poly (phenylene vinylene), poly (annelen vinylene) and poly (chenylene vinylene) are alternately bonded Carbon-based conjugated polymers such as molecules can be used. In addition, polymers containing oligosilanes and carbon-based conjugated structures such as polysilanes, disilanylene-arylene polymers, and disilanylene carbon-based conjugated polymer structures such as (disilanylene) ethynylene polymers Can be used. In addition, polymer chains made of inorganic elements such as phosphorus and nitrogen may be used, and polymers having aromatic chain ligands such as phthalocyanate polysiloxane coordinated, perylenetetracarboxylic Polymers in which perylenes such as acids are heat-treated and condensed, ladder-type polymers obtained by heat-treating polyethylene derivatives having a cyano group such as polyacrylonitrile, and organic compounds intercalated in perovskites The composite material may be used.
また、上記の実施例ではゲート絶縁膜１２の材料としてＰＶＰとメラミンとを混合したポリマー材料を用いることとしたが、これに限定されず、無機材料、有機材料のいずれの絶縁膜もゲート絶縁膜として使用することができる。例えば、LiOx、LiNx、NaOx、KOx、RbOx、CsOx、BeOx、MgOx、MgNx、CaOx、CaNx、SrOx、BaOx、ScOx、YOx、YNx、LaOx、LaNx、CeOx、PrOx、NdOx、SmOx、EuOx、GdOx、TbOx、DyOx、HoOx、ErOx、TmOx、YbOx、LuOx、TiOx、TiNx、ZrOx、ZrNx、HfOx、HfNx、ThOx、VOx、VNx、NbOx、TaOx、TaNx、CrOx、CrNx、MoOx、MoNx、WOx、WNx、MnOx、ReOx、FeOx、FeNx、RuOx、OsOx、CoOx、RhOx、IrOx、NiOx、PdOx、PtOx、CuOx、CuNx、AgOx、AuOx、ZnOx、CdOx、HgOx、BOx、BNx、AlOx、AlNx、GaOx、GaNx、InOx、TiOx、TiNx、SiOx、SiNx、GeOx、SnOx、PbOx、POx、PNx、AsOx、SbOx、SeOx、TeOxなどの金属酸化物、LiAlO2、Li2SiO3、Li2TiO3、Na2Al22O34、NaFeO2、Na4SiO4、K2SiO3、K2TiO3、K2WO4、Rb2CrO4、Cs2CrO4、MgAl2O4、MgFe2O4、MgTiO3、CaTiO3、CaWO4、CaZrO3、SrFe12O19、SrTiO3、SrZrO3、BaAl2O4、BaFe12O19、BaTiO3、Y3Al5O12、Y3Fe5O12、LaFeO3、La3Fe5O12、La2Ti2O7、CeSnO4、CeTiO4、Sm3Fe5O12、EuFeO3、Eu3Fe5O12、GdFeO3、Gd3Fe5O12、DyFeO3、Dy3Fe5O12、HoFeO3、Ho3Fe5O12、ErFeO3、Er3Fe5O12、Tm3Fe5O12、LuFeO3、Lu3Fe5O12、NiTiO3、Al2TiO3、FeTiO3、BaZrO3、LiZrO3、MgZrO3、HfTiO4、NH4VO3、AgVO3、LiVO3、BaNb2O6、NaNbO3、SrNb2O6、KTaO3、NaTaO3、SrTa2O6、CuCr2O4、Ag2CrO4、BaCrO4、K2MoO4、Na2MoO4、NiMoO4、BaWO4、Na2WO4、SrWO4、MnCr2O4、MnFe2O4、MnTiO3、MnWO4、CoFe2O4、ZnFe2O4、FeWO4、CoMoO4、CuTiO3、CuWO4、Ag2MoO4、Ag2WO4、ZnAl2O4、ZnMoO4、ZnWO4、CdSnO3、CdTiO3、CdMoO4、CdWO4、NaAlO2、MgAl2O4、SrAl2O4、Gd3Ga5O12、InFeO3、MgIn2O4、Al2TiO5、FeTiO3、MgTiO3、Na2SiO3、CaSiO3、ZrSiO4、K2GeO3、Li2GeO3、Na2GeO3、Bi2Sn3O9、MgSnO3、SrSnO3、PbSiO3、PbMoO4、PbTiO3、SnO2-Sb2O3、CuSeO4、Na2SeO3、ZnSeO3、K2TeO3、K2TeO4、Na2TeO3、Na2TeO4などの金属複合酸化物、FeS、Al2S3、MgS、ZnSなどの硫化物、LiF、MgF2、SmF3などのフッ化物、HgCl、FeCl2、CrCl3などの塩化物、AgBr、CuBr、MnBr2などの臭化物、PbI2、CuI、FeI2などのヨウ化物、またはSiAlONなどの金属酸化窒化物でも有効である。またボトムコンタクト構造ではゲート電極を陽極酸化することによりゲート絶縁膜を形成してもよい。例えばTa、Al、Mg、Ti、Nb、Zr等の単体もしくはそれらの合金などが有効である。また、ポリイミド、ポリアミド、ポリエステル、ポリアクリレート、エポキシ樹脂、フェノール樹脂、ポリビニルアルコール、などポリマー系材料でも有効である。また、ゲート絶縁膜表面をOTS、HMDSなどで撥水処理を行っても良い。
In the above embodiment, a polymer material in which PVP and melamine are mixed is used as the material of the gate insulating film 12. However, the present invention is not limited to this, and any insulating film of an inorganic material or an organic material can be used as the gate insulating film. Can be used as For example, LiOx, LiNx, NaOx, KOx, RbOx, CsOx, BeOx, MgOx, MgNx, CaOx, CaNx, SrOx, BaOx, ScOx, YOx, YNx, LaOx, LaNx, CeOx, PrOx, NdOx, SmOx, E TbOx, DyOx, HoOx, ErOx, TmOx, YbOx, LuOx, TiOx, TiNx, ZrOx, ZrNx, HfOx, HfNx, ThOx, VOx, VNx, NbOx, TaOx, TaNx, CrOx, CrNx, MoOx, MoN MnOx, ReOx, FeOx, FeNx, RuOx, OsOx, CoOx, RhOx, IrOx, NiOx, PdOx, PtOx, CuOx, CuNx, AgOx, AuOx, ZnOx, CdOx, HgOx, BOx, BNx, AlOx, Nx InOx, TiOx, TiNx, SiOx, SiNx, GeOx, SnOx, pbOx, POx, PNx, AsOx, sbOx, SeOx, metal oxides such as TeOx, LiAlO 2, Li 2 SiO 3, Li 2 TiO 3, Na 2 Al 22 O 34 , NaFeO 2 , Na 4 SiO 4 , K 2 SiO 3 , K 2 TiO 3 , K 2 WO 4 , Rb 2 CrO 4 , Cs 2 CrO 4 , MgAl 2 O 4 , MgFe 2 O 4 , MgTiO 3 , CaTiO 3, CaWO 4, CaZrO 3, SrFe 12 O 19, SrTiO 3, SrZrO 3, BaAl 2 O 4, BaFe 12 O 19, BaTiO 3, Y 3 A l5 O 12, Y 3 Fe 5 O 12, LaFeO 3, La 3 Fe 5 O 12 , La 2 Ti 2 O 7 , CeSnO 4 , CeTiO 4 , Sm 3 Fe 5 O 12 , EuFeO 3 , Eu 3 Fe 5 O 12 , GdFeO 3 , Gd 3 Fe 5 O 12 , DyFeO 3 , Dy 3 Fe 5 O 12 , HoFeO 3 , Ho 3 Fe 5 O 12 , ErFeO 3 , Er 3 Fe 5 O 12 , Tm 3 Fe 5 O 12 , LuFeO 3 , Lu 3 Fe 5 O 12 , NiTiO 3 , Al 2 TiO 3 , FeTiO 3 , BaZrO 3, LiZrO 3, MgZrO 3, HfTiO 4, NH 4 VO 3, AgVO 3, LiVO 3, BaNb 2 O 6, NaNbO 3, SrNb 2 O 6, KTaO 3, NaTaO 3, SrTa 2 O 6, CuCr 2 O 4 , Ag 2 CrO 4 , BaCrO 4 , K 2 MoO 4 , Na 2 MoO 4 , NiMoO 4 , BaWO 4 , Na 2 WO 4 , SrWO 4 , MnCr 2 O 4 , MnFe 2 O 4 , MnTiO 3 , MnWO 4 , CoFe 2 O 4 , ZnFe 2 O 4 , FeWO 4 , CoMoO 4 , CuTiO 3 , CuWO 4 , Ag 2 MoO 4 , Ag 2 WO 4 , ZnAl 2 O 4 , ZnMoO 4 , ZnWO 4 , CdSnO 3 , CdTiO 3 , CdMoO 4 , CdWO 4 , NaAlO 2 , MgAl 2 O 4 , SrAl 2 O 4 , Gd 3 Ga 5 O 12 , InFeO 3 , MgIn 2 O 4 , Al 2 TiO 5 , FeTiO 3 , MgTiO 3 , Na 2 SiO 3 , CaSiO 3 , ZrSiO 4 , K 2 GeO 3 , Li 2 GeO 3 , Na 2 GeO 3 , Bi 2 Sn 3 O 9 , MgSnO 3 , SrSn O 3 , PbSiO 3 , PbMoO 4 , PbTiO 3 , SnO 2 -Sb 2 O 3 , CuSeO 4 , Na 2 SeO 3 , ZnSeO 3 , K 2 TeO 3 , K 2 TeO 4 , Na 2 TeO 3 , Na 2 TeO 4 Metal composite oxides such as, sulfides such as FeS, Al 2 S 3 , MgS, ZnS, fluorides such as LiF, MgF 2 , SmF 3 , chlorides such as HgCl, FeCl 2 , CrCl 3 , AgBr, CuBr, Even bromides such as MnBr 2 , iodides such as PbI 2 , CuI, and FeI 2 , or metal oxynitrides such as SiAlON are also effective. In the bottom contact structure, the gate insulating film may be formed by anodizing the gate electrode. For example, simple substances such as Ta, Al, Mg, Ti, Nb, Zr, or alloys thereof are effective. Further, it is also effective for polymer materials such as polyimide, polyamide, polyester, polyacrylate, epoxy resin, phenol resin, and polyvinyl alcohol. Further, the surface of the gate insulating film may be subjected to water repellent treatment using OTS, HMDS, or the like.
また、上記の実施例では、ボトムコンタクト構造を有する有機ＴＦＴに本発明を適用した場合について説明したが、図４に示すトップゲート構造を有する有機ＴＦＴに本発明を適用することも可能である。
In the above embodiments, the case where the present invention is applied to the organic TFT having the bottom contact structure has been described. However, the present invention can also be applied to the organic TFT having the top gate structure shown in FIG.
トップゲート構造とは、図４に示すように、基板１０上にソース／ドレイン電極１５が形成され、有機半導体層１６、ゲート絶縁膜１２を介して最表面にゲート電極１１が形成された構造をいう。すなわち、トップゲート構造の有機ＴＦＴ３は、基板１０上に互いに離間して設けられた一対のソース／ドレイン電極１５と、基板１０上にソース／ドレイン電極１５を覆うように設けられた有機半導体層１６と、有機半導体層１６の上に設けられたゲート絶縁膜１２と、ゲート絶縁膜１２の上に設けられたゲート電極１１と、を含む。ソース／ドレイン電極１５は、基板１０上に延在する例えばニッケルリン（Ｎｉ－Ｐ）からなる第１の電極層１３と、第１の電極層１３上の一部を覆うように設けられた例えばＡｕからなる第２の電極層１４とにより構成される。第２の電極層１４は、例えば有機半導体層１６からの電荷注入が行われる第１の電極層１３の端部に設けられる。
As shown in FIG. 4, the top gate structure is a structure in which a source / drain electrode 15 is formed on a substrate 10, and a gate electrode 11 is formed on the outermost surface via an organic semiconductor layer 16 and a gate insulating film 12. Say. That is, the organic TFT 3 having a top gate structure includes a pair of source / drain electrodes 15 provided on the substrate 10 so as to be separated from each other, and an organic semiconductor layer 16 provided on the substrate 10 so as to cover the source / drain electrodes 15. And a gate insulating film 12 provided on the organic semiconductor layer 16 and a gate electrode 11 provided on the gate insulating film 12. The source / drain electrode 15 is provided so as to cover the first electrode layer 13 made of, for example, nickel phosphorus (Ni—P) extending on the substrate 10 and a part on the first electrode layer 13. The second electrode layer 14 is made of Au. The second electrode layer 14 is provided at the end of the first electrode layer 13 where charge injection from the organic semiconductor layer 16 is performed, for example.
１０ 基板
１１ ゲート電極
１２ ゲート絶縁膜
１３ 第１の電極層
１４ 第２の電極層
１５ ソース／ドレイン電極
１６ 有機半導体層
１７ チャネル領域 DESCRIPTION OFSYMBOLS 10 Substrate 11 Gate electrode 12 Gate insulating film 13 1st electrode layer 14 2nd electrode layer 15 Source / drain electrode 16 Organic-semiconductor layer 17 Channel area | region
１１ ゲート電極
１２ ゲート絶縁膜
１３ 第１の電極層
１４ 第２の電極層
１５ ソース／ドレイン電極
１６ 有機半導体層
１７ チャネル領域 DESCRIPTION OF
Claims (15)
- ゲート絶縁膜を介してゲート電極と対向する位置に配された一対のソース／ドレイン電極と、前記一対のソース／ドレイン電極と接する有機半導体層と、を有する有機薄膜トランジスタを含む半導体装置であって、
前記ソース／ドレイン電極は、前記有機半導体層と接する部分を含む一部にのみ無電解めっきにより形成されためっき処理部を有することを特徴とする半導体装置。 A semiconductor device including an organic thin film transistor having a pair of source / drain electrodes disposed at positions facing a gate electrode through a gate insulating film, and an organic semiconductor layer in contact with the pair of source / drain electrodes,
The semiconductor device according to claim 1, wherein the source / drain electrode has a plating treatment part formed by electroless plating only at a part including a portion in contact with the organic semiconductor layer. - 基板上に形成された前記ゲート電極と、
前記ゲート電極を覆うように形成された前記ゲート絶縁膜と、
前記ゲート絶縁膜を介して前記ゲート電極の上部から前記基板上まで延在し、且つ前記ゲート電極の上部において離間部を有する前記一対のソース／ドレイン電極と、
前記離間部において露出している前記ゲート絶縁膜および前記一対のソース／ドレイン電極と接するように設けられた前記有機半導体層と、を含み、
前記ソース／ドレイン電極は、前記ゲート電極上部から前記基板上部まで延在している第１の電極層と、前記第１の電極層の端部に設けられた前記めっき処理部に相当する第２の電極層と、を含むことを特徴とする請求項１に記載の半導体装置。 The gate electrode formed on the substrate;
The gate insulating film formed to cover the gate electrode;
A pair of source / drain electrodes extending from the upper part of the gate electrode to the substrate via the gate insulating film and having a separation portion on the upper part of the gate electrode;
The organic semiconductor layer provided so as to be in contact with the gate insulating film and the pair of source / drain electrodes exposed in the separation portion,
The source / drain electrodes include a first electrode layer extending from an upper portion of the gate electrode to an upper portion of the substrate, and a second corresponding to the plating processing portion provided at an end portion of the first electrode layer. The semiconductor device according to claim 1, further comprising: - 基板上に互いに離間して設けられた前記一対のソース／ドレイン電極と、
前記基板上に前記一対のソース／ドレイン電極を覆うように設けられた前記有機半導体層と、
前記有機半導体層の上に設けられた前記ゲート絶縁膜と、
前記ゲート絶縁膜の上に設けられた前記ゲート電極と、を含み、
前記ソース／ドレイン電極は、前記基板上に延在する第１の電極層と、前記第１の電極層上の端部に設けられた前記めっき処理部に相当する第２の電極層と、を含むことを特徴とする請求項１に記載の半導体装置。 A pair of source / drain electrodes provided apart from each other on a substrate;
The organic semiconductor layer provided on the substrate so as to cover the pair of source / drain electrodes;
The gate insulating film provided on the organic semiconductor layer;
The gate electrode provided on the gate insulating film,
The source / drain electrodes include: a first electrode layer extending on the substrate; and a second electrode layer corresponding to the plating portion provided at an end on the first electrode layer. The semiconductor device according to claim 1, further comprising: - 前記第２の電極層は、前記有機半導体層のチャネル領域と接する部分を含んでいることを特徴とする請求項２又は３に記載の半導体装置。 4. The semiconductor device according to claim 2, wherein the second electrode layer includes a portion in contact with a channel region of the organic semiconductor layer.
- 前記第２の電極層と前記有機半導体層との接触は、オーミック性接触であることを特徴とする請求項２乃至４のいずれか１つに記載の半導体装置。 5. The semiconductor device according to claim 2, wherein the contact between the second electrode layer and the organic semiconductor layer is an ohmic contact.
- 前記第２の電極層は、置換めっき法によって形成されることを特徴とする請求項２乃至５のいずれか１つに記載の半導体装置。 The semiconductor device according to claim 2, wherein the second electrode layer is formed by a displacement plating method.
- 前記第２の電極層は、置換めっき法および還元めっき法を併用して形成されることを特徴とする請求項２乃至５のいずれか１つに記載の半導体装置。 6. The semiconductor device according to claim 2, wherein the second electrode layer is formed by using a displacement plating method and a reduction plating method in combination.
- 前記第２の電極層は、前記第１の電極層の構成材料よりもイオン化傾向の小さい材料からなることを特徴とする請求項２乃至７のいずれか１つに記載の半導体装置。 8. The semiconductor device according to claim 2, wherein the second electrode layer is made of a material having a smaller ionization tendency than the constituent material of the first electrode layer.
- 前記第２の電極層は、貴金属または貴金属を含む合金からなることを特徴とする請求項８に記載の半導体装置。 The semiconductor device according to claim 8, wherein the second electrode layer is made of a noble metal or an alloy containing a noble metal.
- 前記第２の電極層は、金または金を含む合金からなることを特徴とする請求項９に記載の半導体装置。 10. The semiconductor device according to claim 9, wherein the second electrode layer is made of gold or an alloy containing gold.
- 有機薄膜トランジスタを含む半導体装置の製造方法であって、
基板上にゲート電極を形成する工程と、
前記ゲート電極を覆うようにゲート絶縁膜を形成する工程と、
前記ゲート電極の上部において離間部を有する一対のソース／ドレイン電極を前記ゲート絶縁膜上に形成する工程と、
前記離間部において露出している前記ゲート絶縁膜および前記一対のソース／ドレイン電極と接するように有機半導体層を形成する工程と、を含み、
前記一対のソース／ドレイン電極を形成する工程は、前記ゲート絶縁膜上に前記ゲート電極上部から前記基板上部まで延在している第１の電極層を形成する工程と、前記一対のソース／ドレイン電極が前記有機半導体層と接する部分を含む領域に開口部を有するレジストマスクを前記第１の電極層の上に形成する工程と、前記レジストマスクの開口部において露出した前記第１の電極層の一部に無電解めっき法により第２の電極層を形成す工程と、を含むことを特徴とする半導体装置の製造方法。 A method of manufacturing a semiconductor device including an organic thin film transistor,
Forming a gate electrode on the substrate;
Forming a gate insulating film so as to cover the gate electrode;
Forming a pair of source / drain electrodes having a separation portion on the gate electrode on the gate insulating film;
Forming an organic semiconductor layer so as to be in contact with the gate insulating film and the pair of source / drain electrodes exposed in the spaced-apart portion,
The step of forming the pair of source / drain electrodes includes the step of forming a first electrode layer extending from the upper part of the gate electrode to the upper part of the substrate on the gate insulating film, and the pair of source / drain electrodes. Forming a resist mask having an opening in a region including a portion where the electrode is in contact with the organic semiconductor layer on the first electrode layer; and exposing the first electrode layer exposed in the opening of the resist mask. Forming a second electrode layer in part by an electroless plating method. A method for manufacturing a semiconductor device, comprising: - 前記第２電極層を形成する工程は、置換めっき工程を含むことを特徴とする請求項１１に記載の半導体装置の製造方法。 12. The method of manufacturing a semiconductor device according to claim 11, wherein the step of forming the second electrode layer includes a displacement plating step.
- 前記第２電極層を形成する工程は、置換めっき工程および還元めっき工程を含むことを特徴とする請求項１１に記載の半導体装置の製造方法。 12. The method of manufacturing a semiconductor device according to claim 11, wherein the step of forming the second electrode layer includes a displacement plating step and a reduction plating step.
- 前記第２の電極層は、前記第１の電極層の構成材料よりもイオン化傾向の小さい材料からなることを特徴とする請求項１２又は１３に記載の半導体装置の製造方法。 14. The method of manufacturing a semiconductor device according to claim 12, wherein the second electrode layer is made of a material having a smaller ionization tendency than the constituent material of the first electrode layer.
- 前記第２の電極層は、貴金属または貴金属を含む合金からなることを特徴とする請求項１４に記載の半導体装置の製造方法。 15. The method of manufacturing a semiconductor device according to claim 14, wherein the second electrode layer is made of a noble metal or an alloy containing a noble metal.
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