WO2010125607A1 - Radiation detector and method of manufacturing same - Google Patents

Radiation detector and method of manufacturing same Download PDF

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Publication number
WO2010125607A1
WO2010125607A1 PCT/JP2009/001957 JP2009001957W WO2010125607A1 WO 2010125607 A1 WO2010125607 A1 WO 2010125607A1 JP 2009001957 W JP2009001957 W JP 2009001957W WO 2010125607 A1 WO2010125607 A1 WO 2010125607A1
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WIPO (PCT)
Prior art keywords
cable
conductor
common electrode
semiconductor
radiation detector
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PCT/JP2009/001957
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French (fr)
Japanese (ja)
Inventor
鈴木準一
吉牟田利典
古井真悟
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株式会社島津製作所
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Priority to PCT/JP2009/001957 priority Critical patent/WO2010125607A1/en
Publication of WO2010125607A1 publication Critical patent/WO2010125607A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/02002Arrangements for conducting electric current to or from the device in operations
    • H01L31/02005Arrangements for conducting electric current to or from the device in operations for device characterised by at least one potential jump barrier or surface barrier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/085Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors the device being sensitive to very short wavelength, e.g. X-ray, Gamma-rays

Definitions

  • the present invention relates to a radiation detector that includes a radiation-sensitive semiconductor that generates a charge upon incidence of radiation and is used in the medical field, the industrial field, and the nuclear field, and a manufacturing method thereof.
  • this type of radiation eg, X-ray detector indirectly converts radiation into charge by generating light once by the incidence of radiation (eg, X-ray) and generating charge from the light.
  • Indirect conversion type detectors that detect radiation
  • “direct conversion type” detectors that detect radiation by directly converting radiation into electric charge by generating charges by the incidence of radiation. is there. Note that a radiation-sensitive semiconductor generates a charge.
  • the direct conversion type radiation detector includes an active matrix substrate 51, a radiation-sensitive semiconductor 52 that generates a charge by the incidence of radiation, and a common electrode 53 for applying a bias voltage.
  • the active matrix substrate 51 is configured by forming a plurality of collection electrodes (not shown) on the radiation incident surface side and disposing an electric circuit (not shown) for accumulating / reading charges collected by each collection electrode. ing. Each collection electrode is set in a two-dimensional matrix arrangement within the radiation detection effective area SA.
  • the semiconductor 52 is stacked on the incident surface side of the collecting electrode of the active matrix substrate 51, and the common electrode 53 is formed in a planar shape on the incident side of the semiconductor 52 and stacked.
  • a lead wire 54 for supplying bias voltage is connected to the incident surface of the common electrode 53.
  • a bias voltage is applied from a bias supply power source (not shown) to a bias voltage applying common electrode 53 via a lead wire 54 for supplying a bias voltage.
  • a bias voltage is applied from a bias supply power source (not shown) to a bias voltage applying common electrode 53 via a lead wire 54 for supplying a bias voltage.
  • electric charges are generated by the radiation-sensitive semiconductor 52 with the incidence of radiation. This generated charge is once collected by the collecting electrode.
  • the collected charge is taken out as a radiation detection signal for each collecting electrode by an electric circuit for accumulation / reading composed of a capacitor, a switching element, electric wiring, and the like.
  • Each collection electrode of the two-dimensional matrix array corresponds to an electrode (pixel electrode) corresponding to each pixel of the radiation image.
  • the semiconductor 52 is formed using amorphous selenium
  • the common electrode 53 is formed on the incident side of the semiconductor 52, and a bias voltage is applied to the common electrode 53.
  • the semiconductor 52 is operated with high sensitivity.
  • a bias voltage a high voltage of about 10 kV or more is conventionally used.
  • the semiconductor 52 is laminated on the active matrix substrate 51 as described above. The distance between the ground line and other patterns on the substrate 51 is reduced.
  • a high voltage of about 10 kV or more is used as the bias voltage, and creeping discharge occurs when the distance between the common electrode 53 and the pattern is reduced.
  • the common electrode 53 is formed inside the semiconductor 52 as shown in FIG. 20 so that the edge of the common electrode 53 has a certain distance from the edge of the semiconductor 52. Each is formed to keep.
  • the cable used as the lead wire 54 for supplying the bias voltage not only needs to withstand a high voltage, but also an insulator covering the cable. It is necessary to perform wiring so that (that is, the covering portion of the cable) reaches the common electrode 53.
  • a cable having as thin a coating as possible is necessary, but the diameter of such a high voltage cable needs to be at least about 2 mm.
  • the thickness of the structure covered with the resin is set to 2 mm or more.
  • the active matrix substrate 51 is changed when the temperature is changed due to the difference in linear expansion coefficient between the upper cover glass (insulating auxiliary plate), the active matrix substrate 51, the semiconductor 52, and the resin covering the semiconductor 52.
  • a strong force acts between the semiconductor 52 and the semiconductor 52, and the semiconductor 52 may be peeled off from the active matrix substrate 51 in some cases.
  • the thickness is about 2 mm, so that the performance of the detector is deteriorated. Therefore, by reducing the thickness of the X-ray irradiation part to about 1 mm and connecting the common electrode 53 to the lead wire (cable) 54 for supplying the bias voltage to about 2 mm, the detector performance is lowered. Although it can be avoided, there is a disadvantage that the structure becomes complicated in that case.
  • the cable is formed of a hard material such as a fluororesin, and connecting a long cable to the common electrode 53 as it is is when a large mechanical stress is applied.
  • a hard material such as a fluororesin
  • the present invention has been made in view of such circumstances, and provides a radiation detector capable of easily performing connection work and avoiding damage and stress to a semiconductor and a common electrode, and a method of manufacturing the same.
  • the purpose is to do.
  • the radiation detector according to the present invention is a radiation detector that detects radiation, and includes a radiation-sensitive semiconductor that generates an electric charge upon incidence of radiation, and a bias formed in a planar shape on the incident side of the semiconductor.
  • the cable for supplying the bias voltage is not directly connected to the common electrode for applying the bias voltage, but the common electrode and the conductor are connected, and the conductor and the cable are connected at a place other than the semiconductor.
  • the cable and the common electrode are indirectly connected through the conductor. Since the conductor is made thinner in the thickness direction than the cable, it is connected to the common electrode with a conductor thinner in the thickness direction than the cable, and the semiconductor or common by the insulator covering the cable (that is, the covering portion of the cable) It is possible to avoid occurrence of damage and stress to the electrode. Further, the connection work is facilitated by connecting to the common electrode with a conductor thinner in the thickness direction than the cable. As a result, the connection work is easy to perform, and it is possible to avoid the occurrence of damage and stress on the semiconductor and the common electrode.
  • connection portion between the common electrode, the conductor and the cable is sealed with resin.
  • the common electrode and the connection point between the conductor and cable are stably installed, the mechanical strength of the entire radiation detector is increased, and creeping discharge and corona near the common electrode are further increased. The occurrence of discharge can be prevented.
  • the radiation detectors of these inventions described above may include a structure surrounding the semiconductor from its periphery, and the conductor and the cable may be connected at the position of the structure. Further, a structure surrounding the semiconductor from its periphery may be provided, and the conductor and the cable may be connected inside the structure and at a place other than the semiconductor.
  • the former invention is useful when there is little spatial space between the structure and the semiconductor. In the case of the latter invention, there is a space between the structure and the semiconductor, which is useful when there is room in the space. Furthermore, in the case of the latter invention, since it is not necessary to connect a conductor and a cable in the location of a structure, it can be set as a simpler structure.
  • an insulator is installed on the lower side of the conductor outside at least the connection point with the common electrode. If an insulator is not installed, there is a possibility that a discharge will occur in at least a conductor outside the connection point with the common electrode. However, if an insulator is installed, the discharge can be prevented.
  • a method of manufacturing a radiation detector according to the present invention is a method of manufacturing a radiation detector for detecting radiation, wherein (A) a conductor formed thinner in the thickness direction than a cable for supplying a bias voltage, and radiation A first connection step of connecting a bias voltage applying common electrode formed in a planar shape on the incident side of the radiation-sensitive semiconductor that generates electric charge upon incidence of (B), at the location other than the semiconductor And a second connecting step for connecting the conductor and the cable.
  • a bias voltage application common electrode formed in a planar shape is connected to the incident side of the sensitive semiconductor.
  • the conductor and the cable are connected at a place other than the semiconductor. Instead of connecting the cable directly to the common electrode, in these connection processes, the common electrode and the conductor are connected, and the conductor and the cable are connected at a place other than the semiconductor, so that the cable and the common electrode are connected via the conductor. And indirectly. Since the conductor is thinner than the cable in the thickness direction, the conductor is thinner in the thickness direction than the cable, and it is connected to the common electrode, making connection work easier, causing damage and stress to the semiconductor and the common electrode. Can be avoided.
  • the above-described method for manufacturing a radiation detector according to the present invention includes a frame mounting step (C). Specifically, in the frame attaching step (C), a frame surrounding the semiconductor from its periphery is attached on a substrate on which a circuit for accumulating and reading out charges is formed. Further, when the frame attachment process of (C) is provided, the conductor and the cable at the location of the structure composed of the frame attached in the frame attachment process of (C) in the second connection process of (B) described above. And may be connected. In the second connection step (B) described above, the conductor and the cable are connected to each other inside the structure including the frame attached in the frame attachment step (C) and at a place other than the semiconductor. Also good.
  • first installation step (D) and the second installation step (E) are provided, specifically, in the first installation step (D), there is no insulator covering the cable, and the conductor of the cable.
  • second installation step (E) an insulator is placed on the above-described substrate below the exposed portion, and in the second installation step (E), at least the conductor outside the connection point with the common electrode is placed.
  • An insulator is installed on the lower side, and in the frame attachment process in (C), a frame is attached on the substrate together with the insulator installed in the first installation process in (D), and in the second installation process in (E), An insulator is installed so as to fit in the groove portion of the frame attached in the frame attachment step (C) and in the connection portion between the conductor and the cable. If an insulator is not installed, there is a possibility that a discharge will occur between the part where there is no insulator covering the cable and the cable conductor is exposed and the circuit pattern formed on the board. The installation can prevent discharge.
  • the installation step (E ′) when the installation step (E ′) is provided, specifically, in the installation step (E ′), at least the lower side of the conductor outside the connection portion with the common electrode among the conductors, and Install insulation underneath the part where there is no insulation covering the cable and the cable conductors are exposed. If no insulator is installed, the conductor is at least outside the connection point with the common electrode, and there is no insulator covering the cable, and the conductor of the cable is exposed on the board. Although there is a possibility of causing a discharge in the circuit pattern, it is possible to prevent the discharge by installing an insulator.
  • the common electrode and the conductor are connected without connecting the bias voltage feeding cable directly to the common electrode for applying the bias voltage, and the part other than the semiconductor is connected.
  • the cable and the common electrode are indirectly connected through the conductor. Since the conductor is thinner than the cable in the thickness direction, the conductor is thinner in the thickness direction than the cable, and it is connected to the common electrode, making connection work easier, causing damage and stress to the semiconductor and the common electrode. Can be avoided.
  • FIG. 1 is a schematic plan view of the direct conversion type flat panel X-ray detector (FPD) according to the first embodiment
  • (b) is a cross-sectional view taken along line AA in (a)
  • (c) ) Is a cross-sectional view taken along the line BB in FIG.
  • It is a block diagram which shows the equivalent circuit of the active matrix board
  • FPD flat panel type X-ray detector
  • 2 is a flowchart showing a flow of a manufacturing method of a series of flat panel X-ray detectors (FPDs) according to the first embodiment.
  • BRIEF DESCRIPTION OF THE DRAWINGS It is the schematic which shows the manufacturing process of the flat panel type X-ray detector (FPD) based on Example 1, 2, (a) is a schematic plan view, (b) is an AA arrow view of (a). It is sectional drawing, (c) is BB arrow sectional drawing of (a). BRIEF DESCRIPTION OF THE DRAWINGS It is the schematic which shows the manufacturing process of the flat panel type X-ray detector (FPD) based on Example 1, (a) is a schematic plan view, (b) is AA arrow sectional drawing of (a). (C) is a cross-sectional view taken along the line BB of (a).
  • BRIEF DESCRIPTION OF THE DRAWINGS It is the schematic which shows the manufacturing process of the flat panel type X-ray detector (FPD) based on Example 1, (a) is a schematic plan view, (b) is AA arrow sectional drawing of (a). (C) is a cross-sectional view taken along the line BB of (a). BRIEF DESCRIPTION OF THE DRAWINGS It is the schematic which shows the manufacturing process of the flat panel type X-ray detector (FPD) based on Example 1, (a) is a schematic plan view, (b) is AA arrow sectional drawing of (a). (C) is a cross-sectional view taken along the line BB of (a).
  • BRIEF DESCRIPTION OF THE DRAWINGS It is the schematic which shows the manufacturing process of the flat panel type X-ray detector (FPD) based on Example 1, (a) is a schematic plan view, (b) is AA arrow sectional drawing of (a). (C) is a cross-sectional view taken along the line BB of (a). BRIEF DESCRIPTION OF THE DRAWINGS It is the schematic which shows the manufacturing process of the flat panel type X-ray detector (FPD) based on Example 1, (a) is a schematic plan view, (b) is AA arrow sectional drawing of (a). (C) is a cross-sectional view taken along the line BB of (a).
  • FIG. 12 is a flowchart showing a flow of a series of flat panel X-ray detector (FPD) manufacturing methods according to the second embodiment.
  • FIG. 5 is a schematic view illustrating a manufacturing process of a flat panel X-ray detector (FPD) according to a second embodiment, (a) is a schematic plan view, and (b) is a cross-sectional view taken along line AA in (a). (C) is a cross-sectional view taken along the line BB of (a).
  • FIG. 5 is a schematic view illustrating a manufacturing process of a flat panel X-ray detector (FPD) according to a second embodiment, (a) is a schematic plan view, and (b) is a cross-sectional view taken along line AA in (a). (C) is a cross-sectional view taken along the line BB of (a).
  • FIG. 5 is a schematic view illustrating a manufacturing process of a flat panel X-ray detector (FPD) according to a second embodiment, (a) is a schematic plan view, and (b) is a cross-sectional view taken along line AA in (a). (C) is a cross-sectional
  • FIG. 5 is a schematic view illustrating a manufacturing process of a flat panel X-ray detector (FPD) according to a second embodiment, (a) is a schematic plan view, and (b) is a cross-sectional view taken along line AA in (a). (C) is a cross-sectional view taken along the line BB of (a).
  • FIG. 5 is a schematic view illustrating a manufacturing process of a flat panel X-ray detector (FPD) according to a second embodiment, (a) is a schematic plan view, and (b) is a cross-sectional view taken along line AA in (a). (C) is a cross-sectional view taken along the line BB of (a).
  • FIG. 1 is a schematic plan view of a direct conversion type flat panel X-ray detector (FPD) according to the third embodiment
  • FPD direct conversion type flat panel X-ray detector
  • FIG. 1 is a schematic plan view of a direct conversion type flat panel X-ray detector (FPD) according to the third embodiment
  • (b) is a cross-sectional view taken along line AA in (a)
  • (c) ) Is a cross-sectional view taken along the line BB in FIG.
  • (a) is a schematic sectional drawing when installing a base
  • (b) is when interposing a copper plate
  • FIG. is a schematic sectional drawing of the conventional radiation detector.
  • FIG. 1A is a schematic plan view of a direct conversion type flat panel X-ray detector (hereinafter abbreviated as “FPD” as appropriate) according to the first embodiment
  • FIG. 1A is a cross-sectional view taken along line AA in FIG. 1A
  • FIG. 1C is a cross-sectional view taken along line BB in FIG. 1A
  • FIG. 2 is a flat panel X-ray detector (FPD).
  • FPD flat panel X-ray detector
  • FIG. 3 is a schematic sectional view of the active matrix substrate of the flat panel X-ray detector (FPD).
  • a flat panel X-ray detector (FPD) will be described as an example of the radiation detector.
  • illustration of an upper cover glass is abbreviate
  • the FPD according to the first embodiment is a radiation that generates charges by the incidence of the active matrix substrate 1 and radiation (X-rays in the first to third embodiments).
  • a sensitive semiconductor 2 and a common electrode 3 for applying a bias voltage are provided.
  • the active matrix substrate 1 has a plurality of collecting electrodes 11 formed on the radiation incident surface side, and an electric circuit 12 for storing and reading out charges collected by the collecting electrodes 11. It is configured.
  • Each collection electrode 11 is set in a two-dimensional matrix arrangement within the radiation detection effective area SA.
  • the active matrix substrate 1 corresponds to a substrate on which a circuit for accumulating and reading out charges is formed in the present invention
  • the radiation sensitive semiconductor 2 is equivalent to the radiation sensitive semiconductor in the present invention, and is used for applying a bias voltage.
  • the electrode 3 corresponds to a common electrode for applying a bias voltage in the present invention.
  • the semiconductor 2 is laminated on the incident surface side of the collecting electrode of the active matrix substrate 1, and the common electrode 3 is formed in a planar shape on the incident side of the semiconductor 2 And laminated.
  • a lead wire 4 for supplying bias voltage is connected to the incident surface of the common electrode 3.
  • the lead wire 4 is formed by a bias voltage feeding cable 4A and a single wire 4B formed thinner in the thickness direction than the cable 4A.
  • the insulator covering the cable 4A at the end (that is, the covering portion of the cable 4A) is peeled off to make only the core wire 4a.
  • the core wire 4a and the single wire 4B of the cable 4A are connected via a conductive paste (for example, silver paste), and the single wire 4B and the common electrode 3 are similarly connected via a conductive paste.
  • a connection location between the single wire 4B and the core wire 4a of the cable 4A is a location other than the semiconductor 2, and is a location of a structure including the frame 6 in the first embodiment.
  • the single wire 4B is adopted as the conductor.
  • the bias voltage supply cable 4A corresponds to the bias voltage supply cable in the present invention
  • the single line 4B corresponds to the conductor in the present invention.
  • the FPD is protected by the upper cover glass 5.
  • a frame 6 surrounding the semiconductor 2 from its periphery is attached on the active matrix substrate 1, and the upper cover glass 5 is supported by the frame 6.
  • the upper cover glass 5 is preferably fixedly formed by a resin film 7 made of a curable synthetic resin so that the upper cover glass 5 covers the semiconductor 2 and the common electrode 3.
  • a resin film 7 made of a curable synthetic resin so that the upper cover glass 5 covers the semiconductor 2 and the common electrode 3.
  • connection portion between the common electrode 3, single wire 4B and the core wire 4a of the cable 4A may be sealed with resin, and at least the connection portion between the common electrode 3, single wire 4B and the core wire 4a of the cable 4A is sealed with resin. If it does, it will not be limited in particular.
  • the frame 6 corresponds to the frame in the present invention.
  • an insulating sheet 8 is provided on the lower side of the single wire 4B outside the connecting portion with the common electrode 3 in the single wire 4B. Further, as shown in FIGS. 1A and 1C, there is no insulator covering the cable 4A and insulation is provided below the portion where the conductor of the cable 4A (here, the core wire 4a) is exposed. A sheet 9 is provided. The insulating sheets 8 and 9 correspond to the insulator in this invention.
  • the active matrix substrate 1 is formed with the collecting electrode 11 as described above, and the storage / reading electric circuit 12 is provided.
  • the electric circuit 12 for accumulation / reading includes a capacitor 12A, a TFT (thin film field effect transistor) 12B as a switching element, a gate line 12a, a data line 12b, and the like, and one capacitor 12A and one for each collecting electrode 11 TFT12B are connected in association with each other.
  • a gate driver 13, a charge / voltage conversion amplifier 14, a multiplexer 15, and an A / D converter 16 are arranged and connected around the storage / reading electric circuit 12 of the active matrix substrate 1.
  • the gate driver 13, the charge / voltage conversion amplifier 14, the multiplexer 15, and the A / D converter 16 are connected to a substrate different from the active matrix substrate 1. Note that some or all of the gate driver 13, the charge-voltage conversion amplifier 14, the multiplexer 15, and the A / D converter 16 may be built in the active matrix substrate 1.
  • a bias voltage is applied from a bias supply power source (not shown) to the common electrode 3 for bias voltage application via a lead wire 4 for supplying bias voltage.
  • the lead wire 4 is formed by the cable 4A and the single wire 4B.
  • the lead wire 4 connects the core wire 4a and the single wire 4B of the cable 4A and connects the single wire 4B and the common electrode 3, so that a bias is supplied.
  • a bias voltage from a power source (not shown) is applied to the common electrode 3 via the cable 4A and the single wire 4B.
  • the bias voltage applied charges are generated in the radiation-sensitive semiconductor 2 with the incidence of radiation (X-rays in Examples 1 to 3).
  • the generated charges are once collected by the collecting electrode 11.
  • the electric charge collected by the storage / readout electric circuit 12 is taken out as a radiation detection signal for each collection electrode 11 (in the first to third embodiments, an X-ray detection signal).
  • the charges collected by the collecting electrode 11 are temporarily accumulated in the capacitor 12A.
  • a read signal is sequentially applied from the gate driver 13 to the gate of each TFT 12B through the gate line 12a.
  • the TFT 12B to which the read signal is given shifts from OFF to ON.
  • the data line 12b connected to the source of the shifted TFT 12B is sequentially switched and connected by the multiplexer 15
  • the charge accumulated in the capacitor 12A is read from the TFT 12B via the data line 12b.
  • the read charge is amplified by the charge / voltage conversion amplifier 14 and sent to the A / D converter 16 as a radiation detection signal (X-ray detection signal in the first to third embodiments) for each collection electrode 11 by the multiplexer 15. To convert from analog value to digital value.
  • an X-ray detection signal is sent to an image processing circuit at a subsequent stage, image processing is performed, and a two-dimensional X-ray fluoroscopic image is output.
  • Each collection electrode 11 in the two-dimensional matrix array corresponds to an electrode (pixel electrode) corresponding to each pixel of the radiation image (here, a two-dimensional X-ray fluoroscopic image).
  • the FPD according to the first embodiment including the second and third embodiments described later detects the two-dimensional intensity distribution of the radiation (X-rays in the first to third embodiments) projected onto the radiation detection effective area SA. It is a two-dimensional array type radiation detector that can be used.
  • FIG. 4 is a flowchart showing a flow of a series of manufacturing methods of a flat panel X-ray detector (FPD) according to the first embodiment
  • FIGS. 5 to 10 illustrate flat panel X-ray detection according to the first embodiment.
  • FIG. 5C is a cross-sectional view taken along the line AA
  • FIGS. 5C to 10C are cross-sectional views taken along the line BB in FIGS. 5A to 10A.
  • the upper cover glass is not shown in FIGS. 5 (a) to 10 (a).
  • Step S1 Installation of Insulating Sheet
  • the semiconductor 2 is laminated on the incident surface side of the collecting electrode of the active matrix substrate 1, and the common electrode 3 is formed in a planar shape on the incident side of the semiconductor 2
  • the insulating sheet 9 is placed on the active matrix substrate 1.
  • This installation place is a place below the portion where there is no insulator covering the cable 4A (see FIGS. 1, 9, and 10) and the conductor (core wire 4a) of the cable 4A is exposed.
  • . 5 and 6 and 3A in FIG. 7 to be described later are common for connecting a single wire 4B (see FIGS. 1, 9, and 10) to be described later and the common electrode 3.
  • This step S1 corresponds to the first installation step (D) in this invention.
  • Step S2 Attachment of Frame
  • a frame 6 surrounding the semiconductor 2 from its periphery is attached on the active matrix substrate 1 together with the insulating sheet 9 installed in Step S1.
  • the frame 6 is provided with a groove 6A at a portion facing the protruding portion 3A, and a cut portion 6B communicated with the groove 6A.
  • the grooves 6A and the cut portions 6B may be provided after the frame 6 is attached on the active matrix substrate 1, or the frame 6 may be attached on the active matrix substrate 1 after being provided in advance.
  • the notch 6B penetrates the frame 6 in the introduction region 6a for introducing the cable 4A (see FIGS.
  • step S2 corresponds to the frame attaching step (C).
  • Step S3 Installation of Insulating Sheet Of the single wire 4B (see FIG. 1, FIG. 9, and FIG. 10), as shown in FIG. 8, insulation is performed on the lower side of the single wire 4B outside the connection point with the common electrode 3.
  • the seat 8 is installed. Specifically, the insulating sheet is fitted so as to fit in the groove 6A of the frame 6 attached in step S2 and in the connection portion between the single wire 4B and the core wire 4a of the cable 4A (see FIGS. 1, 9, and 10). 8 is installed. In addition, about the installation place of the insulating sheet 8, you may include the connection location of the single wire 4B and the common electrode 3. FIG. However, it is necessary to install so as not to damage the surface of the semiconductor 2 and the common electrode 3.
  • the insulating sheet 8 may be installed below the single wire 4B at the connection point with the common electrode 3, and at least the single wire 4B below the single wire 4B outside the connection point with the common electrode 3. If the insulating sheet 8 is installed, it will not be specifically limited.
  • This step S3 corresponds to the second installation step (E).
  • Step S4 Installation of Cable / Single Wire
  • the cable 4A and the core wire 4a are inserted into the cut portion 6B of the frame 6 (see FIG. 7A) so that the cable is placed on the insulating sheet 9.
  • 4A and the core wire 4a are installed. And it installs so that the front-end
  • the single wire 4B is installed on the insulating sheet 8, the single wire 4B and the common electrode 3 are connected via a conductive paste, and the single wire 4B and the core wire 4a of the cable 4A are connected via a conductive paste.
  • the connecting portion between the single wire 4B and the common electrode 3 is formed on a pattern protruding slightly from the common electrode 3, but this is for easy understanding of the connecting portion, and there is no protruding pattern. Even if it is 3, there is no problem if it is directly connected to the inside of the common electrode 3. Since the upper cover glass 5 (see FIG. 10) is not installed at the time of this step S4, the cables 4A and single wires 4B can be easily installed from above. In addition, at the time before step S4, the single wire 4B and the core wire 4a of the cable 4A are connected by soldering in another place in advance, and the connected single wire 4B and the core wire 4a of the cable 4A are connected to the frame 6.
  • the single wire 4B and the common electrode 3 may be connected after the cable 4A and the single wire 4B are installed on the insulating sheets 8 and 9 by being inserted into the cut portion 6B.
  • This step S4 corresponds to the first connection step (A) and corresponds to the second connection step (B).
  • Step S5 Installation of Upper Cover Glass After installing the cables 4A and single wires 4B in step S4 and connecting them with conductive paste, the upper cover glass 5 is installed on the upper part of the frame 6 as shown in FIG. .
  • Step S6 Resin Encapsulation
  • a liquid room temperature curable resin composition is injected and cured between the active matrix substrate 1 and the upper cover glass 5 so that the room temperature curable resin composition after curing becomes a resin 7.
  • the upper cover glass 5 is fixedly formed by a resin 7 made of a curable synthetic resin.
  • the curable synthetic resin for example, a room temperature curable epoxy resin is used as an appropriate resin material.
  • a glass substrate is used for the active matrix substrate 1, and a Pyrex (registered trademark), a Tempax (registered trademark) glass substrate, or a quartz glass substrate is used for the upper cover glass 5, for example.
  • the thickness of the glass substrate of the active matrix substrate 1 and the glass substrate of the upper cover glass 5 is, for example, about 0.5 mm to 1.5 mm.
  • the thickness of the semiconductor 2 is normally a thick film of about 0.5 mm to 1.5 mm, and the area is, for example, about 20 cm to 50 cm long ⁇ 20 cm to 50 cm wide.
  • a polyimide film of about 0.1 mm to 0.6 mm, preferably 0.2 mm thick is used.
  • the radiation-sensitive semiconductor 2 includes high-purity amorphous selenium (a-Se), alkali metals such as Na, halogens such as Cl, selenium doped with As or Te, and amorphous semiconductors of selenium compounds, CdTe, CdZnTe, PbI 2 , It is preferably one of non-selenium-based polycrystalline semiconductors such as HgI 2 and TlBr.
  • Amorphous selenium, amorphous semiconductors of selenium and selenium compounds doped with alkali metal, halogen or As or Te, and non-selenium-based polycrystalline semiconductors are excellent in suitability for large area and thick film.
  • a-Se having a specific resistance of 10 9 ⁇ or more, preferably 10 11 ⁇ or more is used for the semiconductor 2, the suitability for increasing the area and the suitability for increasing the film thickness are remarkably excellent.
  • the incident surface upper surface in FIG. 1B
  • the surface opposite to the incident side lower surface in FIG. 1B
  • both surfaces The combination with the intermediate layer which is the formed carrier selective high resistance semiconductor layer is also included.
  • an intermediate layer 2a is formed between the semiconductor 2 and the common electrode 3
  • an intermediate layer 2b is formed between the semiconductor 2 and the collecting electrode 11 (see FIG. 3).
  • the intermediate layer 2a may be formed only between the semiconductor 2 and the common electrode 3, or as shown in FIG.
  • the intermediate layer 2b may be formed only between the collecting electrode 11 (see FIG. 3).
  • the dark current can be reduced by providing the carrier selective intermediate layers 2a and 2b.
  • the carrier selectivity mentioned here refers to the property that the contribution rate to the charge transfer action is remarkably different between electrons and holes which are charge transfer media (carriers) in the semiconductor.
  • the following modes are exemplified.
  • a positive bias voltage is applied to the common electrode 3
  • a material having a large contribution ratio of electrons is used for the intermediate layer 2a.
  • the injection of holes from the common electrode 3 is blocked, and the dark current can be reduced.
  • a material having a large contribution ratio of holes is used for the intermediate layer 2b.
  • the injection of electrons from the collecting electrode 11 is blocked, and the dark current can be reduced.
  • the thickness of the carrier selective intermediate layers 2a and 2b is usually preferably in the range of 0.1 ⁇ m to 10 ⁇ m. If the thickness of the intermediate layers 2a and 2b is less than 0.1 ⁇ m, there is a tendency that the dark current cannot be sufficiently suppressed, and conversely, if the thickness exceeds 10 ⁇ m, radiation detection tends to be hindered (for example, the sensitivity tends to decrease). Appears.
  • semiconductors used for the carrier selective intermediate layers 2a and 2b include polycrystalline semiconductors such as Sb 2 S 3 , ZnTe, CeO 2 , CdS, ZnSe, and ZnS, alkali metals such as Na, halogens such as Cl, Selenium doped with As or Te and an amorphous semiconductor of a selenium compound may be mentioned as having excellent suitability for large area.
  • those having a large contribution of electrons include polycrystalline semiconductors such as CeO 2 , CdS, CdSe, ZnSe, and ZnS that are n-type semiconductors, alkali metals, As, and Te.
  • An amorphous body such as amorphous Se that has been doped to reduce the contribution ratio of holes can be used.
  • examples of the material having a large contribution of holes include a polycrystalline semiconductor such as ZnTe which is a p-type semiconductor, and an amorphous material such as amorphous Se doped with halogen to reduce the contribution of electrons.
  • the film can be selectively formed by adjusting the film forming conditions, regardless of whether the contribution of electrons is large or the contribution of holes is large.
  • the cable 4A for supplying the bias voltage is not directly connected to the common electrode 3 for applying the bias voltage.
  • the cable 4A is connected to the cable 4A via the conductor (single wire 4B).
  • the common electrode 3 is indirectly connected. Since the conductor (single wire 4B) is formed thinner than the cable 4A in the thickness direction, the conductor (single wire 4B) thinner than the cable 4A is connected to the common electrode 3, and the insulation covering the cable 4A.
  • connection portion between the common electrode 3 and the conductor (single wire 4B in the first embodiment) and the cable 4A is sealed with resin.
  • the connection portion between the common electrode 3 and the conductor (single wire 4B) and the cable 4A is stably installed, the mechanical strength of the entire FPD is increased, and further, in the vicinity of the common electrode 3 It is possible to prevent the occurrence of creeping discharge and corona discharge.
  • the FPD according to the first embodiment includes a structure (frame 6) surrounding the semiconductor 2 from the periphery thereof, and a conductor (a groove 6A of the frame 6 in the first embodiment) is a conductor (in the first embodiment, in the first embodiment).
  • the single wire 4B) and the cable 4A are connected. In the case of the first embodiment, it is useful when there is little spatial space between the structure (frame 6) and the semiconductor 2.
  • an insulator (the main wire 4B in the first embodiment) is provided below the conductor (single wire 4B) outside the connection portion with the common electrode 3 at least.
  • Example 1 it has the structure which installs the insulating sheet 8). If an insulator (insulating sheet 8) is not installed, there is a possibility that a discharge will occur in at least the conductor (single wire 4B) outside the connecting portion with the common electrode 3 among the conductors (single wire 4B). Discharging can be prevented by installing (insulating sheet 8).
  • step S4 the conductor (single wire 4B in the first embodiment) formed thinner in the thickness direction than the bias voltage feeding cable 4A and the radiation ( In the first embodiment, a bias voltage application common electrode 3 formed in a planar shape is connected to the incident side of the radiation-sensitive semiconductor 2 that generates charges by the incidence of X-rays).
  • the conductor (single wire 4B) and the core wire 4a of the cable 4A are connected at locations other than the semiconductor 2.
  • the cable 4A is not directly connected to the common electrode 3, but the common electrode 3 and the conductor (single wire 4B) are connected in step S4, and the conductor (single wire 4B) and the core wire 4a of the cable 4A are connected at a place other than the semiconductor 2.
  • the cable 4A and the common electrode 3 are indirectly connected via a conductor (single wire 4B). Since the conductor (single wire 4B) is formed thinner in the thickness direction than the cable 4A, it is connected to the common electrode 3 with a conductor (single wire 4B) thinner in the thickness direction than the cable 4A. It is possible to avoid the occurrence of damage and stress on the semiconductor 2 and the common electrode 3.
  • step S2 the semiconductor 2 is formed on the active matrix substrate 1 on which a circuit for accumulating and reading electric charges (accumulation / readout electric circuit 12 in the first embodiment) is formed.
  • a frame 6 surrounding the periphery is attached.
  • the conductor (the first embodiment 1) is provided at the position of the structure including the frame 6 attached in step S2 (the groove 6A of the frame 6 in the first embodiment). Then, the single wire 4B) and the core wire 4a of the cable 4A are connected.
  • step S1 there is no insulator (the main wire 4a in this case) without an insulator covering the cable 4A and the conductor (the core wire 4a in this case) is exposed.
  • the insulating sheet 9) is installed on the active matrix substrate 1, and in step S3, the conductor (single wire 4B in the first embodiment) is at least a conductor (single wire) outside the connecting portion with the common electrode 3. 4B)
  • An insulator in this embodiment, the insulating sheet 8) is installed on the lower side.
  • step S2 the frame 6 is attached on the active matrix substrate 1 together with the insulator (insulating sheet 9) installed in step S1, and in step S3, the groove 6A of the frame 6 attached in step S2 is used.
  • An insulator (insulating sheet 8) is installed so as to fit in a connecting portion between the (single wire 4B) and the core wire 4a of the cable 4A. If an insulator (insulating sheet 9) is not installed, there is no insulator covering the cable 4A and the conductor (core wire 4a) of the cable 4A is exposed, and a circuit pattern formed on the active matrix substrate 1 However, it is possible to prevent discharge by installing an insulator (insulating sheet 9).
  • the conductor (single wire 4B) is at least a conductor (single wire) outside the connection portion with the common electrode 3 at least. 4B) and a circuit pattern formed on the active matrix substrate 1 may cause a discharge, but the discharge can be prevented by installing an insulator (insulating sheet 8).
  • FIG. 12A is a schematic plan view of a direct conversion flat panel X-ray detector (FPD) according to the second embodiment
  • FIG. 12B is an AA arrow in FIG.
  • FIG. 12C is a cross-sectional view taken along the line BB in FIG. 12A.
  • the portions common to the above-described first embodiment are denoted by the same reference numerals, the description thereof is omitted, and the illustration is omitted. Further, similarly to FIG. 1A, the illustration of the upper cover glass is omitted in FIG.
  • the single wire 4B is adopted as the conductor formed thinner in the thickness direction than the cable 4A.
  • the FPD according to the second embodiment is used.
  • a ribbon-like metal plate 4C is adopted as a conductor formed thinner in the thickness direction than the cable 4A. That is, as shown in FIG. 12A, the lead wire 4 is formed of a cable 4A and a ribbon-like metal plate 4C formed thinner in the thickness direction than the cable 4A.
  • the core 4a of the cable 4A and the ribbon-like metal plate 4C are connected via a conductive paste (for example, Ni-based conductive paste), and the ribbon-like metal plate 4C is also connected via the conductive paste.
  • a conductive paste for example, Ni-based conductive paste
  • the connection place between the ribbon-like metal plate 4C and the core wire 4a of the cable 4A is a place other than the semiconductor 2.
  • the conductor is plate-like like the ribbon-like metal plate 4C, the area to be connected is larger than that of the single wire 4B of Example 1, the conduction resistance is low, and the FPD can be manufactured stably.
  • Ribbon-shaped metal plate 4C corresponds to the conductor in the present invention.
  • the FPD according to the first embodiment described above there is no insulator covering the cable 4A, and the conductor of the cable 4A (here, the core wire 4a) is exposed.
  • An insulating material (insulating sheet 9 in the first embodiment) is placed on the active matrix substrate 1 below the portion where it is present, and at least outside of the conductor (single wire 4B in the first embodiment) connected to the common electrode 3.
  • an insulator (insulating sheet 8 in Example 1) was installed under the conductor (single wire 4B)
  • the FPD according to Example 2 has a conductor (ribbon in Example 2) as shown in FIG.
  • insulating sheet 8 ' The lower part are being installed insulating sheet 8 '. That is, in the above-described first embodiment, the two insulating sheets 8 and 9 are installed according to the size of the single wire 4B and the core wire 4a of the cable 4A, whereas in the second embodiment, one insulating sheet is provided. 8 'is simplified compared to the structure of the first embodiment.
  • a step 6C is provided on the frame 6 as shown in FIGS. 12A and 12C, and the above-described insulating sheet 8 ′ is installed along the step 6C.
  • the insulating sheet 8 ′ corresponds to an insulator in the present invention.
  • FIG. 5 is a schematic view showing a manufacturing process of a flat panel X-ray detector (FPD) according to the second embodiment.
  • FIG. 5 is shared with the first and second embodiments.
  • FIG. 13 is a flowchart showing the flow of a series of manufacturing methods of a flat panel X-ray detector (FPD) according to the second embodiment, and FIGS. 14 to 17 show the flat panel X-ray detection according to the second embodiment.
  • It is the schematic which shows the manufacturing process of a container (FPD).
  • FIGS. 14 (a) to 17 (a) are schematic plan views, and FIGS. 14 (b) to 17 (b) are the same as FIGS.
  • FIGS. 14 (c) to 17 (c) are cross-sectional views taken along the line BB in FIGS. 14 (a) to 17 (a).
  • the illustration of the upper cover glass is omitted in FIGS. 14A to 17A.
  • Step T2 Attaching the Frame
  • the semiconductor 2 is laminated on the incident surface side of the collecting electrode of the active matrix substrate 1, and the common electrode 3 is formed in a planar shape on the incident side of the semiconductor 2 and laminated.
  • a frame 6 surrounding the semiconductor 2 from its periphery is attached on the active matrix substrate 1 as shown in FIG.
  • the frame 6 is provided with a step 6C as shown in FIGS. 14 (a) to 14 (c).
  • the step 6C may be provided after the frame 6 is mounted on the active matrix substrate 1, or the frame 6 may be mounted on the active matrix substrate 1 after being provided in advance.
  • This step T2 corresponds to the frame attaching step (C).
  • Step T3 Installation of Insulating Sheet Of the ribbon-like metal plate 4C (see FIGS. 12, 16, and 17), as shown in FIG. 15, the ribbon-like metal plate outside the connection location with the common electrode 3 Insulating sheet 8 below 4C and below the portion where cable 4A (see FIGS. 12, 16, and 17) does not have an insulator to cover and conductor 4 (core wire 4a) of cable 4A is exposed Install ⁇ .
  • the insulating sheet 8 ′ is installed along the step 6C of the frame 6 attached in Step T3.
  • the connection location of the metal plate 4C and the common electrode 3 was included in FIG.16 (b) and FIG.17 (b)
  • the metal plate 4C and the common electrode 3 are included.
  • the insulating sheet 8 ′ may be installed below the metal plate 4 ⁇ / b> C at the connection location with the common electrode 3. Of the metal plates 4 ⁇ / b> C, the metal plate 4 ⁇ / b> C outside the connection location with at least the common electrode 3. If insulating sheet 8 'is installed in the lower side, it will not be specifically limited.
  • This step T3 corresponds to the installation step (E ′).
  • Step T4 Installation of Cable / Metal Plate
  • the cable 4A and the core wire 4a are installed on the insulating sheet 8 ′ installed in step T3, and the ribbon-shaped metal plate 4C is installed.
  • the metal plate 4C and the common electrode 3 are connected by bonding with a conductive paste interposed therebetween, and the core wire 4a is inserted under the metal plate 4C to be connected through the conductive paste. Since the upper cover glass 5 (see FIG. 17) is not installed at the time of step T4, the cable 4A and the metal plate 4C can be easily installed from above.
  • step T4 corresponds to the first connection step (A) and corresponds to the second connection step (B).
  • Step T5 Installation of Upper Cover Glass After the cable 4A and the metal plate 4C are installed in Step T4, the upper cover glass 5 is installed on the upper portion of the frame 6 as shown in FIG.
  • Step T6 Resin Encapsulation A liquid room temperature curable resin composition is injected and cured between the active matrix substrate 1 and the upper cover glass 5, so that the cured room temperature curable resin composition becomes a resin 7.
  • the upper cover glass 5 is fixedly formed by a resin 7 made of a curable synthetic resin.
  • the bias voltage supply cable 4A is connected to the common electrode for applying the bias voltage as in the first embodiment.
  • 3 is connected directly to the common electrode 3 and the conductor (ribbon-shaped metal plate 4C in the present embodiment 2), and the conductor (metal plate 4C) and the core wire 4a of the cable 4A are connected to a portion other than the semiconductor 2 By connecting these, the cable 4A and the common electrode 3 are indirectly connected via a conductor (metal plate 4C).
  • the conductor (metal plate 4C) is formed thinner than the cable 4A in the thickness direction, the conductor (metal plate 4C) is thinner than the cable 4A in the thickness direction and is connected to the common electrode 3, and the connection work is performed. It is easy to avoid the occurrence of damage and stress on the semiconductor 2 and the common electrode 3.
  • connection portion between the common electrode 3 and the conductor (ribbon-shaped metal plate 4C in the second embodiment) and the cable 4A be sealed with resin. Stop. By sealing with the resin in this way, the connection portion between the common electrode 3 and the conductor (metal plate 4C) and the cable 4A is stably installed, the mechanical strength of the entire FPD is increased, and the vicinity of the common electrode 3 is further increased. It is possible to prevent the occurrence of creeping discharge and corona discharge.
  • the semiconductor 2 is placed on the active matrix substrate 1 on which a circuit for accumulating and reading electric charges (the electric circuit 12 for accumulation / readout in the second embodiment) is formed.
  • a frame 6 surrounding from the periphery is attached.
  • the conductor the ribbon-like metal plate 4C in the second embodiment
  • the core wire of the cable 4A at the position of the structure composed of the frame 6 the step 6C of the frame 6 in the second embodiment). 4a is connected.
  • the conductor (ribbon-like metal plate 4C in the second embodiment) at least the conductor (metal plate 4C) outside the connection portion with the common electrode 3 is used. It has a structure in which an insulator (insulating sheet 8 ′ in the present embodiment 2) is installed on the lower side. Discharging can be prevented by installing an insulator (insulating sheet 8 ').
  • step T3 among the conductors (ribbon-like metal plate 4C in the second embodiment), at least the conductor (metal plate 4C) outside the connection portion with the common electrode 3 is used.
  • An insulator (insulating sheet 8 'in the present embodiment 2) is activated on the lower side and below the portion where there is no insulator covering the cable 4A and the conductive wire (core wire 4a) of the cable 4A is exposed. It is installed on the matrix substrate 1. Discharging can be prevented by installing an insulator (insulating sheet 8 ').
  • FIG. 18 is a schematic plan view of a direct conversion type flat panel X-ray detector (FPD) according to the third embodiment
  • FIG. 18B is a cross-sectional view taken along line AA in FIG.
  • FIG. 18C is a cross-sectional view taken along the line BB in FIG.
  • the parts common to the above-described first and second embodiments are denoted by the same reference numerals, description thereof is omitted, and illustration is omitted. Further, similarly to FIG. 1A, the illustration of the upper cover glass is omitted in FIG.
  • the portion of the structure including the frame 6 (the groove 6A of the frame 6 in the first embodiment, the step 6C of the frame 6 in the second embodiment). ),
  • the conductor (single wire 4A in Example 1, ribbon-like metal plate 4C in Example 2) and the core wire 4a of the cable 4A are connected.
  • the conductor and the core wire 4a of the cable 4A are connected to each other inside the structure composed of 6 and at a place other than the semiconductor 2.
  • the same single wire 4B as in the first embodiment is adopted as the conductor.
  • the relay pedestal S is installed between the frame 6 and the semiconductor 2.
  • the same insulating sheet 8 ′ as that of the second embodiment is installed on the relay pedestal S, the cable 4A and the core wire 4a are installed on the insulating sheet 8 ′, and the single wire 4B is installed.
  • the insulating sheets 8 and 9 of Example 1 may be installed, and the cable 4A and the single wire 4B may be installed on each of them.
  • the relay base S is insulative, and a hard resin material (high hardness after curing) such as an epoxy resin, a polyurethane resin, or an acrylic resin is used.
  • the third embodiment it is useful when there is a space between the structure composed of the frame 6 and the semiconductor 2 and there is room in the space. Furthermore, in the case of the third embodiment, since it is not necessary to connect the conductor (single wire 4B in the third embodiment) and the cable 4A at the place of the structure, a simpler structure can be obtained. In the third embodiment, the same single wire 4B as that of the first embodiment is employed as the conductor, but the same ribbon-like metal plate 4C as that of the second embodiment may be employed.
  • the present invention is not limited to the above embodiment, and can be modified as follows.
  • the radiation detector typified by the flat panel X-ray detector is a two-dimensional array type.
  • the collection electrode is a one-dimensional matrix.
  • a one-dimensional array type formed by an array may be used, or a non-array type having only one electrode for extracting a radiation detection signal may be used.
  • the X-ray detector is described as an example of the radiation detector.
  • the radiation detector for example, a gamma ray detector
  • the radiation detector that detects radiation other than the X-ray (for example, gamma ray) is also described. Applicable.
  • the common electrode 3 is formed on the inner side of the semiconductor 2 in order to prevent the creeping discharge.
  • the edge of the common electrode 3 and the semiconductor 2 may be aligned with each other, or the common electrode 3 may be formed outside the semiconductor 2.
  • an insulator (insulating sheets 8 and 9 in Example 1 and insulating sheet 8 'in Examples 2 and 3) was installed to prevent discharge, but no discharge occurred, or In the case where discharge is not considered, it is not always necessary to install an insulator.
  • the single wire 4B is used as the conductor, but the conductor is not necessarily limited to a single wire.
  • a twisted wire such as a cable core wire may be used as the conductor.
  • the order of the first connection step (A) for connecting the conductor and the common electrode and the second connection step (B) for connecting the conductor and the cable at a place other than the semiconductor are not particularly limited.
  • the second connection step (B) may be performed after the first connection step (A), and conversely, the first connection step (A) may be performed after the second connection step (B). Then, the first connection step (A) and the second connection step (B) may be performed in parallel.
  • a frame surrounding the semiconductor from its periphery is attached on the substrate (active matrix substrate 1) on which a circuit for accumulating and reading out charges is formed.
  • a frame may be attached on top.
  • the relay pedestal S shown in Example 3 is not necessarily limited to resin as long as it has insulating properties, and for example, glass or ceramics may be used.
  • the single wire 4B and the common electrode 3 are connected via the conductive paste, but the connection mode between the single wire 4B and the common electrode 3 is not particularly limited.
  • a base S made of a hard resin material (high hardness after curing) such as an epoxy resin, a polyurethane resin, an acrylic resin (the relay base S described in the third embodiment).
  • the common electrode 3 is formed so as to cover at least a part of the pedestal S, and the single wire 4B is included in the incident surface of the common electrode 3 You may form so that it may be connected to the location located in the base S.
  • Ni paste for example, Ni paste.
  • a planar copper plate 4D is interposed, and even if a conductive paste having a high resistance value is used, the connection resistance can be lowered, the same as when using a silver paste.
  • the effect of expanding the selection range of the conductive paste can be achieved. Note that by using a Ni paste having a higher resistance value than that of the silver paste, it is possible to avoid a through discharge of the film due to diffusion into the semiconductor 2 due to the use of silver.

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Abstract

In a radiation detector, a cable (4A) and a common electrode (3) are not directly connected, but indirectly connected to each other through a conductor (here, the single line (4B)) by connecting the common electrode (3) and the single line (4B) formed thinner than the cable (4A) in the thickness direction to each other, and by connecting the single line (4B) and the cable (4A) to each other at a portion other than a semiconductor (2).  Since the single line (4B) is thinner than the cable (4A) in the thickness direction, the single line (4B) thinner than the cable (4A) in the thickness direction is connected to the common electrode (3).  Consequently, the connecting operation can be easily performed, and damage to and stress in the semiconductor (2) and the common electrode (3) can be avoided.

Description

放射線検出器およびその製造方法Radiation detector and manufacturing method thereof
 この発明は、放射線の入射により電荷を生成する放射線感応型の半導体を備えていて、医療分野,工業分野,さらには、原子力分野などに用いられる放射線検出器およびその製造方法に関する。 The present invention relates to a radiation detector that includes a radiation-sensitive semiconductor that generates a charge upon incidence of radiation and is used in the medical field, the industrial field, and the nuclear field, and a manufacturing method thereof.
 従来、この種放射線(例えばX線)検出器には、放射線(例えばX線)の入射により光を一旦生成して、その光から電荷を生成することで、放射線から電荷に間接的に変換して放射線を検出する「間接変換型」の検出器と、放射線の入射により電荷を生成することで、放射線から電荷に直接的に変換して放射線を検出する「直接変換型」の検出器とがある。なお、放射線感応型の半導体が電荷を生成する。 Conventionally, this type of radiation (eg, X-ray) detector indirectly converts radiation into charge by generating light once by the incidence of radiation (eg, X-ray) and generating charge from the light. Indirect conversion type detectors that detect radiation and “direct conversion type” detectors that detect radiation by directly converting radiation into electric charge by generating charges by the incidence of radiation. is there. Note that a radiation-sensitive semiconductor generates a charge.
 直接変換型の放射線検出器は、図20に示すように、アクティブマトリックス基板51と、放射線の入射により電荷を生成する放射線感応型の半導体52と、バイアス電圧印加用の共通電極53とを備えている。アクティブマトリックス基板51は、放射線の入射面側に複数の収集電極(図示省略)を形成し、各収集電極で収集される電荷の蓄積・読み出し用電気回路(図示省略)を配設して構成されている。各収集電極については放射線検出有効エリアSA内で2次元状マトリックス配列で設定している。 As shown in FIG. 20, the direct conversion type radiation detector includes an active matrix substrate 51, a radiation-sensitive semiconductor 52 that generates a charge by the incidence of radiation, and a common electrode 53 for applying a bias voltage. Yes. The active matrix substrate 51 is configured by forming a plurality of collection electrodes (not shown) on the radiation incident surface side and disposing an electric circuit (not shown) for accumulating / reading charges collected by each collection electrode. ing. Each collection electrode is set in a two-dimensional matrix arrangement within the radiation detection effective area SA.
 このアクティブマトリックス基板51の収集電極の入射面側に半導体52を積層し、その半導体52の入射側に共通電極53を面状に形成して積層している。そして、共通電極53の入射面にバイアス電圧給電用のリード線54を接続している。 The semiconductor 52 is stacked on the incident surface side of the collecting electrode of the active matrix substrate 51, and the common electrode 53 is formed in a planar shape on the incident side of the semiconductor 52 and stacked. A lead wire 54 for supplying bias voltage is connected to the incident surface of the common electrode 53.
 放射線検出器によって放射線を検出する際には、バイアス供給電源(図示省略)からバイアス電圧を、バイアス電圧給電用のリード線54を介してバイアス電圧印加用の共通電極53に印加する。バイアス電圧を印加した状態で、放射線の入射に伴って放射線感応型の半導体52で電荷を生成する。この生成された電荷を収集電極で一旦収集する。コンデンサやスイッチング素子および電気配線等からなる蓄積・読み出し用電気回路によって、収集された電荷を各収集電極毎の放射線検出信号として取り出す。 When detecting radiation with a radiation detector, a bias voltage is applied from a bias supply power source (not shown) to a bias voltage applying common electrode 53 via a lead wire 54 for supplying a bias voltage. In a state where a bias voltage is applied, electric charges are generated by the radiation-sensitive semiconductor 52 with the incidence of radiation. This generated charge is once collected by the collecting electrode. The collected charge is taken out as a radiation detection signal for each collecting electrode by an electric circuit for accumulation / reading composed of a capacitor, a switching element, electric wiring, and the like.
 2次元状マトリックス配列の各収集電極は、放射線画像の各画素に対応する電極(画素電極)にそれぞれ対応している。放射線検出信号を取り出すことで、放射線検出有効エリアSAに投影される放射線の2次元強度分布に応じた放射線画像を作成することができる。 Each collection electrode of the two-dimensional matrix array corresponds to an electrode (pixel electrode) corresponding to each pixel of the radiation image. By extracting the radiation detection signal, a radiation image corresponding to the two-dimensional intensity distribution of the radiation projected on the radiation detection effective area SA can be created.
 図20に示す従来の放射線検出器において、半導体52にアモルファスセレンを使用して形成する場合を例に採って説明する。上述したように半導体52の入射側に共通電極53を形成し、その共通電極53にバイアス電圧を印加するが、半導体52が約1.0mm程度の厚膜の場合には、感度良く作動させるためにバイアス電圧として、約10kV以上の高電圧を従来では使用している。また、共通電極53の電極領域を広げてその端が半導体52の端縁部に近づくと、上述したようにアクティブマトリックス基板51上に半導体52を積層形成しているので、共通電極53とアクティブマトリックス基板51上の接地線などのパターンとの間の距離が縮まる。約10kV以上の高電圧をバイアス電圧として使用していて、共通電極53とパターンとの間の距離が縮まることで、沿面放電が生じる。 In the conventional radiation detector shown in FIG. 20, the case where the semiconductor 52 is formed using amorphous selenium will be described as an example. As described above, the common electrode 53 is formed on the incident side of the semiconductor 52, and a bias voltage is applied to the common electrode 53. In the case where the semiconductor 52 is a thick film of about 1.0 mm, the semiconductor 52 is operated with high sensitivity. As a bias voltage, a high voltage of about 10 kV or more is conventionally used. Further, when the electrode region of the common electrode 53 is expanded and its end approaches the edge of the semiconductor 52, the semiconductor 52 is laminated on the active matrix substrate 51 as described above. The distance between the ground line and other patterns on the substrate 51 is reduced. A high voltage of about 10 kV or more is used as the bias voltage, and creeping discharge occurs when the distance between the common electrode 53 and the pattern is reduced.
 そこで、沿面放電等の発生を防ぐために、図20に示すように共通電極53を半導体52よりも内側に形成して、共通電極53の端縁部が半導体52の端縁部からある程度の距離を保つようにそれぞれを形成している。 Therefore, in order to prevent the occurrence of creeping discharge or the like, the common electrode 53 is formed inside the semiconductor 52 as shown in FIG. 20 so that the edge of the common electrode 53 has a certain distance from the edge of the semiconductor 52. Each is formed to keep.
 さらにバイアス電圧を安全に供給して共通電極53に印加するために、バイアス電圧給電用のリード線54として使用されているケーブルは高電圧に耐える必要があるのみならず、ケーブルを被覆する絶縁体(すなわちケーブルの被覆部分)が共通電極53にまで及ぶように配線する必要がある。後述するように樹脂(保護部材)で封止する場合には、できる限り細い被覆を持ったケーブルが必要であるが、このような高耐圧のケーブルの直径は最低でも約2mm必要である。 Further, in order to safely supply a bias voltage and apply it to the common electrode 53, the cable used as the lead wire 54 for supplying the bias voltage not only needs to withstand a high voltage, but also an insulator covering the cable. It is necessary to perform wiring so that (that is, the covering portion of the cable) reaches the common electrode 53. As will be described later, when sealing with resin (protective member), a cable having as thin a coating as possible is necessary, but the diameter of such a high voltage cable needs to be at least about 2 mm.
 一方、半導体52や共通電極53へのX線による損傷や放射線検出器の汚染を防止するために、樹脂(保護部材)で封止する(例えば、特許文献1参照)。このとき、ケーブルが半導体52の上を通る部分については、ケーブルが樹脂よりも上にはみ出ないようにケーブルの直径である2mmの厚みを確保する必要がある。
特開2001-148475号公報(第14-17頁、図9)
On the other hand, in order to prevent damage to the semiconductor 52 and the common electrode 53 due to X-rays and contamination of the radiation detector, sealing is performed with a resin (protective member) (for example, see Patent Document 1). At this time, for the portion where the cable passes over the semiconductor 52, it is necessary to secure a thickness of 2 mm which is the diameter of the cable so that the cable does not protrude above the resin.
JP 2001-148475 A (pages 14-17, FIG. 9)
 したがって、この約2mmの直径のケーブルを半導体52の上に通すためには、樹脂で覆った構造物の厚さを2mm以上にする。しかしながら、この形状では、上部カバーガラス(絶縁性の補助板)、アクティブマトリックス基板51、半導体52および半導体52を覆う樹脂との線膨張係数の差から、温度を変化させた場合にアクティブマトリックス基板51と半導体52との間に強い力が働き、場合によっては半導体52がアクティブマトリックス基板51から剥離するという問題点がある。 Therefore, in order to pass the cable having a diameter of about 2 mm over the semiconductor 52, the thickness of the structure covered with the resin is set to 2 mm or more. However, in this shape, the active matrix substrate 51 is changed when the temperature is changed due to the difference in linear expansion coefficient between the upper cover glass (insulating auxiliary plate), the active matrix substrate 51, the semiconductor 52, and the resin covering the semiconductor 52. There is a problem that a strong force acts between the semiconductor 52 and the semiconductor 52, and the semiconductor 52 may be peeled off from the active matrix substrate 51 in some cases.
 また、この樹脂に、例えばX線透過率が比較的高いエポキシ樹脂を使用した場合においても、2mm程度の厚さになるので、検出器として性能低下を招く。したがって、X線照射箇所を1mm程度の厚さにして、共通電極53とバイアス電圧給電用のリード線(ケーブル)54との接続箇所を2mm程度の厚さにすることで検出器の性能低下を回避することも可能であるが、その場合には構造が複雑になるという欠点がある。 Moreover, even when an epoxy resin having a relatively high X-ray transmittance is used for this resin, for example, the thickness is about 2 mm, so that the performance of the detector is deteriorated. Therefore, by reducing the thickness of the X-ray irradiation part to about 1 mm and connecting the common electrode 53 to the lead wire (cable) 54 for supplying the bias voltage to about 2 mm, the detector performance is lowered. Although it can be avoided, there is a disadvantage that the structure becomes complicated in that case.
 さらに、耐圧性を持たせるためにケーブルは被覆がフッ素樹脂のような硬い素材で形成されており、長いケーブルをそのままに共通電極53に接続することは、機械的に大きなストレスが印加される場合があり、また長いケーブルを扱うので接続作業も行い難い。 Furthermore, in order to provide pressure resistance, the cable is formed of a hard material such as a fluororesin, and connecting a long cable to the common electrode 53 as it is is when a large mechanical stress is applied. In addition, since long cables are used, connection work is difficult.
 この発明は、このような事情に鑑みてなされたものであって、接続作業が行いやすく、半導体や共通電極への損傷の発生や応力を回避することができる放射線検出器およびその製造方法を提供することを目的とする。 The present invention has been made in view of such circumstances, and provides a radiation detector capable of easily performing connection work and avoiding damage and stress to a semiconductor and a common electrode, and a method of manufacturing the same. The purpose is to do.
 この発明は、このような目的を達成するために、次のような構成をとる。
 すなわち、この発明の放射線検出器は、放射線を検出する放射線検出器であって、放射線の入射により電荷を生成する放射線感応型の半導体と、その半導体の前記入射側に面状に形成されたバイアス電圧印加用の共通電極と、バイアス電圧給電用のケーブルと、そのケーブルよりも厚み方向に薄く形成された導体とを備え、前記共通電極と前記導体とを接続し、前記半導体以外の箇所で前記導体と前記ケーブルとを接続することを特徴とするものである。
In order to achieve such an object, the present invention has the following configuration.
That is, the radiation detector according to the present invention is a radiation detector that detects radiation, and includes a radiation-sensitive semiconductor that generates an electric charge upon incidence of radiation, and a bias formed in a planar shape on the incident side of the semiconductor. A common electrode for applying a voltage, a cable for supplying a bias voltage, and a conductor formed thinner in the thickness direction than the cable, connecting the common electrode and the conductor, and at a place other than the semiconductor, A conductor and the cable are connected.
 この発明の放射線検出器によれば、バイアス電圧給電用のケーブルをバイアス電圧印加用の共通電極に直接に接続せずに、共通電極と導体とを接続し、半導体以外の箇所で導体とケーブルとを接続することで、導体を介してケーブルと共通電極とを間接的に接続する。導体はケーブルよりも厚み方向に薄く形成されているので、ケーブルよりも厚み方向に薄い導体で共通電極に接続することになり、ケーブルを被覆する絶縁体(すなわちケーブルの被覆部分)による半導体や共通電極への損傷の発生や応力を回避することができる。また、ケーブルよりも厚み方向に薄い導体で共通電極に接続することで、接続作業が行いやすくなる。その結果、接続作業が行いやすく、半導体や共通電極への損傷の発生や応力を回避することができる。 According to the radiation detector of the present invention, the cable for supplying the bias voltage is not directly connected to the common electrode for applying the bias voltage, but the common electrode and the conductor are connected, and the conductor and the cable are connected at a place other than the semiconductor. By connecting, the cable and the common electrode are indirectly connected through the conductor. Since the conductor is made thinner in the thickness direction than the cable, it is connected to the common electrode with a conductor thinner in the thickness direction than the cable, and the semiconductor or common by the insulator covering the cable (that is, the covering portion of the cable) It is possible to avoid occurrence of damage and stress to the electrode. Further, the connection work is facilitated by connecting to the common electrode with a conductor thinner in the thickness direction than the cable. As a result, the connection work is easy to perform, and it is possible to avoid the occurrence of damage and stress on the semiconductor and the common electrode.
 上述したこの発明の放射線検出器では、少なくとも共通電極、導体とケーブルとの接続箇所を樹脂で封止するのが好ましい。このように樹脂で封止することで、共通電極や、導体とケーブルとの接続箇所を安定して設置し、放射線検出器全体の機械的強度を増し、さらに共通電極近傍での沿面放電やコロナ放電の発生を防止することができる。 In the above-described radiation detector of the present invention, it is preferable that at least the connection portion between the common electrode, the conductor and the cable is sealed with resin. By sealing with resin in this way, the common electrode and the connection point between the conductor and cable are stably installed, the mechanical strength of the entire radiation detector is increased, and creeping discharge and corona near the common electrode are further increased. The occurrence of discharge can be prevented.
 上述したこれらの発明の放射線検出器では、半導体をその周囲から取り囲む構造物を備え、その構造物の箇所で導体とケーブルとを接続してもよい。また、半導体をその周囲から取り囲む構造物を備え、その構造物の内部であって、かつ半導体以外の箇所で導体とケーブルとを接続してもよい。前者の発明の場合には、構造物と半導体との間に空間的なスペースが少ない場合において有用である。後者の発明の場合には、構造物と半導体との間に空間的なスペースがあって、スペースに余裕があるときに有用である。さらに、後者の発明の場合には、構造物の箇所で導体とケーブルとを接続せずに済むので、より簡単な構造とすることができる。 The radiation detectors of these inventions described above may include a structure surrounding the semiconductor from its periphery, and the conductor and the cable may be connected at the position of the structure. Further, a structure surrounding the semiconductor from its periphery may be provided, and the conductor and the cable may be connected inside the structure and at a place other than the semiconductor. The former invention is useful when there is little spatial space between the structure and the semiconductor. In the case of the latter invention, there is a space between the structure and the semiconductor, which is useful when there is room in the space. Furthermore, in the case of the latter invention, since it is not necessary to connect a conductor and a cable in the location of a structure, it can be set as a simpler structure.
 上述したこれらの発明の放射線検出器では、導体のうち、少なくとも共通電極との接続箇所よりも外側の導体の下側に絶縁物を設置する構造を有するのが好ましい。絶縁物を設置しないと、導体のうち、少なくとも共通電極との接続箇所よりも外側の導体で、放電を起こす可能性があるが、絶縁物を設置することで放電を防止することができる。 In the radiation detectors of these inventions described above, it is preferable to have a structure in which an insulator is installed on the lower side of the conductor outside at least the connection point with the common electrode. If an insulator is not installed, there is a possibility that a discharge will occur in at least a conductor outside the connection point with the common electrode. However, if an insulator is installed, the discharge can be prevented.
 また、この発明の放射線検出器の製造方法は、放射線を検出する放射線検出器を製造する方法であって、(A)バイアス電圧給電用のケーブルよりも厚み方向に薄く形成された導体と、放射線の入射により電荷を生成する放射線感応型の半導体の前記入射側に面状に形成されたバイアス電圧印加用の共通電極とを接続する第1接続工程と、(B)前記半導体以外の箇所で前記導体と前記ケーブルとを接続する第2接続工程とを備えることを特徴とするものである。 A method of manufacturing a radiation detector according to the present invention is a method of manufacturing a radiation detector for detecting radiation, wherein (A) a conductor formed thinner in the thickness direction than a cable for supplying a bias voltage, and radiation A first connection step of connecting a bias voltage applying common electrode formed in a planar shape on the incident side of the radiation-sensitive semiconductor that generates electric charge upon incidence of (B), at the location other than the semiconductor And a second connecting step for connecting the conductor and the cable.
 この発明の放射線検出器の製造方法によれば、(A)の第1接続工程では、バイアス電圧給電用のケーブルよりも厚み方向に薄く形成された導体と、放射線の入射により電荷を生成する放射線感応型の半導体の入射側に面状に形成されたバイアス電圧印加用の共通電極とを接続する。一方、(B)の第2接続工程では、半導体以外の箇所で導体とケーブルとを接続する。ケーブルを共通電極に直接に接続せずに、これらの接続工程で、共通電極と導体とを接続し、半導体以外の箇所で導体とケーブルとを接続することで、導体を介してケーブルと共通電極とを間接的に接続する。導体はケーブルよりも厚み方向に薄く形成されているので、ケーブルよりも厚み方向に薄い導体で共通電極に接続することになり、接続作業が行いやすく、半導体や共通電極への損傷の発生や応力を回避することができる。 According to the method for manufacturing a radiation detector of the present invention, in the first connection step (A), the conductor that is formed thinner in the thickness direction than the bias voltage feeding cable and the radiation that generates an electric charge by the incidence of the radiation. A bias voltage application common electrode formed in a planar shape is connected to the incident side of the sensitive semiconductor. On the other hand, in the second connection step (B), the conductor and the cable are connected at a place other than the semiconductor. Instead of connecting the cable directly to the common electrode, in these connection processes, the common electrode and the conductor are connected, and the conductor and the cable are connected at a place other than the semiconductor, so that the cable and the common electrode are connected via the conductor. And indirectly. Since the conductor is thinner than the cable in the thickness direction, the conductor is thinner in the thickness direction than the cable, and it is connected to the common electrode, making connection work easier, causing damage and stress to the semiconductor and the common electrode. Can be avoided.
 上述したこの発明の放射線検出器の製造方法では、(C)の枠取り付け工程を備える。具体的には、(C)の枠取り付け工程では、電荷を蓄積して読み出す回路を形成した基板上に、半導体をその周囲から取り囲む枠を取り付ける。さらに、(C)の枠取り付け工程を備えた場合には、上述した(B)の第2接続工程では、(C)の枠取り付け工程で取り付けられた枠からなる構造物の箇所で導体とケーブルとを接続してもよい。また、上述した(B)の第2接続工程では、(C)の枠取り付け工程で取り付けられた枠からなる構造物の内部であって、かつ半導体以外の箇所で導体とケーブルとを接続してもよい。前者の発明の場合には、放射線検出器の発明でも述べたように、構造物と半導体との間に空間的なスペースが少ない場合において有用である。後者の発明の場合には、放射線検出器の発明でも述べたように、構造物と半導体との間に空間的なスペースがあって、スペースに余裕があるときに有用である。さらに、後者の発明の場合には、構造物の箇所で導体とケーブルとを接続せずに済むので、より簡単な構造とすることができる。 The above-described method for manufacturing a radiation detector according to the present invention includes a frame mounting step (C). Specifically, in the frame attaching step (C), a frame surrounding the semiconductor from its periphery is attached on a substrate on which a circuit for accumulating and reading out charges is formed. Further, when the frame attachment process of (C) is provided, the conductor and the cable at the location of the structure composed of the frame attached in the frame attachment process of (C) in the second connection process of (B) described above. And may be connected. In the second connection step (B) described above, the conductor and the cable are connected to each other inside the structure including the frame attached in the frame attachment step (C) and at a place other than the semiconductor. Also good. In the case of the former invention, as described in the invention of the radiation detector, it is useful when there is little space between the structure and the semiconductor. In the case of the latter invention, as described in the invention of the radiation detector, there is a space between the structure and the semiconductor, which is useful when there is a sufficient space. Furthermore, in the case of the latter invention, since it is not necessary to connect a conductor and a cable in the location of a structure, it can be set as a simpler structure.
 また、前者の発明の場合には、(D)の第1設置工程と(E)の第2設置工程とを備える、あるいは(E´)の設置工程を備えるのが好ましい。 Further, in the case of the former invention, it is preferable to include the first installation step (D) and the second installation step (E), or to include the installation step (E ′).
 (D)の第1設置工程と(E)の第2設置工程とを備える場合には、具体的には、(D)の第1設置工程では、ケーブルを被覆する絶縁体がなくケーブルの導線が剥きだしになっている部分の下側に絶縁物を上述した基板上に設置し、(E)の第2設置工程では、導体のうち、少なくとも共通電極との接続箇所よりも外側の導体の下側に絶縁物を設置し、(C)の枠取り付け工程では、(D)の第1設置工程で設置された絶縁物とともに基板上に枠を取り付け、(E)の第2設置工程では、(C)の枠取り付け工程で取り付けられた枠の溝部分で、かつ導体とケーブルとの接続箇所に嵌まるように絶縁物を設置する。絶縁物を設置しないと、ケーブルを被覆する絶縁体がなくケーブルの導線が剥きだしになっている部分と、基板上に形成された回路パターンとで放電を起こす可能性があるが、絶縁物を設置することで放電を防止することができる。また、放射線検出器の発明でも述べたように、絶縁物を設置しないと、導体のうち、少なくとも共通電極との接続箇所よりも外側の導体と、基板上に形成された回路パターンとで放電を起こす可能性があるが、絶縁物を設置することで放電を防止することができる。 In the case where the first installation step (D) and the second installation step (E) are provided, specifically, in the first installation step (D), there is no insulator covering the cable, and the conductor of the cable. In the second installation step (E), an insulator is placed on the above-described substrate below the exposed portion, and in the second installation step (E), at least the conductor outside the connection point with the common electrode is placed. An insulator is installed on the lower side, and in the frame attachment process in (C), a frame is attached on the substrate together with the insulator installed in the first installation process in (D), and in the second installation process in (E), An insulator is installed so as to fit in the groove portion of the frame attached in the frame attachment step (C) and in the connection portion between the conductor and the cable. If an insulator is not installed, there is a possibility that a discharge will occur between the part where there is no insulator covering the cable and the cable conductor is exposed and the circuit pattern formed on the board. The installation can prevent discharge. In addition, as described in the invention of the radiation detector, if an insulator is not installed, a discharge is caused by at least the conductor outside the connection portion with the common electrode and the circuit pattern formed on the substrate. Although there is a possibility of causing this, it is possible to prevent discharge by installing an insulator.
 また、(E´)の設置工程を備える場合には、具体的には、(E´)の設置工程では、導体のうち、少なくとも共通電極との接続箇所よりも外側の導体の下側、およびケーブルを被覆する絶縁体がなくケーブルの導線が剥きだしになっている部分の下側に絶縁物を設置する。絶縁物を設置しないと、導体のうち、少なくとも共通電極との接続箇所よりも外側の導体、およびケーブルを被覆する絶縁体がなくケーブルの導線が剥きだしになっている部分で、基板上に形成された回路パターンで放電を起こす可能性があるが、絶縁物を設置することで放電を防止することができる。 In addition, when the installation step (E ′) is provided, specifically, in the installation step (E ′), at least the lower side of the conductor outside the connection portion with the common electrode among the conductors, and Install insulation underneath the part where there is no insulation covering the cable and the cable conductors are exposed. If no insulator is installed, the conductor is at least outside the connection point with the common electrode, and there is no insulator covering the cable, and the conductor of the cable is exposed on the board. Although there is a possibility of causing a discharge in the circuit pattern, it is possible to prevent the discharge by installing an insulator.
 この発明に係る放射線検出器およびその製造方法によれば、バイアス電圧給電用のケーブルをバイアス電圧印加用の共通電極に直接に接続せずに、共通電極と導体とを接続し、半導体以外の箇所で導体とケーブルとを接続することで、導体を介してケーブルと共通電極とを間接的に接続する。導体はケーブルよりも厚み方向に薄く形成されているので、ケーブルよりも厚み方向に薄い導体で共通電極に接続することになり、接続作業が行いやすく、半導体や共通電極への損傷の発生や応力を回避することができる。 According to the radiation detector and the manufacturing method thereof according to the present invention, the common electrode and the conductor are connected without connecting the bias voltage feeding cable directly to the common electrode for applying the bias voltage, and the part other than the semiconductor is connected. By connecting the conductor and the cable at, the cable and the common electrode are indirectly connected through the conductor. Since the conductor is thinner than the cable in the thickness direction, the conductor is thinner in the thickness direction than the cable, and it is connected to the common electrode, making connection work easier, causing damage and stress to the semiconductor and the common electrode. Can be avoided.
(a)は実施例1に係る直接変換型のフラットパネル型X線検出器(FPD)の概略平面図であり、(b)は(a)のA-A矢視断面図であり、(c)は(a)のB-B矢視断面図である。(A) is a schematic plan view of the direct conversion type flat panel X-ray detector (FPD) according to the first embodiment, (b) is a cross-sectional view taken along line AA in (a), (c) ) Is a cross-sectional view taken along the line BB in FIG. フラットパネル型X線検出器(FPD)のアクティブマトリックス基板の等価回路を示すブロック図である。It is a block diagram which shows the equivalent circuit of the active matrix board | substrate of a flat panel type X-ray detector (FPD). フラットパネル型X線検出器(FPD)のアクティブマトリックス基板の概略断面図である。It is a schematic sectional drawing of the active-matrix board | substrate of a flat panel type X-ray detector (FPD). 実施例1に係る一連のフラットパネル型X線検出器(FPD)の製造方法の流れを示すフローチャートである。2 is a flowchart showing a flow of a manufacturing method of a series of flat panel X-ray detectors (FPDs) according to the first embodiment. 実施例1、2に係るフラットパネル型X線検出器(FPD)の製造工程を示す概略図であり、(a)は概略平面図であり、(b)は(a)のA-A矢視断面図であり、(c)は(a)のB-B矢視断面図である。BRIEF DESCRIPTION OF THE DRAWINGS It is the schematic which shows the manufacturing process of the flat panel type X-ray detector (FPD) based on Example 1, 2, (a) is a schematic plan view, (b) is an AA arrow view of (a). It is sectional drawing, (c) is BB arrow sectional drawing of (a). 実施例1に係るフラットパネル型X線検出器(FPD)の製造工程を示す概略図であり、(a)は概略平面図であり、(b)は(a)のA-A矢視断面図であり、(c)は(a)のB-B矢視断面図である。BRIEF DESCRIPTION OF THE DRAWINGS It is the schematic which shows the manufacturing process of the flat panel type X-ray detector (FPD) based on Example 1, (a) is a schematic plan view, (b) is AA arrow sectional drawing of (a). (C) is a cross-sectional view taken along the line BB of (a). 実施例1に係るフラットパネル型X線検出器(FPD)の製造工程を示す概略図であり、(a)は概略平面図であり、(b)は(a)のA-A矢視断面図であり、(c)は(a)のB-B矢視断面図である。BRIEF DESCRIPTION OF THE DRAWINGS It is the schematic which shows the manufacturing process of the flat panel type X-ray detector (FPD) based on Example 1, (a) is a schematic plan view, (b) is AA arrow sectional drawing of (a). (C) is a cross-sectional view taken along the line BB of (a). 実施例1に係るフラットパネル型X線検出器(FPD)の製造工程を示す概略図であり、(a)は概略平面図であり、(b)は(a)のA-A矢視断面図であり、(c)は(a)のB-B矢視断面図である。BRIEF DESCRIPTION OF THE DRAWINGS It is the schematic which shows the manufacturing process of the flat panel type X-ray detector (FPD) based on Example 1, (a) is a schematic plan view, (b) is AA arrow sectional drawing of (a). (C) is a cross-sectional view taken along the line BB of (a). 実施例1に係るフラットパネル型X線検出器(FPD)の製造工程を示す概略図であり、(a)は概略平面図であり、(b)は(a)のA-A矢視断面図であり、(c)は(a)のB-B矢視断面図である。BRIEF DESCRIPTION OF THE DRAWINGS It is the schematic which shows the manufacturing process of the flat panel type X-ray detector (FPD) based on Example 1, (a) is a schematic plan view, (b) is AA arrow sectional drawing of (a). (C) is a cross-sectional view taken along the line BB of (a). 実施例1に係るフラットパネル型X線検出器(FPD)の製造工程を示す概略図であり、(a)は概略平面図であり、(b)は(a)のA-A矢視断面図であり、(c)は(a)のB-B矢視断面図である。BRIEF DESCRIPTION OF THE DRAWINGS It is the schematic which shows the manufacturing process of the flat panel type X-ray detector (FPD) based on Example 1, (a) is a schematic plan view, (b) is AA arrow sectional drawing of (a). (C) is a cross-sectional view taken along the line BB of (a). (a)~(c)は、キャリア選択性の高抵抗半導体層である中間層の組み合わせをそれぞれ示した概略断面図である。(A) to (c) are schematic cross-sectional views respectively showing combinations of intermediate layers which are carrier-selective high-resistance semiconductor layers. (a)は実施例2に係る直接変換型のフラットパネル型X線検出器(FPD)の概略平面図であり、(b)は(a)のA-A矢視断面図であり、(c)は(a)のB-B矢視断面図である。(A) is a schematic plan view of a direct conversion type flat panel X-ray detector (FPD) according to the second embodiment, (b) is a cross-sectional view taken along line AA in (a), and (c) ) Is a cross-sectional view taken along the line BB in FIG. 実施例2に係る一連のフラットパネル型X線検出器(FPD)の製造方法の流れを示すフローチャートである。12 is a flowchart showing a flow of a series of flat panel X-ray detector (FPD) manufacturing methods according to the second embodiment. 実施例2に係るフラットパネル型X線検出器(FPD)の製造工程を示す概略図であり、(a)は概略平面図であり、(b)は(a)のA-A矢視断面図であり、(c)は(a)のB-B矢視断面図である。FIG. 5 is a schematic view illustrating a manufacturing process of a flat panel X-ray detector (FPD) according to a second embodiment, (a) is a schematic plan view, and (b) is a cross-sectional view taken along line AA in (a). (C) is a cross-sectional view taken along the line BB of (a). 実施例2に係るフラットパネル型X線検出器(FPD)の製造工程を示す概略図であり、(a)は概略平面図であり、(b)は(a)のA-A矢視断面図であり、(c)は(a)のB-B矢視断面図である。FIG. 5 is a schematic view illustrating a manufacturing process of a flat panel X-ray detector (FPD) according to a second embodiment, (a) is a schematic plan view, and (b) is a cross-sectional view taken along line AA in (a). (C) is a cross-sectional view taken along the line BB of (a). 実施例2に係るフラットパネル型X線検出器(FPD)の製造工程を示す概略図であり、(a)は概略平面図であり、(b)は(a)のA-A矢視断面図であり、(c)は(a)のB-B矢視断面図である。FIG. 5 is a schematic view illustrating a manufacturing process of a flat panel X-ray detector (FPD) according to a second embodiment, (a) is a schematic plan view, and (b) is a cross-sectional view taken along line AA in (a). (C) is a cross-sectional view taken along the line BB of (a). 実施例2に係るフラットパネル型X線検出器(FPD)の製造工程を示す概略図であり、(a)は概略平面図であり、(b)は(a)のA-A矢視断面図であり、(c)は(a)のB-B矢視断面図である。FIG. 5 is a schematic view illustrating a manufacturing process of a flat panel X-ray detector (FPD) according to a second embodiment, (a) is a schematic plan view, and (b) is a cross-sectional view taken along line AA in (a). (C) is a cross-sectional view taken along the line BB of (a). (a)は実施例3に係る直接変換型のフラットパネル型X線検出器(FPD)の概略平面図であり、(b)は(a)のA-A矢視断面図であり、(c)は(a)のB-B矢視断面図である。(A) is a schematic plan view of a direct conversion type flat panel X-ray detector (FPD) according to the third embodiment, (b) is a cross-sectional view taken along line AA in (a), and (c) ) Is a cross-sectional view taken along the line BB in FIG. 変形例に係る直接変換型のフラットパネル型X線検出器(FPD)の概略図であり、(a)は台座を設置したときの概略断面図であり、(b)は銅板を介在させたときの拡大平面図である。It is the schematic of the direct conversion type flat panel type X-ray detector (FPD) which concerns on a modification, (a) is a schematic sectional drawing when installing a base, (b) is when interposing a copper plate FIG. 従来の放射線検出器の概略断面図である。It is a schematic sectional drawing of the conventional radiation detector.
 1 … アクティブマトリクス基板
 2 … (放射線感応型の)半導体
 3 … (バイアス電圧印加用の)共通電極
 4A … (バイアス電圧給電用の)ケーブル
 4B … 単線
 4C … (リボン状)金属板
 6 … 枠
 8、9、8´ … 絶縁シート
DESCRIPTION OF SYMBOLS 1 ... Active matrix substrate 2 ... (Radiosensitive type) semiconductor 3 ... Common electrode (for bias voltage application) 4A ... Cable (for bias voltage feeding) 4B ... Single wire 4C ... (Ribbon-like) Metal plate 6 ... Frame 8 , 9, 8 '... Insulating sheet
 以下、図面を参照してこの発明の実施例1を説明する。図1(a)は、実施例1に係る直接変換型のフラットパネル型X線検出器(以下、適宜「FPD」と略記する)の概略平面図であり、図1(b)は、図1(a)のA-A矢視断面図であり、図1(c)は、図1(a)のB-B矢視断面図であり、図2は、フラットパネル型X線検出器(FPD)のアクティブマトリックス基板の等価回路を示すブロック図であり、図3は、フラットパネル型X線検出器(FPD)のアクティブマトリックス基板の概略断面図である。後述する実施例2、3も含めて、本実施例1では、放射線検出器としてフラットパネル型X線検出器(FPD)を例に採って説明する。また、図1(a)では、上部カバーガラスの図示を省略する。 Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1A is a schematic plan view of a direct conversion type flat panel X-ray detector (hereinafter abbreviated as “FPD” as appropriate) according to the first embodiment, and FIG. 1A is a cross-sectional view taken along line AA in FIG. 1A, FIG. 1C is a cross-sectional view taken along line BB in FIG. 1A, and FIG. 2 is a flat panel X-ray detector (FPD). ) Is a block diagram showing an equivalent circuit of the active matrix substrate, and FIG. 3 is a schematic sectional view of the active matrix substrate of the flat panel X-ray detector (FPD). In the present embodiment 1, including later-described embodiments 2 and 3, a flat panel X-ray detector (FPD) will be described as an example of the radiation detector. Moreover, illustration of an upper cover glass is abbreviate | omitted in Fig.1 (a).
 本実施例1に係るFPDは、図1(a)、図1(b)に示すように、アクティブマトリックス基板1と、放射線(実施例1~3ではX線)の入射により電荷を生成する放射線感応型の半導体2と、バイアス電圧印加用の共通電極3とを備えている。アクティブマトリックス基板1は、図2、図3に示すように、放射線の入射面側に複数の収集電極11を形成し、各収集電極11で収集される電荷の蓄積・読み出し用電気回路12を配設して構成されている。各収集電極11については放射線検出有効エリアSA内で2次元状マトリックス配列で設定している。アクティブマトリクス基板1は、この発明における電荷を蓄積して読み出す回路を形成した基板に相当し、放射線感応型の半導体2は、この発明における放射線感応型の半導体に相当し、バイアス電圧印加用の共通電極3は、この発明におけるバイアス電圧印加用の共通電極に相当する。 As shown in FIGS. 1 (a) and 1 (b), the FPD according to the first embodiment is a radiation that generates charges by the incidence of the active matrix substrate 1 and radiation (X-rays in the first to third embodiments). A sensitive semiconductor 2 and a common electrode 3 for applying a bias voltage are provided. As shown in FIGS. 2 and 3, the active matrix substrate 1 has a plurality of collecting electrodes 11 formed on the radiation incident surface side, and an electric circuit 12 for storing and reading out charges collected by the collecting electrodes 11. It is configured. Each collection electrode 11 is set in a two-dimensional matrix arrangement within the radiation detection effective area SA. The active matrix substrate 1 corresponds to a substrate on which a circuit for accumulating and reading out charges is formed in the present invention, and the radiation sensitive semiconductor 2 is equivalent to the radiation sensitive semiconductor in the present invention, and is used for applying a bias voltage. The electrode 3 corresponds to a common electrode for applying a bias voltage in the present invention.
 図1(a)、図1(b)に示すように、このアクティブマトリックス基板1の収集電極の入射面側に半導体2を積層し、その半導体2の入射側に共通電極3を面状に形成して積層している。そして、共通電極3の入射面にバイアス電圧給電用のリード線4を接続している。 As shown in FIGS. 1A and 1B, the semiconductor 2 is laminated on the incident surface side of the collecting electrode of the active matrix substrate 1, and the common electrode 3 is formed in a planar shape on the incident side of the semiconductor 2 And laminated. A lead wire 4 for supplying bias voltage is connected to the incident surface of the common electrode 3.
 リード線4は、図1(a)に示すように、バイアス電圧給電用のケーブル4Aと、そのケーブル4Aよりも厚み方向に薄く形成された単線4Bとで形成されている。端部においてケーブル4Aを被覆する絶縁体(すなわちケーブル4Aの被覆部分)を剥いて、芯線4aのみにする。このケーブル4Aの芯線4aと単線4Bとを導電ペースト(例えば銀ペースト)を介して接続するとともに、単線4Bと共通電極3とを同じく導電ペーストを介して接続する。単線4Bとケーブル4Aの芯線4aとの接続箇所は、半導体2以外の箇所となっており、本実施例1では枠6からなる構造物の箇所である。本実施例1では、導体として単線4Bを採用している。単線4Bの場合には縒り線でないので、捩れることによる断線の心配が少ない。バイアス電圧給電用のケーブル4Aは、この発明におけるバイアス電圧給電用のケーブルに相当し、単線4Bは、この発明における導体に相当する。 As shown in FIG. 1A, the lead wire 4 is formed by a bias voltage feeding cable 4A and a single wire 4B formed thinner in the thickness direction than the cable 4A. The insulator covering the cable 4A at the end (that is, the covering portion of the cable 4A) is peeled off to make only the core wire 4a. The core wire 4a and the single wire 4B of the cable 4A are connected via a conductive paste (for example, silver paste), and the single wire 4B and the common electrode 3 are similarly connected via a conductive paste. A connection location between the single wire 4B and the core wire 4a of the cable 4A is a location other than the semiconductor 2, and is a location of a structure including the frame 6 in the first embodiment. In the first embodiment, the single wire 4B is adopted as the conductor. In the case of the single wire 4B, since it is not a twisted wire, there is little fear of disconnection due to twisting. The bias voltage supply cable 4A corresponds to the bias voltage supply cable in the present invention, and the single line 4B corresponds to the conductor in the present invention.
 図1(b)、図1(c)に示すように、上部カバーガラス5でFPDを保護している。具体的には、アクティブマトリックス基板1上に、半導体2をその周囲から取り囲む枠6を取り付け、その枠6によって上部カバーガラス5を支持する。上部カバーガラス5が半導体2および共通電極3を覆うように、硬化性合成樹脂からなる樹脂膜7によって上部カバーガラス5を固定形成するのが好ましい。この樹脂膜7によって、共通電極3、単線4Bとケーブル4Aの芯線4aとの接続箇所も樹脂で封止される。なお、共通電極3、単線4Bとケーブル4Aの芯線4aとの接続箇所のみ樹脂で封止してもよく、少なくとも共通電極3、単線4Bとケーブル4Aの芯線4aとの接続箇所を樹脂で封止すれば特に限定されない。枠6は、この発明における枠に相当する。 1) As shown in FIGS. 1B and 1C, the FPD is protected by the upper cover glass 5. Specifically, a frame 6 surrounding the semiconductor 2 from its periphery is attached on the active matrix substrate 1, and the upper cover glass 5 is supported by the frame 6. The upper cover glass 5 is preferably fixedly formed by a resin film 7 made of a curable synthetic resin so that the upper cover glass 5 covers the semiconductor 2 and the common electrode 3. By this resin film 7, the connection portion of the common electrode 3, the single wire 4B, and the core wire 4a of the cable 4A is also sealed with resin. Note that only the connection portion between the common electrode 3, single wire 4B and the core wire 4a of the cable 4A may be sealed with resin, and at least the connection portion between the common electrode 3, single wire 4B and the core wire 4a of the cable 4A is sealed with resin. If it does, it will not be limited in particular. The frame 6 corresponds to the frame in the present invention.
 図1(a)~図1(c)に示すように、単線4Bのうち、共通電極3との接続箇所よりも外側の単線4Bの下側に絶縁シート8を備える。また、図1(a)、図1(c)に示すように、ケーブル4Aを被覆する絶縁体がなくケーブル4Aの導線(ここでは芯線4a)が剥きだしになっている部分の下側に絶縁シート9を備える。絶縁シート8、9は、この発明における絶縁物に相当する。 As shown in FIGS. 1 (a) to 1 (c), an insulating sheet 8 is provided on the lower side of the single wire 4B outside the connecting portion with the common electrode 3 in the single wire 4B. Further, as shown in FIGS. 1A and 1C, there is no insulator covering the cable 4A and insulation is provided below the portion where the conductor of the cable 4A (here, the core wire 4a) is exposed. A sheet 9 is provided. The insulating sheets 8 and 9 correspond to the insulator in this invention.
 図2、図3に示すようにアクティブマトリクス基板1は、上述したように収集電極11を形成し、蓄積・読み出し用電気回路12を配設している。蓄積・読み出し用電気回路12は、コンデンサ12Aやスイッチング素子としてのTFT(薄膜電界効果トランジスタ)12Bおよびゲート線12a,データ線12bなどからなり、各収集電極11毎に1個のコンデンサ12Aおよび1個のTFT12Bが対応付けて接続されている。 As shown in FIGS. 2 and 3, the active matrix substrate 1 is formed with the collecting electrode 11 as described above, and the storage / reading electric circuit 12 is provided. The electric circuit 12 for accumulation / reading includes a capacitor 12A, a TFT (thin film field effect transistor) 12B as a switching element, a gate line 12a, a data line 12b, and the like, and one capacitor 12A and one for each collecting electrode 11 TFT12B are connected in association with each other.
 また、アクティブマトリックス基板1の蓄積・読み出し用電気回路12の周囲にはゲートドライバ13と電荷電圧変換型増幅器14とマルチプレクサ15とA/D変換器16とを配設して接続している。これらのゲートドライバ13、電荷電圧変換型増幅器14、マルチプレクサ15、A/D変換器16は、アクティブマトリックス基板1とは別基板で接続されている。なお、ゲートドライバ13、電荷電圧変換型増幅器14、マルチプレクサ15、A/D変換器16の一部または全部を、アクティブマトリックス基板1に内蔵してもよい。 A gate driver 13, a charge / voltage conversion amplifier 14, a multiplexer 15, and an A / D converter 16 are arranged and connected around the storage / reading electric circuit 12 of the active matrix substrate 1. The gate driver 13, the charge / voltage conversion amplifier 14, the multiplexer 15, and the A / D converter 16 are connected to a substrate different from the active matrix substrate 1. Note that some or all of the gate driver 13, the charge-voltage conversion amplifier 14, the multiplexer 15, and the A / D converter 16 may be built in the active matrix substrate 1.
 FPDによってX線を検出する際には、バイアス供給電源(図示省略)からバイアス電圧を、バイアス電圧給電用のリード線4を介してバイアス電圧印加用の共通電極3に印加する。リード線4は、上述したように、ケーブル4Aと単線4Bとで形成されており、ケーブル4Aの芯線4aと単線4Bとを接続するとともに、単線4Bと共通電極3とを接続するので、バイアス供給電源(図示省略)からバイアス電圧を、ケーブル4Aおよび単線4Bを介して共通電極3に印加する。バイアス電圧を印加した状態で、放射線(実施例1~3ではX線)の入射に伴って放射線感応型の半導体2で電荷を生成する。この生成された電荷を収集電極11で一旦収集する。蓄積・読み出し用電気回路12によって、収集された電荷を各収集電極11毎の放射線検出信号(実施例1~3ではX線検出信号)として取り出す。 When X-rays are detected by the FPD, a bias voltage is applied from a bias supply power source (not shown) to the common electrode 3 for bias voltage application via a lead wire 4 for supplying bias voltage. As described above, the lead wire 4 is formed by the cable 4A and the single wire 4B. The lead wire 4 connects the core wire 4a and the single wire 4B of the cable 4A and connects the single wire 4B and the common electrode 3, so that a bias is supplied. A bias voltage from a power source (not shown) is applied to the common electrode 3 via the cable 4A and the single wire 4B. With the bias voltage applied, charges are generated in the radiation-sensitive semiconductor 2 with the incidence of radiation (X-rays in Examples 1 to 3). The generated charges are once collected by the collecting electrode 11. The electric charge collected by the storage / readout electric circuit 12 is taken out as a radiation detection signal for each collection electrode 11 (in the first to third embodiments, an X-ray detection signal).
 具体的には、収集電極11で収集された電荷がコンデンサ12Aに一旦蓄積される。そして、ゲートドライバ13からゲート線12aを介して読み出し信号を各TFT12Bのゲートに順に与える。読み出し信号を与えることで、読み出し信号が与えられたTFT12BがOFFからONに移行する。その移行したTFT12Bのソースに接続されたデータ線12bがマルチプレクサ15によって順に切り換え接続されるのにしたがって、コンデンサ12Aに蓄積された電荷を、TFT12Bからデータ線12bを介して読み出す。読み出された電荷を電荷電圧変換型増幅器14で増幅して、マルチプレクサ15によって各収集電極11毎の放射線検出信号(実施例1~3ではX線検出信号)としてA/D変換器16に送り出してアナログ値からディジタル値に変換する。 Specifically, the charges collected by the collecting electrode 11 are temporarily accumulated in the capacitor 12A. Then, a read signal is sequentially applied from the gate driver 13 to the gate of each TFT 12B through the gate line 12a. By giving the read signal, the TFT 12B to which the read signal is given shifts from OFF to ON. As the data line 12b connected to the source of the shifted TFT 12B is sequentially switched and connected by the multiplexer 15, the charge accumulated in the capacitor 12A is read from the TFT 12B via the data line 12b. The read charge is amplified by the charge / voltage conversion amplifier 14 and sent to the A / D converter 16 as a radiation detection signal (X-ray detection signal in the first to third embodiments) for each collection electrode 11 by the multiplexer 15. To convert from analog value to digital value.
 例えば、FPDをX線透視撮影装置に備えた場合には、X線検出信号を後段の画像処理回路に送り込んで、画像処理を行って2次元X線透視画像等を出力する。2次元状マトリックス配列の各収集電極11は、放射線画像(ここでは2次元X線透視画像)の各画素に対応する電極(画素電極)にそれぞれ対応している。放射線検出信号(実施例1~3ではX線検出信号)を取り出すことで、放射線検出有効エリアSAに投影される放射線の2次元強度分布に応じた放射線画像(ここでは2次元X線透視画像)を作成することができる。つまり、後述する実施例2、3も含めて、本実施例1に係るFPDは、放射線検出有効エリアSAに投影される放射線(実施例1~3ではX線)の2次元強度分布を検出することができる2次元アレイタイプの放射線検出器である。 For example, when an FPD is provided in an X-ray fluoroscopic apparatus, an X-ray detection signal is sent to an image processing circuit at a subsequent stage, image processing is performed, and a two-dimensional X-ray fluoroscopic image is output. Each collection electrode 11 in the two-dimensional matrix array corresponds to an electrode (pixel electrode) corresponding to each pixel of the radiation image (here, a two-dimensional X-ray fluoroscopic image). By extracting a radiation detection signal (X-ray detection signal in Examples 1 to 3), a radiation image (here, a two-dimensional X-ray fluoroscopic image) corresponding to the two-dimensional intensity distribution of the radiation projected onto the radiation detection effective area SA Can be created. That is, the FPD according to the first embodiment including the second and third embodiments described later detects the two-dimensional intensity distribution of the radiation (X-rays in the first to third embodiments) projected onto the radiation detection effective area SA. It is a two-dimensional array type radiation detector that can be used.
 次に、FPDの製造方法について、図4~図10を参照して説明する。図4は、実施例1に係る一連のフラットパネル型X線検出器(FPD)の製造方法の流れを示すフローチャートであり、図5~図10は、実施例1に係るフラットパネル型X線検出器(FPD)の製造工程を示す概略図である。図1と同様に、図5(a)~図10(a)は、概略平面図であり、図5(b)~図10(b)は、図5(a)~図10(a)のA-A矢視断面図であり、図5(c)~図10(c)は、図5(a)~図10(a)のB-B矢視断面図である。また、図1(a)と同様に、図5(a)~図10(a)では、上部カバーガラスの図示を省略する。 Next, an FPD manufacturing method will be described with reference to FIGS. FIG. 4 is a flowchart showing a flow of a series of manufacturing methods of a flat panel X-ray detector (FPD) according to the first embodiment, and FIGS. 5 to 10 illustrate flat panel X-ray detection according to the first embodiment. It is the schematic which shows the manufacturing process of a container (FPD). As in FIG. 1, FIGS. 5 (a) to 10 (a) are schematic plan views, and FIGS. 5 (b) to 10 (b) are the same as FIGS. 5 (a) to 10 (a). FIG. 5C is a cross-sectional view taken along the line AA, and FIGS. 5C to 10C are cross-sectional views taken along the line BB in FIGS. 5A to 10A. Similarly to FIG. 1 (a), the upper cover glass is not shown in FIGS. 5 (a) to 10 (a).
 (ステップS1)絶縁シートの設置
 図5に示すように、アクティブマトリックス基板1の収集電極の入射面側に半導体2を積層し、その半導体2の入射側に共通電極3を面状に形成して積層した状態で、図6(a)、図6(c)に示すように、絶縁シート9をアクティブマトリックス基板1上に設置する。この設置場所は、ケーブル4A(図1、図9、図10を参照)を被覆する絶縁体がなくケーブル4Aの導線(芯線4a)が剥きだしになっている部分の下側となる場所である。なお、図5、図6中の符号3A、および後述する図7中の符号3Aは、後述する単線4B(図1、図9、図10を参照)と共通電極3とを接続するための共通電極3の張り出し箇所である。このステップS1は、この発明における(D)の第1設置工程に相当する。
(Step S1) Installation of Insulating Sheet As shown in FIG. 5, the semiconductor 2 is laminated on the incident surface side of the collecting electrode of the active matrix substrate 1, and the common electrode 3 is formed in a planar shape on the incident side of the semiconductor 2 In the laminated state, as shown in FIGS. 6A and 6C, the insulating sheet 9 is placed on the active matrix substrate 1. This installation place is a place below the portion where there is no insulator covering the cable 4A (see FIGS. 1, 9, and 10) and the conductor (core wire 4a) of the cable 4A is exposed. . 5 and 6 and 3A in FIG. 7 to be described later are common for connecting a single wire 4B (see FIGS. 1, 9, and 10) to be described later and the common electrode 3. This is a protruding portion of the electrode 3. This step S1 corresponds to the first installation step (D) in this invention.
 (ステップS2)枠の取り付け
 ステップS1で設置された絶縁シート9とともにアクティブマトリックス基板1上に、図7に示すように、半導体2をその周囲から取り囲む枠6を取り付ける。この枠6には、図7(a)に示すように、張り出し箇所3Aに対向する部分に溝6Aを設け、この溝6Aに連通された切り込み部6Bを設ける。この溝6Aおよび切り込み部6Bについては、アクティブマトリックス基板1上に枠6を取り付けた後に設けてもよいし、予め設けた後でアクティブマトリックス基板1上に枠6を取り付けてもよい。また、切り込み部6Bは、図7(c)に示すように、ケーブル4A(図1、図9、図10を参照)を枠6に導入する導入領域6aでは枠6を貫通しており、溝6Aに近い溝側領域6bでは枠6を中段程度に残すように形成されている。また、導入領域6aと溝側領域6bとの間では、ケーブル4Aの芯線4a(図1、図9、図10を参照)が折り曲がることによるストレスを防ぐために、芯線4aが滑らかに延在するように枠6は徐々に傾斜している。このステップS2は、(C)の枠取り付け工程に相当する。
(Step S2) Attachment of Frame As shown in FIG. 7, a frame 6 surrounding the semiconductor 2 from its periphery is attached on the active matrix substrate 1 together with the insulating sheet 9 installed in Step S1. As shown in FIG. 7A, the frame 6 is provided with a groove 6A at a portion facing the protruding portion 3A, and a cut portion 6B communicated with the groove 6A. The grooves 6A and the cut portions 6B may be provided after the frame 6 is attached on the active matrix substrate 1, or the frame 6 may be attached on the active matrix substrate 1 after being provided in advance. Further, as shown in FIG. 7C, the notch 6B penetrates the frame 6 in the introduction region 6a for introducing the cable 4A (see FIGS. 1, 9, and 10) into the frame 6, and the groove 6B In the groove side region 6b close to 6A, the frame 6 is formed so as to remain in the middle level. Also, between the introduction region 6a and the groove side region 6b, the core wire 4a extends smoothly in order to prevent stress due to bending of the core wire 4a (see FIGS. 1, 9, and 10) of the cable 4A. Thus, the frame 6 is gradually inclined. This step S2 corresponds to the frame attaching step (C).
 (ステップS3)絶縁シートの設置
 単線4B(図1、図9、図10を参照)のうち、図8に示すように、共通電極3との接続箇所よりも外側の単線4Bの下側に絶縁シート8を設置する。具体的には、ステップS2で取り付けられた枠6の溝6Aで、かつ単線4Bとケーブル4Aの芯線4a(図1、図9、図10を参照)との接続箇所に嵌まるように絶縁シート8を設置する。なお、絶縁シート8の設置場所については、単線4Bと共通電極3との接続箇所を含ませてもよい。ただし、半導体2の表面や共通電極3に傷をつけないように設置する必要がある。すなわち、共通電極3との接続箇所において単線4Bの下側にも絶縁シート8を設置してもよく、単線4Bのうち、少なくとも共通電極3との接続箇所よりも外側の単線4Bの下側に絶縁シート8を設置すれば特に限定されない。このステップS3は、(E)の第2設置工程に相当する。
(Step S3) Installation of Insulating Sheet Of the single wire 4B (see FIG. 1, FIG. 9, and FIG. 10), as shown in FIG. 8, insulation is performed on the lower side of the single wire 4B outside the connection point with the common electrode 3. The seat 8 is installed. Specifically, the insulating sheet is fitted so as to fit in the groove 6A of the frame 6 attached in step S2 and in the connection portion between the single wire 4B and the core wire 4a of the cable 4A (see FIGS. 1, 9, and 10). 8 is installed. In addition, about the installation place of the insulating sheet 8, you may include the connection location of the single wire 4B and the common electrode 3. FIG. However, it is necessary to install so as not to damage the surface of the semiconductor 2 and the common electrode 3. That is, the insulating sheet 8 may be installed below the single wire 4B at the connection point with the common electrode 3, and at least the single wire 4B below the single wire 4B outside the connection point with the common electrode 3. If the insulating sheet 8 is installed, it will not be specifically limited. This step S3 corresponds to the second installation step (E).
 (ステップS4)ケーブル・単線の設置
 図9に示すように、ケーブル4Aおよび芯線4aを枠6の切り込み部6B(図7(a)を参照)に挿入することで、絶縁シート9の上にケーブル4Aおよび芯線4aを設置する。そして、芯線4aの先端が絶縁シート8上に位置するように設置する。一方、絶縁シート8上に単線4Bを設置し、単線4Bと共通電極3とを導電ペーストを介して接続し、単線4Bとケーブル4Aの芯線4aとを導電ペーストを介して接続する。なおこの図では単線4Bと共通電極3との接続部分が、共通電極3から小さく突き出たパターン上で行われているが、これは接続箇所をわかりやすくしたためであり、突き出たパターンがない共通電極3であっても、共通電極3の内側に直接に接続して問題ない。上部カバーガラス5(図10を参照)がこのステップS4の時点では設置されていないので、上方からケーブル4A・単線4Bを容易に設置することができる。なお、ステップS4よりも前の時点で、予め、単線4Bとケーブル4Aの芯線4aとを別の場所ではんだ付けで接続して、接続された単線4Bとケーブル4Aの芯線4aとを、枠6の切り込み部6Bに挿入することで、絶縁シート8、9の上にケーブル4A・単線4Bを設置した上で、単線4Bと共通電極3とを接続してもよい。このステップS4は、(A)の第1接続工程に相当し、(B)の第2接続工程に相当する。
(Step S4) Installation of Cable / Single Wire As shown in FIG. 9, the cable 4A and the core wire 4a are inserted into the cut portion 6B of the frame 6 (see FIG. 7A) so that the cable is placed on the insulating sheet 9. 4A and the core wire 4a are installed. And it installs so that the front-end | tip of the core wire 4a may be located on the insulating sheet 8. FIG. On the other hand, the single wire 4B is installed on the insulating sheet 8, the single wire 4B and the common electrode 3 are connected via a conductive paste, and the single wire 4B and the core wire 4a of the cable 4A are connected via a conductive paste. In this figure, the connecting portion between the single wire 4B and the common electrode 3 is formed on a pattern protruding slightly from the common electrode 3, but this is for easy understanding of the connecting portion, and there is no protruding pattern. Even if it is 3, there is no problem if it is directly connected to the inside of the common electrode 3. Since the upper cover glass 5 (see FIG. 10) is not installed at the time of this step S4, the cables 4A and single wires 4B can be easily installed from above. In addition, at the time before step S4, the single wire 4B and the core wire 4a of the cable 4A are connected by soldering in another place in advance, and the connected single wire 4B and the core wire 4a of the cable 4A are connected to the frame 6. The single wire 4B and the common electrode 3 may be connected after the cable 4A and the single wire 4B are installed on the insulating sheets 8 and 9 by being inserted into the cut portion 6B. This step S4 corresponds to the first connection step (A) and corresponds to the second connection step (B).
 (ステップS5)上部カバーガラスの設置
 ステップS4でケーブル4A・単線4Bを設置して、それぞれを導電ペーストで接続した後に、図10に示すように、枠6の上部に上部カバーガラス5を設置する。
(Step S5) Installation of Upper Cover Glass After installing the cables 4A and single wires 4B in step S4 and connecting them with conductive paste, the upper cover glass 5 is installed on the upper part of the frame 6 as shown in FIG. .
 (ステップS6)樹脂封止
 アクティブマトリックス基板1と上部カバーガラス5との間に液状の常温硬化型樹脂組成物を注入硬化させることで、硬化後の常温硬化型樹脂組成物は樹脂7となって、硬化性合成樹脂からなる樹脂7によって上部カバーガラス5を固定形成する。硬化性合成樹脂には、例えば常温硬化型のエポキシ樹脂などが適当な樹脂材料として用いられる。この一連のステップS1~S6を行うことで、図1に示すようなFPDが完成する。
(Step S6) Resin Encapsulation A liquid room temperature curable resin composition is injected and cured between the active matrix substrate 1 and the upper cover glass 5 so that the room temperature curable resin composition after curing becomes a resin 7. The upper cover glass 5 is fixedly formed by a resin 7 made of a curable synthetic resin. As the curable synthetic resin, for example, a room temperature curable epoxy resin is used as an appropriate resin material. By performing a series of steps S1 to S6, an FPD as shown in FIG. 1 is completed.
 アクティブマトリックス基板1には、例えばガラス基板が用いられるとともに、上部カバーガラス5には、例えばパイレックス(登録商標)、テンパックス(登録商標)ガラス基板や石英ガラス基板が用いられる。アクティブマトリックス基板1のガラス基板や、上部カバーガラス5のガラス基板の厚みは、例えば0.5mm~1.5mm程度である。半導体2の厚さは、通常、0.5mm~1.5mm前後の厚膜であり、面積は、例えば縦20cm~50cm×横20cm~50cm程度のものである。絶縁シート8、9については、いずれもポリイミドフィルムの0.1mm~0.6mm程度、望ましくは0.2mm厚膜を使用する。 For example, a glass substrate is used for the active matrix substrate 1, and a Pyrex (registered trademark), a Tempax (registered trademark) glass substrate, or a quartz glass substrate is used for the upper cover glass 5, for example. The thickness of the glass substrate of the active matrix substrate 1 and the glass substrate of the upper cover glass 5 is, for example, about 0.5 mm to 1.5 mm. The thickness of the semiconductor 2 is normally a thick film of about 0.5 mm to 1.5 mm, and the area is, for example, about 20 cm to 50 cm long × 20 cm to 50 cm wide. As for the insulating sheets 8 and 9, a polyimide film of about 0.1 mm to 0.6 mm, preferably 0.2 mm thick is used.
 放射線感応型の半導体2は、高純度アモルファスセレン(a-Se),Na等のアルカリ金属やCl等のハロゲンもしくはAsやTeをドープしたセレンおよびセレン化合物のアモルファス半導体,CdTe,CdZnTe,PbI2 ,HgI2 ,TlBr等の非セレン系多結晶半導体のうちのいずれかであるのが好ましい。アモルファスセレン,アルカリ金属やハロゲンもしくはAsやTeをドープしたセレンおよびセレン化合物のアモルファス半導体,非セレン系多結晶半導体は、大面積化適性および厚膜化適性に優れる。特に、109 Ω以上、好ましくは1011Ω以上の比抵抗を有するa-Seを半導体2に用いると大面積化適性および厚膜化適性が顕著に優れている。 The radiation-sensitive semiconductor 2 includes high-purity amorphous selenium (a-Se), alkali metals such as Na, halogens such as Cl, selenium doped with As or Te, and amorphous semiconductors of selenium compounds, CdTe, CdZnTe, PbI 2 , It is preferably one of non-selenium-based polycrystalline semiconductors such as HgI 2 and TlBr. Amorphous selenium, amorphous semiconductors of selenium and selenium compounds doped with alkali metal, halogen or As or Te, and non-selenium-based polycrystalline semiconductors are excellent in suitability for large area and thick film. In particular, when a-Se having a specific resistance of 10 9 Ω or more, preferably 10 11 Ω or more is used for the semiconductor 2, the suitability for increasing the area and the suitability for increasing the film thickness are remarkably excellent.
 また、半導体2としては、上述した感応型の半導体2の他に、その入射面(図1(b)では上面)または入射側と逆側の面(図1(b)では下面)もしくは両面に形成されたキャリア選択性の高抵抗半導体層である中間層との組み合わせも含む。図11(a)に示すように、半導体2と共通電極3との間に中間層2aを形成するとともに、半導体2と収集電極11(図3を参照)との間に中間層2bを形成してもよいし、図11(b)に示すように、半導体2と共通電極3との間のみに中間層2aを形成してもよいし、図11(c)に示すように、半導体2と収集電極11(図3を参照)との間のみに中間層2bを形成してもよい。 Further, as the semiconductor 2, in addition to the sensitive semiconductor 2 described above, the incident surface (upper surface in FIG. 1B) or the surface opposite to the incident side (lower surface in FIG. 1B) or both surfaces The combination with the intermediate layer which is the formed carrier selective high resistance semiconductor layer is also included. As shown in FIG. 11A, an intermediate layer 2a is formed between the semiconductor 2 and the common electrode 3, and an intermediate layer 2b is formed between the semiconductor 2 and the collecting electrode 11 (see FIG. 3). Alternatively, as shown in FIG. 11B, the intermediate layer 2a may be formed only between the semiconductor 2 and the common electrode 3, or as shown in FIG. The intermediate layer 2b may be formed only between the collecting electrode 11 (see FIG. 3).
 このように、キャリア選択性の中間層2a,2bを設けることにより暗電流を低減させることができる。ここで言うキャリア選択性とは半導体中の電荷移動媒体(キャリア)である電子と正孔とで、電荷移動作用への寄与率が著しく異なる性質を指す。 Thus, the dark current can be reduced by providing the carrier selective intermediate layers 2a and 2b. The carrier selectivity mentioned here refers to the property that the contribution rate to the charge transfer action is remarkably different between electrons and holes which are charge transfer media (carriers) in the semiconductor.
 半導体2とキャリア選択性の中間層2a,2bとの組み合わせ方としては、次のような態様が挙げられる。共通電極3に正のバイアス電圧を印加する場合には、中間層2aに電子の寄与率が大きい材料を使用する。これにより共通電極3からの正孔の注入が阻止され、暗電流を低減させることができる。中間層2bには正孔の寄与率が大きい材料を使用する。これにより収集電極11からの電子の注入が阻止され、暗電流を低減させることができる。 As a method of combining the semiconductor 2 and the carrier-selective intermediate layers 2a and 2b, the following modes are exemplified. When a positive bias voltage is applied to the common electrode 3, a material having a large contribution ratio of electrons is used for the intermediate layer 2a. Thereby, the injection of holes from the common electrode 3 is blocked, and the dark current can be reduced. A material having a large contribution ratio of holes is used for the intermediate layer 2b. Thereby, the injection of electrons from the collecting electrode 11 is blocked, and the dark current can be reduced.
 逆に、共通電極3に負のバイアス電圧を印加する場合には、中間層2aに正孔の寄与率が大きい材料を使用する。これにより共通電極3からの電子の注入が阻止され、暗電流を低減させることができる。中間層2bには電子の寄与率が大きい材料を使用する。これにより収集電極11からの正孔の注入が阻止され、暗電流を低減させることができる。 Conversely, when a negative bias voltage is applied to the common electrode 3, a material having a large contribution ratio of holes is used for the intermediate layer 2a. Thereby, the injection of electrons from the common electrode 3 is blocked, and the dark current can be reduced. A material having a large contribution ratio of electrons is used for the intermediate layer 2b. Thereby, the injection of holes from the collecting electrode 11 is blocked, and the dark current can be reduced.
 キャリア選択性の中間層2a,2bの厚さは、通常、0.1μm~10μmの範囲が好ましい。中間層2a,2bの厚さが0.1μm未満では暗電流を十分に抑制できない傾向が現れ、逆に、厚さが10μmを越えると放射線検出の妨げとなる傾向(例えば感度が低下する傾向)が現れる。 The thickness of the carrier selective intermediate layers 2a and 2b is usually preferably in the range of 0.1 μm to 10 μm. If the thickness of the intermediate layers 2a and 2b is less than 0.1 μm, there is a tendency that the dark current cannot be sufficiently suppressed, and conversely, if the thickness exceeds 10 μm, radiation detection tends to be hindered (for example, the sensitivity tends to decrease). Appears.
 また、キャリア選択性の中間層2a,2bに用いられる半導体としては、Sb2 S,ZnTe,CeO,CdS,ZnSe,ZnS等の多結晶半導体、Na等のアルカリ金属やCl等のハロゲンもしくはAsやTeをドープしたセレンおよびセレン化合物のアモルファス半導体が大面積化適性に優れるものとして挙げられる。
Further, semiconductors used for the carrier selective intermediate layers 2a and 2b include polycrystalline semiconductors such as Sb 2 S 3 , ZnTe, CeO 2 , CdS, ZnSe, and ZnS, alkali metals such as Na, halogens such as Cl, Selenium doped with As or Te and an amorphous semiconductor of a selenium compound may be mentioned as having excellent suitability for large area.
 中間層2a,2bに用いられる半導体のうち、電子の寄与が大きいものとして、n型半導体であるCeO,CdS,CdSe,ZnSe,ZnSのような多結晶半導体や、アルカリ金属やAsやTeをドープして正孔の寄与率を低下させたアモルファスSe等のアモルファス体が挙げられる。 Among the semiconductors used for the intermediate layers 2a and 2b, those having a large contribution of electrons include polycrystalline semiconductors such as CeO 2 , CdS, CdSe, ZnSe, and ZnS that are n-type semiconductors, alkali metals, As, and Te. An amorphous body such as amorphous Se that has been doped to reduce the contribution ratio of holes can be used.
 また、正孔の寄与が大きいものとして、p型半導体であるZnTeのような多結晶半導体や、ハロゲンをドープして電子の寄与率を低下させたアモルファスSe等のアモルファス体が挙げられる。 Moreover, examples of the material having a large contribution of holes include a polycrystalline semiconductor such as ZnTe which is a p-type semiconductor, and an amorphous material such as amorphous Se doped with halogen to reduce the contribution of electrons.
 さらに、Sb,CdTe,CdZnTe,PbI2 ,HgI,TlBrや、ノンドープのアモルファスSeまたはSe化合物の場合、電子の寄与が大きいものと正孔の寄与が大きいもとの両方がある。これらの場合、製膜条件の調節で電子の寄与が大きいものでも、正孔の寄与が大きいものでも、選択形成することができる。 Furthermore, Sb 2 S 3, CdTe, CdZnTe, or PbI 2, HgI 2, TlBr, when the non-doped amorphous Se or Se compound, there is both a large contribution original electronic ones large contribution and the hole. In these cases, the film can be selectively formed by adjusting the film forming conditions, regardless of whether the contribution of electrons is large or the contribution of holes is large.
 上述の本実施例1に係るフラットパネル型X線検出器(FPD)によれば、バイアス電圧給電用のケーブル4Aをバイアス電圧印加用の共通電極3に直接に接続せずに、共通電極3と導体(本実施例1では単線4B)とを接続し、半導体2以外の箇所で導体(単線4B)とケーブル4Aの芯線4aとを接続することで、導体(単線4B)を介してケーブル4Aと共通電極3とを間接的に接続する。導体(単線4B)はケーブル4Aよりも厚み方向に薄く形成されているので、ケーブル4Aよりも厚み方向に薄い導体(単線4B)で共通電極3に接続することになり、ケーブル4Aを被覆する絶縁体(すなわちケーブル4Aの被覆部分)による半導体2や共通電極3への損傷の発生や応力を回避することができる。また、ケーブル4Aよりも厚み方向に薄い導体(単線4B)で共通電極3に接続することで、接続作業が行いやすくなる。その結果、接続作業が行いやすく、半導体2や共通電極3への損傷の発生や応力を回避することができる。なお、バイアス電圧として20kVの高電圧を印加して沿面放電等の異常が発生しなかったことが確認されている。 According to the flat panel X-ray detector (FPD) according to the first embodiment described above, the cable 4A for supplying the bias voltage is not directly connected to the common electrode 3 for applying the bias voltage. By connecting the conductor (single wire 4B in the first embodiment) and connecting the conductor (single wire 4B) and the core wire 4a of the cable 4A at a place other than the semiconductor 2, the cable 4A is connected to the cable 4A via the conductor (single wire 4B). The common electrode 3 is indirectly connected. Since the conductor (single wire 4B) is formed thinner than the cable 4A in the thickness direction, the conductor (single wire 4B) thinner than the cable 4A is connected to the common electrode 3, and the insulation covering the cable 4A. It is possible to avoid the occurrence of damage and stress on the semiconductor 2 and the common electrode 3 due to the body (that is, the covering portion of the cable 4A). Further, by connecting to the common electrode 3 with a conductor (single wire 4B) that is thinner in the thickness direction than the cable 4A, the connection work is facilitated. As a result, the connection work is easy to perform, and it is possible to avoid the occurrence of damage and stress on the semiconductor 2 and the common electrode 3. It has been confirmed that a high voltage of 20 kV was applied as the bias voltage and no abnormalities such as creeping discharge occurred.
 本実施例1に係るFPDでは、好ましくは、少なくとも共通電極3、導体(本実施例1では単線4B)とケーブル4Aとの接続箇所を樹脂で封止する。このように樹脂で封止することで、共通電極3や、導体(単線4B)とケーブル4Aとの接続箇所を安定して設置し、FPD全体の機械的強度を増し、さらに共通電極3近傍での沿面放電やコロナ放電の発生を防止することができる。 In the FPD according to the first embodiment, preferably, at least the connection portion between the common electrode 3 and the conductor (single wire 4B in the first embodiment) and the cable 4A is sealed with resin. By sealing with the resin in this way, the connection portion between the common electrode 3 and the conductor (single wire 4B) and the cable 4A is stably installed, the mechanical strength of the entire FPD is increased, and further, in the vicinity of the common electrode 3 It is possible to prevent the occurrence of creeping discharge and corona discharge.
 本実施例1に係るFPDでは、半導体2をその周囲から取り囲む構造物(枠6)を備え、その構造物の箇所(本実施例1では枠6の溝6A)で導体(本実施例1では単線4B)とケーブル4Aとを接続している。本実施例1の場合には、構造物(枠6)と半導体2との間に空間的なスペースが少ない場合において有用である。 The FPD according to the first embodiment includes a structure (frame 6) surrounding the semiconductor 2 from the periphery thereof, and a conductor (a groove 6A of the frame 6 in the first embodiment) is a conductor (in the first embodiment, in the first embodiment). The single wire 4B) and the cable 4A are connected. In the case of the first embodiment, it is useful when there is little spatial space between the structure (frame 6) and the semiconductor 2.
 本実施例1に係るFPDでは、好ましくは、導体(本実施例1では単線4B)のうち、少なくとも共通電極3との接続箇所よりも外側の導体(単線4B)の下側に絶縁物(本実施例1では絶縁シート8)を設置する構造を有する。絶縁物(絶縁シート8)を設置しないと、導体(単線4B)のうち、少なくとも共通電極3との接続箇所よりも外側の導体(単線4B)で、放電を起こす可能性があるが、絶縁物(絶縁シート8)を設置することで放電を防止することができる。 In the FPD according to the first embodiment, preferably, an insulator (the main wire 4B in the first embodiment) is provided below the conductor (single wire 4B) outside the connection portion with the common electrode 3 at least. In Example 1, it has the structure which installs the insulating sheet 8). If an insulator (insulating sheet 8) is not installed, there is a possibility that a discharge will occur in at least the conductor (single wire 4B) outside the connecting portion with the common electrode 3 among the conductors (single wire 4B). Discharging can be prevented by installing (insulating sheet 8).
 本実施例1に係るFPDの製造方法から着目すると、以下のような作用・効果を奏する。すなわち、本実施例1に係るFPDの製造方法によれば、ステップS4では、バイアス電圧給電用のケーブル4Aよりも厚み方向に薄く形成された導体(本実施例1では単線4B)と、放射線(本実施例1ではX線)の入射により電荷を生成する放射線感応型の半導体2の入射側に面状に形成されたバイアス電圧印加用の共通電極3とを接続する。一方、ステップS4では、半導体2以外の箇所で導体(単線4B)とケーブル4Aの芯線4aとを接続する。ケーブル4Aを共通電極3に直接に接続せずに、ステップS4で、共通電極3と導体(単線4B)とを接続し、半導体2以外の箇所で導体(単線4B)とケーブル4Aの芯線4aとを接続することで、導体(単線4B)を介してケーブル4Aと共通電極3とを間接的に接続する。導体(単線4B)はケーブル4Aよりも厚み方向に薄く形成されているので、ケーブル4Aよりも厚み方向に薄い導体(単線4B)で共通電極3に接続することになり、接続作業が行いやすく、半導体2や共通電極3への損傷の発生や応力を回避することができる。 Focusing on the FPD manufacturing method according to the first embodiment, the following operations and effects are achieved. That is, according to the FPD manufacturing method according to the first embodiment, in step S4, the conductor (single wire 4B in the first embodiment) formed thinner in the thickness direction than the bias voltage feeding cable 4A and the radiation ( In the first embodiment, a bias voltage application common electrode 3 formed in a planar shape is connected to the incident side of the radiation-sensitive semiconductor 2 that generates charges by the incidence of X-rays). On the other hand, in step S4, the conductor (single wire 4B) and the core wire 4a of the cable 4A are connected at locations other than the semiconductor 2. The cable 4A is not directly connected to the common electrode 3, but the common electrode 3 and the conductor (single wire 4B) are connected in step S4, and the conductor (single wire 4B) and the core wire 4a of the cable 4A are connected at a place other than the semiconductor 2. By connecting these, the cable 4A and the common electrode 3 are indirectly connected via a conductor (single wire 4B). Since the conductor (single wire 4B) is formed thinner in the thickness direction than the cable 4A, it is connected to the common electrode 3 with a conductor (single wire 4B) thinner in the thickness direction than the cable 4A. It is possible to avoid the occurrence of damage and stress on the semiconductor 2 and the common electrode 3.
 本実施例1に係るFPDの製造方法では、ステップS2では、電荷を蓄積して読み出す回路(本実施例1では蓄積・読み出し用電気回路12)を形成したアクティブマトリックス基板1上に、半導体2をその周囲から取り囲む枠6を取り付ける。さらに、本実施例1の場合には、上述したステップS4では、ステップS2で取り付けられた枠6からなる構造物の箇所(本実施例1では枠6の溝6A)で導体(本実施例1では単線4B)とケーブル4Aの芯線4aとを接続している。本実施例1の場合には、本実施例1に係るFPDでも述べたように、構造物(枠6)と半導体2との間に空間的なスペースが少ない場合において有用である。 In the FPD manufacturing method according to the first embodiment, in step S2, the semiconductor 2 is formed on the active matrix substrate 1 on which a circuit for accumulating and reading electric charges (accumulation / readout electric circuit 12 in the first embodiment) is formed. A frame 6 surrounding the periphery is attached. Further, in the case of the first embodiment, in step S4 described above, the conductor (the first embodiment 1) is provided at the position of the structure including the frame 6 attached in step S2 (the groove 6A of the frame 6 in the first embodiment). Then, the single wire 4B) and the core wire 4a of the cable 4A are connected. In the case of the first embodiment, as described in the FPD according to the first embodiment, it is useful when there is little spatial space between the structure (frame 6) and the semiconductor 2.
 また、本実施例1の場合には、ステップS1では、ケーブル4Aを被覆する絶縁体がなくケーブル4Aの導線(ここでは芯線4a)が剥きだしになっている部分の下側に絶縁物(本実施例1では絶縁シート9)をアクティブマトリックス基板1上に設置し、ステップS3では、導体(本実施例1では単線4B)のうち、少なくとも共通電極3との接続箇所よりも外側の導体(単線4B)の下側に絶縁物(本実施例1では絶縁シート8)を設置する。また、ステップS2では、ステップS1で設置された絶縁物(絶縁シート9)とともにアクティブマトリックス基板1上に枠6を取り付け、ステップS3では、ステップS2で取り付けられた枠6の溝6Aで、かつ導体(単線4B)とケーブル4Aの芯線4aとの接続箇所に嵌まるように絶縁物(絶縁シート8)を設置する。絶縁物(絶縁シート9)を設置しないと、ケーブル4Aを被覆する絶縁体がなくケーブル4Aの導線(芯線4a)が剥きだしになっている部分と、アクティブマトリックス基板1上に形成された回路パターンとで放電を起こす可能性があるが、絶縁物(絶縁シート9)を設置することで放電を防止することができる。また、本実施例1に係るFPDでも述べたように、絶縁物(絶縁シート8)を設置しないと、導体(単線4B)のうち、少なくとも共通電極3との接続箇所よりも外側の導体(単線4B)と、アクティブマトリックス基板1上に形成された回路パターンとで放電を起こす可能性があるが、絶縁物(絶縁シート8)を設置することで放電を防止することができる。 Further, in the case of the first embodiment, in step S1, there is no insulator (the main wire 4a in this case) without an insulator covering the cable 4A and the conductor (the core wire 4a in this case) is exposed. In the first embodiment, the insulating sheet 9) is installed on the active matrix substrate 1, and in step S3, the conductor (single wire 4B in the first embodiment) is at least a conductor (single wire) outside the connecting portion with the common electrode 3. 4B) An insulator (in this embodiment, the insulating sheet 8) is installed on the lower side. In step S2, the frame 6 is attached on the active matrix substrate 1 together with the insulator (insulating sheet 9) installed in step S1, and in step S3, the groove 6A of the frame 6 attached in step S2 is used. An insulator (insulating sheet 8) is installed so as to fit in a connecting portion between the (single wire 4B) and the core wire 4a of the cable 4A. If an insulator (insulating sheet 9) is not installed, there is no insulator covering the cable 4A and the conductor (core wire 4a) of the cable 4A is exposed, and a circuit pattern formed on the active matrix substrate 1 However, it is possible to prevent discharge by installing an insulator (insulating sheet 9). Further, as described in the FPD according to the first embodiment, if the insulator (insulating sheet 8) is not installed, the conductor (single wire 4B) is at least a conductor (single wire) outside the connection portion with the common electrode 3 at least. 4B) and a circuit pattern formed on the active matrix substrate 1 may cause a discharge, but the discharge can be prevented by installing an insulator (insulating sheet 8).
 次に、図面を参照してこの発明の実施例2を説明する。図12(a)は、実施例2に係る直接変換型のフラットパネル型X線検出器(FPD)の概略平面図であり、図12(b)は、図12(a)のA-A矢視断面図であり、図12(c)は、図12(a)のB-B矢視断面図である。上述した実施例1と共通する箇所については、同じ符号を付してその説明を省略するとともに図示を省略する。また、図1(a)と同様に、図12(a)では、上部カバーガラスの図示を省略する。 Next, Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 12A is a schematic plan view of a direct conversion flat panel X-ray detector (FPD) according to the second embodiment, and FIG. 12B is an AA arrow in FIG. FIG. 12C is a cross-sectional view taken along the line BB in FIG. 12A. The portions common to the above-described first embodiment are denoted by the same reference numerals, the description thereof is omitted, and the illustration is omitted. Further, similarly to FIG. 1A, the illustration of the upper cover glass is omitted in FIG.
 上述した実施例1に係るFPDでは、図1、図5~図10に示すように、ケーブル4Aよりも厚み方向に薄く形成された導体として単線4Bを採用したが、本実施例2に係るFPDは、図12に示すように、ケーブル4Aよりも厚み方向に薄く形成された導体としてリボン状金属板4Cを採用する。すなわち、リード線4は、図12(a)に示すように、ケーブル4Aと、そのケーブル4Aよりも厚み方向に薄く形成されたリボン状金属板4Cとで形成されている。ケーブル4Aの芯線4aとリボン状金属板4Cとを導電ペースト(例えばNi系導電ペースト)を介して接続するとともに、リボン状金属板4Cとを同じく導電ペーストを介して接続する。実施例1と同様に、リボン状金属板4Cとケーブル4Aの芯線4aとの接続箇所は、半導体2以外の箇所となっている。また、導体がリボン状金属板4Cのように板状であるので、実施例1の単線4Bよりも接続される面積が広く、導通抵抗が低く、安定してFPDを製造することができる。リボン状金属板4Cは、この発明における導体に相当する。 In the FPD according to the first embodiment described above, as shown in FIGS. 1 and 5 to 10, the single wire 4B is adopted as the conductor formed thinner in the thickness direction than the cable 4A. However, the FPD according to the second embodiment is used. As shown in FIG. 12, a ribbon-like metal plate 4C is adopted as a conductor formed thinner in the thickness direction than the cable 4A. That is, as shown in FIG. 12A, the lead wire 4 is formed of a cable 4A and a ribbon-like metal plate 4C formed thinner in the thickness direction than the cable 4A. The core 4a of the cable 4A and the ribbon-like metal plate 4C are connected via a conductive paste (for example, Ni-based conductive paste), and the ribbon-like metal plate 4C is also connected via the conductive paste. As in the first embodiment, the connection place between the ribbon-like metal plate 4C and the core wire 4a of the cable 4A is a place other than the semiconductor 2. Further, since the conductor is plate-like like the ribbon-like metal plate 4C, the area to be connected is larger than that of the single wire 4B of Example 1, the conduction resistance is low, and the FPD can be manufactured stably. Ribbon-shaped metal plate 4C corresponds to the conductor in the present invention.
 また、上述した実施例1に係るFPDでは、図1、図5~図10に示すように、ケーブル4Aを被覆する絶縁体がなくケーブル4Aの導線(ここでは芯線4a)が剥きだしになっている部分の下側に絶縁物(実施例1では絶縁シート9)をアクティブマトリックス基板1上に設置し、導体(実施例1では単線4B)のうち、少なくとも共通電極3との接続箇所よりも外側の導体(単線4B)の下側に絶縁物(実施例1では絶縁シート8)を設置したが、本実施例2に係るFPDは、図12に示すように、導体(本実施例2ではリボン状金属板4C)のうち、少なくとも共通電極3との接続箇所よりも外側の導体(リボン状金属板4C)の下側、およびケーブル4Aを被覆する絶縁体がなくケーブル4Aの導線(芯線4a)が剥きだしになっている部分の下側に絶縁シート8´を設置している。つまり、上述した実施例1では、2つの絶縁シート8、9を単線4B、ケーブル4Aの芯線4aの大きさに合わせて設置していたのに対して、本実施例2では、1つの絶縁シート8´にして、実施例1の構造のときよりも簡素化している。本実施例2では、図12(a)、図12(c)に示すように枠6に段差6Cを設け、この段差6Cに沿うように上述した絶縁シート8´を設置する。絶縁シート8´は、この発明における絶縁物に相当する。 In the FPD according to the first embodiment described above, as shown in FIGS. 1 and 5 to 10, there is no insulator covering the cable 4A, and the conductor of the cable 4A (here, the core wire 4a) is exposed. An insulating material (insulating sheet 9 in the first embodiment) is placed on the active matrix substrate 1 below the portion where it is present, and at least outside of the conductor (single wire 4B in the first embodiment) connected to the common electrode 3. Although an insulator (insulating sheet 8 in Example 1) was installed under the conductor (single wire 4B), the FPD according to Example 2 has a conductor (ribbon in Example 2) as shown in FIG. 4C), at least the lower side of the conductor (ribbon-like metal plate 4C) outside the connection point with the common electrode 3, and the conductor of the cable 4A (core wire 4a) without an insulator covering the cable 4A Becomes bare The lower part are being installed insulating sheet 8 '. That is, in the above-described first embodiment, the two insulating sheets 8 and 9 are installed according to the size of the single wire 4B and the core wire 4a of the cable 4A, whereas in the second embodiment, one insulating sheet is provided. 8 'is simplified compared to the structure of the first embodiment. In Example 2, a step 6C is provided on the frame 6 as shown in FIGS. 12A and 12C, and the above-described insulating sheet 8 ′ is installed along the step 6C. The insulating sheet 8 ′ corresponds to an insulator in the present invention.
 次に、FPDの製造方法について、図5、図13~図17を参照して説明する。図5は、実施例2に係るフラットパネル型X線検出器(FPD)の製造工程を示す概略図であり、図5については実施例1、2と共用する。図13は、実施例2に係る一連のフラットパネル型X線検出器(FPD)の製造方法の流れを示すフローチャートであり、図14~図17は、実施例2に係るフラットパネル型X線検出器(FPD)の製造工程を示す概略図である。図12と同様に、図14(a)~図17(a)は、概略平面図であり、図14(b)~図17(b)は、図14(a)~図17(a)のA-A矢視断面図であり、図14(c)~図17(c)は、図14(a)~図17(a)のB-B矢視断面図である。また、図12(a)と同様に、図14(a)~図17(a)では、上部カバーガラスの図示を省略する。 Next, an FPD manufacturing method will be described with reference to FIGS. 5 and 13 to 17. FIG. 5 is a schematic view showing a manufacturing process of a flat panel X-ray detector (FPD) according to the second embodiment. FIG. 5 is shared with the first and second embodiments. FIG. 13 is a flowchart showing the flow of a series of manufacturing methods of a flat panel X-ray detector (FPD) according to the second embodiment, and FIGS. 14 to 17 show the flat panel X-ray detection according to the second embodiment. It is the schematic which shows the manufacturing process of a container (FPD). Similarly to FIG. 12, FIGS. 14 (a) to 17 (a) are schematic plan views, and FIGS. 14 (b) to 17 (b) are the same as FIGS. 14 (a) to 17 (a). FIGS. 14 (c) to 17 (c) are cross-sectional views taken along the line BB in FIGS. 14 (a) to 17 (a). Similarly to FIG. 12A, the illustration of the upper cover glass is omitted in FIGS. 14A to 17A.
 (ステップT2)枠の取り付け
 図5に示すように、アクティブマトリックス基板1の収集電極の入射面側に半導体2を積層し、その半導体2の入射側に共通電極3を面状に形成して積層した状態で、アクティブマトリックス基板1上に、図14に示すように、半導体2をその周囲から取り囲む枠6を取り付ける。上述したように、この枠6には、図14(a)~図14(c)に示すように段差6Cを設ける。この段差6Cについては、アクティブマトリックス基板1上に枠6を取り付けた後に設けてもよいし、予め設けた後でアクティブマトリックス基板1上に枠6を取り付けてもよい。このステップT2は、(C)の枠取り付け工程に相当する。
(Step T2) Attaching the Frame As shown in FIG. 5, the semiconductor 2 is laminated on the incident surface side of the collecting electrode of the active matrix substrate 1, and the common electrode 3 is formed in a planar shape on the incident side of the semiconductor 2 and laminated. In this state, a frame 6 surrounding the semiconductor 2 from its periphery is attached on the active matrix substrate 1 as shown in FIG. As described above, the frame 6 is provided with a step 6C as shown in FIGS. 14 (a) to 14 (c). The step 6C may be provided after the frame 6 is mounted on the active matrix substrate 1, or the frame 6 may be mounted on the active matrix substrate 1 after being provided in advance. This step T2 corresponds to the frame attaching step (C).
 (ステップT3)絶縁シートの設置
 リボン状金属板4C(図12、図16、図17を参照)のうち、図15に示すように、共通電極3との接続箇所よりも外側のリボン状金属板4Cの下側、およびケーブル4A(図12、図16、図17を参照)を被覆する絶縁体がなくケーブル4Aの導線(芯線4a)が剥きだしになっている部分の下側に絶縁シート8´を設置する。具体的には、ステップT3で取り付けられた枠6の段差6Cに沿うように絶縁シート8´を設置する。なお、絶縁シート8´の設置場所については、図16(b)、図17(b)では金属板4Cと共通電極3との接続箇所を含ませたが、金属板4Cと共通電極3との接続箇所を含ませてもよい。すなわち、共通電極3との接続箇所において金属板4Cの下側にも絶縁シート8´を設置してもよく、金属板4Cのうち、少なくとも共通電極3との接続箇所よりも外側の金属板4Cの下側に絶縁シート8´を設置すれば特に限定されない。このステップT3は、(E´)の設置工程に相当する。
(Step T3) Installation of Insulating Sheet Of the ribbon-like metal plate 4C (see FIGS. 12, 16, and 17), as shown in FIG. 15, the ribbon-like metal plate outside the connection location with the common electrode 3 Insulating sheet 8 below 4C and below the portion where cable 4A (see FIGS. 12, 16, and 17) does not have an insulator to cover and conductor 4 (core wire 4a) of cable 4A is exposed Install ´. Specifically, the insulating sheet 8 ′ is installed along the step 6C of the frame 6 attached in Step T3. In addition, about the installation place of insulating sheet 8 ', although the connection location of the metal plate 4C and the common electrode 3 was included in FIG.16 (b) and FIG.17 (b), the metal plate 4C and the common electrode 3 are included. You may include a connection location. In other words, the insulating sheet 8 ′ may be installed below the metal plate 4 </ b> C at the connection location with the common electrode 3. Of the metal plates 4 </ b> C, the metal plate 4 </ b> C outside the connection location with at least the common electrode 3. If insulating sheet 8 'is installed in the lower side, it will not be specifically limited. This step T3 corresponds to the installation step (E ′).
 (ステップT4)ケーブル・金属板の設置
 図16に示すように、ステップT3で設置された絶縁シート8´の上にケーブル4Aおよび芯線4aを上に設置し、リボン状金属板4Cを設置する。金属板4Cと共通電極3との間を、導電ペーストを介在させて接着して接続し、金属板4Cの下に芯線4aを潜り込ませて導電ペーストを介して接続する。上部カバーガラス5(図17を参照)がこのステップT4の時点では設置されていないので、上方からケーブル4A・金属板4Cを容易に設置することができる。なお、ステップT4よりも前の時点で、予め、金属板4Cとケーブル4Aの芯線4aとを別の場所ではんだ付けで接続して、接続された金属板4Cとケーブル4Aの芯線4aとを絶縁シート8´の上に設置した上で、金属板4Cと共通電極3とを接続してもよい。このステップT4は、(A)の第1接続工程に相当し、(B)の第2接続工程に相当する。
(Step T4) Installation of Cable / Metal Plate As shown in FIG. 16, the cable 4A and the core wire 4a are installed on the insulating sheet 8 ′ installed in step T3, and the ribbon-shaped metal plate 4C is installed. The metal plate 4C and the common electrode 3 are connected by bonding with a conductive paste interposed therebetween, and the core wire 4a is inserted under the metal plate 4C to be connected through the conductive paste. Since the upper cover glass 5 (see FIG. 17) is not installed at the time of step T4, the cable 4A and the metal plate 4C can be easily installed from above. In addition, at the time before step T4, the metal plate 4C and the core wire 4a of the cable 4A are connected by soldering in another place in advance, and the connected metal plate 4C and the core wire 4a of the cable 4A are insulated. The metal plate 4C and the common electrode 3 may be connected after being installed on the sheet 8 ′. This step T4 corresponds to the first connection step (A) and corresponds to the second connection step (B).
 (ステップT5)上部カバーガラスの設置
 ステップT4でケーブル4A・金属板4Cを設置した後に、図17に示すように、枠6の上部に上部カバーガラス5を設置する。
(Step T5) Installation of Upper Cover Glass After the cable 4A and the metal plate 4C are installed in Step T4, the upper cover glass 5 is installed on the upper portion of the frame 6 as shown in FIG.
 (ステップT6)樹脂封止
 アクティブマトリックス基板1と上部カバーガラス5との間に液状の常温硬化型樹脂組成物を注入硬化させることで、硬化後の常温硬化型樹脂組成物は樹脂7となって、硬化性合成樹脂からなる樹脂7によって上部カバーガラス5を固定形成する。この一連のステップT1~T6を行うことで、図12に示すようなFPDが完成する。
(Step T6) Resin Encapsulation A liquid room temperature curable resin composition is injected and cured between the active matrix substrate 1 and the upper cover glass 5, so that the cured room temperature curable resin composition becomes a resin 7. The upper cover glass 5 is fixedly formed by a resin 7 made of a curable synthetic resin. By performing a series of steps T1 to T6, an FPD as shown in FIG. 12 is completed.
 上述の本実施例2に係るフラットパネル型X線検出器(FPD)およびその製造方法によれば、上述した実施例1と同様に、バイアス電圧給電用のケーブル4Aをバイアス電圧印加用の共通電極3に直接に接続せずに、共通電極3と導体(本実施例2ではリボン状金属板4C)とを接続し、半導体2以外の箇所で導体(金属板4C)とケーブル4Aの芯線4aとを接続することで、導体(金属板4C)を介してケーブル4Aと共通電極3とを間接的に接続する。導体(金属板4C)はケーブル4Aよりも厚み方向に薄く形成されているので、ケーブル4Aよりも厚み方向に薄い導体(金属板4C)で共通電極3に接続することになり、接続作業が行いやすく、半導体2や共通電極3への損傷の発生や応力を回避することができる。 According to the flat panel X-ray detector (FPD) and the manufacturing method thereof according to the second embodiment described above, the bias voltage supply cable 4A is connected to the common electrode for applying the bias voltage as in the first embodiment. 3 is connected directly to the common electrode 3 and the conductor (ribbon-shaped metal plate 4C in the present embodiment 2), and the conductor (metal plate 4C) and the core wire 4a of the cable 4A are connected to a portion other than the semiconductor 2 By connecting these, the cable 4A and the common electrode 3 are indirectly connected via a conductor (metal plate 4C). Since the conductor (metal plate 4C) is formed thinner than the cable 4A in the thickness direction, the conductor (metal plate 4C) is thinner than the cable 4A in the thickness direction and is connected to the common electrode 3, and the connection work is performed. It is easy to avoid the occurrence of damage and stress on the semiconductor 2 and the common electrode 3.
 上述した実施例1と同様に、本実施例2に係るFPDでは、好ましくは、少なくとも共通電極3、導体(本実施例2ではリボン状金属板4C)とケーブル4Aとの接続箇所を樹脂で封止する。このように樹脂で封止することで、共通電極3や、導体(金属板4C)とケーブル4Aとの接続箇所を安定して設置し、FPD全体の機械的強度を増し、さらに共通電極3近傍での沿面放電やコロナ放電の発生を防止することができる。 Similar to the first embodiment described above, in the FPD according to the second embodiment, it is preferable that at least the connection portion between the common electrode 3 and the conductor (ribbon-shaped metal plate 4C in the second embodiment) and the cable 4A be sealed with resin. Stop. By sealing with the resin in this way, the connection portion between the common electrode 3 and the conductor (metal plate 4C) and the cable 4A is stably installed, the mechanical strength of the entire FPD is increased, and the vicinity of the common electrode 3 is further increased. It is possible to prevent the occurrence of creeping discharge and corona discharge.
 上述した実施例1と同様に、本実施例2では、電荷を蓄積して読み出す回路(本実施例2では蓄積・読み出し用電気回路12)を形成したアクティブマトリックス基板1上に、半導体2をその周囲から取り囲む枠6を取り付ける。さらに、本実施例2の場合には、枠6からなる構造物の箇所(本実施例2では枠6の段差6C)で導体(本実施例2ではリボン状金属板4C)とケーブル4Aの芯線4aとを接続している。本実施例2の場合には、上述した実施例1と同様に、構造物(枠6)と半導体2との間に空間的なスペースが少ない場合において有用である。 Similar to the first embodiment described above, in the second embodiment, the semiconductor 2 is placed on the active matrix substrate 1 on which a circuit for accumulating and reading electric charges (the electric circuit 12 for accumulation / readout in the second embodiment) is formed. A frame 6 surrounding from the periphery is attached. Further, in the case of the second embodiment, the conductor (the ribbon-like metal plate 4C in the second embodiment) and the core wire of the cable 4A at the position of the structure composed of the frame 6 (the step 6C of the frame 6 in the second embodiment). 4a is connected. In the case of the second embodiment, similarly to the first embodiment described above, it is useful when the space between the structure (frame 6) and the semiconductor 2 is small.
 上述した実施例1と同様に、本実施例2では、導体(本実施例2ではリボン状金属板4C)のうち、少なくとも共通電極3との接続箇所よりも外側の導体(金属板4C)の下側に絶縁物(本実施例2では絶縁シート8´)を設置する構造を有する。絶縁物(絶縁シート8´)を設置することで放電を防止することができる。 Similar to the first embodiment described above, in the second embodiment, among the conductors (ribbon-like metal plate 4C in the second embodiment), at least the conductor (metal plate 4C) outside the connection portion with the common electrode 3 is used. It has a structure in which an insulator (insulating sheet 8 ′ in the present embodiment 2) is installed on the lower side. Discharging can be prevented by installing an insulator (insulating sheet 8 ').
 特に、本実施例2の場合には、ステップT3では、導体(本実施例2ではリボン状金属板4C)のうち、少なくとも共通電極3との接続箇所よりも外側の導体(金属板4C)の下側、およびケーブル4Aを被覆する絶縁体がなくケーブル4Aの導線(ここでは芯線4a)が剥きだしになっている部分の下側に絶縁物(本実施例2では絶縁シート8´)をアクティブマトリックス基板1上に設置する。絶縁物(絶縁シート8´)を設置することで放電を防止することができる。 In particular, in the case of the second embodiment, in step T3, among the conductors (ribbon-like metal plate 4C in the second embodiment), at least the conductor (metal plate 4C) outside the connection portion with the common electrode 3 is used. An insulator (insulating sheet 8 'in the present embodiment 2) is activated on the lower side and below the portion where there is no insulator covering the cable 4A and the conductive wire (core wire 4a) of the cable 4A is exposed. It is installed on the matrix substrate 1. Discharging can be prevented by installing an insulator (insulating sheet 8 ').
 次に、図面を参照してこの発明の実施例3を説明する。図18は、実施例3に係る直接変換型のフラットパネル型X線検出器(FPD)の概略平面図であり、図18(b)は、図18(a)のA-A矢視断面図であり、図18(c)は、図18(a)のB-B矢視断面図である。上述した実施例1、2と共通する箇所については、同じ符号を付してその説明を省略するとともに図示を省略する。また、図1(a)と同様に、図18(a)では、上部カバーガラスの図示を省略する。 Next, Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 18 is a schematic plan view of a direct conversion type flat panel X-ray detector (FPD) according to the third embodiment, and FIG. 18B is a cross-sectional view taken along line AA in FIG. FIG. 18C is a cross-sectional view taken along the line BB in FIG. The parts common to the above-described first and second embodiments are denoted by the same reference numerals, description thereof is omitted, and illustration is omitted. Further, similarly to FIG. 1A, the illustration of the upper cover glass is omitted in FIG.
 上述した実施例1、2に係るFPDでは、図1、図12に示すように、枠6からなる構造物の箇所(実施例1では枠6の溝6A、実施例2では枠6の段差6C)で導体(実施例1では単線4A、実施例2ではリボン状金属板4C)とケーブル4Aの芯線4aとを接続したが、本実施例3に係るFPDは、図18に示すように、枠6からなる構造物の内部であって、かつ半導体2以外の箇所で導体とケーブル4Aの芯線4aとを接続する。導体として実施例1と同じ単線4Bを採用する。 In the FPDs according to the first and second embodiments described above, as shown in FIGS. 1 and 12, the portion of the structure including the frame 6 (the groove 6A of the frame 6 in the first embodiment, the step 6C of the frame 6 in the second embodiment). ), The conductor (single wire 4A in Example 1, ribbon-like metal plate 4C in Example 2) and the core wire 4a of the cable 4A are connected. As shown in FIG. The conductor and the core wire 4a of the cable 4A are connected to each other inside the structure composed of 6 and at a place other than the semiconductor 2. The same single wire 4B as in the first embodiment is adopted as the conductor.
 具体的には、枠6と半導体2との間に中継台座Sを設置する。この中継台座Sの上に実施例2と同じ絶縁シート8´を設置して、絶縁シート8´の上にケーブル4Aおよび芯線4aを上に設置し、単線4Bを設置する。なお、絶縁シート8´の代わりに実施例1の絶縁シート8、9を設置して、それぞれの上にケーブル4A・単線4Bを設置してもよい。中継台座Sは絶縁性であり、エポキシ樹脂,ポリウレタン樹脂,アクリル樹脂等の(硬化後の硬度が高い)硬質樹脂材料などが用いられる。 Specifically, the relay pedestal S is installed between the frame 6 and the semiconductor 2. The same insulating sheet 8 ′ as that of the second embodiment is installed on the relay pedestal S, the cable 4A and the core wire 4a are installed on the insulating sheet 8 ′, and the single wire 4B is installed. Instead of the insulating sheet 8 ′, the insulating sheets 8 and 9 of Example 1 may be installed, and the cable 4A and the single wire 4B may be installed on each of them. The relay base S is insulative, and a hard resin material (high hardness after curing) such as an epoxy resin, a polyurethane resin, or an acrylic resin is used.
 本実施例3の場合には、枠6からなる構造物と半導体2との間に空間的なスペースがあって、スペースに余裕があるときに有用である。さらに、本実施例3の場合には、構造物の箇所で導体(本実施例3では単線4B)とケーブル4Aとを接続せずに済むので、より簡単な構造とすることができる。本実施例3では、導体として実施例1と同じ単線4Bを採用しているが、実施例2と同じリボン状金属板4Cを採用してもよい。 In the case of the third embodiment, it is useful when there is a space between the structure composed of the frame 6 and the semiconductor 2 and there is room in the space. Furthermore, in the case of the third embodiment, since it is not necessary to connect the conductor (single wire 4B in the third embodiment) and the cable 4A at the place of the structure, a simpler structure can be obtained. In the third embodiment, the same single wire 4B as that of the first embodiment is employed as the conductor, but the same ribbon-like metal plate 4C as that of the second embodiment may be employed.
 この発明は、上記実施形態に限られることはなく、下記のように変形実施することができる。 The present invention is not limited to the above embodiment, and can be modified as follows.
 (1)上述した各実施例では、フラットパネル型X線検出器に代表される放射線検出器は、2次元アレイタイプであったが、この発明の放射線検出器は、収集電極が1次元状マトリックス配列で形成されている1次元アレイタイプでもよいし、放射線検出信号取り出し用の電極が1個だけの非アレイタイプでもよい。 (1) In each of the above-described embodiments, the radiation detector typified by the flat panel X-ray detector is a two-dimensional array type. However, in the radiation detector of the present invention, the collection electrode is a one-dimensional matrix. A one-dimensional array type formed by an array may be used, or a non-array type having only one electrode for extracting a radiation detection signal may be used.
 (2)上述した各実施例では、放射線検出器としてX線検出器を例に採って説明したが、X線以外の放射線(例えばガンマ線)を検出する放射線検出器(例えばガンマ線検出器)にも適用できる。 (2) In each of the above-described embodiments, the X-ray detector is described as an example of the radiation detector. However, the radiation detector (for example, a gamma ray detector) that detects radiation other than the X-ray (for example, gamma ray) is also described. Applicable.
 (3)上述した各実施例では、沿面放電を防止するために、共通電極3を半導体2よりも内側に形成したが、沿面放電を考慮しない場合には、共通電極3の端縁部と半導体2の端縁部とを揃えてもよいし、共通電極3を半導体2よりも外側に形成してもよい。 (3) In each of the above-described embodiments, the common electrode 3 is formed on the inner side of the semiconductor 2 in order to prevent the creeping discharge. However, when the creeping discharge is not considered, the edge of the common electrode 3 and the semiconductor 2 may be aligned with each other, or the common electrode 3 may be formed outside the semiconductor 2.
 (4)上述した各実施例では、少なくとも共通電極3、導体(実施例1、3では単線4B)とケーブル4Aとの接続箇所を樹脂で封止したが、印加される電圧が低いなどで、沿面放電を考慮しない場合には、必ずしも樹脂で封止する必要はない。 (4) In each of the above-described examples, at least the common electrode 3, the conductor (single wire 4B in Examples 1 and 3) and the cable 4A are sealed with resin, but the applied voltage is low, etc. When creeping discharge is not considered, it is not always necessary to seal with resin.
 (5)上述した各実施例では、絶縁物(実施例1では絶縁シート8、9、実施例2、3では絶縁シート8´)を設置して放電を防止したが、放電が生じない、あるいは放電を考慮しない場合には、必ずしも絶縁物を設置する必要はない。 (5) In each of the above-described examples, an insulator (insulating sheets 8 and 9 in Example 1 and insulating sheet 8 'in Examples 2 and 3) was installed to prevent discharge, but no discharge occurred, or In the case where discharge is not considered, it is not always necessary to install an insulator.
 (6)上述した実施例1、3では、導体として単線4Bを採用したが、必ずしも単線に限定されない。ケーブルの芯線のような縒り線を導体として使用してもよい。 (6) In the first and third embodiments described above, the single wire 4B is used as the conductor, but the conductor is not necessarily limited to a single wire. A twisted wire such as a cable core wire may be used as the conductor.
 (7)導体と共通電極とを接続する(A)の第1接続工程、半導体以外の箇所で導体とケーブルとを接続する(B)の第2接続工程の順番は特に限定されない。(A)の第1接続工程の後に(B)の第2接続工程を行ってもよいし、逆に(B)の第2接続工程の後に(A)の第1接続工程を行ってもよいし、(A)の第1接続工程と(B)の第2接続工程とを同時に並行して行ってもよい。 (7) The order of the first connection step (A) for connecting the conductor and the common electrode and the second connection step (B) for connecting the conductor and the cable at a place other than the semiconductor are not particularly limited. The second connection step (B) may be performed after the first connection step (A), and conversely, the first connection step (A) may be performed after the second connection step (B). Then, the first connection step (A) and the second connection step (B) may be performed in parallel.
 (8)上述した各実施例では、電荷を蓄積して読み出す回路を形成した基板(アクティブマトリックス基板1)上に、半導体をその周囲から取り囲む枠を取り付けたが、単に半導体等を支持する支持基板上に枠を取り付けてもよい。 (8) In each of the above-described embodiments, a frame surrounding the semiconductor from its periphery is attached on the substrate (active matrix substrate 1) on which a circuit for accumulating and reading out charges is formed. A frame may be attached on top.
 (9)実施例3に示した中継台座Sは、絶縁性を有しているものであれば必ずしも樹脂に限定されず、たとえばガラスやセラミックスのようなものを使用してもよい。 (9) The relay pedestal S shown in Example 3 is not necessarily limited to resin as long as it has insulating properties, and for example, glass or ceramics may be used.
 (10)上述した各実施例では、単線4Bと共通電極3とを導電ペーストを介して接続したが、単線4Bと共通電極3との接続態様については特に限定されない。例えば、図19(a)の断面図に示すように、エポキシ樹脂,ポリウレタン樹脂,アクリル樹脂等の(硬化後の硬度が高い)硬質樹脂材料からなる台座S(実施例3で述べた中継台座Sと同じ構造)を放射線検出有効エリアSA外に半導体2の入射面に設置し、共通電極3がその台座Sの一部を少なくとも覆うように形成し、単線4Bが共通電極3の入射面のうちの台座Sに位置する箇所に接続されるように形成してもよい。また、例えば、図19(b)の拡大平面図に示すように、面状に形成された導電性の板材として小判状の銅板4Dと単線4Bとを予めハンダ等で接続したものを、導電ペースト(例えばNiペースト)を介して共通電極3に接続してもよい。このように接続することで、面状に形成された銅板4Dが介在した状態となり、たとえ抵抗値が高い導電ペーストを用いたとしても接続抵抗を下げることができ、銀ペーストを使用したときと同程度になるなど、導電ペーストの選択の幅を広げるなどの効果をも奏する。なお、銀ペーストよりも抵抗値が高いNiペーストを用いることで、銀を用いることによる半導体2への拡散による膜の貫通放電を回避することができる。 (10) In each embodiment described above, the single wire 4B and the common electrode 3 are connected via the conductive paste, but the connection mode between the single wire 4B and the common electrode 3 is not particularly limited. For example, as shown in the cross-sectional view of FIG. 19A, a base S made of a hard resin material (high hardness after curing) such as an epoxy resin, a polyurethane resin, an acrylic resin (the relay base S described in the third embodiment). Is formed on the incident surface of the semiconductor 2 outside the radiation detection effective area SA, the common electrode 3 is formed so as to cover at least a part of the pedestal S, and the single wire 4B is included in the incident surface of the common electrode 3 You may form so that it may be connected to the location located in the base S. Further, for example, as shown in the enlarged plan view of FIG. 19 (b), a conductive paste in which an oval copper plate 4D and a single wire 4B are connected in advance by solder or the like as a conductive plate material formed in a planar shape. You may connect to the common electrode 3 via (for example, Ni paste). By connecting in this way, a planar copper plate 4D is interposed, and even if a conductive paste having a high resistance value is used, the connection resistance can be lowered, the same as when using a silver paste. For example, the effect of expanding the selection range of the conductive paste can be achieved. Note that by using a Ni paste having a higher resistance value than that of the silver paste, it is possible to avoid a through discharge of the film due to diffusion into the semiconductor 2 due to the use of silver.

Claims (11)

  1.  放射線を検出する放射線検出器であって、放射線の入射により電荷を生成する放射線感応型の半導体と、その半導体の前記入射側に面状に形成されたバイアス電圧印加用の共通電極と、バイアス電圧給電用のケーブルと、そのケーブルよりも厚み方向に薄く形成された導体とを備え、前記共通電極と前記導体とを接続し、前記半導体以外の箇所で前記導体と前記ケーブルとを接続することを特徴とする放射線検出器。 A radiation detector that detects radiation, a radiation-sensitive semiconductor that generates a charge upon incidence of radiation, a common electrode for applying a bias voltage formed in a planar shape on the incident side of the semiconductor, and a bias voltage A power supply cable and a conductor formed thinner in the thickness direction than the cable, connecting the common electrode and the conductor, and connecting the conductor and the cable at a place other than the semiconductor Characteristic radiation detector.
  2.  請求項1に記載の放射線検出器において、少なくとも前記共通電極、前記導体と前記ケーブルとの接続箇所を樹脂で封止することを特徴とする放射線検出器。 2. The radiation detector according to claim 1, wherein at least a connection portion between the common electrode, the conductor and the cable is sealed with a resin.
  3.  請求項1または請求項2に記載の放射線検出器において、前記半導体をその周囲から取り囲む構造物を備え、その構造物の箇所で前記導体と前記ケーブルとを接続することを特徴とする放射線検出器。 3. The radiation detector according to claim 1, further comprising a structure surrounding the semiconductor from the periphery thereof, wherein the conductor and the cable are connected at a position of the structure. 4. .
  4.  請求項1または請求項2に記載の放射線検出器において、前記半導体をその周囲から取り囲む構造物を備え、その構造物の内部であって、かつ前記半導体以外の箇所で前記導体と前記ケーブルとを接続することを特徴とする放射線検出器。 3. The radiation detector according to claim 1, further comprising a structure surrounding the semiconductor from the periphery thereof, wherein the conductor and the cable are disposed inside the structure and at a place other than the semiconductor. A radiation detector characterized by being connected.
  5.  請求項1から請求項4のいずれかに記載の放射線検出器において、前記導体のうち、少なくとも前記共通電極との接続箇所よりも外側の導体の下側に絶縁物を設置する構造を有することを特徴とする放射線検出器。 5. The radiation detector according to claim 1, further comprising: a structure in which an insulator is installed on a lower side of a conductor outside the connection portion with at least the common electrode among the conductors. Characteristic radiation detector.
  6.  放射線を検出する放射線検出器を製造する方法であって、(A)バイアス電圧給電用のケーブルよりも厚み方向に薄く形成された導体と、放射線の入射により電荷を生成する放射線感応型の半導体の前記入射側に面状に形成されたバイアス電圧印加用の共通電極とを接続する第1接続工程と、(B)前記半導体以外の箇所で前記導体と前記ケーブルとを接続する第2接続工程とを備えることを特徴とする放射線検出器の製造方法。 A method of manufacturing a radiation detector for detecting radiation, comprising: (A) a conductor formed thinner in a thickness direction than a cable for supplying a bias voltage; and a radiation-sensitive semiconductor that generates a charge upon incidence of radiation. A first connection step of connecting a common electrode for bias voltage application formed in a plane on the incident side; and (B) a second connection step of connecting the conductor and the cable at a place other than the semiconductor. A method for manufacturing a radiation detector.
  7.  請求項6に記載の放射線検出器の製造方法において、(C)前記電荷を蓄積して読み出す回路を形成した基板上に、前記半導体をその周囲から取り囲む枠を取り付ける枠取り付け工程を備えることを特徴とする放射線検出器の製造方法。 7. The method of manufacturing a radiation detector according to claim 6, further comprising: (C) a frame attaching step of attaching a frame surrounding the semiconductor from its periphery on a substrate on which a circuit for accumulating and reading out the electric charge is formed. A method of manufacturing a radiation detector.
  8.  請求項7に記載の放射線検出器の製造方法において、前記(B)の第2接続工程では、前記(C)の枠取り付け工程で取り付けられた枠からなる構造物の箇所で前記導体と前記ケーブルとを接続することを特徴とする放射線検出器の製造方法。 8. The method of manufacturing a radiation detector according to claim 7, wherein, in the second connection step of (B), the conductor and the cable at a place of a structure including a frame attached in the frame attachment step of (C). And a method of manufacturing a radiation detector.
  9.  請求項8に記載の放射線検出器の製造方法において、(D)前記ケーブルを被覆する絶縁体がなくケーブルの導線が剥きだしになっている部分の下側に絶縁物を前記基板上に設置する第1設置工程と、(E)前記導体のうち、少なくとも前記共通電極との接続箇所よりも外側の導体の下側に絶縁物を設置する第2設置工程とを備え、前記(C)の枠取り付け工程では、前記(D)の第1設置工程で設置された前記絶縁物とともに前記基板上に前記枠を取り付け、前記(E)の第2設置工程では、前記(C)の枠取り付け工程で取り付けられた枠の溝部分で、かつ前記導体と前記ケーブルとの接続箇所に嵌まるように前記絶縁物を設置することを特徴とする放射線検出器の製造方法。 9. The method of manufacturing a radiation detector according to claim 8, wherein (D) an insulator is provided on the substrate below a portion where there is no insulator covering the cable and the conductor of the cable is exposed. A first installation step; and (E) a second installation step of installing an insulator on the lower side of the conductor outside at least a connection location with the common electrode among the conductors, and the frame of (C) In the attaching step, the frame is attached onto the substrate together with the insulator installed in the first installation step of (D), and in the second installation step of (E), the frame attachment step of (C) A method for manufacturing a radiation detector, comprising: installing the insulator so as to fit into a groove portion of an attached frame and to be connected to a connection portion between the conductor and the cable.
  10.  請求項8に記載の放射線検出器の製造方法において、(E´)前記導体のうち、少なくとも前記共通電極との接続箇所よりも外側の導体の下側、および前記ケーブルを被覆する絶縁体がなくケーブルの導線が剥きだしになっている部分の下側に絶縁物を設置する設置工程を備えることを特徴とする放射線検出器の製造方法。 In the manufacturing method of the radiation detector according to claim 8, (E ') Among the conductors, there is no insulator covering at least the lower side of the conductor outside the connection portion with the common electrode and the cable. A method of manufacturing a radiation detector, comprising: an installation step of installing an insulator below a portion where a cable conductor is exposed.
  11.  請求項7に記載の放射線検出器の製造方法において、前記(B)の第2接続工程では、前記(C)の枠取り付け工程で取り付けられた枠からなる構造物の内部であって、かつ前記半導体以外の箇所で前記導体と前記ケーブルとを接続することを特徴とする放射線検出器の製造方法。 In the manufacturing method of the radiation detector of Claim 7, It is an inside of the structure consisting of the frame attached in the frame attachment process of said (C) in the said 2nd connection process of (B), and said A method of manufacturing a radiation detector, comprising connecting the conductor and the cable at a place other than a semiconductor.
PCT/JP2009/001957 2009-04-30 2009-04-30 Radiation detector and method of manufacturing same WO2010125607A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014181935A (en) * 2013-03-18 2014-09-29 Shimadzu Corp Flat panel type radiation detector and manufacturing method of the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000241556A (en) * 1999-02-25 2000-09-08 Toshiba Corp X-ray plane detector
JP2005286183A (en) * 2004-03-30 2005-10-13 Shimadzu Corp Flat-panel radiation detector
JP2008197110A (en) * 2008-02-18 2008-08-28 Toshiba Corp Plane sensor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000241556A (en) * 1999-02-25 2000-09-08 Toshiba Corp X-ray plane detector
JP2005286183A (en) * 2004-03-30 2005-10-13 Shimadzu Corp Flat-panel radiation detector
JP2008197110A (en) * 2008-02-18 2008-08-28 Toshiba Corp Plane sensor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014181935A (en) * 2013-03-18 2014-09-29 Shimadzu Corp Flat panel type radiation detector and manufacturing method of the same

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