WO2010117340A1 - Systèmes et procédés de données sur courants porteurs - Google Patents

Systèmes et procédés de données sur courants porteurs Download PDF

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Publication number
WO2010117340A1
WO2010117340A1 PCT/SG2010/000138 SG2010000138W WO2010117340A1 WO 2010117340 A1 WO2010117340 A1 WO 2010117340A1 SG 2010000138 W SG2010000138 W SG 2010000138W WO 2010117340 A1 WO2010117340 A1 WO 2010117340A1
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WO
WIPO (PCT)
Prior art keywords
data
control
transmitter
elements
receiver
Prior art date
Application number
PCT/SG2010/000138
Other languages
English (en)
Inventor
Khet Ah Hong
Original Assignee
Power Link Technology Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from SG200902388-8A external-priority patent/SG166007A1/en
Application filed by Power Link Technology Pte Ltd filed Critical Power Link Technology Pte Ltd
Priority to SG2011073822A priority Critical patent/SG176548A1/en
Publication of WO2010117340A1 publication Critical patent/WO2010117340A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/54—Systems for transmission via power distribution lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
    • H05B47/10—Controlling the light source
    • H05B47/175—Controlling the light source by remote control
    • H05B47/185—Controlling the light source by remote control via power line carrier transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2203/00—Indexing scheme relating to line transmission systems
    • H04B2203/54—Aspects of powerline communications not already covered by H04B3/54 and its subgroups
    • H04B2203/5404—Methods of transmitting or receiving signals via power distribution lines
    • H04B2203/5412—Methods of transmitting or receiving signals via power distribution lines by modofying wave form of the power source
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B2203/00—Indexing scheme relating to line transmission systems
    • H04B2203/54—Aspects of powerline communications not already covered by H04B3/54 and its subgroups
    • H04B2203/5404—Methods of transmitting or receiving signals via power distribution lines
    • H04B2203/542—Methods of transmitting or receiving signals via power distribution lines using zero crossing information

Definitions

  • Embodiments of the present invention relate to systems and methods for transmitting digital data to various types of devices using existing power lines.
  • one prior art system uses the Power Line Carrier (PLC) method of data transmission.
  • PLC Power Line Carrier
  • a main controller is equipped with a PLC modem.
  • One or more devices under control are also each equipped with a PLC modem.
  • Each of the modems, devices, and main controller are connected to power lines.
  • Control signals from the main controller are fed to PLC modem.
  • a PLC signal is then fed to the power lines and on to the modems connected to the devices under control.
  • the PLC modems then recover the control command(s) and send corresponding signals to a device controller associated with the devices, which executes the commands as desired.
  • PLC systems are subject to line noise and interference which may be found on the associated power lines.
  • PLC systems are expensive to implement, as they require a PLC modem having both a transmitter and a receiver) to be attached to every single device that a user would want to control.
  • the associated receiver is very expensive.
  • the receiver must be able to handle the low level signal PLC carrier, which is usually measured in micro-volts.
  • These low level PLC carriers are subject to line noise interference, especially in electronic ballast systems. Reducing the noise interference level can be a very expensive process.
  • PLC systems are also quite large and are thus not suitable for use in the electronic ballast.
  • PLC systems are thus especially expensive if the user wishes to control lighting using only the PLC system, given the large number of light fixtures found in a typical home or business.
  • PLC systems are also normally limited to short distance control.
  • Triac triode of alternating current
  • main controller is connected to two alternating current wires.
  • One or more devices, each having a corresponding phase detector are also connected in series to the ac wires and main controller.
  • the system uses pulse width modulation to modulate the ac power supply to each of the devices.
  • the phase detectors detect the pulse width, and use this information to control the devices.
  • the depth of control is proportional to the width of the detected pulse.
  • the system may generate high harmonic content in the power supply system when dimming the lights by more than 60 percent.
  • precise light brightness control is difficult, as the recovered pulse width may vary when the line supply amplitude changes. This means that the same percentage dimming pulse width control signal provided by the main controller might result in different light brightness for each of the devices when the supply voltage fluctuates or the load changes from resistive to inductive as the light is dimmed.
  • Triac and main controller are connected to two alternating current wires and to a separate live wire.
  • One or more devices, each having a corresponding phase detector are also connected in series to the ac wires, the separate live wire, and the main controller.
  • the main controller provides pulse width modulated ac signals to the separate live wire, which connects to all devices. Because the control signals are sent through the separate live wire, the problem of the generation of high harmonics in the power supply can be alleviated.
  • a further prior art system provides digital two wire phase control.
  • a Triac and main controller are connected to two alternating current wires.
  • the controller modulates the pulse from the Triac, and this phase modulated ac signal is fed to one or more devices.
  • a comparator in the device under control recovers this modulated pulse signal.
  • This recovered pulse is then fed to an integrator circuit to eliminate narrow pulses and noise.
  • the output of the integrator is the modulated pulse.
  • this method should recover all of the modulated pulses perfectly.
  • the line supply voltage varies by +/- 15%
  • voltage variations and inductive loads may cause the pulse width to vary, and d.c. voltage superimposes on the recovered signal before it reaches the comparator.
  • the integrator circuit may be unable to differentiate the two, thus causing an error signal.
  • Frequency Shift Keying (FSK) transmitters to accomplish this task.
  • FSK Frequency Shift Keying
  • One such system uses a phase locked loop which locks on to the power line carrier frequency.
  • a crystal oscillator is modulated by incoming data.
  • the crystal oscillator output is then fed to a phase comparator.
  • the phase comparator compares the output with a voltage control oscillator (VCO) output, which is passed through a divide by N counter. Phase differences and error signals from the phase comparator are then fed back to the VCO to correct the VCO frequency.
  • the output of the VCO is proportional to the crystal oscillator frequency.
  • the modulating data causes the crystal oscillator frequency to change.
  • the VCO output frequency also changes in proportion to the crystal oscillator frequency change.
  • FSK carrier is generated.
  • This method is suitable for high frequency FSK carriers.
  • the carrier frequency stability depends on the specific type of crystal used.
  • One problem with this system is that the cost of the FSK generator is quite high.
  • the receiver is expensive and is also quite large.
  • the receiver requires a good filter to remove the line noise interference, especially when the communication distance is more than a hundred meters, and the signal is exposed to high line noise interference conditions, which may be generated by electronic ballast systems.
  • the line noise is thus generally very high, while the PLC carrier level is very low. Expensive filters are required to remove the line interference.
  • this type of system is not suitable for low frequency FSK carriers, i.e. frequencies below 1 MHz.
  • An alternate system which may be used to generate low frequency FSK carriers includes first and second clock pulse generators which may be alternately used to modulate input data using a switch.
  • the output of the switch is then sent to a counter circuit, which generates an address proportional pulse frequency of generator 1 or 2, respectively.
  • the counter signal is passed to a CPU which includes a Read Only Memory (ROM).
  • ROM Read Only Memory
  • the CPU reads the content in the ROM, and sends the signal to a D/A circuit, which reconstructs a low frequency carrier which is proportional to the frequency of pulse generators 1 or 1.
  • the signal is then passed through a low pass filter, then output to downstream systems.
  • This system is suitable for use as a low frequency FSK carrier generator.
  • the frequency stability of the system depends on the pulse generators land 2. Unfortunately, the cost of the system is quite high.
  • the system is also not suitable as a medium and/or high frequency FSK carrier generator.
  • One aspect of the present invention provides a transmitter for transmitting control data over alternating current (ac) power lines, the transmitter including: a zero crossing detector; a microprocessor; and a triode for alternating current (Triac) or a silicon-controlled rectifier (SCR) triggering device; wherein said transmitter receives the control data from a data source; and said microprocessor splits said control data into a plurality of elements, provides a fixed time delay for each of said elements and transmits each of said elements to said Triad or SCR triggering device, which is capable of triggering a corresponding Triac or SCR connected to said ac power line when said zero crossing detector detects a zero crossing of a supply voltage of said ac power line.
  • ac alternating current
  • the elements may function as a preamble signal in series with synchronous and control command data for transmission to one or more receivers connected to an electrical device down stream of said transmitter.
  • the plurality of elements may include one of four stages, eight stages, or sixteen stages.
  • An alternate embodiment of the present invention provides a system for controlling ac electrical devices, the system including: a transmitter as defined in any one of the previous claims; a computer for inputting said control data to said transmitter; and a receiver connected to said ac electrical device; wherein said plurality of elements function as a preamble signal in series with synchronous and control command data, and said receiver converts said control command data into control commands for said ac electrical device.
  • the receiver may further include a full wave rectifier electrically connected to said ac power lines; an attenuator electrically connected to said full wave rectifier; a comparator and filter circuit electrically connected to said attenuator; and a receiver processor electrically connected to said full wave rectifier, said attenuator, and said comparator and filter circuit where in said receiver processor; stores said preamble signal as a corresponding pulse width for each of said elements; compares said pulse width of each of said elements of said preamble signal with a pulse width of said synchronous and control command data and uses said comparison to reconstruct said control data; and sends said control data to said ac electrical device.
  • the comparator may be replaced with one of a Schmitt trigger device or a CMOS device.
  • the system may also include a local receiver connected to said ac power lines and said transmitter, wherein said local receiver: receives said elements; determines if an unacceptable level of noise or system harmonics are present in said elements; and generates an alert signal to said transmitter; and wherein said transmitter then reduces a baud rate of said control data in response to said alert.
  • the processor may split said data into one of 4, 8, or 16 stages. When 4 control elements are used, the system may transmit said data at a baud rate of 240BPS for 60 hertz power systems, and a baud rate of 200BPS for 50 hertz power systems.
  • the system may also include a Frequency Shift Keying transmitter electrically connected to said power lines and said receiver.
  • the FSK transmitter may further include: a first crystal oscillator electrically connected to an oscillator control and a first divide by n divider; a second crystal oscillator electrically connected to said oscillator control and a second divide by n divider; and an amplifier electrically connected to each of said first and second divide by n dividers; wherein said first divide by n divider receives modulating data from said receiver and outputs said modulating data to said amplifier at a first carrier frequency determined by said first crystal oscillator; second divide by n divider receives inverted modulating data and outputs said inverted modulating data to said amplifier at a second carrier frequency determined by said second crystal oscillator; and said amplifier combines said first and second carrier frequencies and outputs FSK carrier data to said ac power line.
  • An alternate aspect of the present invention provides a method for transmitting control data over alternating current (ac) power lines, the method including the steps of: providing a transmitter electrically connected to the ac power lines, said transmitter comprising: a zero crossing detector; a microprocessor; and a triode for alternating current (Triac) or a silicon-controlled rectifier (SCR) triggering device; receiving the control data from a data source at the transmitter; and splitting said control data into a plurality of elements; providing a fixed time delay for each of said elements; and transmitting each of said elements to said Tr ⁇ ac or SCR triggering device; wherein; said Triac or SCR triggering device is capable of triggering a corresponding Triac or SCR connected to said ac power line to transmit each of said elements to a corresponding receiver connected to a load and said ac power line when said zero crossing detector detects a zero crossing of a supply voltage of said ac power line, in order to control said load.
  • a further aspect of the present invention provides a system for generating and transmitting a Frequency Shift Keying (FSK) carrier frequency on a power line to control devices connected to said power line, the system including: a first crystal oscillator electrically connected to an oscillator control and a first divide by n divider; a second crystal oscillator electrically connected to said oscillator control and a second divide by n divider; and an amplifier electrically connected to each of said first and second divide by n dividers; wherein said first divide by n divider receives modulating data and outputs said modulating data to said amplifier at a first carrier frequency determined by said first crystal oscillator; second divide by n divider receives inverted modulating data and outputs said inverted modulating data to said amplifier at a second carrier frequency determined by said second crystal oscillator; and said amplifier combines said first and second carrier frequencies and outputs FSK carrier data to said ac power line.
  • FSK Frequency Shift Keying
  • the system may also include a low pass filter and a coupling transformer, wherein said low pass filter filters said FSK carrier data and transmits said data through said transformer to said power line.
  • the first and second crystal oscillators may be switched on by an oscillator controller when said modulating data is being received, and switched off by said oscillator control when no modulating data is being received.
  • a further aspect of the present invention provides a method for generating and transmitting a Frequency Shift Keying (FSK) carrier frequency on a power line to control devices connected to said power line, the method including the steps of providing a first crystal oscillator electrically connected to an oscillator control and a first divide by n divider; providing a second crystal oscillator electrically connected to said oscillator control and a second divide by n divider; providing an amplifier electrically connected to each of said first and second divide by n dividers; receiving modulating data at said first divide by n divider and outputting said modulating data to said amplifier at a first carrier frequency determined by said first crystal oscillator; receiving inverted modulating data at said second divide by n divider and outputting said inverted modulating data to said amplifier at a second carrier frequency determined by said second crystal oscillator; and combining said first and second carrier frequencies at said amplifier and outputting said combined carrier frequencies as said FSK carrier data to said ac power line.
  • FSK Frequency Shift Key
  • Figure 1 is a circuit diagram illustrating one system of controlling devices using pulse width modulation of power line signals according to an embodiment of the present invention
  • Figure 2 illustrates one embodiment of a transmitter which may be used with the system of Figure 1 , and associated waveforms produced by the transmitter;
  • Figure 2a is a circuit diagram illustrating additional detail of one example transmitter of Figures 1 and 2;
  • Figure 3 illustrates one embodiment of a receiver which may be used with the system of Figure 1 and the transmitter of Figure 2, and associated waveforms produced by the transmitter;
  • Figure 3a is a circuit diagram illustrating additional detail of one example receiver of Figures 1 and 3;
  • Figure 4 illustrates one example of a relationship between the waveforms produced by the transmitter and receiver of Figures 2 and 3 using the system of Figure 1 ;
  • Figure 5 illustrates one embodiment of possible recovery pulse width changes in relation to line voltage variations using the fixed pulse width modulation system of Figures 1-3;
  • Figure 6 is a circuit diagram illustrating an alternate embodiment of a system of controlling devices using power line signals
  • Figure 7 is a circuit diagram illustrating one embodiment of a FSK transmitter for short distance communications, which may be used with the system of Figure 6;
  • Figure ⁇ illustrates one example of various waveforms related to oscillator control and modulating data using the system of Figure 7.
  • Embodiments of the present invention provide a reliable and low cost control system and method to transmit control data from a transmitter (or controller) to devices under control downstream using existing power lines. Some embodiments also allow the system to keep track of line voltage variations and inductive loads which may cause the recovered pulse width to vary. The system and method may then automatically adjust and compensate the recovered pulse width for variations in the line voltage and/or load changes from resistive to inductive.
  • the system provides signals at up to 240BPS (60Hz supply) or 200BPS (50Hz supply) from the controller to the device under control. When severe line distortion or noise is present in the supply line, the system automatically reduces the communication baud rate to 120 BPS (60 Hz supply) or 100 BPS (50 Hz supply). For all of the waveforms discussed below, voltage is represented on the "y" axis as a function of time on the "x" axis.
  • Figure 1 is a circuit diagram illustrating one system 200 of controlling devices using pulse width modulation of power line signals according to an embodiment of the present invention.
  • Figure 2 is a circuit diagram illustrating one embodiment of a transmitter or controller 202 which may be used with the system 200 of Figure 1, and associated waveforms produced by the transmitter 202.
  • Figure 3 is a circuit diagram illustrating one embodiment of a receiver 240 which may be used with the system 200 shown in Figure 1 to receive signals from the transmitter 202 of Figure 2, and associated waveforms.
  • the system 200 includes a controller 202 connected to a Triac 204.
  • the Triac 204 is electrically connected to an ac power source 201.
  • the controller 202 and Triac 204 adjust the pulse widths of the power signals provided by the ac power source 201 such that desired data may be encoded onto the signals.
  • the Triac 204 may be replaced with a silicon controlled rectifier (SCR).
  • the controller 202 is used to control the Triac 204 such that the power source signals provided by the ac power source 201 have their pulse widths modified and placed on the electrical lines 201a, 201b.
  • the ac power is delivered to respective loads/devices 210 via the electrical lines 201a, 201b.
  • each of the loads/devices 210 has a corresponding receiver 240 which is also connected to the electrical lines 201a, 201b.
  • the receivers 240 are capable of decoding the encoded data from the power signals in the electrical lines 201a, 201 b.
  • the data may comprise specific instructions for controlling the functionality of the load 210. The specific operation of the system is discussed below. It will be appreciated that while the receiver 240 in Figure 1 operates a single load/device 210, two or more loads may also be connected to the same receiver, such that a single receiver may operate more than one device.
  • the transmitter 202 includes a Triac or SCR triggering device 220, a microprocessor circuit 222 (CPU), and a zero crossing detector 224.
  • a system controller or computer 700 may be connected to the controller 202 using, for example, an RS-485 communication protocol 702. It is understood that other communication protocols may also be used. It is further understood that a plurality of systems 200 may be implemented in a building, each of which may be controlled independently by the computer 700.
  • each device 210 may have a 3 digit (0 to 256) unique address and up to 16 group addresses.
  • the controller 202 may send out a control command to all devices downstream.
  • the control command may include the addresses of the devices the command is intended for, and the desired control functions, such as to switch on or switch off the devices, report back the status of the devices, or other functions. Only those devices having an address or group address matching the device address in the control command will act according to the control command.
  • the control functions may be stored in the controller 202 or computer 700.
  • Devices 210 may be controlled, for example, according to a pre-fixed time schedule, e.g. at 0800 hours the controller sends out a command to switch on certain devices, and at 1700 hours the controller sends out a command to switch off certain devices.
  • Devices also . can be instructed to perform other functions, such as dimming a light to 50% of its full brightness, or report the room temperature back to controller or computer. It is understood that various functions may be enabled within the controller according to actual requirements
  • FIG 2a is a circuit diagram illustrating additional detail of the transmitter 202 of Figures 1 and 2.
  • the transmitter 202 may include a transformer 402 for converting the high voltage a.c. supply to a low voltage supply.
  • the output of the transformer 402 may then be fed to a power supply circuit 404, which provides a low voltage d.c. output (Vcc) 406 to the transmitter 202 components.
  • the output of the transformer 402 also connects to the zero crossing pulse generator 224.
  • the zero crossing pulse generator 224 circuit may include a rectifier bridge 410, resistors 412, 414, and 416, and a transistor 418.
  • the zero crossing pulse is fed to the CPU circuit 222 for phase modulation control purposes.
  • the CPU 222 output control command data is then fed to a phase modulator circuit 420 which may include a buffer gate 422, an Opto coupler Triac 424 and the Triac 204 (or SCR). As described below, the Triac signal is controlled by a precise timing signal from the CPU 222. The output from the Triac (or SCR) 204 is then fed via power lines 201a, 201 b to downstream devices.
  • a phase modulator circuit 420 which may include a buffer gate 422, an Opto coupler Triac 424 and the Triac 204 (or SCR).
  • the Triac signal is controlled by a precise timing signal from the CPU 222.
  • the output from the Triac (or SCR) 204 is then fed via power lines 201a, 201 b to downstream devices.
  • the receiver 240 receives the input signal from the power lines 201a, 201 b via a full wave rectifier 242.
  • the output of the full wave rectifier is fed to attenuator 246 and a zener diode 244.
  • the zener diode 244 is used to offset the floating voltage which may result from the rectifier 242 when the load is inductive.
  • the output of the zener diode 244 is then coupled to a comparator (and filtering circuit) 250, which compares it with a fixed reference voltage Vr 252.
  • the value of Vr 252 will depend on the supply voltage of the comparator. For example, Vr 252 can be fixed at 2.5v or 3v when the Vcc of the comparator is 5v.
  • the value of Vr is close to half of Vcc.
  • the value of Vr may also depend on the attenuator 246.
  • the attenuation value of the attenuator 246 varies for different the a.c. supply voltage systems.
  • the attenuation value of the attenuator 246 may be different for a 110v / 60 Hz power system or a 23Ov /50 Hz supply system.
  • FIG. 3a shows additional details of one possible example of the receiver circuit 240 shown in Figure 3.
  • Vcc 256 represents tttedc supply voltage to the receiver circuit 240.
  • the attenuator 246 circuit may include one or more resistors R1 and R2. Output from the attenuator 246 is then fed to the zener diode 244 and through another resistor R3 to the voltage comparator 250 input.
  • the reference voltage Vr 252 is derived from voltage divider resistors R5 and R6.
  • a diode 254 may be used to protect the comparator and filter circuit 250 to prevent the voltage input to the comparator 250 from exceeding the supply voltage Vcc 256, which might damage the comparator 250.
  • the comparator output may then be fed to a filter circuit 251 to remove jittering noise.
  • the filter circuit 251 may include a resistor R7, a diode D3, a capacitor C1 and a CMOS gate or Schmitt trigger CMOS gate U2. Output from the Gate U2 is then fed to the CPU 260 to process and retrieve the control command(s) from the controller transmitter 202. This will be discussed in more detail below.
  • a Schmitt trigger device 253 or a CMOS device 255 may be used in place of the voltage comparator 252. In these embodiments, no fixed reference voltage is required.
  • a diode 254 may be used to protect the comparator and filter circuit 250 (or Schmitt trigger device or CMOS device) when the output of the attenuator 246 through zener diode 244 exceeds a dc supply voltage Vcc 256 to the comparator.
  • the diode 254 is used to protect the comparator (or Schmitt trigger device or CMOS device) 250 input. For example, for a 23Ov a.c. supply system, the supply voltage might go as high as 27Ov.
  • digital data in the form of "0"s and "1"s is encoded by the controller 202 by means of the Triac 204 and sent to the receiver 240 for decoding.
  • the controller 202 may also be referred to as a transmitter "transmitting" data pulses for receipt by the receiver 240.
  • the example data transmitted is sent from the controller may be a control command issued to operate the load 210.
  • the control command from the transmitter 202 to the receiver 240 contains a series of O's and Ts, which are broken down into, by way of example and not limitation, 4-stage data elements.
  • the 4-stage data elements are e.g.
  • the controller 202 and Triac 204 collectively modulate the pulse widths of the original ac power source signal 229 for output on the power lines 201a, 201b, according to which of the data elements e.g. 1 OO', '01', '10' and '11' is to be transmitted in the present cycle. Pulse width modulation is achieved by introducing delays in the triggering of the Triac 220. Each data element has an associated precise fixed time delay TO, T1 223a, T2 223b and T3 223c respectively introduced by the CPU 222 (see Figure 2).
  • the time delay TO associated with data '00' is zero.
  • This time delay TO, T1 223a, T2 223b and T3 223c is then fed to the Triac or SCR triggering circuit 220 to delay the switching of ac supply power signals 229 by the Triac or SCR 204.
  • the Triac is turned off until the time delay TO, T1 223a, T2 223b and T3 223c has lapsed. This results in a pulse moderated signal at the output of the Triac 204, on the power lines 201a, 201b.
  • pulse width modulation is done close to the zero crossing point of the ac supply signal 229.
  • An associated time delay for each data element causes a respective delayed triggering of the Triac or SCR 220 after the zero crossing point of the ac supply power signal 229.
  • the 1 OO' data element triggers the Triac or SCR 220 immediately after zero crossing.
  • Each of the '01' '10' and '11' data elements cause a delayed triggering of the Triac or SCR (refer to Fig 4) after time delays T1 223a, T2 223b and T3 223c respectively. As shown in Figure 2, the duration of T3 223c is the longest.
  • the output of the Triac 204 is a pulse modulated signal 234 ( Figures 2 and 4) which is transmitted to the receiver 240.
  • the signal 234 may be in the form of a resistive load waveform 236, or an inductive load waveform 238. This will be described in more detail below.
  • the pulse width modulated signal 234 is only transmitted to those receivers 240 and loads 210 located downstream of the controller 202. No power isolation is thus required in the embodiment.
  • the format of the data transmitted from the transmitter 202 to the receiver 240 is 'preamble + synchronous + command'. This will be discussed in more detail below with reference to Figures 4 and 5.
  • the line supply voltage of the ac power signal 229 from the ac power source 201 normally fluctuates slowly, varying at e.g. +/- 15% over 24 hours.
  • the ac supply voltage 229 may be considered very stable, in particular to the embodiments of the present invention where data transmission from the transmitter 202 to the receiver 240 takes less than 1 second.
  • the inventors have recognised that any line voltage variations and/or inductive load variations in a 1 second period may be considered negligible.
  • variations in the supply voltage and load affect the recovered pulse widths of the preamble, synchronous and control command data in the same manner, as they are transmitted within, for example, 1 second of each other. Therefore, by including reference pulse widths in the preamble, the receiver 240 can use the reference pulse widths to recover the control command(s) accurately.
  • Figure 4 illustrates one example of a relationship between some of the signal waveforms produced by the transmitter 202 and receiver 240 of Figures 2 and 3 using the system 200 of Figure 1.
  • Figure 5 illustrates one possibility for recovery pulse width changes in relation to line voltage variations using the fixed pulse width modulation system 200 of Figures 1-3.
  • the microprocessor 222 in the transmitter 202 re-arranges or divides the command signal data bits (series of '0' or '1') e.g. 230 into a plurality of stage data elements, for example, a '00', '01 ', '10', and '11' pattern, as shown with reference numeral 232.
  • the CPU 222 then converts the '00', '01', '10', and '11' stage data elements into a data signal with fixed time delay pulses, as shown with reference numeral 233, for delaying triggering of the Triac 204 at each zero crossing of the input supply 229.
  • the Triac 204 may be triggered without time delay (TO is zero) after zero crossing of the line supply voltage 229 is detected by the zero crossing detector 224.
  • the triggering delay pulse is T1 223a
  • the delay triggering time will be T2 223b and T3 223c respectively.
  • time delays TO, T1 223a, T2 223b and T3 224c are unique as they are each associated with a different data element. It will also be appreciated that each of the time delays TO, T1 223a, T2 223b and T3 224c, are less than half the period of the ac supply signal 229, e.g. TO, T1 223a, T2 223b and T3 224c are between 0 and 10ms for a 50hz supply; or between 0 and 8.3ms for a 60hz supply. In one example embodiment, the delay time for T2 is 2mS, T3 is 3mS, and T4 is 4mS. It is understood that other delay times may also be used.
  • the delay times should be long enough for the receiver to easily recover the transmit data.
  • the delay times T1 , T2 and T3 may also depend on whether the a.c. supply system is 60Hz or 50Hz.
  • the microprocessor 222 sends out a data signal 233 comprising of precisely timed delay triggering pulses to the triggering device 220 immediately after a zero crossing of the line voltage 235 is detected by zero crossing detector 224.
  • the precisely timed delay pulses from the trigger circuit 120 are then fed to trigger the Triac or SCR 204.
  • the amount of delay in triggering the Triac or SCR 204 after the zero crossing pulse is detected depends on whether the command stage data element is '00', '01', '10' or '11'.
  • Ac power supplied through the Triac 204 via power lines 201a, 201b to each of the downstream devices 210, 240, will incorporate the delayed data pulses.
  • Signal waveforms of the ac power supply delivered on power lines 201a, 201b are shown as reference numeral 234.
  • the specific characteristics of the waveform 234 depend on the type of load.
  • the ac power delivered on power lines 201a, 201b now include pulse modulated signals, control commands or data are now incorporated within the ac power signals, and are thus also sent from the controller 202 to each of the downstream devices 210, 240.
  • the duration of the data transmission is less than 1 second.
  • the format of the data transmitted from the transmitter 202 to the receiver 240 is 'preamble + synchronous + command'.
  • the transmission bit rate is 240 BPS (bits per second) for a 60 Hz supply or 200 BPS for a 50 Hz supply, when using 4 stage data elements comprising two bits e.g. 1 OO', '01 ,' '10' and '11' as discussed above.
  • 4 stage data elements comprising two bits e.g. 1 OO', '01 ,' '10' and '11' as discussed above.
  • the term "Baud” refers to the number of 0 or 1 data transmitted in one second. For a.c. power supplies, every cycle will have two zero crossing points. The phase modulation of the a.c. supply is performed after a zero crossing is detected. The a.c. supply is modulated according to 00, 01, 10 and 11 data as discussed above. Thus the maximum baud transmit rate is 200 for a 50Hz a.c. supply system, and 240 for a 60Hz a.c. supply system.
  • the receiver 240 receives the Triac 204 controlled ac supply with waveform 234 from the transmitter 202. It will be appreciated that the transmitter 202 transmits data by encoding the data in the form of modulated pulses of the ac power supply 229, and using the ac power lines 201a, 201b as the medium for data transmission. The transmitted ac power 229 with waveform 234 is received at the rectifier 242, which outputs a rectified signal, shown as waveform 270 for a resistive load in Figures 3 and 4.
  • This rectified signal 270 passes through the attenuator 246 and comparator (or Schmitt trigger device or CMOS device) and filtering circuit 250, and is output to the receiver CPU 260 as a recovered pulse signal 272, the waveform of which is shown as reference numeral 272 in Figures 3 and 4.
  • the recovered pulse signal 272 comprises pulses whose pulse widths are proportional to associated transmitted pulse widths of pulses of the data signal 233 for data elements '00' to '11', provided by the microprocessor 222 of the transmitter 202.
  • data transmission first begins with the transmission of a preamble.
  • This preamble comprises a sequence of fixed data elements such that the receiver can calibrate itself to associate each recovered pulse width with a data element.
  • the preamble comprises a sequence of data elements OO 01 10 11'.
  • the transmitter generates and transmits a data signal 235 with pulses having pulse widths associated with the sequence, e.g. TO, T1 , T2 and T3.
  • pulse widths of pulses in the recovered pulse signal 272 are identified to correspond with a particular data element.
  • the CPU 260 identifies pulses with pulse widths T4 272a, T5 272b, T6 272c and T7 272d to represent the data elements or data bits OO', '01', '10' and '11' respectively.
  • Subsequent synchronous and command data pulses with pulse widths T4 272a, T5 272b, T6 272c and T7 272d which follow the preamble can then be identified to represent data elements or data bits '00', '01', '10' and '11' respectively. Details of this identification are described below.
  • the CPU 260 identifies pulses with pulse widths T8 239a, T9 239b, T10 239c and T11 239d to represent the data elements or data bits OO', '01', '10' and '11' respectively.
  • Subsequent synchronous and command data pulses with pulse widths T8 239a, T9 239b, T10 239c and T11 239d which follow the preamble can then be identified to represent data elements or data bits OO', '01', '10' and '11' respectively. Details of this identification are described below.
  • the recovered waveform pulse width with inductive load is T8, T9, T10 and T11 which are narrower than those associated with the resistive load T4, T5, T6 and T7. . This is due to the effect of the inductive load.
  • the received data element is "00". If the recovered pulse has pulse width of less than T5 + ((T6 - T5)/2, and more than T4 + (T5 - T4)/2, then the received data element is "01". If the recovered pulse has pulse width of less than T6 + (T7 - T6)/2, and more then T5 + (T6 - T5)/2, then the received data element is "10". If the recovered pulse has pulse width of more than T6 + (T7 - T6)/2, then the received data element is "11". The receiver CPU 260 then re-structures the retrieved 1 OO' to '11' data elements back into the original control command format. The receiver CPU 260 then controls the load 210 according to the re-structured control command instructions. By way of example and not limitation, the control command instructions may switch on or switch off a light, or dim the lights to the percentage specified in the control command instructions.
  • FIG 4 illustrates some of the various waveforms discussed above over a single control element cycle.
  • the top waveform represents the incoming ac supply waveform 229 to the transmitter (or controller) 202 ( Figure 2) and Triac ( Figure 2).
  • the next waveform is the signal output 235 from the zero crossing detector 224 ( Figure 2) to the transmitter CPU circuit 222 ( Figure 8).
  • Below the waveform 235 is the data signal output 233 comprising time delay pulses from the transmitter CPU circuit 222 ( Figure 2)
  • the time delay pulses have pulse widths which are associated with a control data element OO' to '11'.
  • the delay triggering pulses with pulse widths TO (equal zero delay time) to T3 are then sent to the Triac or SCR triggering circuit 220 ( Figure 2) of the transmitter 202 ( Figure 2) immediately after a zero crossing of the supply voltage is detected by the zero crossing detector 224 ( Figure 2).
  • the amount of the delay in triggering the Triac or SCR 204 ( Figure 2) thus depends on whether the modulating data is '00', '01' '10' or '11'.
  • the pulse modulated output waveform 234 ( Figure 2) from the transmitter 202 to the receiver 204 is shown below the signal output 233 of the time delayed pulses from the transmitter CPU circuit 222 ( Figure 2).
  • the output waveform 270 from the rectifier 242 ( Figure 3) in the receiver 240 ( Figure 3) is illustrated.
  • Reference numeral 271 denotes the comparator 250 ( Figure 3) reference voltage.
  • the bottom waveform in Figure 4 shows the waveform output 272 of the receiver comparator and filtering circuit 250 ( Figure 3) to the receiver CPU circuit 260.
  • T4 272a, T5 272b, T6 272c, and T7 272d represent data 1 OO', data '01', data '10' and data '11', respectively for a resistive load.
  • Figure 5 illustrates one example of possible recovery pulse width changes in relation to line voltage variations using the fixed pulse width modulation system 200 of Figures 1-3.
  • the loads 210 under control are not pure resistive loads.
  • the a.c. power supply might fluctuate by +/- 15% of the standard supply voltage. This variation can affect the pulse widths of the recovered pulses at the receiver, and is illustrated generally in the first graph 280.
  • the standard supply voltage from the transmitter 202 to the receiver 204 is shown with reference numeral 282. When the supply voltage increases, this waveform also changes, as shown with reference numeral 284.
  • a general illustration 290 of the received waveforms is shown below the first graph 280.
  • the output of the rectifier 242 of the receiver 240 is shown as reference numeral 282a.
  • the reference voltage of the comparator is shown as reference numeral 252.
  • the recovered pulse width of pulse 282b of the comparator and filtering circuit 250 to the receiver CPU circuit 260 is shown proportionally below.
  • the output 284a of the rectifier 242 of the receiver 240 increases as well.
  • the recovered pulse width of pulse 284b of the comparator (or Schmitt trigger device or CMOS device) and filtering circuit 250 to the receiver CPU circuit 260 also changes.
  • both 282 and 284 are different supply voltages having the same pulse width modulation.
  • the supply voltage 284 is higher than the supply voltage 282.
  • 284b and 282b are the recovered pulses of 284 and 282 respectively. Note that the pulse width of pulse 282b is wider than the pulse width of pulse 284b. This shows that when the supply voltage increases, the recovered pulse width of the comparator output is reduced and vice versa.
  • Embodiments of the present invention send pulses associated with each of the '00' to '11' data elements prior to the control command as a preamble.
  • the recover preamble pulse widths of pulses associated with each of the OO' to '11' data elements changes accordingly when line voltages and loads vary.
  • the synchronous and control command pulses have pulse widths which also vary by the same amount.
  • Pulses with pulse widths associated with the '00' to '11' data elements are sent prior to the control command as a preamble.
  • the receiver CPU 260 first extracts the pulse widths associated with each of the 1 OO' to '11' data elements from the preamble, and stores this information. Subsequently, the synchronous and control command pulses which follow may be compared with the information on the preamble pulse widths to identify the OO' to '11' data elements in the synchronous and control command pulses. Since the reference pulse widths vary by the same amount as the synchronous and control command pulse widths when the supply voltages or loads change, the receiver CPU 260 is able to extract the '00' to '11' data elements regardless of line voltage and load variations.
  • the preamble signal may repeat '00' + '01' + '10' +'11' data element stream. Sending out a minimum of 2 cycles of '00' to '11' data element streams as the preamble may allow the receiver CPU 260 ( Figure 3) to more accurately record the associated pulse widths of the '00', '01', '10' and '11' data elements. The recorded pulse widths may then be temporarily stored and used as reference to extract the synchronous and control command data from subsequently received pulses which follow.
  • the standard transmission baud rate is 240BPS (60 Hz supply) or 200BPS (50Hz supply).
  • the recovered pulse width in the receiver 204 ( Figure 3) may be affected by high noise interference or harmonics present in the power line. This may adversely affect the recovered control commands. Such noise may make it difficult for the receiver CPU 260 ( Figure 3) to extract and recover the data.
  • an alternate embodiment of the system 200 provides for automatically reducing the transmission baud rate to 120 BPS (60 Hz supply) or 100 BPS (50 Hz supply).
  • the associated pulse widths of the preamble data recovered by the receiver 204 is T4, T5, T6 and T7, which represent the data elements or bits '00', '01', '10' and '11' respectively.
  • the local receiver 206 near the transmitter 202 detects the recover preamble pulse width of '00' (T4), '01' (T5), '10' (T6) and '11' (T7) data elements bits closely after transmission to determine if severe noise may be present on the supply lines 101a, 101 b, or if the incoming supply has a high harmonic content. These conditions may cause errors in receiving the control data at the receiver 240.
  • the local receiver 206 may then send out an alert signal to the transmitter 202.
  • the transmitter 202 receives the alert signal from the local receiver 206, and reduces the transmission bit rate to 120 BPS (60 Hz supply) or 100 BPS (50 Hz supply).
  • the local receiver circuit is identical to the receiver in the control device 240.
  • the recovered data from the local receiver is fed to the CPU in the main controller.
  • the CPU compares the recovered data from the local receiver with the transmitted data. If the recovered data is different from the transmitted data, it may be an indication that the transmitted data is corrupted. In this case, the CPU may then reduce the transmission baud rate to 120 for 60HZ supply or 100 for 50Hz supply.
  • the preamble signal sent out from the transmitter 202 may contain delay times TO and T3 only.
  • the Triac 204 will be triggered by time delays of TO and T3 only.
  • the delay time TO is associated with the data element or bit 1 O'
  • the delay time T3 is associated with the data element or bit '1' of the control command.
  • the transmitter CPU 222 detects the preamble data containing only 2 stage time delays representing data elements OO' and '11'. Elements '01' and '10' data are absent.
  • the transmitter CPU 222 reduces the control command bit rate from 240 BPS to 120BPS (or 200 BPS to 100BPS).
  • the pulse width associated with the recovered data element '00' will be treated as data bit O' and the pulse width associated with the recovered data element '11' will treat as data bit '1'.
  • the receiver CPU 260 can then re-construct the command data at the reduced baud rate.
  • the synchronous signal may also include a minimum 2 cycles of pulses associated with '00' + '11' data elements. This is to inform the CPU 222 of the starting bit of the retrieved control command.
  • the control command(s) may include, by way of example and not limitation, a device address, an operation command, and an operand. It is understood that the control command may include additional features as well.
  • the device address is a unique address assigned to every device under control. These addresses may also include a group address such that multiple devices may be controlled with the same command.
  • Operation commands may include, by way of example and not limitation, a command to switch on or switch off the device, or to perform other functions, such as dimming lights. The Operand may be used to instruct the device to perform a specific operation e.g. dim the lights to 20% of full brightness, etc.
  • the systems and methods described above may be used at any supply voltage and supply operating frequency.
  • the embodiments described use 4-stage data elements of 4 data stages comprising of 2 bits, e.g. OO', '01 ,' '10' and '11', it is understood that the data elements may be of 4, 8, 16 or more data stages, without departing from the scope of the present embodiments. However, it will be appreciated the bit error rate would increase with the number of data elements used.
  • the described embodiment uses a single transmitter to control two devices, it is understood that multiple transmitters may be used within a large system. Each of these multiple transmitters may control several devices.
  • the system 200 provides several advantages over prior art systems.
  • the system provides a reliable and low cost control method from the transmitter to devices under control downstream.
  • the system keeps track of line voltage variations and inductive loads which may cause the recovered pulse width to vary.
  • the system can automatically adjust and compensate the recovered pulse width for these variations.
  • the system provides data at up to 240BPS (60Hz supply) or 200BPS (50Hz supply) from the controller to the device under control.
  • the system can automatically reduces the communication baud rate to 120 BPS (60 Hz supply) or 100 BPS (50 Hz supply).
  • FIG. 6 is a circuit diagram illustrating an alternate embodiment of a system, designated generally with reference numeral 600, for controlling devices using power line signals. As many of the components of the system 600 are identical to the system 200, the same reference numerals are used to denote these components. Additionally, the system 600 includes one or more devices under control 610. Each device under control 610 now includes a Frequency Shift Keying (FSK) transmitter 300. A FSK receiver 620 is electrically connected to power lines 201a, 201b, and the controller 202. Details concerning the operation of the system 600 are provided below Figure 7 is a circuit diagram illustrating one embodiment of a FSK transmitter 300 for short distance communications, which may be used with the system of Figure 6.
  • FSK Frequency Shift Keying
  • Figure 8 illustrates one example of various waveforms related to oscillator control and modulating data using the system 300 of Figure 7. Note that for all of the waveforms shown in Figure 8, voltage is represented on the "y" axis as a function of time on the "x" axis.
  • the phase controlled a.c. supply is used to transmit the control data from the controller or computer to devices under control 610 downstream, as discussed above with reference to Figures 1-5.
  • the devices under control 610 cannot use the phase modulated method to transmit data back to controller 202, because the controller is up stream in the a.c. supply line.
  • the FSK transmitter 300 solves this problem.
  • the transmitter 300 includes two separate crystal oscillators 302, 307 and respective divide by n dividers 304, 309. Crystal oscillators 302 and 307 are controlled by oscillator control 301 input. The output of the n dividers 304, 309 is controlled by modulating data signals 311 and their inverted data signals 312. When modulating data control signals to either n divider 304 and 309 is at the logic O', no output is resultant from that n divider.
  • the crystal oscillator 302 includes a crystal 303, while the crystal oscillator 307 includes a crystal 308.
  • the control input signal 301 provides a logic gate transmitting either a logic '0' or logic '1'. At logic '1' both oscillators 302, 307 stop oscillation. At logic '0' both oscillators 302, 307 start oscillation. It is understood that the operation could be reversed if desired.
  • control input 301 signal transmits a logic O', and both crystal oscillators 302 and 307 will start oscillation.
  • control input signal 301 reverts back to logic 'V.
  • Figure 8 shows examples of the waveform output 318 of crystal oscillator 302 and output 319 of crystal oscillator 307 related to control input 301.
  • Both crystal oscillator 302 and 307 stop oscillation when control data 301 is high (at logic '1') and start oscillation when control data signal 301 is low (at logic O'). It is understood that the reverse configuration may also be used.
  • Modulating data input 311 connects to the divide by n divider 309. The data from modulating data input 311 is also inverted and connected to divide by n divider 304, as shown with reference numeral 312.
  • the output of the divide by n divider 304 is the FSK output carrier f 1 , as shown with reference numeral 305.
  • the output of divider 304 is disabled (no output) when modulating data signal 311 is at logic '1' (inverted out at logic O') and enabled when the modulating data signal 311 is at logic O'.
  • the output waveform 305 of divider 304 as it relates to the modulating data signal 311 is shown in Figure 8.
  • the output of divide by n divider 309 is the FSK output carrier f2, shown as reference numeral 310 in Figures 12 and 13.
  • the divider 309 is disabled (no output) when modulating data 311 is at logic O', and enabled when modulating data 311 is at logic '1'.
  • the output waveform 310 of divider 309 as it relates to the modulating data 311 is shown in Figure 8.
  • Both outputs 305 and 310 are fed to an amplifier 313.
  • a single FSK carrier output 314 is then sent through , for example, a low pass filter 315, and a coupling transformer 316 to transmit the signal to all devices under control through ac power lines 201a, 201b.
  • the low pass filter 315 may be used to filter out higher order harmonics of the FSK power line carrier.
  • the receiver 240 in the device under control 610 receives the status request command from the controller 202.
  • the receiver 240 may then decode the control command from the controller 202. If, for example, a status request command from the controller 202 match with the address of the device under control 610 address, the device 610 status information may be fed to the FSK transmitter 300 through the a.c. supply cable 201a and 201b to the FSK receiver 620.
  • the FSK receiver 620 will then provide the received devices status to the controller 202 for further processing. This allows for two way communication between the controller and devices under control, as both are connected to the same a.c. supply cable.
  • Graph 350 shows the waveform of the oscillator control signal 301 in an on and off state.
  • Graph 352 shows the modulating data signal 312.
  • Graph 354 shows the output 318 of the crystal oscillator 1 302.
  • Graph 356 shows the carrier frequency f1 output 305 from the first divide by n counter 304.
  • Graph 358 shows the modulating data signal 311.
  • Graph 360 shows the output 319 of the crystal oscillator 307.
  • Graph 362 shows the carrier frequency f2 output 310 from the second divide by n counter 309.
  • Graph 364 shows the FSK carrier output 314 from the amplifier 313.
  • both crystal oscillators 302 and 307 stop oscillation.
  • both oscillator 302 and 307 start to oscillate and to output respective waveforms 318, 319, as shown in graphs 354 and 360, respectively.
  • the output 305 of divider 304 at frequency f1 , and the output 309 of divider 309 at frequency f2 depends on the modulating data 311 and inverted modulating data 312, respectively.
  • the outputs 305, 311 are then sent to the amplifier 313, which combines them into the FSK carrier frequency output 314.
  • the FSK power line carrier output 314 is at frequency f1 when the modulating data 311 is at logic 1 O'.
  • the FSK power line carrier output 314 shifts to frequency f2 when the modulating data 311 is at logic '1'.
  • the system 300 thus combines the two frequency outputs f1 and f2 into a single carrier frequency, which may be used to control various devices on the electrical network.
  • the frequency stability of the power line carrier 314 will depend on the type of crystal used in crystal oscillators 302, 307. In general, a low cost crystal having a stability better than 20 ppm is preferred for low frequency FSK applications.
  • the system 300 provides a low cost and highly stable power line carrier FSK transmitter for short distance communication applications. Additionally, the FSK transmitter 300 is small and can easily be integrated into any device under control 610.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Power Conversion In General (AREA)

Abstract

L'invention concerne des systèmes et des procédés pour transmettre des données de commande sur des lignes d'alimentation de courant alternatif (ac). Le système peut comprendre un émetteur comportant : un détecteur de passage à zéro ; un microprocesseur ; et un dispositif de déclenchement de triode pour courant alternatif (Triac) ou de redresseur de courant au silicium (SCR) ; ledit émetteur recevant les données de commande d'une source de données ; et ledit microprocesseur sépare lesdites données de commande en une pluralité d'éléments, obtient un délai fixé pour chacun desdits éléments et transmet chacun desdits éléments audit dispositif de déclenchement SCR ou de Triac, qui est susceptible de déclencher une Triac ou un SCR correspondant connecté à ladite ligne d'alimentation ac lorsque ledit détecteur de passage à zéro détecte un passage à zéro d'une tension d'alimentation de ladite ligne d'alimentation ac.
PCT/SG2010/000138 2009-04-07 2010-04-07 Systèmes et procédés de données sur courants porteurs WO2010117340A1 (fr)

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SG200902388-8A SG166007A1 (en) 2009-04-07 2009-04-07 Pulse width modulate power line communication
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EP2640166A1 (fr) * 2012-03-12 2013-09-18 Anteya Technology Corporation Gradateur de puissance élevée et système de gradation à modes de puissance commutables, dispositif de gradation et procédé de transmission de puissance et commandes de gradation
AT14345U1 (de) * 2014-03-27 2015-09-15 Tridonic Gmbh & Co Kg Betriebsgerät für Leuchtmittel zur Übertragung von Informationen
AT14505U1 (de) * 2012-11-06 2015-12-15 Tridonic Gmbh & Co Kg Verfahren und Vorrichtung zur Datenübertragung über eine Lastleitung und Beleuchtungssystem
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DE102016217747A1 (de) 2016-09-16 2018-03-22 Tridonic Gmbh & Co Kg Bidirektionale Kommunikation mittels Phasenschnittmodulation einer AC-Versorgungsspannung
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CN113794491A (zh) * 2021-09-15 2021-12-14 上海工程技术大学 一种深井电力线载波通信的智能抗电磁干扰装置
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DE102010052662B4 (de) * 2010-11-26 2013-12-05 Abb Ag Datentelegramm-Generierungsverfahren zur Ansteuerung mindestens eines Lastmoduls bzw. einer Lampe über eine Lastleitung
DE102010052662A1 (de) * 2010-11-26 2012-05-31 Abb Ag Datentelegramm-Generierungsverfahren zur Ansteuerung mindestens eines Lastmoduls bzw. einer Lampe über eine Lastleitung
CN102651657A (zh) * 2011-02-25 2012-08-29 富泰华工业（深圳）有限公司 基于电力线的数据传输系统
CN102651657B (zh) * 2011-02-25 2016-06-29 富泰华工业（深圳）有限公司 基于电力线的数据传输系统
EP2640166A1 (fr) * 2012-03-12 2013-09-18 Anteya Technology Corporation Gradateur de puissance élevée et système de gradation à modes de puissance commutables, dispositif de gradation et procédé de transmission de puissance et commandes de gradation
AT14505U1 (de) * 2012-11-06 2015-12-15 Tridonic Gmbh & Co Kg Verfahren und Vorrichtung zur Datenübertragung über eine Lastleitung und Beleuchtungssystem
AT14345U1 (de) * 2014-03-27 2015-09-15 Tridonic Gmbh & Co Kg Betriebsgerät für Leuchtmittel zur Übertragung von Informationen
US9854649B2 (en) 2014-03-27 2017-12-26 Tridonic Gmbh & Co Kg Operating device for lamps for transmitting information
WO2016120786A1 (fr) * 2015-01-27 2016-08-04 Delta Electric Srl Procédé et dispositif de régulation de tension d'alimentation électrique
US10461809B2 (en) 2015-03-30 2019-10-29 Lighting And Illumination Technology Experience Limited Controlling power to a load with signals along a power line
WO2016156832A1 (fr) * 2015-03-30 2016-10-06 Lighting And Illumination Technology Experience Limited Commande d'énergie électrique vers une charge au moyen de signaux le long d'une ligne électrique
CN107710093A (zh) * 2015-04-07 2018-02-16 地球之星解决方案有限责任公司 用于定制化负载控制的系统和方法
EP3281078A4 (fr) * 2015-04-07 2018-09-05 Earth Star Solutions LLC Systèmes et procédés de commande de charge personnalisés
RU2706412C2 (ru) * 2015-04-07 2019-11-18 Ерт Стар Солюшнз, Ллк Системы и способы для индивидуального управления нагрузками
CN107710093B (zh) * 2015-04-07 2021-06-04 地球之星解决方案有限责任公司 用于定制化负载控制的系统、方法及电子设备
DE102016217747A1 (de) 2016-09-16 2018-03-22 Tridonic Gmbh & Co Kg Bidirektionale Kommunikation mittels Phasenschnittmodulation einer AC-Versorgungsspannung
DE102016217747B4 (de) 2016-09-16 2024-02-22 Tridonic Gmbh & Co Kg Verfahren zur bidirektionalen kommunikation mittelsphasenschnittmodulation einer ac-versorgungsspannung sowieentsprechend ausgestaltetes betriebsgerät, steuergerät undsystem
DE102018205756A1 (de) * 2018-04-16 2019-10-17 Tridonic Gmbh & Co Kg Vorrichtung, system und verfahren zur steuerung von leuchtvorrichtungen
AT17671U1 (de) * 2018-04-16 2022-10-15 Tridonic Gmbh & Co Kg Vorrichtung, System und Verfahren zur Steuerung von Leuchtvorrichtungen
CN113794491A (zh) * 2021-09-15 2021-12-14 上海工程技术大学 一种深井电力线载波通信的智能抗电磁干扰装置
CN113794491B (zh) * 2021-09-15 2023-02-24 上海工程技术大学 一种深井电力线载波通信的智能抗电磁干扰装置
WO2024125865A1 (fr) 2022-12-16 2024-06-20 Signify Holding B.V. Appareil d'entraînement de lampe et lampe à del

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