WO2010109816A1

WO2010109816A1 - Solid state image pickup device

Info

Publication number: WO2010109816A1
Application number: PCT/JP2010/001915
Authority: WO
Inventors: 片桐哲也; 楠田将之
Original assignee: コニカミノルタオプト株式会社
Priority date: 2009-03-24
Filing date: 2010-03-17
Publication date: 2010-09-30
Also published as: JPWO2010109816A1; JP4582267B1

Abstract

In a state where a column amplifier (10) is isolated from a pixel portion (1) and connected to a voltage source (80), the voltage source (80) outputs such a pseudo-pixel signal as to cause an SA register (60) to connect one of four capacitors (C1 to C4) to the column amplifier (10). A latch unit (40) measures a signal inputted to a comparator unit (30). A correction unit (61) corrects a weighting value for a bit corresponding to the one capacitor on the basis of the measurement result of the latch unit (40).

Description

Solid-state imaging device

The present invention relates to a solid-state imaging device that performs analog-digital conversion of a pixel signal by a successive approximation type analog-digital conversion method, and particularly relates to a technique for correcting a weighted value of each bit of digital data.

2. Description of the Related Art In recent years, a pixel unit in which a plurality of pixels are arranged in a matrix and a column AD conversion unit that reads a pixel signal from each pixel provided corresponding to each column of the pixel unit are provided. A CMOS image sensor that performs analog-to-digital conversion of the pixel signal read out in (1) is known. In such a CMOS image sensor, the column AD conversion unit generally includes an integration type AD converter, and generally performs AD (analog digital) conversion of a pixel signal by an integration type AD conversion method.

Here, when the resolution is increased in the integral type AD converter, there is a problem that the number of clocks required increases and AD conversion takes time. This is because, for example, in order to obtain n-bit digital data, a time of 2 n clocks is required.

In order to solve this problem, a technique for performing AD conversion by dividing digital data into an upper bit group and a lower bit group is known (Patent Document 2).

However, in the technique of Patent Document 2, since both the upper bit group and the lower bit group are AD-converted by the integral AD conversion method, the AD conversion speed cannot be increased so much.

In order to solve this problem, a technique is known in which the upper bit group is AD-converted using a successive approximation type instead of an integration type (Patent Document 3).

FIG. 8 shows a circuit diagram of a column AD conversion unit that AD-converts the upper bit group by the successive approximation AD conversion method and AD-converts the lower bit group by the integration AD conversion method. FIG. 9 shows a timing chart of the column AD converter shown in FIG.

The column AD conversion unit shown in FIG. 8 is a 15-bit column AD conversion unit in which one bit is added as a redundant bit, and is divided into an upper bit group of upper 4 bits and a lower bit group of lower 11 bits including redundant bits. Then, AD conversion is performed.

As shown in FIG. 8, the column AD conversion unit includes a column amplifier 100, a clamp unit 200, a comparator unit 300, a latch circuit 400, a successive approximation signal generation unit 500, and an SA (Successive Approximation) register 600.

The operation of the pixel circuit shown in FIG. 8 will be described with reference to FIGS. First, when a high-potential signal, which is a noise (Noise) component pixel signal Video, is output to the vertical signal line L1, φARST, φCL, φCRST1, and φCRST2 are set to Hi (high level) for a certain period, When the amplifier 100, the clamp unit 200, and the comparator unit 300 are reset and φGainA = Hi and φGainB = Lo, the pixel signal Video of the Noise component is sampled and held in the capacitor CA.

Thereafter, in the pixel, the charge accumulated in the photodiode is transferred to the floating diffusion, and is lower by the magnitude of the Signal component than the Noise component which is the pixel signal Video of the (Noise + Signal) component from the pixel portion via the vertical signal line L1. A potential signal is output.

When the pixel signal Video decreases to the level of the (Signal + Noise) component, the output signal AOUT of the column amplifier 100 increases from VOPA, which is the reset level of the column amplifier 100, according to the magnitude of the Signal component. The magnitude of this change in VOPA depends on the gain settings of φGainA and φGainB. That is, as shown in the timing chart of FIG. 9, when both φGainA and φGainB are Hi, the gain of the column amplifier 100 is (CA + CB) / CF, and the output signal AOUT of the column amplifier 100 is Signal · Increase by (CA + CB) / CF.

Thereafter, AD conversion of the upper bit group is started by the successive approximation AD conversion method. First, φSA1 = Hi, and the capacitor C1 is connected to the column amplifier 100. Here, since the voltage VREF is input to the other end of the capacitor C1, the potential input to the column amplifier 100 increases by VREF · C1. When the potential input to the column amplifier 100 increases, AOUT decreases by VREF · (C1 / CF).

A signal CIN (hereinafter referred to as “CIN”) input to the comparator unit 300 has a DC level different from AOUT because the clamp unit 200 exists between the column amplifier 100 and the comparator unit 300, but the AC level. Changes in the same way as AOUT.

Specifically, since the gain KG of the clamp part 200 is KG = C21 / (C21 + C22), when φSA1 = Hi, CIN decreases by KG · VREF · (C1 / CF) = TH1. Here, when φSA1 = Hi, if CIN becomes equal to or lower than VOPC which is the threshold voltage of the comparator unit 300, COUT is inverted from Hi to Lo. In the timing chart of FIG. 9, even if TH1 decreases by TH1, it is higher than VOPC, so COUT does not invert and maintains Hi (period T1).

In this case, since COUT = Hi is maintained, the SA register 600 maintains φSA1 = Hi. Maintaining φSA1 = Hi means MSB (D1) = 1 of the upper bit group, and therefore SA register 600 sets D1 = 1.

Next, the SA register 600 maintains φSA1 = Hi and sets φSA2 = Hi, and connects the capacitor C2 to the column amplifier 100.

At this time, the potential of AOUT changes by VREF · (C2 / CF), and the potential of CIN changes by KG · VREF · (C2 / CF) = TH2. In the example of FIG. 9, since CIN becomes equal to or less than VOPC, COUT is inverted from Hi to Lo (period T2).

When COUT = Lo, the SA register 600 returns φSA2 from Hi to Lo, and disconnects the capacitor C2 from the column amplifier 100. Here, the SA register 600 sets D2 = 0 since φSA2 has returned to Lo.

Next, the SA register 600 maintains φSA1 = Hi and φSA2 = Lo, sets φSA3 = Hi, and connects the capacitor C3 to the column amplifier 100. As a result, the potential of AOUT changes according to VREF · (C3 / CF), and the potential of CIN changes according to KG · VREF · (C3 / CF) = TH3. In the example of FIG. 9, CIN increases, but CIN is equal to or lower than VOPC, so COUT = Lo is maintained (period T3). Since COUT = Lo is maintained, the SA register 600 returns φSA3 from Hi to Lo, and disconnects the capacitor C3 from the column amplifier 100. Here, the SA register 600 sets D3 = 0 since φSA3 returns to Lo.

Next, the SA register 600 maintains φSA1 = Hi, φSA2 = Lo, φSA3 = Lo, sets φSA4 = Hi, and connects the capacitor C4 to the column amplifier 100. Thus, the potential of AOUT changes according to VREF · (C4 / CF), and the potential of CIN changes according to KG · VREF · (C4 / CF) = TH4 (not shown). In the example of FIG. 9, since the potential of CIN exceeds VOPC, COUT is inverted from Lo to Hi (period T4). Since COUT is inverted to Hi, the SA register 600 maintains φSA4 = Hi. Here, since the SA register 600 maintains φSA4 = Hi, D4 = 1 is set.

Then, the upper bit group can be digitized by performing the above-described operation by giving C1, C2, C3, C4, CF, C21, C22, and VREF a certain relationship.

Next, when a ramp signal (hereinafter referred to as “VRAMP”) is input to the comparator unit 300, VRAMP is superimposed on CIN after AD conversion of the upper bit group, and the time until CIN becomes VOPC is counted. (Time T6), this count value becomes the value of the lower bit group.

FIG. 10 is a diagram conceptually illustrating an AD conversion operation by the successive approximation AD conversion method. Here, the vertical direction indicates the CIN level. TH1 to TH4 are KG · (C1 / CF) · VREF, KG · (C2 / CF) · VREF, KG · (C3 / CF) · VREF, and KG · (C4 / CF) · VREF, respectively. Yes. D1 to D4 indicate 4-bit digital data.

The operation of the column AD conversion unit is conceptually described with reference to FIG. 10. First, the column AD conversion unit compares CIN with TH1, and when CIN> TH1, D1 = 1, and when CIN <TH1, Let D1 = 0.

Next, when D1 = 1, the column AD conversion unit compares CIN with TH2 as a value obtained by subtracting TH1 from CIN, and when D1 = 0, CIN is directly compared with TH2, and CIN> TH2 In this case, D2 = 1, and if CIN <TH2, D2 = 0.

Next, when D2 = 1, the column AD converter compares CIN with TH3 as a value obtained by subtracting TH2 from CIN, and when D2 = 0, CIN is directly compared with TH3, and CIN> TH3 In this case, D3 = 1, and if CIN <TH3, D3 = 0.

Next, when D3 = 1, the column AD conversion unit compares CIN with TH4 as a value obtained by subtracting TH3 from CIN, and when D3 = 0, CIN is directly compared with TH4, and CIN> TH4. In this case, D4 = 1, and if CIN <TH4, D4 = 0.

In the example of the timing chart of FIG. 9, CIN belongs to 升 α. Therefore, D1 to D4 = 1, 0, 0, 1.

FIG. 11 is a graph showing an ideal AD conversion characteristic of the upper bit group and an AD conversion characteristic of the lower bit group in the column AD conversion unit of FIG. In FIG. 11, the horizontal axis represents an analog pixel signal (analog input) input to the column AD converter, the left vertical axis represents the value of the upper bit group, and the right vertical axis represents the value of the lower bit group. G1 indicates the AD conversion characteristic of the upper bit group, and g2 indicates the AD conversion characteristic of the lower bit group.

As shown in FIG. 11, the value of the high-order bit group changes in 16 steps from 0 to 15 stepwise as the analog input increases. It can be seen that the value of the lower bit group changes in a saw-like manner, with one step of the upper bit group being one period.

As described in Patent Document 3, when AD conversion is performed by dividing into an upper bit group and a lower bit group, a matching error always occurs between the value of the upper bit group and the value of the lower bit group. In general, one redundant bit is provided in the lower bit group.

The column AD converter in FIG. 8 finally obtains 14-bit digital data. Since the upper bit group is 4 bits, the resolution of the lower bit group is 10 bits, but the lower bit group is 1-bit redundant. It has a bit and is 11 bits.

Therefore, as shown in FIG. 11, the dynamic range of the lower bit group is obtained by removing the upper 0.5-bit redundant bit and the lower 0.5-bit redundant bit.

When the AD conversion characteristics shown in FIG. 11 are shown, if the dynamic range of the lower and upper redundant bits is subtracted from the lower bit group and synthesized with the upper bit group, the smooth linear 14 bits as shown in FIG. The AD conversion characteristics can be obtained.

That is, by removing redundant bits from the lower bit group and multiplying each bit of the upper bit group by the weighting value, the AD conversion characteristics of FIG. 12 can be obtained. Here, the weighting value is a weighting value used when converting a binary number to a decimal number, and the finally obtained digital data is 14 bits. 2 ¹³ = 8192, 2 ¹² = 4096, 2 ¹¹ = 2048, 2 ¹⁰ = 1024, respectively.

In practice, however, the capacitances of the capacitors C1 to C4 are deviated from the ideal values, and the CIN when the capacitors C1 to C4 are connected to the column amplifier 100 is generally deviated from the ideal values. The AD conversion characteristics of the bit group and the lower bit group are as shown in FIG. In FIG. 13, it can be seen that the dynamic range of the lower bit group varies depending on the value of the upper bit group.

In the case of the AD conversion characteristics as shown in FIG. 13, in the method of simply removing redundant bits from the lower bit group and synthesizing it into the upper bit group, if the weight values of each bit of the upper bit group are directly adopted, as shown in FIG. Smooth linear AD conversion characteristics cannot be obtained. Specifically, an AD conversion characteristic in which the straight line shown in FIG. 12 is divided and discontinuously connected for each step of the upper bit group is obtained.

Therefore, conventionally, the signal input to the column amplifier 100 is set to 0, the column amplifier 100 and the capacitors C1 to C4 are forcibly connected to the SA register 600, the value of CIN is measured, and based on the measurement result. Correction of the weight value of each bit of the upper bit group has been performed.

On the other hand, when the signal input to the column amplifier 100 during normal operation is 0, since the values of the upper bit group are all 0 for D1 to D4, the SA register 600 causes the capacitors C1 to C4 to be connected to the column amplifier. After sequentially connecting to 100, all the capacitors C1 to C4 should not be connected to the column amplifier 100 in the end.

However, in the conventional CIN measurement method, for example, when measuring CIN when the capacitor C1 is connected to the column amplifier 100, the SA register 600 is compulsory even though the values of D1 to D4 are all zero. The capacitor C1 is connected to the column amplifier 100. Therefore, the SA register 600 is forced to operate differently from the normal operation. As a result, for example, the value of CIN input to the comparator unit 300 when the capacitor C1 is connected to the column amplifier 100 differs between normal operation and measurement, and CIN cannot be measured with high accuracy. there were. As a result, there is a problem that the weighting value of each bit of the upper bit group cannot be corrected with high accuracy.

Japanese Patent No. 2532374 Japanese Patent No. 3507800 JP 2008-244716 A

An object of the present invention is to provide a solid-state imaging device capable of accurately correcting the weighting value of each bit of digital data.

According to one aspect of the present invention, a solid-state imaging device is provided corresponding to a pixel portion in which a plurality of pixels are arranged in a matrix, a vertical scanning circuit that sequentially selects each row of the pixel portion, and each column of the pixel portion. A plurality of readout circuits that read out pixel signals from pixels in a row selected by the vertical scanning circuit and perform analog-to-digital conversion, and the readout circuit includes a column amplifier that amplifies the pixel signals read out from the pixel unit; A comparator unit that inverts the output signal by comparing the signal output from the column amplifier with a predetermined reference voltage, and a signal having a different level provided for each bit of the digital data to be converted from analog to digital A plurality of successive approximation capacitors for outputting to the column amplifier, a voltage source for outputting a pseudo pixel signal, the successive approximation capacitor, The bit determination unit that sequentially switches the connection relationship with the column amplifier and determines the value of the digital data of the pixel signal by the successive approximation type analog-to-digital conversion method based on the output signal output from the comparator unit; A measurement unit that measures a signal input to the comparator unit, and one sequential comparison with the bit determination unit in a state where the column amplifier and the pixel unit are disconnected and the column amplifier is connected to the voltage source A pseudo pixel signal that connects a capacitor to the column amplifier is output to the voltage source, and a signal input to the comparator unit is measured by the measurement unit. Based on a measurement result by the measurement unit, the one A correction unit that corrects the weighting value of the bit corresponding to the successive approximation capacitor.

1 is an overall configuration diagram of a solid-state imaging device according to an embodiment of the present invention. The circuit diagram of the column AD conversion part shown in FIG. 1 is shown. It is a flowchart which shows a correction process. It is the graph which showed Y <0>. It is the graph which showed Y <4>. It is the graph which showed Y <3>. It is the graph which showed Y <2>. The circuit diagram of the column AD conversion part which AD-converts an upper bit group by a successive approximation AD conversion system, and AD-converts a lower bit group by an integral AD conversion system is shown. 9 shows a timing chart of the column AD converter shown in FIG. It is a figure which illustrates notionally AD conversion operation | movement of a successive approximation type AD conversion system. It is the graph which showed the AD conversion characteristic of the ideal upper bit group and lower bit group. 3 is a graph showing ideal AD conversion characteristics. It is the graph which showed the actual AD conversion characteristic of a high-order bit group and a low-order bit group.

FIG. 1 is an overall configuration diagram of a solid-state imaging device according to an embodiment of the present invention. As shown in FIG. 1, the solid-state imaging device is a solid-state imaging device using a column parallel AD conversion type (column AD conversion type) CMOS image sensor, and includes a pixel unit 1, a vertical scanning circuit 2, and a column AD as a readout circuit. A conversion unit 3, a horizontal scanning circuit 4, a control unit 5, an image processing unit 6, and an image memory 7 are provided.

The pixel unit 1 has a plurality of pixels arranged in a matrix of 8 rows × 8 columns. Note that 8 rows × 8 columns is an example, and may be arranged in M (M is a positive integer of 2 or more) rows × N (N is a positive integer of 2 or more) columns.

The vertical scanning circuit 2 is configured by, for example, a shift register, and is connected to the pixel unit 1 via eight pixel control lines HL1 corresponding to the first to eighth rows of the pixel unit 1. . The vertical scanning circuit 2 performs vertical scanning of the pixel unit 1 by cyclically selecting the pixel control lines HL1 in the first to eighth rows in synchronization with the vertical synchronization signal VD.

The horizontal scanning circuit 4 is composed of, for example, a shift register, and outputs a column selection signal in synchronization with the horizontal synchronization signal HD, so that the column AD conversion units for the first to eighth columns in one horizontal scanning period. 3 is selected cyclically, the column AD conversion unit 3 is horizontally scanned, and the pixel signals of the first to eighth columns held by the column AD conversion unit 3 are sequentially output.

The control unit 5 includes a microcomputer including a CPU (Central Processing Unit), a ROM (Read Only Memory), and a RAM (Random Access Memory), and controls the entire solid-state imaging device.

The image processing unit 6 is configured by a dedicated hardware circuit, and performs various image processing on the image data output from each column AD conversion unit 3. In the present embodiment, the image processing unit 6 particularly includes a correction unit 61. Details of the processing of the correction unit 61 will be described later.

The image memory 7 is composed of a storage device such as a hard disk, and stores image data that has been subjected to predetermined image processing by the image processing unit 6.

FIG. 2 shows a circuit diagram of the column AD conversion unit 3 shown in FIG. The column AD conversion unit 3 includes a column amplifier 10, a clamp unit 20, a comparator unit 30, a latch unit 40 as a measurement unit, a successive approximation signal generation unit 50, an SA register 60 as a bit determination unit, and a switch unit 70. Yes.

In FIG. 2, φCORR, φXCORR, φGainA, φGainB, φARST, φCL, φSH, φCMP, φCRST1, and φCRST2 indicate control signals, and are output from the control unit 5, for example. VRAMP indicates a ramp signal and is output from the control unit 5, for example.

The column amplifier 10 performs an amplification process on the pixel signal Video output from the pixel unit 1 while performing a CDS process, and removes a noise signal from the pixel signal Video.

Specifically, the column amplifier 10 includes an operational amplifier A10, capacitors CA, CB, and CF, and switches SW3, SW4, and SW5. The capacitors CA and CB are connected to the negative terminal side of the operational amplifier A10 via switches SW3 and SW4. The capacitor CF is a feedback capacitor provided between the input and output terminals of the operational amplifier A10.

The switch SW3 is a switch for connecting the capacitor CA to the operational amplifier A10. For example, the switch SW3 is turned on when φGainA = Hi (high level) to connect the capacitor CA to the negative terminal of the operational amplifier A10, and φGainA = Lo (low level). Is turned off and the capacitor CA is disconnected from the negative terminal of the operational amplifier A10.

The switch SW4 is a switch for connecting the capacitor CB to the operational amplifier A10. For example, the switch SW4 is turned on when φGainB = Hi (high level) to connect the capacitor CB to the negative terminal of the operational amplifier A10, and φGainB = Lo (low level). Is turned off to disconnect the capacitor CB from the negative terminal of the operational amplifier A10.

The switch SW5 is connected in parallel with the capacitor CF and is turned on when φARST = Hi, turned off when φARST = Lo, resets the column amplifier 10, and sets the potential between the negative terminal of the operational amplifier A10 and the output terminal of the operational amplifier A10 to a predetermined value. To the reset level (hereinafter referred to as “VOPA”). Note that VOPA is always applied to the plus terminal of the operational amplifier A10.

Here, the column amplifier 10 amplifies the input signal with the gain of CA / CF when the switch SW3 = on, and amplifies the input signal with the gain of CB / CF when the switch SW4 = on. When the switches SW3 and SW4 are on, the input signal is amplified with a gain of (CA + CB) / CF.

The clamp unit 20 is provided on the output terminal side of the column amplifier 10 and clamps the black level of the pixel signal Video to a clamp voltage VCL that is a predetermined constant voltage. Here, the clamp unit 20 includes switches SW6 and SW7 and capacitors C21 and C22. One end of the switch SW6 is grounded via the capacitors C21 and Cx, and is connected to the output terminal of the operational amplifier A10 via the capacitor C21. The other end is connected to a clamp voltage source (not shown) that outputs the clamp voltage VCL. Turns on when φCL = Hi, and turns off when φCL = Lo.

The switch SW7 has one end connected to the capacitor C21 and the other end connected to the comparator unit 30 via the capacitor C22. The switch SW7 is turned on when φSH = Hi to connect between the column amplifier 10 and the comparator unit 30, and φSH = When it is Lo, it is turned off and the column amplifier 10 and the comparator unit 30 are disconnected.

The capacitor Cx has one end connected to the capacitor C21 and the other end grounded to hold AOUT.

The comparator unit 30 includes switches SW10, SW8, SW9, a capacitor C31, and comparators A31, A32.

One end of the switch SW10 is connected to the negative terminal of the comparator A31 via the capacitor C22, and VRAMP is input to the other end, and is turned on when φCMP = Hi, and VRAMP is input to the negative terminal of the comparator A31. When φCMP = Lo, it turns off and VRAMP is not input to the negative terminal of the comparator A31.

In this embodiment, the pixel signal Video is AD-converted separately into an upper bit group of upper 4 bits and a lower bit group of lower 11 bits (including 1 redundant bit). Then, the column AD conversion unit 3 performs AD conversion on the upper bit group by the successive approximation AD conversion method, and AD converts the lower bit group by the integration AD conversion method.

For this reason, VRAMP employs a ramp signal that increases with time in the range of 0 to 2048 (= 2 ¹¹ ), for example, in order to AD-convert the lower bit group.

The switch SW8 is connected between the input and output terminals of the comparator A31. The switch SW8 is turned on when φCRST1 = Hi and turned off when φCRST1 = Lo. The comparator A31 is reset, and the negative terminal of the comparator A31 and the output terminal of the comparator A31 are connected. The potential is set to a predetermined reset level (hereinafter referred to as “VOPC”). Note that VOPC is always applied to the plus terminal of the comparator A31.

Comparator A31 compares the signal input to the negative terminal (hereinafter referred to as “CIN”) with VOPC. When CIN exceeds VOPC, the output signal is inverted to a low level, and when CIN falls below VOPC, Invert the output signal to high level.

The switch SW9 is connected between the input and output terminals of the comparator A32. The switch SW9 is turned on when φCRST2 = Hi and turned off when φCRST2 = Lo. The comparator A32 is reset, and the negative terminal of the comparator A32 and the output terminal of the comparator A32 are connected. The potential is set to VOPC which is a reset level. Note that VOPC is always applied to the plus terminal of the comparator A32.

The comparator A32 has a negative terminal connected to the comparator A31 via the capacitor C31, and when the output signal from the comparator A31 exceeds VOPC, the output signal (hereinafter referred to as “COUT”) is inverted to Lo and the comparator A31. When the output signal from VOPC falls below VOPC, COUT is inverted to Hi.

The latch unit 40 includes eleven latch circuits 41 that latch the value (= D5 to D15) of each bit of the lower bit group.

The counter 90 is constituted by, for example, an 11-bit counter provided in the control unit 5 shown in FIG. 1. After the input to the comparator unit 30 of VRAMP is started, CIN reaches VOPC and COUT is inverted. Until the count value is counted and the latch circuit 41 latches the count value.

The successive approximation signal generation unit 50 includes capacitors C1 to C4 as successive approximation capacitors and switches SA1 to SA4. Capacitors C1 to C4 output signals having different levels to the column amplifier 10 corresponding to the respective bits of the upper bit group. Specifically, one end of each of the capacitors C1 to C4 is connected to a voltage source (not shown) that outputs a reference voltage (hereinafter referred to as “VREF”) via the switches SA1 to SA4, and the other end is connected to the operational amplifier A10. Is connected to the negative terminal.

In this embodiment, the capacitors C1 to C4 correspond to D1 to D4, where each bit of the upper bit group is D1 to D4 in order from the most significant bit.

Here, when the dynamic range of KG · Signal · ((CA + CB) / CF) is W (where KG = C21 / (C21 + C22)), the capacities of the capacitors C1 to C4 are, for example, KG · (C1 / CF).・ VREF = W / 2, KG ・ (C2 / CF) ・ VREF = W / 4, KG ・ (C3 / CF) ・ VREF = W / 8, KG ・ (C4 / CF) ・ VREF = W / 16 Is set to When the threshold values of D1 to D4 are TH1 to TH4, TH1 = W / 2, TH2 = W / 4, TH3 = W / 8, and TH4 = W / 16.

The switches SA1 to SA4 are turned on when φSA1 to φSA4 = Hi to connect C1 to C4 to VREF, and turned off when φSA1 to φSA4 = Lo to connect C1 to C4 to the ground terminal (Ground). Here, φSA1 to φSA4 are output by the SA register 60.

The SA register 60 sequentially switches the connection relationship between the capacitors C1 to C4 and the column amplifier 10, and based on COUT output from the comparator unit 30, the value of the upper bit of the pixel signal Video is determined by the successive approximation AD conversion method. decide.

Here, the SA register 60 sequentially connects the capacitors C1 to C4 to the column amplifier 10 in the descending order of capacity, and one of the capacitors C1 to C4 is connected to the column amplifier 10. Based on the presence or absence of inversion, whether to maintain the connection of the one capacitor to the column amplifier 10 is determined, and the value of the bit corresponding to the one capacitor is determined.

Specifically, the SA register 60 connects the capacitor C1 to the column amplifier 10, maintains φSA1 = Hi and sets D1 = 1 when COUT does not invert. On the other hand, when the capacitor C1 is connected to the column amplifier 10 and COUT is inverted, the SA register 60 switches φS1 = Lo and sets D1 = 0.

Then, the SA register 60 sequentially connects the capacitors C2 to C4 to the column amplifier 10, and when COUT when a certain capacitor is connected is inverted, the bit value corresponding to the one capacitor is increased by one. When the bit value is opposite to the bit value and the bit corresponding to the one capacitor is 1, the connection of the capacitor to the column amplifier 10 is maintained, and the bit corresponding to the one capacitor is 0. In this case, the connection of the one capacitor to the column amplifier 10 is cut off.

The switch unit 70 is connected between the vertical signal line L1 and the column amplifier 10, and under the control of the correction unit 61, the column amplifier 10 and the vertical signal line L1 are disconnected to connect the column amplifier 10 to the voltage source 80.

Here, the switch unit 70 includes switches SW1 and SW2. The switch SW1 is provided between the voltage source 80 and the column amplifier 10, and is turned on when φCORR = Hi to connect the voltage source 80 to the column amplifier 10, and turned off when φCORR = Lo to turn off the voltage source 80. Disconnect from.

The switch SW2 is provided between the column amplifier 10 and the vertical signal line L1, and is turned on when φXCORR = Hi to connect the vertical signal line L1 to the column amplifier 10, and turned off when φXCORR = Lo to turn off the vertical signal line L1. Disconnect from the column amplifier 10. Here, the Hi and Lo timings of φCORR and φXCORR are determined so that the switches SW1 and SW2 are turned on complementarily.

As described above, since the switches SW1 and SW2 are provided, the load capacity viewed from the operational amplifier A10 is the same in the normal operation of reading the pixel signal Video and in the measurement of measuring CIN.

That is, during normal operation, the switch SW1 = off and the switch SW2 = on, so that the load capacity viewed from the operational amplifier A10 is the capacitors CA, CB and the capacitors C1 to C4 sequentially connected by the SA register 60. On the other hand, at the time of measurement, since the switch SW1 is turned on and the switch SW2 is turned off, the load capacity viewed from the operational amplifier A10 is the capacitors CA1 and C4 and the capacitors C1 to C4 sequentially connected by the SA register 60. Therefore, the load capacity viewed from the operational amplifier A10 is the same during normal operation and during measurement.

Next, the operation of the column AD conversion unit 3 shown in FIG. 2 will be described. The operation of the column AD conversion unit 3 is the same as that in FIG. 9 and will be described with reference to the timing chart of FIG. In the following description, it is assumed that SW3 and SW4 are both turned on.

First, when a Noise component pixel signal Video is output from the pixel to the vertical signal line L1, φARST, φCL, φCRST1, φCRST2, and φSH are set to Hi for a certain period, and the column amplifier 10, the clamp unit 20, and the comparator unit 30 are It is reset.

Next, the noise component pixel signal Video is sampled and held by the capacitors CA and CB.

Next, a signal having a potential lower than the Noise component, which is the (Noise + Signal) component pixel signal Video, is output from the pixel unit 1 through the vertical signal line L1.

Next, when the pixel signal Video decreases to the level of the (Noise + Signal) component, the output signal AOUT of the column amplifier 10 increases from VOPA by Signal · ((CA + CB) / CF) according to the magnitude of the Signal component.

In addition, since the gain KG of the clamp unit 20 is KG = C21 / (C21 + C22), CIN increases from VOPC by KG · Signal · ((CA + CB) / CF). At this time, the comparator unit 30 inverts COUT = Hi because CIN> VOPC.

Next, φSA1 = Hi, the capacitor C1 is connected to the column amplifier 10, the potential input to the column amplifier 10 increases only by VREF · C1, and AOUT decreases by VREF · (C1 / CF). Along with this, CIN decreases by KG · VREF · (C1 / CF) = TH1 and becomes level VL1 (period T1).

At this time, the SA register 60 satisfies CIN> VOPC and COUT does not invert, so φSA1 = Hi is maintained and D1 = 1 is set (period T1).

That is, the SA register 60 compares the initial CIN (= KG · Signal · (CA + CB) / CF) with the threshold TH1 (= KG · VREF · (C1 / CF)) of D1, and CIN> TH1. Therefore, φSA1 = Hi is maintained and D1 = 1 is set.

Next, in the state where φSA1 = Hi, φSA2 = Hi, and the capacitor C2 is connected to the column amplifier 10. As a result, CIN decreases from level VL1 by KG · VREF · (C2 / CF) = TH2, CIN <VPOC, and COUT is inverted from Hi to Lo. Therefore, the SA register 60 returns to φSA2 = Lo and the capacitor C2 is separated from the column amplifier 10, and D2 = 0 is set (period T2).

That is, the SA register 60 compares α (= initial CIN−TH1) obtained by subtracting TH1 from the initial CIN by the period T1 and TH2 (= KG · VREF · (C2 / CF)) which is a threshold value of D2. Since CIN−TH1 <TH2 at the initial stage, φSA2 = Lo is returned to D2 = 0.

Next, in the state of φSA1 = Hi and φSA2 = Lo, φSA3 = Hi and the capacitor C3 is connected to the column amplifier 10. As a result, CIN increases from level VL1 to a level lower by KG · VREF · (C3 / CF) = TH3. However, CIN <VPOC and COUT maintains Lo, so SA register 60 sets φSA3 to Lo. Returning to D3 = 0 (period T3).

That is, the SA register 60 compares β = TH2- (initial CIN-TH1) and γ (= TH2-TH3), and TH2- (initial CIN-TH1)> TH2-TH3 Since CIN-TH1 <TH3, D3 = 0 and φSA3 = Lo are returned. TH3 is a threshold value of D3, and TH3 = KG · VREF · (C3 / CF)).

Next, in the state of φSA1 = Hi, φSA2 = Lo, φSA3 = Lo, φSA4 = Hi and the capacitor C4 is connected to the column amplifier 10. As a result, CIN rises from level VL1 to VL2 which is lower by KG · VREF · (C4 / CF), CIN> VPOC, and COUT inverts from Lo to Hi. Therefore, SA register 60 has φSA4 = Hi. And D4 = 1 (period T4).

That is, the SA register 60 compares TH3- (initial CIN-TH1) with TH3-TH4, and TH3- (initial CIN-TH1) <TH3-TH4 is referred to as initial CIN-TH1> TH4. Therefore, D4 = 1 and φSA4 = Hi is maintained. TH4 is a threshold value of D4, and TH4 = VREF · (C4 / CF)).

Thus, the AD conversion period of the upper bit group ends, and D1 to D4 = 1, 0, 0, 1. At this time, the CIN having the level VL2 is held by the capacitor C22.

Next, φCRST1 and φCRST2 are set to Hi for a certain period, the comparators A31 and A32 are reset, and COUT = VOPC is set.

Next, φSH = Lo and the comparator unit 30 and the clamp unit 20 are disconnected, φCMP = Hi and VRAMP is input to the comparator unit 30, VRAMP is superimposed on CIN of the level VL 2 held in the capacitor C 22, and CIN is The voltage decreases from VL2 by the level ΔVa according to the initial level of VRAMP (time T5). As a result, CIN <VOPC and COUT is inverted from VOPC to Lo. At time T5, the counter 90 starts a counting operation.

Next, when CIN exceeds the level of VOPC (time T6), COUT is inverted from Lo to Hi. Then, the counter 90 stops the count operation and latches the count value at time T6 in the latch circuit 41. Thereby, the value of each bit of the lower bit group is determined.

Returning to FIG. 1, the correction unit 61 disconnects the column amplifier 10 and the pixel unit 1 and connects the column amplifier 10 to the voltage source 80, and the SA register 60 is one capacitor among the capacitors C1 to C4. Is output to the voltage source 80 so as to connect to the column amplifier 10. Then, the correction unit 61 causes the latch unit 40 to measure CIN, and corrects the weighting value of the bit corresponding to the one capacitor based on the measurement result by the latch unit 40.

Here, the correction unit 61 disconnects the column amplifier 10 and the pixel unit 1 and connects the column amplifier 10 to the voltage source 80, and one of the capacitors C1 to C4 is connected to the column amplifier 10. The pseudo pixel signals having different levels to be connected are output to the voltage source 80 at least twice. Then, the correction unit 61 interpolates each time of the digital measurement value measured by the latch unit 40, calculates a first function indicating the relationship between the voltage of the pseudo pixel signal and the digital measurement value, and calculates the calculated first value. Based on this function, the weight value of the bit corresponding to the one capacitor is corrected.

Then, the correction unit 61 causes the voltage source 80 to output a pseudo pixel signal that does not connect all of the capacitors C1 to C4 to the column amplifier 10 at least twice, and in the same manner as the first function, A second function indicating the relationship with the measured value is calculated, and the weight value of the bit corresponding to the one successive approximation capacitor is corrected based on the difference between the first function and the second function.

Thus, the weighting value can be corrected using the first function and the second function. Here, when the solid-state imaging device shown in FIG. 1 acquires a moving image at a predetermined frame rate, the correction unit 61 cuts off the voltage between the column amplifier 10 and the pixel unit 1 by applying voltage to the column amplifier 10 during the vertical blanking period. What is necessary is just to make it the state connected to the source 80.

In this case, it is possible to correct in real time the fluctuation of the weighting value due to the capacitors C1 to C4 that fluctuate as needed during imaging.

Next, the correction process executed centering on the correction unit 61 will be described in detail. FIG. 3 is a flowchart showing this correction processing.

First, the correction unit 61 causes the voltage source 80 to output a pseudo pixel signal at such a level that the SA register 60 blocks the capacitors C1 to C4 from the column amplifier 10 (step S1).

In the present embodiment, the column amplifier 10 subtracts the pixel signal Video of the Noise component output in the first phase from the pixel signal Video of the (Noise + Signal) component, specifically, a signal according to the Signal component, specifically, , Signal · (CA + CB) / CF is output as AOUT.

Therefore, the voltage source 80 outputs a pseudo pixel signal having a level corresponding to the Noise component in the first phase to the column amplifier 10 and then outputs a pseudo pixel signal having a level corresponding to the (Noise + Signal) component in the second phase to the column amplifier 10. Output to.

At this time, if the voltage source 80 uses the difference between the pseudo-pixel signals of the first phase and the second phase as a pseudo-Signal component (hereinafter referred to as “Signal ′”), the SA register 60 sets D1 to D4 = 0. , 0, 0, 0 are output to the first phase and the second phase.

When the pseudo pixel signal is output in step S1, the SA register 60 sequentially connects the capacitors C1 to C4, and finally shuts off all of C1 to C4 from the column amplifier 10.

Next, the latch unit 40 counts the time from when VRAMP is input until CIN exceeds VOPC, and obtains the values of D5 to D15 of the lower bit group, thereby measuring the digital measurement value of CIN ( Step S2).

Next, when the latch unit 40 has finished the two CIN measurements (YES in step S3), the correction unit 61 advances the process to step S4. On the other hand, when the latch unit 40 has not finished the two measurements of CIN (NO in step S3), the correction unit 61 returns the process to step S1 and causes the voltage source 80 to measure the first CIN. The column amplifier 10 is made to output a pseudo-pixel signal of a predetermined level such that Signal ′ is different and D1 to D4 = 0, 0, 0, 0.

Next, the correction unit 61 plots the two digital measurement values of CIN measured by the latch unit 40 in a two-dimensional coordinate space having Signal ′ as the horizontal axis and the CIN digital measurement value as the vertical axis, Y <0> as the second function is calculated (step S4).

FIG. 4 is a graph showing Y <0>. In FIG. 4, the vertical axis indicates the CIN digital measurement value by the latch unit 40, and the horizontal axis indicates Signal ′.

4, X1 represents Signal ′ at the time of the first measurement, and Y1 represents a digital measurement value of CIN at the time of the first measurement. X2 represents Signal 'at the time of the second measurement, and Y2 represents a digital measurement value of CIN at the time of the second measurement.

Then, the correction unit 61 calculates Y <0> by linearly interpolating the two points (X1, Y1) and (X2, Y2), for example. Assuming that Y <0> is Y = a · X + b, Y <0> is Y <0> = ((Y2−Y1) / (X2−X1)) · X + (X2 · Y1−X1 · Y2) / It is represented by (X2-X1).

That is, in Y <0>, the slope a is represented by a = (Y2-Y1) / (X2-X1), and the Y intercept B0 is represented by B0 = (X2, Y1-X1, Y2) / (X2-X1). It is a straight line represented.

Y <0> represents the AD conversion characteristics of D5 to D15 with respect to Signal ′ when D1 to D4 = 0, 0, 0, 0. Therefore, ideally, Y <0> should draw Y = 0 when Signal ′ = 0 and draw an RL that is a straight line with a slope equal to VRAMP.

However, Y <0> deviates from RL due to changes over time in the capacitance of capacitors (for example, capacitors CA, CB, etc.) constituting the column AD conversion unit 3 and due to individual variations inherent in the capacitor.

Returning to FIG. 3, in step S5, the correction unit 61 sets i, which is an index of one capacitor Ci among the capacitors C1 to C4, to i = 4.

Next, the correction unit 61 outputs to the voltage source 80 a pseudo pixel signal such that the SA register 60 sequentially connects the capacitors C1 to C4 to the column amplifier 10 and finally connects only the capacitor Ci and only the column amplifier 10. Let For example, in the case of i = 4, the signal “Signal ′” in which the SA register 60 connects only the capacitor C4 to the column amplifier 10, that is, the pseudo pixel signal in which the SA register 60 sets D1 to D4 = 0, 0, 0, 1. Is output from the voltage source 80.

Next, the latch unit 40 measures the digital measurement value of CIN (step S7). Next, the correction | amendment part 61 advances a process to step S9, when two measurement of CIN is complete | finished with respect to one i (it is YES at step S8).

On the other hand, when the two measurements of CIN for one i have not been completed (NO in step S8), the correction unit 61 returns the process to step S6, and only the capacitor Ci is connected to the column amplifier 10, In addition, a pseudo pixel signal having a different Signal ′ value from the first measurement is output to the voltage source 80.

For example, in the case of i = 4, the pseudo-pixel signal having a different Signal ′ in which the SA register 60 connects only the capacitor C4 to the column amplifier 10, that is, the SA register 60 has D1 to D4 = 0, 0, 0, 1 The pseudo pixel signals having different signals' are output from the voltage source 80 twice. Then, the correction unit 61 acquires two digital measurement values measured by the latch unit 40.

Next, the correction unit 61 plots the digital measurement values measured twice by the latch unit 40 in a two-dimensional coordinate space with Signal ′ as the horizontal axis and CIN's digital measurement value as the vertical axis. For example, Y <i> that is the first function is calculated by linearly interpolating the values (step S9).

Next, the correcting unit 61 uses Y <i> (= Y <1> to Y <4>) and Y <0> as the first function and uses a weighting value of Di (= D1 to D4). A certain Ki (= K1 to K4) is corrected (step S10).

FIG. 5 is a graph showing Y <4>. The vertical and horizontal axes are the same as those in FIG. In FIG. 5, X3 represents Signal ′ at the time of the first measurement, and Y3 represents a digital measurement value of CIN at the time of the first measurement. X4 represents Signal ′ at the time of the second measurement, and Y4 represents a digital measurement value of CIN at the time of the second measurement.

Then, the correction unit 61 calculates Y <4> by linearly interpolating two points (X3, Y3) and (X4, Y4), for example. Assuming that Y <4> is Y = a · X + b, Y <4> is Y <4> = ((Y4−Y3) / (X4−X3)) · X + (X4 · Y3−X3 · Y4) / It is represented by (X4-X3).

That is, for Y <4>, the slope a is represented by a = (Y4-Y3) / (X4-X3), and the Y-intercept B4 is represented by B4 = (X4 · Y3-X3 · Y4) / (X4-X3). It is a straight line represented. Here, since the slope a of Y <4> is determined by VRAMP, it is the same as the slope a of Y <0>.

Y <4> indicates the AD conversion characteristic between Signal ′ and D5 to D15 when D1 to D4 = 0, 0, 0, 1, and ideally RL = K4 (= 2 ¹⁰ = 1024 In the case of Xα1, which is the Signal ′ at the time of Y), Y <4> = 0.

That is, if K4 which is a weighting value for D4 is added to Y <4> as an offset, Y <4> should ride on RL.

However, since the deviation of the capacitance of the capacitor C4 from the ideal value due to changes over time and individual variations, Y <0> is also deviated from RL. Even if K4 is added as an offset to Y <4>, Y <4> is RL. Is not connected to Y <0> smoothly.

Thus, even if D4 is weighted by K4, the ADC characteristic of the column AD converter 3 does not become a smooth straight line as shown in FIG. 12, and the pixel signal Video cannot be AD converted with high accuracy.

Therefore, in step S10, the correction unit 61 calculates a difference ΔB04 between B0 and B4 from Y <0> −Y <4>, and corrects K4 by setting ΔB04 to K4 after correction. Since Y <0> and Y <4> have the same slope, Y <0> −Y <4> indicates that B <0> is a Y intercept of Y <0> and a Y intercept of Y <4>. A difference ΔB04 from a certain B4 can be obtained.

Returning to FIG. 3, in step S11, the correction unit 61 updates i by subtracting 1 from i. If i ≧ 1 (NO in step S12), the process returns to step S6, and if i <1 ( In step S12, YES), the process ends. That is, the correction unit 61 updates i until i <1, and repeats the processes of steps S6 to S12.

Thereby, Y <4>, Y <3>, Y <2>, Y <1> are sequentially calculated, and K4 to K1 are corrected.

FIG. 6 is a graph showing Y <3>. The vertical and horizontal axes are the same as those in FIG. Y <3> is a straight line obtained when the voltage source 80 outputs twice the pseudo pixel signal having different Signal ′ such that only the capacitor C3 is connected to the column amplifier.

6, X5 represents Signal ′ at the time of the first measurement when i = 3, and Y5 represents the digital measurement value of CIN at the time of the first measurement when i = 3. X6 represents Signal ′ at the time of the second measurement when i = 3, and Y6 represents the digital measurement value of CIN at the time of the second measurement of i = 3.

Then, the correction unit 61 calculates Y <3> by linearly interpolating the two points (X5, Y5) and (X6, Y6), for example. Assuming that Y <3> is Y = a · X + b, Y <3> is Y <3> = ((Y6-Y5) / (X6-X5)) · X + (X6 · Y5-X5 · Y6) / It is represented by (X6-X5).

That is, for Y <3>, the slope a is represented by a = (Y6-Y5) / (X6-X5), and the Y-intercept B3 is represented by B3 = (X6 · Y5-X5 · Y6) / (X6-X5). It is a straight line represented. Here, since the slope a of Y <3> is determined by VRAMP, it is the same as the slope a of Y <0>.

Y <3> indicates the AD conversion characteristic between Signal ′ and D5 to D15 when D1 to D4 = 0, 0, 1, 0, and therefore ideally RL = K3 (= 2 ¹¹ = 2048). In the case of Xα2 which is Signal ′ at the time of (), Y <3> = 0.

That is, if K3 is added to Y <3> as an offset, Y <3> should ride on RL.

However, since it deviates from the ideal value due to a change in the capacitance of the capacitor C3 with time and individual variations, even if K3 is added as an offset to Y <3>, Y <3> does not ride on RL, and Y <4>. Does not connect smoothly.

Thus, even if D3 is weighted by K3, the ADC characteristic of the column AD conversion unit 3 does not become a smooth straight line as shown in FIG. 12, and the pixel signal Video cannot be AD converted with high accuracy.

Therefore, in step S10, the correction unit 61 obtains a difference ΔB03 between B0 and B3 from Y <0> −Y <3>, and corrects K3 using ΔB03 as K3 after correction. Since Y <0> and Y <3> have the same slope, Y <0> −Y <3> indicates that the Y intercept of Y <0> is B0 and the Y intercept of Y <3>. A difference ΔB03 from a certain B3 can be obtained.

FIG. 7 is a graph showing Y <2>. The vertical and horizontal axes are the same as those in FIG. Y <3> is a straight line obtained when the voltage source 80 outputs twice the pseudo pixel signal having different Signal ′ such that only the capacitor C3 is connected to the column amplifier.

7, X7 indicates Signal ′ at the time of the first measurement when i = 2, and Y7 indicates the digital measurement value of CIN at the time of the first measurement when i = 2. X8 represents Signal ′ at the time of the second measurement when i = 2, and Y8 represents the CIN digital measurement value at the time of the second measurement of i = 2.

Then, the correction unit 61 calculates Y <2> by linearly interpolating two points (X7, Y7) and (X8, Y8), for example. When Y <2> is set to Y = a · X + b, Y <2> is Y <2> = ((Y8−Y7) / (X8−X7)) × X + (X8 • Y7−X7 • Y8) / It is represented by (X8-X7).

That is, for Y <2>, the slope a is represented by a = (Y8−Y7) / (X8−X7), and the Y intercept B3 is represented by B3 = (X8 · Y7−X7 · Y8) / (X8−X7). It is a straight line represented. Here, since the slope a of Y <2> is determined by VRAMP, it is the same as the slope a of Y <0>.

Y <2> indicates AD conversion characteristics with D5 to D15 with respect to Signal ′ when D1 to D4 = 0, 1, 0, 0, and therefore ideally RL = K2 (= 2 ¹² = 4096). ) Should be Y <2> = 0 in Xα3 which is Signal ′.

That is, if K2 is added to Y <2> as an offset, Y <2> should ride on RL.

However, since TH2 deviates from the ideal value due to a change in the capacitance of the capacitor C2 over time, even if K2 is added as an offset to Y <2>, Y <2> does not ride on RL, and Y <3> It does not connect smoothly.

Thus, even if D2 is weighted by K2, the ADC characteristic of the column AD conversion unit 3 does not become a smooth straight line as shown in FIG. 12, and the pixel signal Video cannot be AD converted with high accuracy.

Therefore, in step S10, the correction unit 61 obtains a difference ΔB02 between B0 and B2 from Y <0> −Y <2>, and corrects K2 with ΔB02 as K2 after correction. Since Y <0> and Y <2> have the same slope, Y <0> −Y <2> indicates that B0 that is the Y intercept of Y <0> and the Y intercept of Y <2>. A difference ΔB02 from a certain B2 can be obtained.

Similarly, the correction unit 61 obtains Y <1>, obtains ΔB01 from Y <0> −Y <1>, and corrects K1 with ΔB01 as K1 after correction.

Then, when D1 to D15, which are digital data of the pixel signal Video, are output from the column AD conversion unit 3 during normal operation, the image processing unit 6 illustrated in FIG. 1 sets the corrected weight values as K1 ′ to K4 ′. Then, K1 ′ · D1 + K2 ′ · D2 + K3 ′ · D3 + K4 ′ · D4 is obtained as the upper bit group digital data. As a result, Y <0> to Y <4> are smoothly connected.

Next, in order to remove redundant bits from D5 to D15, the predetermined value M0 is subtracted from the lower bit group digital data to obtain 10 bit digital data of D5 to D14 of the lower bit group. Here, for example, B0 shown in FIG. 4 may be adopted as M0. Thereby, it is possible to set Y <0> = 0 when Signal ′ = 0. Next, D5 to D14 are multiplied by predetermined weight values K5 to K14 for D5 to D14 and added, that is, K5 · D5 + K6 · D6 +... + K14 · D14 is obtained as digital data of the lower bit group. Next, the digital data of the pixel signal Video is obtained by adding the digital data of the upper bit group and the digital data of the lower bit group.

Thus, according to the solid-state imaging device according to the present embodiment, the column amplifier 10 and the pixel unit 1 are disconnected and the column amplifier 10 is connected to the voltage source 80, and one capacitor Ci (= C 1) is connected from the voltage source 80. When the pseudo pixel signal is output so as to connect .about.C4) to the column amplifier, the SA register 60 sequentially connects the capacitor Ci to the column amplifier 10 and finally connects the capacitor Ci to the column amplifier 10. The latch unit 40 measures the signal (CIN) input to the comparator unit 30 in this state, and the correction unit 61 uses the weighting value of the bit corresponding to the capacitor Ci based on the measurement result by the latch unit 40. A certain Ki is corrected.

That is, the SA register 60 normally reads the pixel signal Video instead of forcibly connecting the capacitor Ci to the column amplifier 10 even though a 0 signal is input to the column amplifier 10 as in the prior art. Similarly to the operation, the capacitors C1 to C4 are sequentially connected to the column amplifier 10, and then the capacitor Ci is connected to the column amplifier 10. The latch unit 40 measures the signal (CIN) input to the comparator unit 30 in this state. Therefore, the SA register 60 can be operated under the same conditions as during normal operation, and the signal input to the comparator unit 30 can be measured. As a result, the weight values K1 to K4 of the bits D1 to D4 can be accurately corrected.

In the above embodiment, Y <1> to Y <4> are obtained. However, only Y <0> is obtained, and the weight values K1 to K4 are corrected from the deviation from the ideal straight line RL. It may be.

In the above embodiment, the pseudo pixel signal is measured twice for one i. However, the present invention is not limited to this, and any number of times may be used as long as it is twice or more.

In the above embodiment, the upper bit group is 4 bits and the lower bit group is 11 bits. However, the present invention is not limited to this, and other numbers of bits may be adopted.

In the solid-state imaging device of the above-described embodiment, the pixel signal Video is AD-converted separately into an upper bit group and a lower bit group. However, the present invention is not limited to this, and all bits of digital data are sequentially converted. A / D conversion may be performed by a comparative AD conversion method. In this case, the latch unit 40 may be used as a measurement unit for measuring CIN.

The technical features of the above solid-state imaging device can be summarized as follows.

(1) A solid-state imaging device according to one aspect of the present invention corresponds to a pixel portion in which a plurality of pixels are arranged in a matrix, a vertical scanning circuit that sequentially selects each row of the pixel portion, and each column of the pixel portion A plurality of readout circuits that read out pixel signals from pixels in a row selected by the vertical scanning circuit and perform analog-to-digital conversion, and the readout circuit amplifies the pixel signals read out from the pixel unit A column amplifier, a comparator unit that inverts an output signal by comparing the signal output from the column amplifier with a predetermined reference voltage, and each level of digital data that is analog-to-digital converted are provided, respectively. A plurality of successive approximation capacitors that output different signals to the column amplifier, a voltage source that outputs a pseudo pixel signal, and the successive approximation capacitor. A bit determining unit that sequentially switches a connection relationship between the column amplifier and the column amplifier, and determines a value of digital data of the pixel signal by a successive approximation type analog-to-digital conversion method based on an output signal output from the comparator unit; The bit determining unit includes a measuring unit that measures a signal input to the comparator unit, and the column amplifier and the pixel unit are disconnected and the column amplifier is connected to the voltage source. A pseudo pixel signal that connects a successive approximation capacitor to the column amplifier is output to the voltage source, a signal input to the comparator unit is measured by the measurement unit, and based on a measurement result by the measurement unit, And a correction unit that corrects a weighting value of a bit corresponding to one successive approximation capacitor.

According to this configuration, when the column amplifier is connected to the voltage source while the column amplifier is disconnected from the pixel unit, and a pseudo pixel signal that connects one successive approximation capacitor to the column amplifier is output from the voltage source. The bit determination unit sequentially connects the successive approximation capacitor to the column amplifier, and finally connects the one successive approximation capacitor to the column amplifier. Then, the measurement unit measures the signal input to the comparator unit in this state, and the correction unit corrects the weight value of the bit corresponding to the one successive approximation capacitor based on the measurement result by the measurement unit.

That is, the bit determination unit reads out the pixel signal instead of forcibly connecting the one successive approximation capacitor to the column amplifier even though a 0 signal is input to the column amplifier as in the prior art. The successive approximation capacitor is connected to the column amplifier in the same manner as in normal operation, and then the one successive approximation capacitor is connected to the column amplifier. The measurement unit measures the signal input to the comparator unit in this state. Therefore, it is possible to measure the signal input to the comparator unit by operating the bit determining unit under the same conditions as in normal operation. As a result, the weight value of each bit of the digital data can be corrected with high accuracy.

(2) The measurement unit performs analog-to-digital conversion on the signal input to the comparator unit by comparing the signal input to the comparator unit and a predetermined ramp signal with the comparator by an integral analog-digital conversion method. The digital measurement value is measured, and the correction unit disconnects the column amplifier and the pixel unit and connects the column amplifier to the voltage source, and one successive approximation capacitor is connected to the column amplifier. The pseudo-pixel signal having different levels connected to the voltage source is output to the voltage source at least twice, and the digital measurement value measured by the measurement unit is interpolated to interpolate the pseudo-pixel signal voltage and the digital measurement. A first function indicating a relationship with the value is calculated, and based on the calculated first function, the first function corresponding to the one successive approximation capacitor is calculated. It is preferable to correct bets weighting value.

According to this configuration, the comparator unit compares the input signal with a predetermined ramp signal, and the measurement unit measures the digital measurement value of the signal input to the comparator unit from the comparison result by the comparator unit. The correction unit causes the voltage source to output a pseudo pixel signal such that a certain successive approximation capacitor is connected to the column amplifier at least twice. On the other hand, the measurement unit measures the digital measurement value of the signal input to the comparator unit every time the pseudo pixel signal is output. Accordingly, the first function indicating the relationship between the pseudo pixel signal and the digital measurement value in a state where the one successive approximation capacitor is connected to the column amplifier by interpolating the digital measurement value each time the measurement value is measured. Can be obtained. That is, it is possible to obtain AD conversion characteristics in a state where the one successive approximation capacitor is connected to the column amplifier.

Therefore, for example, by using a technique such as obtaining a deviation of the first function with respect to an ideal AD conversion characteristic, it is possible to correct a weighting value of a bit corresponding to the one successive approximation capacitor.

(3) The correction unit causes the voltage source to output a pseudo pixel signal such that not all successive approximation capacitors are connected to the column amplifier at least twice, and in the same manner as the first function, A second function indicating a relationship with the digital measurement value is calculated, and a weight value of a bit corresponding to the one successive approximation capacitor is corrected based on a difference between the first function and the second function. It is preferable to do.

According to this configuration, the second function indicating the AD conversion characteristic in a state where all successive approximation capacitors are disconnected from the column amplifier is calculated, and the difference between the first function and the second function is calculated. Yes. Therefore, the calculated difference between the first and second functions is the corrected weighting value.

(4) The readout circuit divides the pixel signal into an upper bit group and a lower bit group and performs analog-to-digital conversion, the bit determination unit determines a value of the upper bit group, and the measurement unit It is preferable to measure a digital measurement value as the value of the lower bit group.

According to this configuration, when the readout circuit is configured to perform analog-to-digital conversion by dividing the pixel signal into an upper bit group and a lower bit group, a signal input to the comparator unit by the circuit that performs analog-digital conversion of the lower bit group Measurement can be performed, and there is no need to provide a separate measurement circuit.

(5) The pixel unit outputs a pixel signal including a noise component and a pixel signal including the noise component and the signal component in two phases, and the column amplifier outputs the pixel signal output in two phases. It is preferable that the noise component is canceled and amplified, and the correction unit causes the voltage source to output the pseudo pixel signal in two phases when the measurement unit measures the digital measurement value once.

According to this configuration, since the pseudo pixel signal is output in two phases for each measurement, even when the readout circuit has a circuit configuration for reading out the pixel signal in two phases, An input signal can be measured.

(6) It is preferable that the correction unit cuts off the column amplifier and the pixel unit during a vertical blanking period to connect the column amplifier to the voltage source.

According to this configuration, since the weighting value is corrected in the vertical blanking period, it is possible to correct in real time the variation of the weighting value due to the capacitance variation of the successive approximation capacitor that varies as needed during imaging.

Claims

A pixel portion in which a plurality of pixels are arranged in a matrix;
A vertical scanning circuit for sequentially selecting each row of the pixel portion;
A plurality of readout circuits which are provided corresponding to the respective columns of the pixel portion, read out pixel signals from pixels in a row selected by the vertical scanning circuit, and perform analog-digital conversion;
The readout circuit includes:
A column amplifier for amplifying a pixel signal read from the pixel unit;
A comparator that inverts the output signal by comparing the signal output from the column amplifier with a predetermined reference voltage;
A plurality of successive approximation capacitors that are provided corresponding to each bit of digital data to be converted from analog to digital, and that output signals of different levels to the column amplifier,
A voltage source that outputs a pseudo pixel signal;
A bit for sequentially switching the connection relationship between the successive approximation capacitor and the column amplifier, and determining the value of the digital data of the pixel signal by the successive approximation analog-to-digital conversion method based on the output signal output from the comparator unit A decision unit;
A measurement unit for measuring a signal input to the comparator unit;
A pseudo pixel signal for connecting one successive approximation capacitor having the bit determining unit to the column amplifier in a state where the column amplifier and the pixel unit are disconnected and the column amplifier is connected to the voltage source. Correction that causes the voltage source to output the signal input to the comparator unit to be measured by the measurement unit, and corrects the weight value of the bit corresponding to the one successive approximation capacitor based on the measurement result by the measurement unit A solid-state imaging device.
The measurement unit compares the signal input to the comparator unit with a predetermined ramp signal by the comparator so that the signal input to the comparator unit is analog-to-digital converted by an integral analog-to-digital conversion method and digitally converted. Measure the measured value,
The correction unit is different in level so that one successive approximation capacitor is connected to the column amplifier in a state where the column amplifier and the pixel unit are disconnected and the column amplifier is connected to the voltage source. A pseudo pixel signal is output to the voltage source at least twice, and a digital measurement value measured each time by the measurement unit is interpolated to show a relationship between the voltage of the pseudo pixel signal and the digital measurement value. The solid-state imaging device according to claim 1, wherein a function is calculated, and a weight value of a bit corresponding to the one successive approximation capacitor is corrected based on the calculated first function.
The correction unit causes the voltage source to output a pseudo pixel signal such that not all successive approximation capacitors are connected to the column amplifier, and outputs the pseudo pixel signal and the digital measurement in the same manner as the first function. Calculating a second function indicating a relationship with a value, and correcting a weighting value of a bit corresponding to the one successive approximation capacitor based on a difference between the first function and the second function. The solid-state imaging device according to claim 2, characterized in that:
The readout circuit divides the pixel signal into an upper bit group and a lower bit group and performs analog-digital conversion,
The bit determining unit determines a value of the upper bit group;
The solid-state imaging device according to claim 2, wherein the measurement unit measures the digital measurement value as a value of the lower-order bit group.
The pixel unit outputs a pixel signal including a noise component and a pixel signal including the noise component and the signal component in two phases,
The column amplifier cancels and amplifies the noise component of the pixel signal output divided into two phases,
5. The correction unit according to claim 2, wherein when the measurement unit measures the digital measurement value once, the correction unit causes the voltage source to output a pseudo pixel signal in two phases. Solid-state imaging device.
6. The correction unit according to claim 1, wherein the column amplifier is disconnected from the pixel unit during a vertical blanking period so that the column amplifier is connected to the voltage source. The solid-state imaging device described.