JPS63116523A - A/d converting system - Google Patents

Abstract

PURPOSE:To check the abnormality of an A/D converting system and to correct the slight adjusting dislocation to an off-setting and a gain without needing a special externally fitted reference voltage source by comparing a digital value converted by an A/D converting means and a digital value set beforehand. CONSTITUTION:By a selecting means 10 to select successively plural analog inputs and hold and output an analog signal, an analog zero signal to a ground analog input 1 is generated at the analog of both polarities with a bias means 13. The analog signal of both polarities is A/D-converted by an A/D converting means 12, a digital signal obtained by doing and the digital value set beforehand are compared by a deciding means 14, a gain error and/or an off-setting error, which come to be characteristic errors, are decided, and the prescribed value of the digital value, in which at A/D converting means converts the digital value determined by the gain error and/or off-setting error, is corrected by a correcting means 14.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to detecting failures in the A/D conversion system and correcting converted values in a CI'U digital system having an A/D conversion system. Can do A/
This relates to the D conversion system.

[Conventional technology]

Is Figure 6 BUI? Published by R-BROWN in 1986
This is a conventional A/D conversion system shown in "Product Data Book" PP5-90 to 5-98, and 1 in the figure.
0 is a multiplexer having N-channel analog inputs, 11 is a sample hold connected to the output of this multiplexer 10, 12 is an A/D converter that takes the sample and hold output as input, 14 is an A/D converter /D converter 12 output and C P tJ connected through a bus,
15 is a control logic connected to each of the above components, and 16 and 17 are reference voltage sources connected to two inputs of the multiplexer 10. The other input of the multiplexer 10 receives an analog signal to be converted from analog to digital.

Next, the operation will be explained.

The CPU 14 provides the control logic 15 with an A/D
Channels CH3 to CH of analog input signals to be converted
One of N is designated via internal bus B1. Control logic 15 responds to multiplexer 10
A channel designation signal is applied to the internal bus B2. Multiplexer 10 selects one analog input designated by control logic 15 from among the N analog inputs, and outputs the selected one analog input to sample and hold 11 . The output analog signal is supplied to the input of sample hold 11.

Subsequently, the control logic 15 provides a hold command signal H to the sample hold 11. The sample hold 11 outputs the input analog signal at the time when the hold command signal H is applied to the A/D converter 12, and holds the output voltage level. Subsequently, the control logic 15 provides an A/D conversion start signal ST to the A/D converter 12. In response, the A/D converter 12 converts the input analog signal into a binary digital value corresponding to the voltage level, and then provides a conversion end signal E to the control logic 15. The control logic 15 sends an end signal, which is an A/D conversion end signal, to the CPU 14 via the internal bus B1. Upon receiving this termination signal, the CPUI 4 sends and receives the converted binary digital value from the A/D converter 12.

By the way, the determination of failure or adjustment deviation of the A/D converter 12 is disclosed in detail in the A/D converter adjustment method, page 5, 95 of the 1986 edition "Product Data Book" published by BURR-BROAN. It is carried out according to the method.

First, it is necessary to input the minimum voltage in the analog input voltage range of the A/D converter 12 to the A/D converter 12, and perform offset adjustment so that the digital conversion value becomes the minimum. Next, it is necessary to input the maximum voltage in the analog input voltage range to the A/D converter 12 and adjust the gain so that the digital conversion value becomes maximum. Therefore, multiplexer 1001
The minimum reference voltage source 16 is connected to one input channel CHI, the maximum reference voltage source 17 is connected to the other input channel CH2, and the remaining channels CH3 to CHN are connected to analog signals that should originally be input into the CPU 14 for A/D conversion. Connect each signal. Under this state, the CPU 14 checks the offset deviation based on the digitally converted value of the minimum reference voltage MIN-V input from the minimum reference voltage source 16 to the channel CHI.

On the other hand, the gain shift is checked based on the digitally converted value of the maximum reference voltage MAX-V inputted from the maximum reference voltage source 17 to channel CH2. In this way,
It is configured so that the functions of each A/D converter 12 can be checked.

[Problem that the invention seeks to solve]

Since the conventional A/D conversion system is configured as described above, two external reference voltage sources, namely, the minimum reference voltage source 16. A maximum reference voltage source 17 is required. Further, there are other problems in that these two reference voltage sources require a specific accuracy for the A/D converter 12.

This invention was made to solve the above-mentioned problems, and allows A/D without the need for a special external reference voltage source.
It is an object of the present invention to provide an A/D conversion system that can check for abnormalities in the conversion system and correct some adjustment deviations in offset and gain.

[Means for solving problems]

The A/D conversion system according to the present invention has an A/D conversion system that responds to a ground analog input inputted from a selection means that sequentially selects a plurality of analog inputs and holds and outputs an analog signal.
A determination means for comparing a digital value converted by the A/D conversion means with a preset digital value to determine characteristic errors such as a gain error and an offset error of the A/D conversion means, and a determination result by the determination means. and a correction means for correcting the digital value converted by the A/D conversion means by a predetermined value based on the digital value.

[Effect]

In the A/D conversion system of the present invention, an analog zero signal corresponding to a ground analog input is generated into a bipolar analog signal by a biasing means by a selection means that sequentially selects a plurality of analog inputs and holds and outputs the analog signal. . The A/D conversion means A/D converts this bipolar analog signal, and the judgment means compares the obtained digital signal with a preset digital value to determine the gain error and/or offset error that would be a characteristic error. The correcting means corrects the digital value by a predetermined value, which is obtained by converting the digital value determined by the gain error and/or offset error by the A/D converting means.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

The same parts as in Fig. 6 are indicated with the same reference numerals as corresponding parts.
In the figure, (2) is a ground analog input, and one channel among the channels CHI to CHN of the multiplexer 10 is connected to the ground side. In addition, C.P.
U], 4 serves as the determination means and the correction means of the present invention, and the analog inputs selected and held by the multiplexer 10 and sample hold 11 constituting the selection means, for example, the ground analog human input 1 input to the channel CHN. is compared to determine whether a characteristic error has occurred in the A/D converter 12, and the digital value converted by the A/D converter 12 is corrected by a predetermined amount.

Next, the operation will be explained.

The bias circuit 13 is necessary when the A/D converter 12 has a unipolar analog input, and adds the bias voltage from the bias circuit 13 to the bipolar analog signal output from the sample hold 11 shown in FIG. generates a unipolar analog signal.

FIG. 2(a) is a circuit diagram illustrating the internal configuration of the bias circuit 13 shown in FIG. 1, and the same components as in FIG. 1 are denoted by the same reference numerals.

In the same figure (a), OP is an operational amplifier, and resistor R
The bipolar analog signal AS1 inputted through the resistor R2 is added to the bias reference voltage ■8 inputted through the resistor R2, and a low impedance unipolar analog signal AS2 is outputted to the A/D converter 12. .

In the same figure (bl, OP2 is an operational amplifier, and resistor R
By adding the bipolar analog signal ASI input through A4 and the bias reference voltage ■□ input through resistor R3 with a gain determined by the value of resistor R5, a low impedance unipolar analog signal AS2 is /D converter 12. Note that if the A/D converter 12 is a bipolar analog input type, it has a built-in bias circuit.
There is no particular need to provide the bias circuit 13.

Next, the configuration and operation of the A/D converter 12 shown in FIG. 1 will be explained with reference to FIGS. 3(a) to 3(C).

FIG. 3 (al is a block diagram explaining the configuration of a successive approximation type A/D converter, 21 is a D/A converter, 2
The digital signal in the hexadecimal register 22 is converted into an analog signal. 23 is a comparator and input analog voltage VI
N and the analog voltage output from the D/A converter 21 are compared, and the difference signal is output to the control logic circuit 24.

The control logic circuit 24 controls the D/A converter 2 based on the conversion characteristics (described later) shown in FIG.
In response to the output of 1, the binary value to be output from the binary number register 22 is determined in order from the upper bit so that the D/A converter output matches the input analog voltage VIN.

In FIG. 3(b), the vertical axis shows the digital output value, and the horizontal axis shows the input analog voltage (VIN). ■
, ~I3 are conversion characteristic straight lines, one conversion characteristic line indicates the optimal conversion state, the conversion characteristic line I2 indicates the conversion characteristic when an offset error occurs, and the conversion characteristic line I is translated in parallel to the conversion characteristic line I. Become. Conversion characteristic straight line 3 shows the conversion characteristic when a gain error occurs, and it appears as a change in slope centered on the minimum analog input value.

On the other hand, in the case of bipolar analog input, by adding the bias voltage as described above, it is converted to a unipolar analog signal, and the maximum output of the binary register 22 in the A/D converter 2 is By inverting the upper bits, a bipolar conversion characteristic can be obtained as shown in FIG. 3(C).

Note that in this embodiment, the digital value is a two's complement code.

However, even in the case of bipolar analog input, Fig. 4(a),
It is necessary to adjust the conversion characteristics due to the offset error and gain error shown in (b).

FIG. 4+al is a diagram for explaining conversion characteristics due to offset errors, and the same parts as in FIGS. 3 (bl, (e)) are given the same reference numerals.

In this figure, III and IIz indicate conversion characteristic straight lines,
The conversion characteristic line (■1) indicates the optimum conversion state, and the conversion characteristic line (2) indicates the conversion characteristic when an offset error occurs, and is a conversion characteristic line that is obtained by moving the conversion characteristic line (■1) in parallel.

FIG. 4(1)) is a diagram for explaining the conversion characteristics due to gain error, and the same reference numerals are given to the same components as in FIG. 3(b), fcl.

In this figure, 113. I[4 is a conversion characteristic straight line, and the conversion characteristic straight line (■3) shows the conversion characteristic straight line when a gain error occurs, which appears as a change in slope centered on the minimum value 11 MIN compared to the conversion characteristic straight line (■1).

The conversion characteristic straight line 4 is a corrected conversion characteristic straight line corrected by the CPU 14, which will be described later.

Next, the conversion characteristic correction operation by the CPU 14 will be explained.

The CPU 14 outputs an A/
By monitoring the digital value converted by the D converter 12, gain errors and offset errors occurring in the A/D converter 12 can be detected.

That is, the CPU 14 instructs the control logic 15 to sample and hold the "0" volt input to the channel CHN of the multiplexer 10. Based on this command, the control logic 15 sends an instruction to the multiplexer 10 to accept the input channel CHN. Based on this instruction, multiplexer 10 outputs the analog value (rOJV) input to channel CHN to sample hold 11. Here, when the control logic 15 gives a hold command signal H to the sample hold 11, the analog signal (analog value) currently input to the sample hold 11 is sent to the A/D converter 1 via the bias circuit 13.
Output to 2.

Here, the value converted by the A/D converter 12 by the CPU 14 is shown in FIG. 3(b), (C) or FIG. 4(al, (
It is determined whether the conversion has been performed correctly based on the conversion characteristics shown in b).

First, the CPU 4 determines whether an offset error or gain has occurred based on a pre-stored program, for example, based on the conversion characteristic line It is determined whether the digital value for the value is within a preset allowable correction range, and if it is outside the range, the CPU 14 considers that correction is impossible and stops the system operation as an excessive adjustment deviation or failure.

On the other hand, if the CPU 14 determines that the digital value for the analog value converted by the A/D converter 12 is within a preset allowable correction range, the A/D converter 1
When the A/D converter 12 converts the analog signal stored in the internal memory and input to channels CHI to CH(N-1) as a correction value, the digital value converted by CP
U14 subtracts the correction value held in the internal memory from the digital value output from the A/D converter 12, so that if an offset error has occurred in the A/D converter 12, the fourth By subtracting the error E1 from the conversion characteristic straight line ``2'' shown in Figure ta), it becomes possible to correct the digital value based on the appropriate conversion characteristic straight line ``1''.

On the other hand, if a gain error has occurred in the A/D converter 12, the conversion characteristic straight line ■3 shown in FIG.
By subtracting the error amount E2, an appropriate conversion characteristic straight line■
It becomes possible to correct to a digital value based on .

Note that in this embodiment, when a gain error occurs,
That is, when the A/D converter 12 A/D converts the analog input based on the conversion characteristic straight line ■3 shown in FIG. Since it is corrected, there is still a gain error, but the error rate near the "0" input is very large (0
The conversion characteristic straight line is
3 has a constant error rate over the entire range, so it works effectively against gain errors as well.

FIG. 5 is a flowchart showing the A/D conversion system correction control operation procedure according to the present invention. In addition, 5T (11~
S T Q2+ indicates each step.

First, the control logic 15 waits for a "0" input selection instruction sent from the CPU 14, and performs step S T (1
), when the "0" input selection instruction signal is input, step ST (2) instructs the multiplexer 10 to select the analog input from channel CIIN.

Next, step 5T (3) in which the A/D converter 12 converts the analog input ("0" ■) held by the sample hold 11 into a digital signal. Next, the CPU 14 determines whether the digital value subjected to A/D conversion matches the digital value (rob) in step ST (31) and performs step ST (4, 1, if YES, the A/D converter 1
Input the digital value of 2 directly into CPUI 4 and get 5T (5
), if NO, the CPU 14 further performs step ST (
Step 5T (6) of determining whether the digital value A/D converted in step 3) exceeds a preset tolerance value. If this determination is YES, it is determined that adjustment is not possible and the control is terminated in step 5T (71), and if NO in step ST (step S of retaining the digital value obtained in step 31 in the internal memory of the CPU 14 as a correction value) T (8). Next, the analog input standby is performed, and step ST (9), the A/D converter 12 converts the analog signal input via the multiplexer 10 into a digital signal (step ST 001). Next, the CPU 14
Step STQυ subtracts the correction value held in the internal memory from the converted digital value, and Step 5TQ processes the corrected digital value as a true digital value.
2+.

In the above embodiment, there is no particular limitation on when to adjust the A/D converter 12; 12 may be adjusted.

〔Effect of the invention〕

As described above, according to the present invention, the digital value converted by the A/D conversion means in response to the ground analog input inputted from the selection means for sequentially selecting a plurality of analog inputs and holding and outputting an analog signal is determined in advance. The correcting means corrects the digital value converted by the A/D converting means by a predetermined value while the determining means compares the set digital value and determines characteristic errors such as gain errors and offset errors of the A/D converting means. With this configuration, the A/D conversion value for analog input can be automatically adjusted to match the true conversion characteristic straight line without adjusting the A/D converter using the power supplied from an external power source as in the past. Since it can be corrected, it has the effect of programmably adjusting the A/D converter.

[Brief explanation of the drawing]

FIG. 1 does not show one embodiment of the present invention; FIG. A diagram explaining the configuration and operation of the A/D converter shown in Figure 1, and Figure 4 (
al is a diagram explaining conversion characteristics due to offset error,
FIG. 4 (bl is a diagram explaining the conversion characteristics due to gain error, FIG. 5 is a flowchart showing the A/D conversion system correction control operation procedure according to the present invention, and FIG. 6 is a diagram for explaining the conversion characteristics due to gain error.
FIG. 2 is a diagram illustrating the configuration of a D conversion system. In the figure, ■ is a ground analog input, 10 is a multiplexer, 11 is a sample hold, 13 is a bias circuit,
12 is an A/D converter, 14 is a CPU, and 15 is a control logic. In the drawings, the same reference numerals indicate the same or corresponding parts. B Figure 3 Anaroa human power VIN Figure 4 (a) (b)

Claims (1)

[Claims] A selection means for sequentially selecting a plurality of analog inputs and holding and outputting the analog signal; and an A/D conversion means for converting the analog input output from the selection means into a bipolar analog signal into a digital value via a bias means. A/ having
In the D conversion system, a digital value converted by the A/D conversion means corresponding to the ground analog input inputted from the selection means is compared with a preset digital value, and a characteristic of the A/D conversion means is determined. The A/D converter is characterized in that it is provided with a determining means for determining an error, and a correcting means for correcting the digital value converted by the A/D converting means by a predetermined amount based on the determination result by the determining means.
D conversion system.