WO2010108044A1 - Digital filtering in a class d amplifier system to reduce noise fold over - Google Patents
Digital filtering in a class d amplifier system to reduce noise fold over Download PDFInfo
- Publication number
- WO2010108044A1 WO2010108044A1 PCT/US2010/027876 US2010027876W WO2010108044A1 WO 2010108044 A1 WO2010108044 A1 WO 2010108044A1 US 2010027876 W US2010027876 W US 2010027876W WO 2010108044 A1 WO2010108044 A1 WO 2010108044A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- setting
- power amplifier
- programmable
- amplifier
- frequency response
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/217—Class D power amplifiers; Switching amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/50—Digital/analogue converters using delta-sigma modulation as an intermediate step
- H03M3/502—Details of the final digital/analogue conversion following the digital delta-sigma modulation
- H03M3/504—Details of the final digital/analogue conversion following the digital delta-sigma modulation the final digital/analogue converter being constituted by a finite impulse response [FIR] filter, i.e. FIRDAC
Definitions
- the present disclosure relates generally to an electronic device, and more specifically to an audio amplification system implemented in an integrated circuit.
- the power amplifier system includes a programmable digital filter and a power amplifier, each responsive to a plurality of frequency response settings and switching frequency settings, respectively.
- Each frequency response setting and switching frequency setting is adaptively selected by a processor device to match a bandwidth of an incoming audio signal.
- the processor device identifies the current bandwidth of an incoming audio signal and adaptively selects a switching rate setting and a frequency response setting based on the current bandwidth.
- the frequency response setting is selected so as to reduce noise fold over in the power amplifier for a corresponding bandwidth, sampling rate setting, and switching frequency setting.
- FIG. 1 is a block diagram of a complete system amplifier chain in accordance with a preferred embodiment.
- FIG. 2 shows a sub-section of the amplifier chain of Figure 1 in accordance with a first preferred embodiment implemented in a differential ended voltage configuration.
- FIG. 3 is an illustrative embodiment of the programmable signal pre- conditioner of Figs. 1 and 2.
- FIG. 4 is an illustrative embodiment of the loop filter of Fig. 2 shown with external toggling switches.
- FIG. 7 is a graphical illustration of frequency response of a non-conditioned digital input, Fsig, for a conventional amplifier chain, showing noise folding at integer multiples of a corresponding switching frequency, Fc.
- FIG. 8 is a graphical illustration of frequency response of a conditioned digitally filtered input, Fsig, in accordance with the preferred embodiments, showing significant reduction of noise folding at integer multiples of Fc.
- FIG.9 is a table showing switching frequency, F c , selection based upon the combination of audio bandwidth, DSM sampling rate, and FIR filter response.
- FIG 10 is the FIR filter response of a FIRl type programmable digital filter.
- FIG 11 is the FIR filter response of a FIR2 type programmable digital filter.
- FIG 12 is the FIR filter response of a FIR3 type programmable digital filter.
- FIG 13 is the FIR filter response of a FIR4 type programmable digital filter.
- the programmable signal pre-conditioner (PSPC) described herein may be used in various portable and non-portable electronic devices that require the use of a power amplifier to drive an audio speaker.
- the source signal to be amplified may either be a digital or analog signal of a plurality of input sources and a plurality of bandwidth and sampling rates.
- the programmable signal pre-conditioner preferred embodiment is to be used with a Class D power amplifier.
- the PSPC may be used with other power amplifier classes as well.
- the terms "amplifier chain” and “amplifier lineup” are used interchangeably and refer to all the components from the input source to the speaker.
- the amplifier configuration may be single-ended or use differential signals throughout the amplifier chain.
- FIG. 1 is a block diagram of a complete system amplifier chain 100 in accordance with the present embodiment as shown.
- System amplifier chain 100 includes a typical up sampling block 104, used to raise the sampling rate of a low rate digital input 103.
- the higher rate, up-sampled output is passed to interpolation filter 108 which filters out baseband spectral copies in the digital domain.
- Interpolation filter 108 is connected to digital delta-sigma modulator 110 which generates a digital input to a programmable signal pre-conditioner (PSPC) 102.
- Power amplifier 120 amplifies a conditioned analog representation of the digital input from the PSPC 102 to drive a resistive load such as a speaker.
- PSPC programmable signal pre-conditioner
- the input to power amplifier 120 may also be a conventional, non-conditioned analog signal, represented by analog input 116.
- Power amplifier 120 in the preferred embodiment shown, is a Class D amplifier. Class D amplifiers are typically non-linear and employ pulse width modulation (PWM), in a known manner.
- a system clock 106 provides unified timing to the entire system amplifier chain 100.
- Clock divider 122 divides the clock signal from system clock 106 to provide power amplifier 120 with a synchronous timing reference.
- Prior art implementations of signal pre-conditioner blocks are typically fixed, non-programmable high order analog filtering designs configured to eliminate high frequency signal components. Because high frequency signal components entering power amplifier 120 can cause a fold over of noise onto an audio signal thus causing distortion, conventional techniques aim to reduce the fold over noise further by including additional stages of analog filtering.
- programmable signal pre-conditioner 102 includes programmable digital filter 112, which is a finite impulse response (FIR) filter (as shown) but may also be substituted by an infinite impulse response filter (HR), or an equivalent thereto.
- FIR finite impulse response
- HR infinite impulse response filter
- programmable digital filter 112 is programmable and configured to generate a digital value representative of a FIR frequency response.
- the FIR frequency response of the digital value is selectably variable and characterized by one or more poles and zeroes depending on source audio bandwidth, selected sample rate, and selected carrier signal frequency, as shall be described in greater detail below.
- Programmability may be via internal or external system controller 124.
- DAC digital- to-analog converter
- FIR 112 and DAC 114 may be implemented as a combination or as two separate blocks.
- DAC 114 may include an additional low pass filter to decrease distortion of the conditioned analog representation of the digital input before it is fed into power amplifier 120.
- power amplifier 120 may be selectably programmed to drive analog input 116, which could be a default operation (a primary input), when the output from PSPC is otherwise not enabled, as further described below.
- FIG. 2 shows a sub-section of the amplifier chain 100 of Figure 1 in accordance with a first preferred embodiment implemented in a differential ended voltage configuration.
- DAC 114 converts the filtered digital signal from programmable digital filter 112 and drives differential signals, I 1n and l ip , into switches 206b and 206c.
- Switches 206a and 206d are also provided to the input of the power amplifier 120 to select input signals from a multitude of alternate analog audio sources.
- power amplifier block 120 is a class D amplifier which includes loop filter 208.
- the input to loop filter 208 are switches 206a, 206b, 206c and feedback signals vfn 210 and vfp 214.
- FIG. 3 is an illustrative embodiment of the programmable signal pre- conditioner of Figs. 1 and 2.
- the output of DSM 110 is fed into programmable digital filter 112 which filters the digital input in accordance with system controller 124.
- Digital filter 112 includes dynamic element matching (DEM) 301 and the output of DEM 301 feeds the first of a series of delay lines 302a, 302b, 302c, ... 302n.
- DEM 301 also feeds the first of a series of DAC 114 sub elements 304a, 304b, 304c, ... 304n.
- Digital filter 112 and DAC 114 may be interconnected into one module to simplify an integrated circuit design.
- the input of switch 206b is Hn, the conditioned output of PSPC 102.
- the positive input of opamp 412 is simultaneously connected to the output of switch 206c, switch 206d, the output of resistor 408 and one end of capacitor 410.
- the other end of capacitor 410 is connected to the negative output of opamp 412.
- loop filter 208 is configured to implement a closed loop control system.
- the example embodiment of loop filter 208 in FIG. 4 is an integrator filter.
- loop filter 208 can be implemented through any combination of proportional, derivative, or integrator control functions.
- FIG. 5 shows a second preferred embodiment in a single-ended voltage configuration.
- PSPC 502 includes programmable digital filter 504, DAC 506, and low pass filter 508.
- Digital filter 504 and DAC 506, in the preferred embodiment operate and interconnect in an identical manner to programmable digital filter 112 and DAC 114.
- Low pass filter 508 receives is the differential analog output of DAC 506, I 1n and l ip .
- the output of low pass filter 508 feeds switches 509b and 509c.
- Low pass filter 508 is added to this single-ended embodiment to provide signal buffering and limit distortion that could be caused in the single-ended configuration if the output of DAC 506 were directly connected to switches 509b and 509c.
- Power amplifier 520 includes loop filter 510, comparator 512, control logic 518 and switches 519.
- loop filter 510 operates and interconnects in an identical manner to loop filter 208
- comparator 512 operates and interconnects in an identical manner to comparator 212.
- Carrier signal 216 and logic control 217 operate and interconnect identically as in the differential output embodiment of FIG. 2.
- Control logic block 518 is fed by the output of comparator 518.
- the output of control logic 518 is a pass through signal from comparator to switches 519a and 519b in accordance with the system controller 124.
- the output of switches 519a and 519b connect together and feed inductor 522.
- the output of inductor 522 is connected capacitor 524 and capacitor 526 forming a typical low pass filter, which drives speaker 528.
- FIG. 6 is an example embodiment of the low pass filter shown in Fig. 5.
- Low pass filter 508 is fed with the conditioned analog representation of the digital input into PSPC 102, Hn and lip.
- the output of low pass filter 508 connects to the input of power amplifier 520.
- Feedback resistor 602 and feedback capacitor 604 are connected in parallel to the positive output and negative input of operational amplifier 606.
- Capacitor 608 and resistor 610 are connected in parallel between the positive input and negative output of operational amplifier 606.
- comparator 212 The example embodiment output of comparator 212 can be expressed as
- Equations (1), (2), and (3) generally describe the nonlinear behavior of comparator 212 and comparator 512 when the input source frequency is many times less than the switching frequency of comparator 212 or comparator 512.
- Nonlinearities and noise are also present when the input source frequency content is closer or even greater in frequency than the switching frequency of the comparator. Specifically, if there is spectral content at integer multiples of the switching frequency of comparator 212 or comparator 512, the nonlinearities become folded over in the digital domain into the input source frequency content representation and cause distortion of the primary output signal of amplifier 120.
- FIG. 7 is a graphical illustration of frequency response of a non-conditioned digital input, Fsig, for a conventional amplifier chain, showing noise folding at integer multiples of a corresponding switching frequency, Fc.
- Digital filter 112 or 504 may be designed to have zeroes in the frequency response corresponding to integer multiples of the switching frequency of comparator 212 to minimize the fold over of the nonlinearities and noise.
- FIG. 8 is a graphical illustration of frequency response of a conditioned digitally filtered input, Fsig, in accordance with the preferred embodiments, showing significant reduction of noise folding at integer multiples of Fc.
- Design of the programmable digital filter 112 (or programmable digital filter 504) may be then selectively variable and characterized by digital DSM 110 sampling rate, the input source signal frequency bandwidth, and the switching frequency. Since the programmability of a programmable digital filter is done very simply in the art, the complete programmable signal pre-conditioner 102 (or 502) implementation may be realized on an ASIC while minimizing die size and heat dissipation.
- FIG.9 is a table showing switching frequency, F c , selection based upon the combination of audio bandwidth, DSM sampling rate, and FIR filter response.
- DSM digital delta sigma modulation
- FIG.9 is a table of the preferred combinations of audio bandwidth, digital delta sigma modulation (DSM) sampling rates, switching frequencies, and programmable digital filter frequency responses.
- the programmable digital filter 112 or 504 is implemented with 4 types of frequency responses, labeled FIRl, FIR2, FIR3, FIR4, respectively.
- the switching frequency, F c is then selected based upon the combination of audio bandwidth, DSM sampling rate, and FIR filter response.
- FIG 10 is the FIR filter response of a FIRl type programmable digital filter.
- FIG 11 is the FIR filter response of a FIR2 type programmable digital filter.
- FIG 12 is the FIR filter response of a FIR3 type programmable digital filter.
- FIG 13 is the FIR filter response of a FIR4 type programmable digital filter.
- signals may be represented using any of a variety of different techniques. For example, data, instructions, signals that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, or any combination thereof.
- DSP digital signal processor
- ASIC application specific integrated circuit
- FPGA field programmable gate array
- a general- purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine.
- a processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
- the steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two.
- a software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
- An exemplary storage medium is coupled to the processor such that the processor may read information from, and write information to, the storage medium.
- the storage medium may be integral to the processor.
- the processor and the storage medium may reside in an ASIC.
- the ASIC may reside in a user terminal.
- the processor and the storage medium may reside as discrete components in a user terminal.
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- Power Engineering (AREA)
- Theoretical Computer Science (AREA)
- Amplifiers (AREA)
Abstract
Description
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Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201080012765.7A CN102356544B (en) | 2009-03-19 | 2010-03-18 | Digital filtering in a class D amplifier system to reduce noise fold over |
JP2012500977A JP5242850B2 (en) | 2009-03-19 | 2010-03-18 | Digital filtering in a class D amplifier system to reduce noise foldover |
KR1020117024564A KR101345680B1 (en) | 2009-03-19 | 2010-03-18 | Method, apparatus and computer readable medium for digital filtering in a class d amplifier system to reduce noise fold over |
EP10716923.7A EP2409401B1 (en) | 2009-03-19 | 2010-03-18 | Digital filtering in a class d amplifier system to reduce noise fold over |
Applications Claiming Priority (2)
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US12/407,238 US8189802B2 (en) | 2009-03-19 | 2009-03-19 | Digital filtering in a Class D amplifier system to reduce noise fold over |
US12/407,238 | 2009-03-19 |
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WO2010108044A1 true WO2010108044A1 (en) | 2010-09-23 |
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PCT/US2010/027876 WO2010108044A1 (en) | 2009-03-19 | 2010-03-18 | Digital filtering in a class d amplifier system to reduce noise fold over |
Country Status (7)
Country | Link |
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US (1) | US8189802B2 (en) |
EP (1) | EP2409401B1 (en) |
JP (1) | JP5242850B2 (en) |
KR (1) | KR101345680B1 (en) |
CN (1) | CN102356544B (en) |
TW (1) | TW201042911A (en) |
WO (1) | WO2010108044A1 (en) |
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CN105720926A (en) * | 2011-12-20 | 2016-06-29 | 瑞典爱立信有限公司 | Selective power amplifier |
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JP6325526B2 (en) * | 2012-04-30 | 2018-05-16 | メルス オーディオ アンパーツゼルスカブ | Class D audio amplifier with adjustable loop filter characteristics |
US8766713B2 (en) * | 2012-05-31 | 2014-07-01 | Qualcomm Incorporated | Switching amplifier with embedded harmonic rejection filter |
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DE112014004142B4 (en) * | 2013-09-10 | 2021-10-21 | Efficient Power Conversion Corporation | Topology in class D high-power voltage operation |
US9301046B1 (en) * | 2013-09-27 | 2016-03-29 | Cirrus Logic, Inc. | Systems and methods for minimizing distortion in an audio output stage |
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JP2019522825A (en) | 2016-05-20 | 2019-08-15 | ケンブリッジ サウンド マネジメント, インコーポレイテッド | Self-contained loudspeaker for sound masking |
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- 2010-03-18 KR KR1020117024564A patent/KR101345680B1/en active IP Right Grant
- 2010-03-18 CN CN201080012765.7A patent/CN102356544B/en active Active
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CN105720926A (en) * | 2011-12-20 | 2016-06-29 | 瑞典爱立信有限公司 | Selective power amplifier |
CN105720926B (en) * | 2011-12-20 | 2018-06-12 | 瑞典爱立信有限公司 | Selective power amplifier |
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Also Published As
Publication number | Publication date |
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KR101345680B1 (en) | 2013-12-30 |
CN102356544B (en) | 2014-12-03 |
US8189802B2 (en) | 2012-05-29 |
CN102356544A (en) | 2012-02-15 |
JP5242850B2 (en) | 2013-07-24 |
EP2409401B1 (en) | 2015-05-27 |
TW201042911A (en) | 2010-12-01 |
JP2012521671A (en) | 2012-09-13 |
KR20110129479A (en) | 2011-12-01 |
EP2409401A1 (en) | 2012-01-25 |
US20100239102A1 (en) | 2010-09-23 |
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