CN102356544B - Digital filtering in a class D amplifier system to reduce noise fold over - Google Patents

Abstract

An improved power amplifier system is provided. The power amplifier system includes a programmable digital filter and a power amplifier, each responsive to a plurality of frequency response settings and switching frequency settings, respectively. Each frequency response setting and switching frequency setting is adaptively selected by a processor device to match a bandwidth of an incoming audio signal. The processor device identifies the current bandwidth of an incoming audio signal and adaptively selects a switching rate setting and a frequency response setting based on the current bandwidth. The frequency response setting is selected so as to reduce noise fold over in the power amplifier for a corresponding bandwidth, sampling rate setting, and switching frequency setting.

Description

In D class A amplifier A system in order to reduce the folding digital filtering of noise

Technical field

The present invention relates generally to electronic installation, and more particularly, relates to the audio amplifier system of implementing with integrated circuit.

Background technology

Portable electron device through widespread deployment so that various abilities to be provided, for example, to video, music, voice and other multimedia audiovisual.In order to hear the audio-frequency unit of these abilities, with audio frequency amplifier drive loud speaker produce sound.In addition, audio source signal type can have different quality and bandwidth.Adapting to a large amount of source signal types can increase the complexity of audio frequency amplifier design.

In holding device size minimum, have with the user of the mancarried device of the ability of various forms audio plays and constantly increase.In order to minimize the size of device, manufacturer is functionally incorporated into application-specific integrated circuit (ASIC) (ASIC) but not in discrete component by ever-increasing conventionally.In order to amplify audio signal to make it can drive external loudspeaker, power amplifier must be able to increase the power of described source signal.

Just as known in the art, power amplifier is converted into source signal electrical output signal and the heat of amplification.The energy of exporting for the electricity amplifying and the ratio of heat dissipation are called the heat efficiency at technique.Small-sized ASIC does not have the ability of dissipation amount of heat due to its little encapsulation.Therefore, need in little encapsulation, be incorporated to high thermal efficiency design and there is the ASIC of low cost and low-complexity simultaneously.A kind of this type of amplifier classification is called D class A amplifier A in technique.

The advantage that D class A amplifier A is better than the amplifier configuration of other type is well-known.The exercise question of the Eric brother Lars (Eric Gaalaas) in simulation dialogue (Analog Dialogue) the 40th volume the 2nd phase 1-7 page of being published by analogue means (Analog Devices) is why and how the list of references of " D class audio amplifier: what, (Class D Audio Amplifiers:What; Why, and How) " is incorporated herein by reference.As explained, power amplifier system need to adapt to the source signal (being generally audio signal) of various bandwidth, and carries out this adaptation with elimination or minimizing from the mode of the noise of separate sources.

Summary of the invention

The invention provides a kind of improved power amplifier system.Described power amplifier system comprises programmable digital-filter and power amplifier, and it is set in response to multiple frequency response settings and switching frequency respectively separately.Select adaptively each frequency response setting and switching frequency to set by processor device, to match with the bandwidth of importing audio signal into.The current bandwidth of audio signal is imported in described processor device identification into, and selects adaptively switching rate to set and frequency response setting based on described current bandwidth.Select described frequency response to set so that the noise reducing in described power amplifier for corresponding bandwidth, sampling rate setting and switching frequency setting folds.

Various other side of the present invention and embodiment are below described in further detail.

Summary of the invention neither wishes also should not be interpreted as representing complete range of the present invention and scope, and these and additional aspect will become more apparent from embodiment, especially in the time considering embodiment together by reference to the accompanying drawings.

Brief description of the drawings

Fig. 1 is according to the block diagram of the holonomic system amplifier chain of preferred embodiment.

Fig. 2 show implement with differential ends voltage configuration according to the sub-segments of the amplifier chain of Fig. 1 of the first preferred embodiment.

Fig. 3 is the illustrative embodiment of the programmable signal preconditioner of Fig. 1 and Fig. 2.

Fig. 4 is the illustrative embodiment of the loop filter through being shown as the Fig. 2 with outside bifurcation trigger switch.

Fig. 5 shows the second preferred embodiment that is single ended voltage configuration.

Fig. 6 is the example embodiment of the low pass filter shown in Fig. 5.

Fig. 7 is the picture specification of the frequency response Fsig of the not modulated numeral input of conventional amplifier chain, and its noise that is illustrated in the integral multiple place of corresponding switching frequency Fc folds.

Fig. 8 is that it is illustrated in the folding remarkable minimizing of noise at the integral multiple place of Fc according to the picture specification of the frequency response Fsig of the digital filtering input through regulating of preferred embodiment.

Fig. 9 is the table of showing the switching frequency Fc selection of the combination based on audio bandwidth, DSM sampling rate and FIR filter response.

Figure 10 is the FIR filter response of FIR1 type programmable digital-filter.

Figure 11 is the FIR filter response of FIR2 type programmable digital-filter.

Figure 12 is the FIR filter response of FIR3 type programmable digital-filter.

Figure 13 is the FIR filter response of FIR4 type programmable digital-filter.

In order to promote to understand, may locate to indicate the common similar elements of each figure with identical reference number, difference just may be added suffix in due course to distinguish these elements.Described image in graphic is for purposes of illustration and through simplifying, and may not describe in proportion.

Brief description of the drawings exemplary configuration of the present invention, and therefore should not be considered to limit the scope of the present invention that can admit other same effective configuration.Correspondingly, expect, the feature of some configurations can be incorporated into valuably in other configuration and not be further described.

Embodiment

Programmable signal preconditioner described herein (PSPC) can use in the various portable and non-portable electronic installation that need to drive with power amplifier audio tweeter.Source signal to be amplified can be numeral or the analog signal with multiple input sources and multiple bandwidth and sampling rate.The preferred embodiment of described programmable signal preconditioner will use together with D power-like amplifier.Just as known in the art, described PSPC also can use together with other power amplifier classification.Term " amplifier chain " and " amplifier queue (amplifier lineup) " use interchangeably, and refer to all component from input source to loud speaker.In whole amplifier chain, that amplifier configuration can be single-ended or use differential signal.

Fig. 1 is the block diagram of the holonomic system amplifier chain 100 of the present embodiment shown in basis.System amplifier chain 100 comprises typical upper sampling piece 104, and it is in order to the sampling rate of the low rate numeral input 103 that raises.The output through upper sampling of higher rate is passed to interpolation filter 108, the baseband frequency spectrum duplicate in its filtering numeric field.Interpolation filter 108 is connected to digital delta sigma modulator 110, and it produces the numeral input to programmable signal preconditioner (PSPC) 102.Power amplifier 120 amplifies the analog representation through regulating of the numeral input from PSPC 102, to drive for example loud speaker constant resistance load.Can be also the routine being represented by analog input 116, not modulated analog signal to the input of power amplifier 120.

Shown in preferred embodiment in, power amplifier 120 is D class A amplifier A.D class A amplifier A is generally nonlinear and utilizes in a known way pulse-width modulation (PWM).System clock 106 provides unified sequential to whole system amplifier chain 100.Clock is divided device 122 to dividing from the clock signal of system clock 106, to provide synchronous sequence reference to power amplifier 120.

The prior art embodiment of signal preconditioner piece is conventionally fixing, non-programmable high-order simulation filter design, and it is configured to eliminate high frequency signal component.Because the high frequency signal component of ingoing power amplifier 120 can cause noise to fold in audio signal, thereby causes distortion, so routine techniques is intended to further reduce aliasing noise by comprising extra analog filtering level.

Extra level has increased the circuit complexity of design greatly, has increased the cost of the every unit in the system amplifier chain of implementing with ASIC, and causes die area loss and power consumption to increase.

In a preferred embodiment, programmable signal preconditioner 102 comprises programmable digital-filter 112, it is finite impulse response (FIR) (FIR) filter (as shown), but also can be replaced by infinite impulse response filter (IIR) or its equivalent.

In illustrative embodiment, programmable digital-filter 112 is programmable, and is configured to produce the digital value that represents FIR frequency response.The FIR frequency response of described digital value can selectively change, and by characterizing at one or more limits (pole) and the zero point (zero) of depending on source audio bandwidth, selected sampling rate and selected frequency of carrier signal, as described in more detail below.Programmability can realize via inside or external system controller 124.

The digital value feed-in D/A converter (DAC) 114 of exporting from programmable digital-filter 112.DAC 114 is in order to convert described digital value to analog signal, and this signal is the analog representation through regulating that enters the numeral input of PSPC 102, and it is delivered to power amplifier 120 always.

FIR 112 and DAC 114 can be embodied as combination or two pieces independently.In aspect other, DAC 114 can comprise extra low pass filter, before being fed into power amplifier 120 in the analog representation through regulating of numeral input, reduces its distortion.In another aspect, power amplifier 120 can be selectively through programming to drive analog input 116, and this can be the default action (mainly input) in the time that the output from PSPC is not activated because of other reason, as described further below.

Fig. 2 show implement with differential ends voltage configuration according to the sub-segments of the amplifier chain 100 of Fig. 1 of the first preferred embodiment.DAC 114 change from programmable digital-filter 112 through filtered digital signal, and drive differential signal l _inand l _ipenter switch 206b and 206c.Also switch 206a and 206d are provided to the input of power amplifier 120, to select input signal from a large amount of analog audio sources for subsequent use.In example embodiment, power amplifier piece 120 is the D class A amplifier A that comprises loop filter 208.Loop filter 208 is input as to switch 206a, 206b, 206c and feedback signal vfn 210 and vfp 214.

The Typical Disposition of loop filter 208 is the integrator circuit that minimizes amplifier distortion as control loop.Comparator 212 is by output vop and the von feed-in of loop filter 208.The difference analogue output feed-in control logic 218 of comparator 212.The output of comparator 212 is delivered to switch 220a, 220b, 220c and 220d by control logic 218 always.System controller 124 produces control logic signal controlling 217.Control logic 218 can realize in a large amount of PMOS and NMOS integrated circuit.Feedback signal vfn 210 and vfp 214 are connected to the output of switch 220a, 220b, 220c and 220d.In example embodiment, comparator 212 is by comparing the signal input to 212 to implement PWM function with the signal input of carrier signal 216 depicted in figure 2.

The output of comparator 212 is generally available larger heat efficiency amplifying signal compared with conventional linear amplifier.The difference output of power amplifier 120 is walked abreast route by the inductor 222 and 224 of connecting with capacitor 226, to form the typical low pass filter of direct driving loud speaker 228.

Fig. 3 is the illustrative embodiment of the programmable signal preconditioner of Fig. 1 and Fig. 2.The output of DSM 110 is in being fed into programmable digital-filter 112, and described programmable digital-filter 112 is inputted and carried out filtering numeral according to system controller 124.Digital filter 112 comprises dynamic element matching (DEM) 301, and a series of delay line 302a of the output feed-in of DEM 301,302b, 302c ..., one in 302n.DEM 301 also a series of DAC114 sub-element of feed-in 304a, 304b, 304c ..., one in 304n.

Digital filter 112 and DAC 114 can be interconnected into a module and design with simplifying integrated circuit.

Configuration in Fig. 3 allows described design to implement dynamic element matching (DEM) 301, thereby minimizes or eliminate linear mismatch and total harmonic distortion.The number of the delay line in programmable digital-filter 112 can be variable.In addition indivedual delay element 302a that interconnect ... the number of every sample position (bits-per-sample) of 302n can be variable.Described illustrative embodiment is for D/A converter sub-element 304a ... 304n uses the structure of 18, every sample.Those skilled in the art will realize that the resolution that can have the position of variable number between interconnection.

Fig. 4 is the illustrative embodiment of the loop filter through being shown as the Fig. 2 with outside bifurcation trigger switch.Loop filter 208 comprises the operational amplifier (opamp) 412 being configured as inverting amplifier.The output of opamp 412 is directly connected to comparator 212.The negative input of opamp 412 is connected to the output of switch 206b, output, the output of resistor 402 and one end of capacitor 414 of switch 206a simultaneously.The other end of capacitor 414 is connected to the positive output of opamp 414.Resistor 402 be input as feedback signal vfp.Resistor 404 be input as analog input ain for subsequent use.The output feed-in switch 206a of resistor 404.Switch 206b be input as PSPC 102 through regulation output lin.The positive input of opamp412 is connected to output, the output of resistor 408 and one end of capacitor 410 of switch 206c, switch 206d simultaneously.The other end of capacitor 410 is connected to the negative output of opamp 412.

To the output lip that is input as PSPC 102 of switch 206c.Switch 206d is by resistor 406 feed-ins.Resistor 406 is the not modulated input signal aip of simulation for subsequent use.Loop filter 208 is configured to implement closed circuit control system.The example embodiment of the loop filter 208 in Fig. 4 is integrator filter.Conventionally, loop filter 208 can passing ratio, any combination of differential or integrator control function implements.

Fig. 5 shows the second preferred embodiment that is single ended voltage configuration.PSPC 502 comprises programmable digital-filter 504, DAC 506 and low pass filter 508.In a preferred embodiment, digital filter 504 and DAC 506 operate and interconnect in the mode identical with programmable digital-filter 112 and DAC 114.Low pass filter 508 receives the difference analogue output l of DAC 506 _inand l _ip.Output feed-in switch 509b and the 509c of low pass filter 508.Be directly connected to the distortion that may cause in the situation of switch 509b and 509c if add low pass filter 508 to this single-ended embodiment with the output that signal buffering is provided and is limited in DAC 506 in single-ended configuration.Power amplifier 520 comprises loop filter 510, comparator 512, control logic 518 and switch 519.

In the present embodiment, loop filter 510 operates and interconnects in the mode identical with loop filter 208, and comparator 512 operates and interconnects in the mode identical with comparator 212.Carrier signal 216 and logic control 217 operate and interconnect with the same in the difference output embodiment of Fig. 2.Control logic piece 518 is by the output feed-in of comparator 518.Control logic 518 is output as according to system controller 124 passes through signal (pass through signal) from comparator to switch 519a and 519b.The output of switch 519a and 519b links together and feed-in inductor 522.The output of inductor 522 is connected to capacitor 524 and capacitor 526, and described capacitor 524 and capacitor 526 form typical low pass filter, and it drives loud speaker 528.

Fig. 6 is the example embodiment of the low pass filter shown in Fig. 5.With enter PSPC 102 numeral input through regulating analog representation lin and lip feed-in low pass filter 508.The output of low pass filter 508 is connected to the input of power amplifier 520.Feedback resistor 602 and feedback condenser 604 are parallel-connected to positive output and the negative input of operational amplifier 606.Capacitor 608 and resistor 610 are connected in parallel between the positive input and negative output of operational amplifier 606.

In December, 1993, the exercise question of David K Soviet Union (David K.SU) of " IEEE solid-state circuit magazine (IEEE Journal Of Solid State Circuits) " the 28th the 12nd phase of volume 1224-1233 page was " CMOS with current-mode Semi-digital reconfigurable filter crosses sampling D/A converter (A CMOS Oversampling D/A Converter with a Current-Mode Semidigital Reconstruction Filter) " list of references (being incorporated herein by reference) has described to use the Finite Impulse Response filter with DAC and low pass filter to increase sampling rate and the quantizing noise through digitally coded audio signal is carried out to shaping.

Compared with other amplifier classification known in technique, D power-like amplifier is benefited from higher thermal efficiency.The primary clustering of realizing this heat efficiency of D class A amplifier A is for being configured to implement comparator 212 and the comparator 512 of pulse-width modulation (PWM) function.In technique, known PWM function is inherent nonlinearity, and the generation intermodulation distortion signals component relevant to the switching frequency of comparator.

The example embodiment output of comparator 212 can be expressed as

$y\left(t\right)=M\sin \left({\mathrm{\ω}}_{M}t\right)+\underset{i=1}{\overset{\∞}{\mathrm{\Σ}}}\frac{{2V}_o}{\mathrm{i\π}}\underset{i=-\∞}{\overset{\∞}{\mathrm{\Σ}}}\frac{1-{(-1)}^{i+1}}{2}B(i,1)\cos (\mathrm{\ω}(i,1)t+i\frac{\mathrm{\π}}{2}),$ Equation (1)

Wherein ω (i, 1)=i ω _c+ 1 ω _m, equation (2)

$B(i,1)=\underset{p=-\∞}{\overset{\∞}{\mathrm{\Σ}}}{J}_p\left(\mathrm{i\β}\right)J_{1-2p}\left({\mathrm{i\β}}_M\right),$ Equation (3)

And ω _cfor the switching frequency (in radian) of comparator 212, ω _mfor input source frequency (in radian), and J _n(x) for thering is the first kind Bessel function of exponent number n and independent variable x.

Equation (1), (2) and (3) have been described the non-linear behavior of comparator 212 and comparator 512 in the time of the little manyfold of switching frequency of input source frequency ratio comparator 212 or comparator 512 substantially.In the time that input source frequency content approaches or is even greater than the switching frequency of described comparator in frequency, non-linear and noise also exists.Specifically, if there is spectral content at the integral multiple place of the switching frequency of comparator 212 or comparator 512, non-linear becoming in numeric field folds into during input source frequency content represents, and causes the main output signal distortion of amplifier 120.

Fig. 7 is the picture specification of the frequency response Fsig of the not modulated numeral input of conventional amplifier chain, and its noise that is illustrated in the integral multiple place of corresponding switching frequency Fc folds.Digital filter 112 or 504 can be designed to have zero point in the frequency response of the integral multiple of the switching frequency corresponding to comparator 212, to minimize the folding of non-linear and noise.

Fig. 8 is that it is illustrated in the folding remarkable minimizing of integral multiple place noise of Fc according to the picture specification of the frequency response Fsig of the digital filtering input through regulating of preferred embodiment.The design of programmable digital-filter 112 (or programmable digital-filter 504) then can optionally change, and is characterized by digital DSM 110 sampling rates, input source signal frequency bandwidth and switching frequency.Because the programmability of programmable digital-filter has been easy in technique, so the embodiment of complete programmable signal preconditioner 102 (or 502) can realize the minimized while of die size and heat dissipation on ASIC.

Fig. 9 is the switching frequency F that shows the combination based on audio bandwidth, DSM sampling rate and FIR filter response _cthe table of selecting.In a preferred embodiment, exist corresponding to the 9 kinds of combinations of DSM sampling rate of different potential audio bandwidths that are usually used in the audio signal in portable electron device now.Fig. 9 is the table of the preferred compositions of audio bandwidth, the modulation of digital Δ ∑ (DSM) sampling rate, switching frequency and programmable digital-filter frequency response.The frequency response of 4 types that described programmable digital-filter 112 or 504 use are denoted as FIR1, FIR2, FIR3, FIR4 is implemented.Then, switching frequency F is selected in the combination based on audio bandwidth, DSM sampling rate and FIR filter response _c.

Just as known in the art, can design other combination of suitable programmable digital-filter 112 or 504 coefficients.Can be stored in inside or outside because implement the coefficient of described programmable digital-filter, so available system controller 124 inner or outside implement to operator scheme (as Fig. 9 describes, pattern=1,2,3 ..., 8,9) control able to programme.

Figure 10 is the FIR filter response of FIR1 type programmable digital-filter.

Figure 11 is the FIR filter response of FIR2 type programmable digital-filter.

Figure 12 is the FIR filter response of FIR3 type programmable digital-filter.

Figure 13 is the FIR filter response of FIR4 type programmable digital-filter.

Those skilled in the art will appreciate that, can represent signal by any one in multiple different technologies.For instance, can above describe in full in data, instruction, the signal of reference can be represented by voltage, electric current, electromagnetic wave, magnetic field or magnetic particle or its any combination.

Technical staff will further understand, in conjunction with described various illustrative radio frequencies of disclosure herein or analog circuit block in the time carrying out identical function described in the invention, can be independent of logical circuit and system or from logical circuit and system in combination implement on one or more integrated circuits with multiple different circuit topologies.

Technical staff will further understand, and can be embodied as electronic hardware, computer software or both combinations in conjunction with the described various illustrative components, blocks of disclosure, module, circuit and algorithm steps herein.For this interchangeability of hardware and software is clearly described, various Illustrative components, piece, module, circuit and step are described at it aspect functional substantially above.By the described functional design restriction that hardware or software depend on application-specific and forces at whole system that is embodied as.Those skilled in the art can implement for each application-specific described functional by different way, but these embodiment decision-makings should not be construed as and can cause departing from scope of the present invention.

Can or implement or carry out with its any combination of carrying out function described herein through design by general processor, digital signal processor (DSP), application-specific integrated circuit (ASIC) (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components in conjunction with the described various illustrative components, blocks of disclosure, module and circuit herein.General processor can be microprocessor, but in replacement scheme, processor can be any conventional processors, controller, microcontroller or state machine.Processor also can be embodied as the combination of calculation element, for example, and the combination of DSP and microprocessor, multi-microprocessor, in conjunction with one or more microprocessors or any other this type of configuration of DSP core.

In conjunction with the step of the described method of disclosure herein or algorithm can be directly with hardware, embody with the software module carried out by processor or with described both combination.Software module can reside in the medium of any other form known in RAM memory, flash memory, ROM memory, eprom memory, eeprom memory, register, hard disk, removable disk, CD-ROM or technique.Exemplary storage medium is coupled to processor, makes processor and to write information to medium from read information.In replacement scheme, medium can with the integral formula of processor.Processor and medium can reside in ASIC.ASIC can reside in user terminal.In replacement scheme, processor and medium can be used as discrete component and reside in user terminal.

Any technical staff in affiliated field provides previous description of the present invention so that can make or use the present invention.Those skilled in the art will easily understand various amendments of the present invention, and General Principle defined herein can be applied to other modification without departing from the scope of the invention.Therefore, the present invention is without wishing to be held to example described herein and design, but should be endowed the widest scope consistent with principle disclosed herein and novel feature.

Claims (18)

1. operation can be set at selected switching frequency a method for the programmable digital-filter of finishing drilling work rate amplifier and can operate under selected frequency response is set, and it comprises:

The bandwidth of audio signal is imported in identification into; And

Select adaptively described switching frequency setting and described frequency response setting based on described bandwidth, wherein said frequency response is set through selecting so that the noise reducing in described power amplifier for described bandwidth, sampling rate setting and the setting of described switching frequency folds.

2. method according to claim 1, wherein said power amplifier is D class A amplifier A.

3. method according to claim 1, wherein said programmable digital-filter is configurable FIR filter.

4. method according to claim 1, wherein said programmable digital-filter and described power amplifier are arranged in single IC for both IC.

5. method according to claim 1, wherein said selection adaptively further comprises selects sampling rate to set.

6. method according to claim 1, wherein said selection adaptively further comprises for single-ended or differential system signal and being configured.

7. for operating the processor device that can set at selected switching frequency the programmable digital-filter of finishing drilling work rate amplifier and can operate under selected frequency response is set, it comprises:

For identifying the device of the bandwidth of importing audio signal into; And

Be used for selecting adaptively based on described bandwidth the device of described switching frequency setting and described frequency response setting, wherein said frequency response is set through selecting so that the noise reducing in described power amplifier for described bandwidth, sampling rate setting and the setting of described switching frequency folds.

8. processor device according to claim 7, wherein said power amplifier is D class A amplifier A.

9. processor device according to claim 7, wherein said programmable digital-filter is configurable FIR filter.

10. processor device according to claim 7, wherein said processor device is IC.

11. processor devices according to claim 7, wherein said power amplifier and described programmable digital-filter are arranged in single IC.

12. processor devices according to claim 7, wherein said processor device is for single-ended or differential system signal and be configured.

13. 1 kinds of programmable amplifier systems, it has the programmable digital-filter of setting in response to multiple frequency responses and the power amplifier of setting in response to multiple switching frequencies, each frequency response setting and switching frequency setting select to match with the bandwidth of importing audio signal into adaptively by processor device, and wherein said frequency response is set through selecting so that the noise reducing in described power amplifier for described bandwidth, sampling rate setting and the setting of described switching frequency folds.

14. programmable amplifier systems according to claim 13, wherein said power amplifier is D class A amplifier A.

15. programmable amplifier systems according to claim 13, wherein said programmable digital-filter is configurable FIR filter.

16. programmable amplifier systems according to claim 13, wherein said programmable amplifier system is IC.

17. programmable amplifier systems according to claim 13, it further comprises the low pass filter that carries out filtering for the high frequency noise component to entering described power amplifier.

18. programmable amplifier systems according to claim 13, wherein said programmable amplifier system further comprises for single-ended or differential system signal and is configured.