CN109546978B - Current detection circuit of loudspeaker - Google Patents
Current detection circuit of loudspeaker Download PDFInfo
- Publication number
- CN109546978B CN109546978B CN201910035468.7A CN201910035468A CN109546978B CN 109546978 B CN109546978 B CN 109546978B CN 201910035468 A CN201910035468 A CN 201910035468A CN 109546978 B CN109546978 B CN 109546978B
- Authority
- CN
- China
- Prior art keywords
- switch
- input
- output
- circuit
- branch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/217—Class D power amplifiers; Switching amplifiers
- H03F3/2175—Class D power amplifiers; Switching amplifiers using analogue-digital or digital-analogue conversion
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/217—Class D power amplifiers; Switching amplifiers
- H03F3/2178—Class D power amplifiers; Switching amplifiers using more than one switch or switching amplifier in parallel or in series
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses a current detection circuit of a loudspeaker, which comprises: the circuit comprises a first detection resistor, a second detection resistor, a sampling selection circuit, an input selection circuit, a sampling holding circuit and a conversion circuit. According to the invention, through the sampling selection circuit and the input selection circuit, voltages at two ends of a corresponding detection resistor are selected and sampled according to whether the potential difference between the output stage VOP and the output stage VON is positioned in a positive half cycle or a negative half cycle; then, according to different potentials of clock control signals output by the clock control circuit, the voltage at two ends of the corresponding detection resistor is sampled or the sampling is stopped and the sampled voltage is output; therefore, the detection of the loudspeaker current is realized, the anti-truncated distortion function is not required to be added to the class D audio power amplifier, and the performance of the class D audio power amplifier is ensured; and the sampling hold circuit adopts a full differential input and full differential output architecture, so that the influence of voltage fluctuation of the power ground PGND on the accuracy of sampling voltage is counteracted.
Description
Technical Field
The invention relates to the technical field of current detection, in particular to a current detection circuit of a loudspeaker.
Background
At present, the class D audio power amplifier is widely applied to portable equipment such as Bluetooth sound boxes, mobile phones and the like due to the advantages of high efficiency, small heat and good performance.
However, since the portable device is small, the internal speaker cavity is smaller, so when playing music with larger volume, especially when playing large and heavy bass songs, the speaker cavity may be damaged due to too large diaphragm displacement or too high speaker temperature, so a current detection circuit is generally designed for the class D audio power amplifier, so as to control the magnitude of the output current of the class D audio power amplifier according to the magnitude of the speaker current, and further protect the speaker from damage caused by too large diaphragm displacement or too high speaker temperature. However, when the output power of the class D audio power amplifier is large, a clipping phenomenon may occur, and the potential of the output stage VOP or the potential of the output stage VON may continuously occur at a high level or a low level within several pwm frequencies, and at this time, it is difficult to accurately detect the horn current by a general current detection method, so that the class D audio power amplifier is generally required to be added with a clipping distortion prevention function, that is, the output power of the class D audio power amplifier is actively limited, so that clipping does not occur in the output.
However, by adding the anti-chipping distortion function to the class D audio power amplifier, the output power of the class D audio power amplifier is reduced, and the performance of the class D audio power amplifier is not exerted to the maximum extent.
Disclosure of Invention
Therefore, the embodiment of the invention provides a current detection circuit of a loudspeaker, which is used for solving the problem that the performance of a class-D audio power amplifier is sacrificed when the current of the loudspeaker is detected.
In order to achieve the above object, the embodiment of the present invention provides the following technical solutions:
a current detection circuit for a loudspeaker adapted for connection to a class D audio power amplifier, comprising: the device comprises a first detection resistor, a second detection resistor, a sampling selection circuit, an input selection circuit, a sampling holding circuit, a clock control circuit and a conversion circuit; wherein:
one end of the first detection resistor is connected with the first input end of the input selection circuit, and a connection point is used as the first input end of the current detection circuit of the loudspeaker and is connected with the source electrode of the low-end NMOS transistor of the output stage VON of the class-D audio power amplifier;
one end of the second detection resistor is connected with the second input end of the input selection circuit, and a connection point is used as the second input end of the current detection circuit of the loudspeaker and is connected with the source electrode of the low-end NMOS transistor of the output stage VOP of the class-D audio power amplifier;
The other end of the first detection resistor, the other end of the second detection resistor and the third input end of the input selection circuit are grounded;
the first output end of the input selection circuit is connected with the first input end of the sample hold circuit; the second output end of the input selection circuit is connected with the second input end of the sample hold circuit;
the first output end of the sampling and holding circuit is connected with the first input end of the conversion circuit, and the second output end of the sampling and holding circuit is connected with the second input end of the conversion circuit; the clock control end of the sampling hold circuit is connected with the output end of the clock control circuit;
the output end of the conversion circuit is used as the output end of the current detection circuit of the loudspeaker;
three input ends of the sampling selection circuit are respectively connected with the output stage VOP, the output stage VON and the first sampling clock; the output end of the sampling selection circuit is connected with the switch control end of the input selection circuit;
the sampling selection circuit is used for controlling the first input end and the second output end of the input selection circuit to form a passage and controlling the third input end and the second output end of the input selection circuit to form a passage when the potential difference between the output stage VOP and the output stage VON is in a positive half period; when the potential difference between the output stage VOP and the output stage VON is in a negative half period, the third input end and the first output end are controlled to form a passage, and the second input end and the second output end are controlled to form a passage;
The sampling hold circuit is used for sampling the voltage between two output ends of the sampling select circuit according to the clock control signal output by the clock control circuit, or stopping sampling and outputting the sampled voltage to the conversion circuit.
Optionally, the input selection circuit includes: the first switch, the second switch, the third switch, the fourth switch and the first control module; wherein:
the input end of the first switch is used as a first input end of the input selection circuit; the input end of the second switch is used as a second input end of the input selection circuit; the input end of the third switch is connected with the input end of the fourth switch, and the connection point is used as the third input end of the input selection circuit;
the output end of the first switch is connected with the output end of the third switch, and the connection point is used as the first output end of the input selection circuit; the output end of the second switch is connected with the output end of the fourth switch, and the connection point is used as the second output end of the input selection circuit;
the control end of the first switch is connected with the control end of the fourth switch, and the connection point is connected with the first output end of the first control module; the control end of the second switch is connected with the control end of the third switch, and the connection point is connected with the second output end of the first control module;
The input end of the first control module is used as a switch control end of the input selection circuit.
Optionally, the sample-and-hold circuit includes: the voice coil motor comprises a first switch branch, a second switch branch, a third switch branch, a fourth switch branch, a voice coil motor, a second control module, a first capacitor and a second capacitor with the same capacitance value, and a third capacitor and a fourth capacitor with the same capacitance value; wherein:
the input end of the first switch branch is connected with the input end of the third switch branch, and the connection point is used as the first input end of the sample hold circuit;
the input end of the second switching branch is connected with the input end of the fourth switching branch, and the connection point is used as a second input end of the sample hold circuit;
the first output end of the first switch branch is connected with one end of the third capacitor, and the connection point is used as the first output end of the sample hold circuit;
the first output end of the fourth switching branch is connected with one end of the fourth capacitor, and the connection point is used as the second output end of the sample hold circuit;
the other end of the third capacitor, the other end of the fourth capacitor and the positive end of the voice coil motor are grounded;
The first output end of the second switch branch is connected with the first output end of the third switch branch, and the connection point is connected with the negative end of the voice coil motor;
one end of the first capacitor is connected with the second output end of the first switch branch; the other end of the first capacitor is connected with the second output end of the second switch branch;
one end of the second capacitor is connected with the second output end of the third switch branch; the other end of the second capacitor is connected with the second output end of the fourth switching branch;
the first control end of the first switch branch, the first control end of the second switch branch, the first control end of the third switch branch and the first control end of the fourth switch branch are connected, and the connection point is connected with the first output end of the second control module;
the second control end of the second switch branch is connected with the second control end of the third switch branch, and the connection point is connected with the second output end of the second control module;
the second control end of the first switching branch is connected with the second control end of the fourth switching branch, and the connection point is connected with the third output end of the second control module;
The input end of the second control module is used as a clock control end of the sample hold circuit.
Optionally, the first switching branch includes: a fifth switch and a sixth switch; wherein:
the input end of the fifth switch is used as the input end of the first switch branch, the output end of the fifth switch is connected with the input end of the sixth switch, the connection point is used as the second output end of the first switch branch, and the output end of the sixth switch is used as the first output end of the first switch branch;
the control end of the fifth switch is used as the first control end of the first switch branch, and the control end of the sixth switch is used as the second control end of the first switch branch.
Optionally, the second switching branch includes: a seventh switch and an eighth switch; wherein:
the input end of the seventh switch is used as the input end of the second switch branch, the output end of the seventh switch is connected with the input end of the eighth switch, the connection point is used as the second output end of the second switch branch, and the output end of the eighth switch is used as the first output end of the second switch branch;
the control end of the seventh switch is used as the first control end of the second switch branch, and the control end of the eighth switch is used as the second control end of the second switch branch.
Optionally, the third switching branch includes: a ninth switch and a tenth switch; wherein:
the input end of the ninth switch is used as the input end of the third switch branch, the output end of the ninth switch is connected with the input end of the tenth switch, the connection point is used as the second output end of the third switch branch, and the output end of the tenth switch is used as the first output end of the third switch branch;
the control end of the ninth switch is used as the first control end of the third switch branch, and the control end of the tenth switch is used as the second control end of the third switch branch.
Optionally, the fourth switching leg includes: an eleventh switch and a twelfth switch; wherein:
the input end of the eleventh switch is used as the input end of the fourth switch branch, the output end of the eleventh switch is connected with the input end of the twelfth switch, the connection point is used as the second output end of the fourth switch branch, and the output end of the twelfth switch is used as the first output end of the fourth switch branch;
the control end of the eleventh switch is used as the first control end of the fourth switch branch, and the control end of the twelfth switch is used as the second control end of the fourth switch branch.
Optionally, the clock control circuit includes: the second sampling clock, the first counter, the second counter and the third counter; wherein:
the output end of the second sampling clock is used as the output end of the clock control circuit; the first input end of the second sampling clock is connected with the first counter; the second input end of the second sampling clock is connected with the second counter; and a third input end of the second sampling clock is connected with the third counter.
Optionally, the conversion circuit is an integral-differential analog-to-digital converter.
Optionally, the resistance values of the first detection resistor and the second detection resistor are equal; the frequency of the first sampling clock is 256 times the pulse width modulation frequency of the potential of the output stage VOP and the potential of the output stage VON.
Compared with the prior art, the voltage across the corresponding detection resistor is selected and sampled by the sampling selection circuit and the input selection circuit according to whether the potential difference between the output stage VOP and the output stage VON is positioned in a positive half cycle or a negative half cycle; then, according to different potentials of clock control signals output by the clock control circuit, the voltage at two ends of the corresponding detection resistor is sampled or the sampling is stopped and the sampled voltage is output; therefore, the detection of the loudspeaker current is realized, the anti-truncated distortion function is not required to be added to the class D audio power amplifier, and the performance of the class D audio power amplifier is ensured; and the sampling hold circuit adopts a full differential input and full differential output architecture, so that the influence of voltage fluctuation of the power ground PGND on the accuracy of sampling voltage is counteracted.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a current detecting device according to an embodiment of the present invention;
FIG. 2 is a schematic waveform diagram of the switch control signal sample_selt during positive and negative half periods (VOP-VON);
FIG. 3 is a schematic diagram of a current detecting device according to another embodiment of the present invention;
FIG. 4 is a schematic diagram of a current detecting device according to another embodiment of the present invention;
fig. 5 is a schematic diagram of a sample-and-hold circuit 220 in a current detection device according to another embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In order that the above-recited objects, features and advantages of the present application will become more readily apparent, a more particular description of the application will be rendered by reference to the appended drawings and appended detailed description.
In the present disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In order to solve the problem of sacrificing the performance of the class D audio power amplifier when detecting the current of the loudspeaker, the embodiment of the application discloses a current detection circuit of the loudspeaker, which is suitable for the loudspeaker connected with the class D audio power amplifier, as shown in fig. 1, and the current detection circuit disclosed in the embodiment is connected with the class D audio power amplifier 600 and the loudspeaker 700; depending on the actual situation, an inductance L may be connected in series to the branch of the horn 700; the current detection circuit disclosed in this embodiment includes: a first detection resistor RSP, a second detection resistor RSN, a sampling selection circuit 100, an input selection circuit 200, a sample hold circuit 300, a clock control circuit 500, and a conversion circuit 800; wherein:
One end of the first detection resistor RSP is connected to the first input end of the input selection circuit 200, and the connection point is used as the first input end of the current detection circuit of the loudspeaker and is connected to the source of the low-side NMOS transistor of the output stage VON of the class D audio power amplifier 600.
One end of the second detection resistor RSN is connected to the second input end of the input selection circuit 200, and the connection point is used as the second input end of the current detection circuit of the loudspeaker and is connected to the source of the low-end NMOS transistor of the output stage VOP of the class D audio power amplifier 600.
The other end of the first detection resistor RSP, the other end of the second detection resistor RSN, and the third input end of the input selection circuit are all grounded.
The first detection resistor RSP and the second detection resistor RSN have the same resistance.
A first output of the input selection circuit 200 is connected to a first input of the sample-and-hold circuit 300 and a second output of the input selection circuit 200 is connected to a second input of the sample-and-hold circuit 300.
A first output terminal of the sample-and-hold circuit 300 is connected to a first input terminal of the conversion circuit 800, a second output terminal of the sample-and-hold circuit 300 is connected to a second input terminal of the conversion circuit 800, and a clock control terminal of the sample-and-hold circuit 300 is connected to an output terminal of the clock control circuit 500.
The output of the switching circuit 800 serves as the output of the current sensing circuit of the horn.
Three input ends of the sampling selection circuit 100 are respectively connected with the output stage VOP, the output stage VON and the first sampling clock 400; an output terminal of the sampling selection circuit 100 is connected to a switch control terminal of the input selection circuit 200.
It should be noted that, the frequency of the first sampling clock is 256 times of the pwm frequency of the potential of the output stage VOP and the potential of the output stage VON, and other settings may be performed in practical application according to the specific application environment, which is only an example and is not limited thereto, and the present application is also within the scope of protection.
Alternatively, the conversion circuit 800 may be an integrate-differentiate analog-to-digital converter, or a circuit formed by discrete devices and capable of implementing a gain amplification function; in practical applications, other embodiments that can realize the same working principle are within the scope of the present application, depending on the specific application environment.
It should be noted that, the sample-and-hold circuit 300 has a low-pass filtering characteristic, filters the high-frequency component of the voltage sampled by the output pole VOP and the output pole VON, and sends the filtered high-frequency component to the conversion module 800, so as to prevent the high-frequency noise from being folded into the audio frequency range to reduce the signal-to-noise ratio of the current detection, and the-3 dB frequency of the sample-and-hold circuit 300 is as follows: f (-3 dB) = (fsw×c1)/(2×pi×c1+c3); where fsw is the frequency of the switching tubes in sample-and-hold circuit 300.
The specific working principle is as follows:
the sampling selection circuit 100 calculates a waveform after VOP-VON filtering according to the potential of the output stage VOP and the potential of the output stage VON, and takes a sine wave as an example, the waveform is shown in the upper half part of fig. 2; the sampling selection circuit 100 determines whether the potential difference between the output stage VOP and the output stage VON (i.e., the VOP-VON filtered value) is in the positive half-period or the negative half-period by combining the frequency of the first sampling clock 400, and outputs a corresponding switch control signal sample_selt.
As shown in fig. 2, when the potential difference between the output stage VOP and the output stage VON is within the positive half period, the potential of the switch control signal sample_selt output by the sampling selection circuit 100 is at a high level, the input selection circuit 200 forms a path between the first input terminal SN1 and the first output terminal thereof, and forms a path between the third input terminal SN3 and the second output terminal thereof; when the potential of the clock control signal received by the clock control terminal of the sample-and-hold circuit 300 is at a high level, the sample-and-hold circuit 300 starts to sample the voltage across the first detection resistor RSP; when the potential of the clock control signal received by the clock control terminal of the sample hold circuit 300 is low, the sample hold circuit 300 stops sampling and outputs the sampled voltage to the conversion circuit 800; the conversion circuit 800 converts the sampled voltage to obtain a PDM (Pulse Density Modulation ) code; the above-described process is repeated until the potential of the switch control signal sample_selt becomes a low level.
When the potential difference between the output stage VOP and the output stage VON is in the negative half period, the potential of the switch control signal sample_selt output by the sampling selection circuit 100 is at a low level, the input selection circuit 200 forms a path between the third input terminal SN3 and the first output terminal thereof, and forms a path between the second input terminal SN2 and the second output terminal thereof; when the potential of the clock control signal received by the clock control end of the sample hold circuit 300 is at a high level, the sample hold circuit 300 starts to collect the voltages at two ends of the second detection resistor RSN; when the potential of the clock control signal received by the clock control terminal of the sample hold circuit 300 is low, the sample hold circuit 300 stops sampling and outputs the sampled voltage to the conversion circuit 800; the conversion circuit 800 converts the sampled voltage to obtain a PDM code; the above-described process is repeated until the potential of the switch control signal sample_selt becomes a high level.
The obtained PDM code CIC filter (Cascaded integrator-comb filter) can convert and restore the sampling voltage values Vsdm, vsdm/(2×rsp) to obtain the current value on the loudspeaker, so as to protect the loudspeaker.
It should be noted that, in the present embodiment, the sampling selection circuit 100 achieves the purpose of controlling the input selection circuit 200 to form different paths by switching different potentials of the control signal sample_selt; other embodiments that achieve the same object as this embodiment are also within the scope of the present application.
It should be noted that, in this embodiment, the clock control circuit 500 controls the sample hold circuit 300 to start sampling or stop sampling by different potentials of the clock control signal; other embodiments that achieve the same objects as this embodiment are also within the scope of the application.
According to the application, through the sampling selection circuit and the input selection circuit, voltages at two ends of a corresponding detection resistor are selected and sampled according to whether the potential difference between the output stage VOP and the output stage VON is positioned in a positive half cycle or a negative half cycle; then, according to different potentials of clock control signals output by the clock control circuit, the voltage at two ends of the corresponding detection resistor is sampled or the sampling is stopped and the sampled voltage is output; therefore, the detection of the loudspeaker current is realized, the anti-truncated distortion function is not required to be added to the class D audio power amplifier, and the performance of the class D audio power amplifier is ensured; and because the sampling hold circuit adopts a fully differential input and fully differential output architecture, the influence of voltage fluctuation of the power ground PGND on the accuracy of sampling voltage is counteracted.
Another embodiment of the present application further provides a specific current detection circuit for a loudspeaker, which, based on the above embodiments and fig. 1 and 2, is optional, as shown in fig. 3, an input selection circuit 200, including: the first switch S1, the second switch S2, the third switch S3, the fourth switch S4 and the first control module 201; wherein:
The input end of the first switch S1 is used as the first input end of the input selection circuit 200, the input end of the second switch S2 is used as the second input end of the input selection circuit 200, the input end of the third switch S3 is connected with the input end of the fourth switch S4, and the connection point is used as the third input end of the input selection circuit.
The output end of the first switch S1 is connected with the output end of the third switch S3, and the connection point is used as a first output end of the input selection circuit 200; the output terminal of the second switch S2 is connected to the output terminal of the fourth switch S4, and the connection point is used as the second output terminal of the input selection circuit 200.
The control end of the first switch S1 is connected with the control end of the fourth switch S4, and the connection point is connected with the first output end of the first control module 201; the control terminal of the second switch is connected to the control terminal of the third switch, and the connection point is connected to the second output terminal of the first control module 201.
An input of the first control module 201 serves as a switch control of the input selection circuit.
The specific working principle is as follows:
when the potential difference between the output stage VOP and the output stage VON is in the positive half period, that is, when the potential of the switch control signal sample_selt received by the switch control terminal of the input selection circuit 200 is at the high level, the first output terminal V1 of the first control module 201 outputs a closing signal to control the first switch S1 and the fourth switch S4 to be closed; and the second output terminal V2 outputs a turn-off signal to control the second switch S2 and the third switch S3 to be turned off.
When the potential difference between the output stage VOP and the output stage VON is in the negative half period, that is, when the potential of the switch control signal sample_selt received by the switch control terminal of the input selection circuit 200 is at the low level, the first output terminal V1 of the first control module 201 outputs the off signal, controls the first switch S1 and the fourth switch S4 to be opened, and the second output terminal V2 thereof outputs the on signal, thereby controlling the second switch S2 and the third switch S3 to be closed.
The embodiment provides a specific implementation manner of the input selection circuit 200, but is not limited thereto, and the input selection circuit may be implemented by a circuit structure or a chip formed by other discrete devices in practical application, depending on the specific application environment, as long as the scheme capable of implementing the above working principle is within the protection scope of the present application.
The other structures and principles are the same as those of the above embodiments, and will not be described in detail here.
Alternatively, as shown in fig. 4, in another embodiment of the present application, an implementation of a clock control circuit 500 includes: a second sampling clock 510, a first counter 520, a second counter 530, and a third counter 540; wherein:
an output end of the second sampling clock 510 is used as an output end of the clock control circuit 500 and is connected with a clock control end of the sample hold circuit 300; a first input of the second sampling clock 510 is connected to a first counter 520; a second input of the second sampling clock 510 is connected to a second counter 530; a third input of the second sampling clock 510 is connected to a third counter 540.
The specific working principle is as follows:
when the potential difference between the output stage VOP and the output stage VON is in the positive half period, that is, the potential of the switch control signal sample_selt is at the high level, the potential of the clock control signal output by the second sampling clock 510 is at the high level when the potential of the output stage VOP is increased; the first counter 520 counts up and the second counter 530 counts up using the first sampling clock 400.
When the potential of the output stage VOP decreases, the first counter 520 continues to count up by two, while the second counter 530 clears; the first counter 520 continues the counting of the above-described process, and when the first counter counts to 256, the potential of the signal output by the second sampling clock 510 becomes a low level; if the voltage drop of the output stage VOP is still not detected when the second counter 530 counts up to 256, the second counter 530 forces the voltage of the clock control signal output by the second acquisition clock 510 to be low, and the third counter 540 starts to count up with the first sampling clock 400.
When the potential of the output stage VOP rises again, the potential of the signal output by the second sampling clock 510 becomes a high level; if the potential rise of the output stage VOP is still not detected when the third counter 540 counts up to 128, the third counter 540 forces the potential of the clock control signal output by the second sampling clock 510 to become a high level.
The clock control circuit 500 repeats the above-described process until the potential of the switch control signal sample_selt becomes low, i.e., the operating state of the class D audio power amplifier 600 changes from the positive half cycle to the negative half cycle.
When the potential difference between the output stage VOP and the output stage VON is in the negative half period, that is, the potential of the switch control signal sample_selt is at the low level, the potential of the clock control signal output by the second sampling clock 510 is at the high level when the potential of the output stage VON is increased; the first counter 520 counts up and the second counter 530 counts up using the first sampling clock 400.
When the potential of the output stage VON decreases, the first counter 520 continues to count up by two, while the second counter 530 clears; the first counter 520 continues the counting of the above-described process, and when the first counter counts to 256, the potential of the signal output by the second sampling clock 510 becomes a low level; if the voltage drop of the output stage VON is still not detected when the second counter 530 counts 256, the second counter 530 forces the voltage of the clock control signal output by the second acquisition clock 510 to be low, and the third counter 540 starts to count up with the first sampling clock 400.
When the potential of the output stage VON rises again, the potential of the signal output by the second sampling clock 510 becomes a high level; if the potential rise of the output stage VON is still not detected when the third counter 540 counts to 128, the third counter 540 forces the potential of the clock control signal output by the second sampling clock 510 to become a high level.
The clock control circuit 500 repeats the above-described process until the potential of the switch control signal sample_selt becomes high level, i.e., the operation state of the class D audio power amplifier 600 is changed from the negative half cycle to the positive half cycle.
It should be noted that, in this embodiment, only one specific implementation manner of the clock control circuit is provided, and in practical application, the clock control circuit may be implemented by a circuit structure or a chip formed by other discrete devices, and, depending on the specific application environment, other schemes capable of implementing the above working principle are all within the scope of the present application.
The other structures and principles are the same as those of the above embodiments, and will not be described in detail here.
Optionally, as shown in fig. 5, the sample-and-hold circuit 300 includes: the voice coil motor VCM comprises a first switching branch 301, a second switching branch 302, a third switching branch 303, a fourth switching branch 304, a voice coil motor VCM, a second control module 305, a first capacitor C1 and a second capacitor C2 with the same capacitance value, and a third capacitor C3 and a fourth capacitor C4 with the same capacitance value; wherein:
The input terminal of the first switching leg 301 is connected to the input terminal of the third switching leg 303, the connection point being the first input terminal of the sample-and-hold circuit 300; an input of the second switching leg 302 is connected to an input of the fourth switching leg 304 at a junction point which is a second input of the sample-and-hold circuit 300.
The first output end of the first switch branch 301 is connected with one end of the third capacitor C3, and the connection point is used as the first output end of the sample-and-hold circuit 300; the first output terminal of the fourth switching leg 304 is connected to one terminal of the fourth capacitor C4, and the connection point is used as the second output terminal of the sample-and-hold circuit 300.
The other end of the third capacitor C3, the other end of the fourth capacitor C4 and the positive end of the voice coil motor VCM are all grounded; a first output terminal of the second switching leg 302 is connected to a first output terminal of the third switching leg 303, and a connection point is connected to a negative terminal of the voice coil motor VCM.
One end of the first capacitor C1 is connected to the second output end of the first switch branch 301; the other end of the first capacitor C1 is connected with the second output end of the second switch branch 302; one end of the second capacitor C2 is connected to the second output end of the third switch branch 303; the other end of the second capacitor C2 is connected to the second output terminal of the fourth switching leg 304.
The first control terminal of the first switching leg 301, the first control terminal of the second switching leg 302, the first control terminal of the third switching leg 303 and the first control terminal of the fourth switching leg 304 are connected, and the connection point is connected to the first output terminal of the second control module 305.
A second control terminal of the second switching leg 302 is connected to a second control terminal of the third switching leg 303, and a connection point is connected to a second output terminal of the second control module 305; the second control terminal of the first switching leg 301 is connected to the second control terminal of the fourth switching leg 304, and the connection point is connected to the third output terminal of the second control module 305; the input of the second control module 305 serves as the clock control of the sample and hold circuit.
Alternatively, as an implementation, as shown in fig. 4, the first switching branch 301 includes: a fifth switch S5 and a sixth switch S6; wherein:
the input end of the fifth switch S5 is used as the input end of the first switch branch 301, the output end of the fifth switch S5 is connected with the input end of the sixth switch S6, the connection point is used as the second output end of the first switch branch 301, and the output end of the sixth switch S6 is used as the first output end of the first switch branch 301;
the control terminal of the fifth switch S5 is used as the first control terminal of the first switching leg 301, and the control terminal of the sixth switch S6 is used as the second control terminal of the first switching leg 301.
Alternatively, as an implementation, as shown in fig. 4, the second switching leg 302 includes: a seventh switch S7 and an eighth switch S8; wherein:
the input end of the seventh switch S7 is used as the input end of the second switch branch 302, the output end of the seventh switch S7 is connected with the input end of the eighth switch S8, the connection point is used as the second output end of the second switch branch 302, and the output end of the eighth switch S8 is used as the first output end of the second switch branch 302;
the control terminal of the seventh switch S7 is used as the first control terminal of the second switch branch 302, and the control terminal of the eighth switch S8 is used as the second control terminal of the second switch branch 302.
Optionally, as an implementation manner, as shown in fig. 3, the third switching branch 303 includes: a ninth switch S9 and a tenth switch S10; wherein:
the input end of the ninth switch S9 is taken as the input end of the third switch branch 303, the output end of the ninth switch S9 is connected with the input end of the tenth switch S10, the connection point is taken as the second output end of the third switch branch 303, and the output end of the tenth switch S10 is taken as the first output end of the third switch branch 303;
the control terminal of the ninth switch S9 is used as the first control terminal of the third switching leg 303, and the control terminal of the tenth switch S10 is used as the second control terminal of the third switching leg 303.
Optionally, as an implementation, as shown in fig. 3, the fourth switching leg 304 includes: an eleventh switch S11 and a twelfth switch S12; wherein:
the input end of the eleventh switch S11 is used as the input end of the fourth switch branch 304, the output end of the eleventh switch S11 is connected with the input end of the twelfth switch S12, the connection point is used as the second output end of the fourth switch branch 304, and the output end of the twelfth switch S12 is used as the first output end of the fourth switch branch 304;
the control terminal of the eleventh switch S11 is used as the first control terminal of the fourth switching leg 304, and the control terminal of the twelfth switch S12 is used as the second control terminal of the fourth switching leg 304.
In the present embodiment, the fifth switch S5, the sixth switch S6, the seventh switch S7, the eighth switch S8, the ninth switch S9, the tenth switch S10, the eleventh switch S11, and the twelfth switch S12 are all turned on when the control terminal receives the high-level signal, and turned off when the control terminal receives the low-level signal; other embodiments that achieve the same objects as this embodiment are within the scope of the application; hereinafter, the operation principle of the sample hold circuit 300 will be described with this embodiment only.
The specific working principle is as follows:
when the potential difference between the output stage VOP and the output stage VON is in the positive half period, i.e., when the potential of the switch control signal sample_selt is at the high level, the input selection circuit 200 forms a path between its first input terminal SN1 and its first output terminal, and between its third input terminal SN3 and its second output terminal.
When the potential of the clock control signal output by the clock control circuit 500 is at the high level, the potential of the signal P1 output by the first output terminal of the second control module 305 is at the high level, the fifth switch S5, the seventh switch S7, the ninth switch S9 and the eleventh switch S11 are closed, and the first capacitor C1 and the second capacitor C2 start to adopt the voltages across the first detection resistor RSP.
When the potential of the clock control signal output by the clock control circuit 500 changes to a low level, the potential of the signal P1 at the first output end of the second control module 305 changes to a low level, the fifth switch S5, the seventh switch S7, the ninth switch S9 and the eleventh switch S11 are turned off, Φ1 changes from high to low, and the first capacitor C1 and the second capacitor C2 stop collecting.
The voltage value sampled by the first capacitor C1 is IL RSP, and the voltage value sampled by the second capacitor C2 is-IL RSP; wherein IL is the operating current of the class D audio power amplifier.
After the potential of the signal P1 at the first output end of the second control module 305 becomes low level, that is, Φ1 becomes low, after a certain non-overlapping time, the potential of the signal at the second output end P2 of the second control module 305 becomes high level, the eighth switch S8 and the tenth switch S10 are closed, Φ2 is changed from low to high, and the voice coil motor VCM voltage is established; after a certain voltage establishment time of the voice coil motor VCM, the potential of the signal at the third output end of the second control module 305 changes to a high level, the sixth switch S6 and the twelfth switch S12 are closed, Φ3 changes from low to high, and the voltages sampled by the first capacitor C1 and the second capacitor C2 are transferred to the third capacitor C3 and the fourth capacitor C4 and are output to the conversion module 800.
The voltages output by the two output terminals of the sample-and-hold circuit 300 are the difference between the potential sh_vop of the first output terminal of the sample-and-hold circuit 300 and the potential sh_von of the first output terminal thereof, i.e., sh_vop-sh_von=2×il×rsp.
The voice coil motor VCM voltage is used to make the voltages of the outputs of the first output terminal and the second output terminal of the sample-and-hold circuit 300 within the input common mode range of the integrating-differentiating analog-to-digital converter.
After the potential of the signal output by the clock control circuit 500 changes to the high level again, the potential of the signal P2 at the second output terminal and the potential of the signal P3 at the third output terminal of the second control module 305 both change to the low level, and the sixth switch S6, the eighth switch S8, the tenth switch S10 and the twelfth switch S12 are turned off, and Φ2 and Φ3 are changed from high to low; after a certain non-overlapping time, the potential of the signal at the first output end of the second control module 305 becomes high level, the fifth switch S5, the seventh switch S7, the ninth switch S9 and the eleventh switch S11 are closed, Φ1 is changed from low to high, the first capacitor C1 and the second capacitor C2 start to Sample the voltage at the two ends of the first detection resistor RSP again, and the above process is repeated until the potential of the switch control signal sample_selt becomes low level, that is, the potential difference between the output stage VOP and the output stage VON is in a negative half period.
When the potential difference between the output stage VOP and the output stage VON is in the negative half period, i.e., when the potential of the switch control signal sample_selt is in the low level, the input selection circuit 200 forms a path with its third input terminal SN3 and its first output terminal, and forms a path with its second input terminal and its second output terminal.
When the potential of the clock control signal output by the clock control circuit 500 is at the high level, the signal P1 output by the first output terminal of the second control module 305 is at the high level, the fifth switch S5, the seventh switch S7, the ninth switch S9, and the eleventh switch S11 are closed, and the first capacitor C1 and the second capacitor C2 begin to sample the voltage between the third input terminal and the second input terminal of the input selection circuit 200, that is, the voltage across the second detection resistor RSN. The rest of the processes are the same as the above processes, and will not be described in detail here.
It should be noted that, the embodiment only provides an implementation manner of the sample-hold circuit, and in practical application, the sample-hold circuit can be implemented by a circuit structure or a chip formed by other discrete devices, and other schemes capable of implementing the above working principle are all within the protection scope of the present application, depending on the specific application environment.
The other structures and principles are the same as those of the above embodiments, and will not be described in detail here.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
It is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
Claims (10)
1. A current detection circuit for a loudspeaker adapted for connection to a class D audio power amplifier, comprising: the device comprises a first detection resistor, a second detection resistor, a sampling selection circuit, an input selection circuit, a sampling holding circuit, a clock control circuit and a conversion circuit; wherein:
One end of the first detection resistor is connected with the first input end of the input selection circuit, and a connection point is used as the first input end of the current detection circuit of the loudspeaker and is connected with the source electrode of the low-end NMOS transistor of the output stage VON of the class-D audio power amplifier;
one end of the second detection resistor is connected with the second input end of the input selection circuit, and a connection point is used as the second input end of the current detection circuit of the loudspeaker and is connected with the source electrode of the low-end NMOS transistor of the output stage VOP of the class-D audio power amplifier;
the other end of the first detection resistor, the other end of the second detection resistor and the third input end of the input selection circuit are grounded;
the first output end of the input selection circuit is connected with the first input end of the sample hold circuit; the second output end of the input selection circuit is connected with the second input end of the sample hold circuit;
the first output end of the sampling and holding circuit is connected with the first input end of the conversion circuit, and the second output end of the sampling and holding circuit is connected with the second input end of the conversion circuit; the clock control end of the sampling hold circuit is connected with the output end of the clock control circuit;
The output end of the conversion circuit is used as the output end of the current detection circuit of the loudspeaker;
three input ends of the sampling selection circuit are respectively connected with the output stage VOP, the output stage VON and the first sampling clock; the output end of the sampling selection circuit is connected with the switch control end of the input selection circuit;
the sampling selection circuit is used for controlling the first input end and the second output end of the input selection circuit to form a passage and controlling the third input end and the second output end of the input selection circuit to form a passage when the potential difference between the output stage VOP and the output stage VON is in a positive half period; when the potential difference between the output stage VOP and the output stage VON is in a negative half period, the third input end and the first output end are controlled to form a passage, and the second input end and the second output end are controlled to form a passage;
the sampling hold circuit is used for sampling the voltage between two output ends of the sampling select circuit according to the clock control signal output by the clock control circuit, or stopping sampling and outputting the sampled voltage to the conversion circuit.
2. The loudspeaker current detection circuit of claim 1, wherein the input selection circuit comprises: the first switch, the second switch, the third switch, the fourth switch and the first control module; wherein:
The input end of the first switch is used as a first input end of the input selection circuit; the input end of the second switch is used as a second input end of the input selection circuit; the input end of the third switch is connected with the input end of the fourth switch, and the connection point is used as the third input end of the input selection circuit;
the output end of the first switch is connected with the output end of the third switch, and the connection point is used as the first output end of the input selection circuit; the output end of the second switch is connected with the output end of the fourth switch, and the connection point is used as the second output end of the input selection circuit;
the control end of the first switch is connected with the control end of the fourth switch, and the connection point is connected with the first output end of the first control module; the control end of the second switch is connected with the control end of the third switch, and the connection point is connected with the second output end of the first control module;
the input end of the first control module is used as a switch control end of the input selection circuit.
3. The loudspeaker current detection circuit of claim 1, wherein the sample-and-hold circuit comprises: the voice coil motor comprises a first switch branch, a second switch branch, a third switch branch, a fourth switch branch, a voice coil motor, a second control module, a first capacitor and a second capacitor with the same capacitance value, and a third capacitor and a fourth capacitor with the same capacitance value; wherein:
The input end of the first switch branch is connected with the input end of the third switch branch, and the connection point is used as the first input end of the sample hold circuit;
the input end of the second switching branch is connected with the input end of the fourth switching branch, and the connection point is used as a second input end of the sample hold circuit;
the first output end of the first switch branch is connected with one end of the third capacitor, and the connection point is used as the first output end of the sample hold circuit;
the first output end of the fourth switching branch is connected with one end of the fourth capacitor, and the connection point is used as the second output end of the sample hold circuit;
the other end of the third capacitor, the other end of the fourth capacitor and the positive end of the voice coil motor are grounded;
the first output end of the second switch branch is connected with the first output end of the third switch branch, and the connection point is connected with the negative end of the voice coil motor;
one end of the first capacitor is connected with the second output end of the first switch branch; the other end of the first capacitor is connected with the second output end of the second switch branch;
one end of the second capacitor is connected with the second output end of the third switch branch; the other end of the second capacitor is connected with the second output end of the fourth switching branch;
The first control end of the first switch branch, the first control end of the second switch branch, the first control end of the third switch branch and the first control end of the fourth switch branch are connected, and the connection point is connected with the first output end of the second control module;
the second control end of the second switch branch is connected with the second control end of the third switch branch, and the connection point is connected with the second output end of the second control module;
the second control end of the first switching branch is connected with the second control end of the fourth switching branch, and the connection point is connected with the third output end of the second control module;
the input end of the second control module is used as a clock control end of the sample hold circuit.
4. A loudspeaker current detection circuit according to claim 3, wherein the first switching branch comprises: a fifth switch and a sixth switch; wherein:
the input end of the fifth switch is used as the input end of the first switch branch, the output end of the fifth switch is connected with the input end of the sixth switch, the connection point is used as the second output end of the first switch branch, and the output end of the sixth switch is used as the first output end of the first switch branch;
The control end of the fifth switch is used as the first control end of the first switch branch, and the control end of the sixth switch is used as the second control end of the first switch branch.
5. A loudspeaker current detection circuit according to claim 3, wherein the second switching branch comprises: a seventh switch and an eighth switch; wherein:
the input end of the seventh switch is used as the input end of the second switch branch, the output end of the seventh switch is connected with the input end of the eighth switch, the connection point is used as the second output end of the second switch branch, and the output end of the eighth switch is used as the first output end of the second switch branch;
the control end of the seventh switch is used as the first control end of the second switch branch, and the control end of the eighth switch is used as the second control end of the second switch branch.
6. A loudspeaker current detection circuit according to claim 3, wherein the third switching branch comprises: a ninth switch and a tenth switch; wherein:
the input end of the ninth switch is used as the input end of the third switch branch, the output end of the ninth switch is connected with the input end of the tenth switch, the connection point is used as the second output end of the third switch branch, and the output end of the tenth switch is used as the first output end of the third switch branch;
The control end of the ninth switch is used as the first control end of the third switch branch, and the control end of the tenth switch is used as the second control end of the third switch branch.
7. A loudspeaker current detection circuit according to claim 3, wherein the fourth switching leg comprises: an eleventh switch and a twelfth switch; wherein:
the input end of the eleventh switch is used as the input end of the fourth switch branch, the output end of the eleventh switch is connected with the input end of the twelfth switch, the connection point is used as the second output end of the fourth switch branch, and the output end of the twelfth switch is used as the first output end of the fourth switch branch;
the control end of the eleventh switch is used as the first control end of the fourth switch branch, and the control end of the twelfth switch is used as the second control end of the fourth switch branch.
8. The loudspeaker current detection circuit of claim 1, wherein the clock control circuit comprises: the second sampling clock, the first counter, the second counter and the third counter; wherein:
the output end of the second sampling clock is used as the output end of the clock control circuit; the first input end of the second sampling clock is connected with the first counter; the second input end of the second sampling clock is connected with the second counter; and a third input end of the second sampling clock is connected with the third counter.
9. The loudspeaker current detection circuit of claim 1 wherein the conversion circuit is an integral-differential analog-to-digital converter.
10. The loudspeaker current detection circuit according to claim 1, wherein the first detection resistor and the second detection resistor have equal resistance values; the frequency of the first sampling clock is 256 times the pulse width modulation frequency of the potential of the output stage VOP and the potential of the output stage VON.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910035468.7A CN109546978B (en) | 2019-01-15 | 2019-01-15 | Current detection circuit of loudspeaker |
| KR1020217025609A KR102577482B1 (en) | 2019-01-15 | 2020-01-13 | Current detection circuit for loudspeaker |
| PCT/CN2020/071720 WO2020147672A1 (en) | 2019-01-15 | 2020-01-13 | Current detection circuit for loudspeaker |
| US17/423,346 US11698393B2 (en) | 2019-01-15 | 2020-01-13 | Current detection circuit for loudspeaker |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910035468.7A CN109546978B (en) | 2019-01-15 | 2019-01-15 | Current detection circuit of loudspeaker |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109546978A CN109546978A (en) | 2019-03-29 |
| CN109546978B true CN109546978B (en) | 2023-09-19 |
Family
ID=65835092
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910035468.7A Active CN109546978B (en) | 2019-01-15 | 2019-01-15 | Current detection circuit of loudspeaker |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109546978B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11698393B2 (en) * | 2019-01-15 | 2023-07-11 | Shanghai Awinic Technology Co., LTD | Current detection circuit for loudspeaker |
| CN110632381B (en) | 2019-11-12 | 2022-02-01 | 上海艾为电子技术股份有限公司 | Current detection circuit, chip and current detection method for loudspeaker protection |
| CN114604173B (en) * | 2020-12-09 | 2024-05-17 | 华为技术有限公司 | Detection system, T-BOX and vehicle |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006279510A (en) * | 2005-03-29 | 2006-10-12 | Sony Corp | Amplifier output controller, audio device, and amplifier output control method |
| JP2007124624A (en) * | 2005-09-28 | 2007-05-17 | Yamaha Corp | Class-d amplifier |
| JP2009267615A (en) * | 2008-04-23 | 2009-11-12 | Toa Corp | Amplifier for audio |
| CN102957383A (en) * | 2011-08-25 | 2013-03-06 | Nxp股份有限公司 | Class d amplifier and control method |
| CN103346745A (en) * | 2013-07-03 | 2013-10-09 | 中国科学院微电子研究所 | Input stage fully differential operational amplifier of class D audio power amplifier |
| CN105048980A (en) * | 2015-08-18 | 2015-11-11 | 矽力杰半导体技术(杭州)有限公司 | Class D amplifier |
| CN109068241A (en) * | 2018-08-27 | 2018-12-21 | 上海艾为电子技术股份有限公司 | A kind of digital audio power amplification system |
| CN209184564U (en) * | 2019-01-15 | 2019-07-30 | 上海艾为电子技术股份有限公司 | A kind of current detection circuit of loudspeaker |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8189802B2 (en) * | 2009-03-19 | 2012-05-29 | Qualcomm Incorporated | Digital filtering in a Class D amplifier system to reduce noise fold over |
-
2019
- 2019-01-15 CN CN201910035468.7A patent/CN109546978B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006279510A (en) * | 2005-03-29 | 2006-10-12 | Sony Corp | Amplifier output controller, audio device, and amplifier output control method |
| JP2007124624A (en) * | 2005-09-28 | 2007-05-17 | Yamaha Corp | Class-d amplifier |
| JP2009267615A (en) * | 2008-04-23 | 2009-11-12 | Toa Corp | Amplifier for audio |
| CN102957383A (en) * | 2011-08-25 | 2013-03-06 | Nxp股份有限公司 | Class d amplifier and control method |
| CN103346745A (en) * | 2013-07-03 | 2013-10-09 | 中国科学院微电子研究所 | Input stage fully differential operational amplifier of class D audio power amplifier |
| CN105048980A (en) * | 2015-08-18 | 2015-11-11 | 矽力杰半导体技术(杭州)有限公司 | Class D amplifier |
| CN109068241A (en) * | 2018-08-27 | 2018-12-21 | 上海艾为电子技术股份有限公司 | A kind of digital audio power amplification system |
| CN209184564U (en) * | 2019-01-15 | 2019-07-30 | 上海艾为电子技术股份有限公司 | A kind of current detection circuit of loudspeaker |
Non-Patent Citations (2)
| Title |
|---|
| An 8 2.5 W 1%-THD 104 dB(A)-Dynamic-Range Class-D Audio Amplifier With Ultra-Low EMI System and Current Sensing for Speaker Protection;Angelo Nagari等;《IEEE JOURNAL OF SOLID-STATE CIRCUITS》;第47卷(第12期);3068-3080 * |
| 高性能D类音频放大器的设计;王宪玉;《中国优秀硕士论文全文数据库信息科技辑》(第08（2018）期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109546978A (en) | 2019-03-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10924069B2 (en) | System and method for low distortion capacitive signal source amplifier | |
| US9722563B2 (en) | System and method for high input capacitive signal amplifier | |
| CN109546978B (en) | Current detection circuit of loudspeaker | |
| CN1835393B (en) | Audio amplifier with high power and high efficiency and its control method | |
| CN100508372C (en) | Class D amplifier | |
| KR20030066847A (en) | Digital pwm input d class amplifier by pwm negative feedback | |
| US6922101B2 (en) | Phase shift modulation class D amplifier | |
| CN1694356B (en) | Method and apparatus for self-oscillating differential feedback class-D amplifier | |
| CN109495078A (en) | A kind of reference voltage generating circuit and Switching Power Supply | |
| US11968503B2 (en) | Current detection circuit, chip, and current detection method used for speaker protection | |
| CN101663813A (en) | A data processing system for clipping correction | |
| US11698393B2 (en) | Current detection circuit for loudspeaker | |
| CN109546979B (en) | Current detection circuit of loudspeaker | |
| US20090160551A1 (en) | Switching Amplifier | |
| CN212305266U (en) | Filter capacitor current feedback self-oscillation audio digital power amplifier | |
| CN209184565U (en) | A kind of current detection circuit of loudspeaker | |
| CN209184564U (en) | A kind of current detection circuit of loudspeaker | |
| CN209184560U (en) | A kind of reference voltage generating circuit and Switching Power Supply | |
| CN203775149U (en) | Class-D power amplification chip with power limiting function and audio play device | |
| KR100453708B1 (en) | High-Efficiency Switching Amplifier | |
| US9825600B2 (en) | Class D amplifier and electronic devices including the same | |
| CN101557200B (en) | Power amplifier capable of regulating noise | |
| CN209881739U (en) | PWM power amplifier capable of reducing phase distortion at modulation stage | |
| CN203457115U (en) | Mute-starting kind-D amplifier | |
| CN202535324U (en) | Switch circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |