CN203457115U - Mute-starting kind-D amplifier - Google Patents
Mute-starting kind-D amplifier Download PDFInfo
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- CN203457115U CN203457115U CN201320139894.3U CN201320139894U CN203457115U CN 203457115 U CN203457115 U CN 203457115U CN 201320139894 U CN201320139894 U CN 201320139894U CN 203457115 U CN203457115 U CN 203457115U
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Abstract
A kind-D amplifier comprises a pre-amplifier. The pre-amplifier is configured for receiving an amplifier reference voltage signal which forms a slope in high speed in starting. An integrator is provided with a first input which is configured for receiving an input signal from the pre-amplifier and is configured for receiving an integrator reference voltage signal that forms a slope in a lower speed in starting. A modulator is provided with an input which is coupled with the output of the integrator. The modulator generates a pulse-width-modulated output signal. In starting, operation of the kind-D amplifier is controlled through applying a slow slope signal which is used as the integrator reference voltage signal and a quick slope signal that is used as an amplifier reference voltage signal, so that the pulse-width-modulated output signal responds to increased voltage of the integrator reference voltage signal and represents duty ratio increase, and furthermore no bang sound is introduced in starting.
Description
Technical field
The utility model relates to amplifier circuit, relates in particular to a kind of D class type amplifier that comprises quiet start-up performance.
Background technology
With reference to figure 1, it illustrates and can operate input signal 12 (for example, audio signal) to be converted into the circuit diagram of the conventional D class A amplifier A 10 of high-frequency impulse 14.Typical D class A amplifier A utilizes pulse-width modulator 18 to generate the high-frequency impulse 14 that its width changes as the function of the amplitude of input signal 12.Pulse-width modulator 18 can comprise comparator 19 conventionally, and it has first (just) input that receives input signal 12 and second (bearing) input that receives sawtooth (or triangle) waveform reference 21.The pulse of the change width of exporting from pulse-width modulator 18 produces the control signal 22 of opposite phase pulse by driving logical circuit 20 to process, to put on the control terminal of the transistor switch 16 of disposing with half-bridge (half-bridge) configuration.The output of transistor bridge is coupled to load 26 (in this case, being illustrated as loud speaker when input signal is audio signal) by low pass filter 24 (having DC block-condenser).Low pass filter 24 is fed back into the amplified version of signal to put on load by pulses switch.In one embodiment, although can use more complicated filter circuit in the situation that of needs, filter 24 is formed by conventional inductance/capacitance circuit.
Although pulse-width modulator 18 is illustrated as the circuit that input signal is converted to high-frequency impulse, it is known in the art utilizing other pulse modulated circuit to carry out processing audio input signal.For example, can use pulse density modulator.
With reference to figure 2, conventional D class A amplifier A 10 may further include integrator circuit 30.Integrator circuit 30 comprises operational amplifier 32, and it has coupling to receive first (bearing) input of input signal 12 by input resistor Rin.Second (just) input of operational amplifier 32 receives fixing reference voltage V ref.The output of this operational amplifier is coupled to the input of pulse-width modulator 18, and further in feedback circuit, by feedback condenser Cfb, is coupled to the negative input of operational amplifier 32.Conventionally half of supply power voltage Vdd that is set to equal operational amplifier 32 to the fixed voltage Vref of the positive input of operational amplifier 32 is provided.The supply power voltage Vcc that supply power voltage Vdd is conventionally used from transistor bridge separate and with it in different voltage levels.
In operation, the output of the square wave of the power switch transistor at transistor bridge place is added so that negative feedback to be provided with the audio frequency input at the negative input place of operational amplifier 32.Before low pass filter 24, (rather than afterwards) obtains this negative feedback, to avoid needing complicated compensating network to process by the caused phase shift of low pass filter in feedback loop.Therefore feedback resistor Rfb is coupling between the output of transistor bridge and the negative input of operational amplifier 32.
The square wave output of transistor bridge is synchronizeed with audio frequency input, but importantly will remove the carrier wave of audio input signal.Integrator circuit 30 is used for square wave output and audio input signal to be added.Integrator circuit 30 is sent into produced error signal the positive input of duty cycle modulator 18.Therefore the comparator circuit of modulator 18 compares and produces the modulation output as square wave using triangular waveform benchmark and this error signal, and the amplitude of its duty ratio and audio input signal is proportional.
For suitable driving transistors bridge circuit, drive logic 20 that modulation output is converted to and drives signal to the high-low power switch in phase reversal relation of this transistor bridge is driven.Drive logic 20 therefore other switch that is saturated this bridge a switch drive of this bridge to be cut off to (vice versa).As known to those skilled, the combination of the switch of transistor bridge and conducting loss has defined the upper bound of efficiency of amplitude.The square wave of modulated output makes bridge switch change as quickly as possible state.High-speed switch is desired, because it has limited bridge switch spent time in linear operating area, has improved thus efficiency and has reduced heat generation.
Those skilled in the art recognize that, D class A amplifier A produces " cloop (pop) " that can be noted at speaker when first the power for amplifier opened.Importantly to retain the fidelity in input signal about input audio signal.The appearance of any illusion " cloop " in output signal when starting is all unacceptable.
Although the multiple solution for starting illusion problem known in the art, many in these solutions are expensive, too complicated, or can introduce other problem (comprising illusion).There is a need in the art for the startup illusion problem being associated with conventional D class A amplifier A a kind of cheapness and effective solution are provided.
Utility model content
In one embodiment, a kind of D class A amplifier A circuit comprises: integrator, and it has to be configured to receive the first input of input signal and to be configured to receive second of reference voltage signal inputs; The first slope maker, it is configured to generate integrator ramp signal when amplifier starts, and described integrator ramp signal puts on the second input of integrator as reference voltage signal; Modulator circuit, it has the input of the output that is coupled to integrator; Transistor bridge circuit, it is configured in response to the modulation signal from modulator circuit output driven; And feedback loop, its output by transistor bridge is coupled to the first input of integrator.This amplifier further comprises preamplifier circuit, it is configured to generate described input signal, wherein this preamplifier circuit has the first input being configured to receiving from wherein deriving the signal of input signal, and there is the second input that is configured to receive reference voltage signal, and the second slope maker that is configured to generate amplifier ramp signal when amplifier starts, described amplifier ramp signal puts on the second input of preamplifier circuit as reference voltage signal.
In one embodiment, a kind of D class A amplifier A circuit comprises: integrator, and it has to be configured to receive the first input of input signal and to be configured to receive second of integrator reference voltage signal inputs; Modulator circuit, it has the input of the output that is coupled to integrator, and described modulator circuit generates the output signal of pulse width-modulated; And start-up circuit, it is configured to the oblique ascension integrator reference voltage signal in response to amplifier starts and changes so that the output signal of described pulse width-modulated shows the increase of duty ratio in response to the voltage rising of integrator reference voltage signal.This circuit further comprises preamplifier circuit, it is configured to generate described input signal, wherein this preamplifier circuit has the first input being configured to receiving from wherein deriving the signal of input signal, and have the second input that is configured to reception amplifier reference voltage signal, this start-up circuit is further configured such that amplifier reference voltage signal is with than integrator reference voltage signal speed oblique ascension faster.
Accompanying drawing explanation
In order to understand better embodiment, now will be only by way of example with reference to accompanying drawing, wherein:
Fig. 1 and 2 illustrates conventional D class A amplifier A Circnit Layout;
Fig. 3 is the circuit diagram with the D class A amplifier A of quiet startup;
Fig. 4 illustrates the circuit diagram of amplifier ramp voltage benchmark;
Fig. 5 illustrates the circuit diagram of integrator ramp voltage benchmark; And
Fig. 6 illustrates the waveform of start-up operation of the amplifier of Fig. 3.
Embodiment
With reference now to Fig. 3,, it shows the circuit diagram of the D class A amplifier A 100 with quiet startup.
Rfb2=(n+1) R2+nR3, wherein R1=nR3
About the stability of amplifier 100, provide as follows loop transfer H (s):
H(s)＝Vout/Vin＝Gpwm/(s*Rfb2*Cfb)
Wherein Gpwm be Vcc with the ratio of Vt (that is, and gain Vcc/Vt) reflecting,
Wherein Vt is the maximum voltage of sawtooth (or triangle) waveform signal 146 that generates of benchmark 144 and the voltage difference between minimum voltage.
The slope of sawtooth (or triangle) waveform signal 146 preferably should be greater than the slope from the output signal of integrator circuit 120.In other words:
dV146/dt＞dVo120/dt
Wherein V146 is the voltage of sawtooth (or triangle) waveform signal 146 and Vo120 is the voltage of the output of integrator circuit 120.
Also will it is also noted that, from the slope of the output signal of integrator circuit 120 by given below:
dVo120/dt＝Ic/Cfb
Modulation depth becomes 100% when the input current Iin for operational amplifier 122 equals the feedback current Ifb at negative input place of operational amplifier 122.In this case, the charge/discharge current Ic of feedback condenser Cfb is maximum.As a result, the standard of the stability of feedback loop becomes:
dV146/dt＞Vcc/(Rfb2*Cfb)，
Because Ic (max)=Vcc/Rfb2
About DC balance and quiet startup, when input signal is zero, the output of load place need to be offset to some extent at Vcc/2.This is the requirement for DC balance.Generate amplifier ramp voltage benchmark 108 sum-product intergrator ramp voltage benchmark 124 to realize desired balance.
According to Kirchhoff rule, by following formula, provided the mean value Vout of output voltage:
Vout=N*V124 (1+ (n+1)/N) N*V108
Wherein Vout is the mean value of V166 or V182 in Fig. 3, and V108 is the voltage of the amplifier ramp voltage signal 110 that generates of benchmark 108, V124 is the voltage of the integrator ramp voltage signal 126 that generates of benchmark 124, n=R1/R3 and N=Rfb2/Rin2.The feedback impedance of Rfb2 is implemented as the resistor network as shown with Rfb2=(n+1) R2+nR3, wherein R1=nR3.
For the audio input signal with respect to zero volt spy, make output in Vcc/2 biasing, the voltage max of amplifier ramp voltage signal 110 sum-product intergrator ramp voltage signal 126 must be as follows:
V126(max)＝Vdd/2
V110 (max)=Vdd (1/2+ (n+1)/(2N)) Vcc/ (2N)
With reference now to Fig. 4,, it illustrates the circuit diagram of amplifier ramp voltage benchmark 108.The circuit diagram of amplifier ramp voltage benchmark 108 comprises resistor R7 and the resistor R8 being connected in series as voltage divider.Resistor R9 and resistor R8 are connected in parallel.Resistor R7 and R8 have the resistance value that equals 2*R1.Resistor R9 has the resistance value that equals R3.Operational amplifier 130 comprises first (just) input being coupled with receiver voltage Vdd/2.The tap node of R7/R8 voltage divider is coupled in second (bearing) input of operational amplifier 130 by resistor R10.Resistor R10 has the impedance that equals R2.The output of operational amplifier 130 is coupled to the negative input of operational amplifier 130 by feedback resistor R11.Resistor R11 has the impedance that equals Rin2.Resistor R12 is coupling between the output of operational amplifier 130 and the output node 132 of benchmark 124.Capacitor C4 be coupling in output node 132 and the low supply node that is associated with low-voltage power supply benchmark between.Switching circuit 134 and resistor R12 parallel coupled.Switching circuit 134 is controlled by control circuit 136.
Utilize illustrated Circnit Layout, output node 132 generates amplifier ramp voltage signal 110, and it has maximum voltage value V110 (max)=Vdd (1/2+ (n+1)/(2N)) Vcc/ (2N).Be coupling in the C4 of appropriate value of output node 132 and R12 and will introduce enough good PSRR (supply-voltage rejection ratio) performances of reference signal 110.Switch 134 is used for carrying out short circuit around and the quick charge of amplifier ramp voltage signal 110 to its maximum voltage value being provided at resistor R12.Switch 134 is controlled and is carried out by this way work by control circuit 136: switch 134 short circuit R12 when applying Vdd electric power, and quick charge V110.To work as V110 is opened by near quick charge switch 134 to its maximum time.By this way, to reach its maximum voltage value td1 time of delay used will be very little to V110 (for example, counting microsecond to tens of microseconds).
With reference now to Fig. 5,, it illustrates the circuit diagram of integrator ramp voltage benchmark 124.The circuit of integrator ramp voltage benchmark 124 comprises resistor R4 and the resistor R5 being connected in series as voltage divider.The impedance of resistor R4 and R5 preferably equates and makes to export from voltage divider tap node the voltage that equals Vdd/2.Operational amplifier 112 comprises that being coupled to resistive voltage divider tap node inputs with receiver voltage Vdd/2 first (just).From the Vdd/2 output of R4/R5 voltage divider tap node, can also be applied to the positive input of the operational amplifier 130 in Fig. 4.The output steering of operational amplifier 112 is connected to second (bearing) input of operational amplifier 112 to form single gain voltage buffer.Resistor R6 is coupling between the output of operational amplifier 112 and the output node 114 of benchmark 124.Capacitor C3 be coupling in output node 114 and the low supply node that is associated with low-voltage power supply benchmark between.
Utilize illustrated Circnit Layout, output node 114 generates has the integrator ramp voltage signal 126 that maximum voltage value is V126 (max)=Vdd/2.The capacitor C3 that is coupling in output node 114 will introduce revolution (slew) in the rising in integrator ramp voltage signal 126, this reaches this signal maximum voltage value and has postponed (time constant by R6 and C3 is set) time delay td2 after having applied Vdd voltage.
With reference to Figure 4 and 5, select the value of R6, R12, C3 and C4 and the control circuit 136 of switch 134, to guarantee with respect to the correct temporal order of time t1, t2 and t3 and time delay td1 and td2, to guarantee, correctly start and suppress " cloop " noise as described above.
Time delay td1 and time delay td2 are controlled to implement certain boot sequence for amplifier 100.Especially, td1 < td2 and more specifically td1 < < td2.Utilize this configuration, amplifier ramp voltage signal 110 will rise to its threshold voltage in integrator ramp voltage signal 126, and (=V108 (max)/(1+ (1+n)/N) rises to its maximum voltage value before, and output will remain zero before this point.If starting like this, " cloop " noise of moment will be able to suppressed.In exemplary realization, td1 in several microseconds to the magnitude td2 of tens of microseconds for example, in the magnitude (, being more than or equal to about 60ms) of tens of milliseconds.By using switch 134, amplifier ramp signal V110 before time t2 by quick charge to its maximum voltage value.
With reference now to Fig. 6,, it illustrates the waveform of the start-up operation of amplifier 100.At time t1, Vcc and Vdd electric power are applied in amplifier 100 and amplifier enters startup (having the signal V110 and the V126 that all start rising).Amplifier ramp voltage signal 110 starts to rise and in time delay td1, rise to its maximum voltage value at time t1.Integrator ramp voltage signal 126 starts its rising and holding time at time t1 and postpones td2 and rise towards its maximum voltage value.Will be noted that, time delay td1 is shorter than in fact time delay td2 and must completes by time t2.When the integrator ramp voltage signal 126 rising reaches threshold value 400, (during=V108 (max)/(1+ (1+n)/N), modulator circuit 140 starts to generate modulation signal (referring to 402).Before this time point, output remains zero.Along with integrator ramp voltage signal 126 continues to rise, output V182 will be from very little towards Vcc/2 rising.Therefore, the duty ratio of the pwm signal V166 exporting from modulator circuit 140 has low duty ratio at first, and the signal V182 of the output of low pass filter 180 is low (referring to 406).Along with integrator ramp voltage signal 126 continues to rise towards its maximum, the duty ratio of PWM output signal increases (referring to 404) accordingly, and the signal V182 of the output of low pass filter 180 rise accordingly (referring to 408).Integrator ramp voltage signal 126 finally reaches its maximum (referring to 410) when time delay td2 finishes, and the PWM output signal signal at this some place with the output of 50% duty ratio and low pass filter 180 has risen to Vcc supply power voltage half.Due to the increase gradually (due to the integrator ramp voltage signal 126 of rising) of the increase of amplifier sum-product intergrator slope benchmark and the duty ratio of PWM output signal, in the signal of the output of low pass filter 180, do not introduce " cloop " or illusion.
Although transistor bridge is illustrated as half-bridge circuit, will be appreciated that, the configuration of amplifier 100 and operation can be applied to full-bridge design equally.
Because " cloop " noise is due to the unmatched potential problems of branch, so the utility model can further be applied to the D amplifier of bridging load (BTL) type.
Below exemplary and mode non-limiting example of having described by the complete and informedness of the utility model exemplary embodiment provides description.Yet, when reading with appended claims by reference to the accompanying drawings, will describe by above, various modifications and adaptive form can become apparent for various equivalent modifications.Yet, within still falling into scope of the present utility model as determined in appended claims to all such and similar modification of the utility model instruction.
Claims (12)
1. a D class A amplifier A circuit, comprising:
Integrator, it has to be configured to receive the first input of input signal and to be configured to receive second of reference voltage signal inputs;
The first slope maker, it is configured to generate integrator ramp signal when amplifier starts, and described integrator ramp signal is applied in the second input of integrator as reference voltage signal;
Modulator circuit, it has the input of the output that is coupled to integrator;
Transistor bridge circuit, it is configured in response to the modulation signal from modulator circuit output driven; And
Feedback loop, its output by transistor bridge is coupled to the first input of integrator.
2. D class A amplifier A circuit according to claim 1, wherein said the first oblique wave maker is configured to generate the integrator ramp signal that reaches the peaked rise time with tens of milliseconds of magnitudes.
3. D class A amplifier A circuit according to claim 1, further comprises:
Preamplifier circuit, it is configured to generate described input signal, and this preamplifier circuit has and is configured to derive out the first input that the signal of input signal receives from it, and has the second input that is configured to receive reference voltage signal; And
The second slope maker, it is configured to generate amplifier ramp signal when amplifier starts, and described amplifier ramp signal is applied in the second input of preamplifier circuit as reference voltage signal.
4. D class A amplifier A circuit according to claim 3, wherein said the first oblique wave maker is configured to generate the integrator ramp signal with the rise time longer than the rise time of amplifier ramp signal.
5. D class A amplifier A circuit according to claim 3, wherein said the first oblique wave maker is configured to generate the integrator ramp signal that reaches the peaked rise time of the magnitude with tens of milliseconds.
6. D class A amplifier A circuit according to claim 5, wherein said the second oblique wave maker is configured to generate the amplifier ramp signal that reaches the peaked rise time with several microsecond magnitudes.
7. D class A amplifier A circuit according to claim 6, wherein the maximum of amplifier ramp signal derives from the high supply power voltage of transistor bridge.
8. D class A amplifier A circuit according to claim 7, wherein the maximum of integrator ramp signal derives from the high supply power voltage of integrator.
9. a D class A amplifier A circuit, comprising:
Integrator, it has to be configured to receive the first input of input signal and to be configured to receive second of integrator reference voltage signal inputs;
Modulator circuit, it has the input of the output that is coupled to integrator, and described modulator circuit generates the output signal of pulse width-modulated; And
Start-up circuit, it is configured to the oblique ascension integrator reference voltage signal in response to amplifier starts, so that the output signal of described pulse width-modulated shows the increase of duty ratio in response to the voltage of the rising of integrator reference voltage signal, changes.
10. D class A amplifier A circuit according to claim 9, the voltage that wherein said integrator is configured to receive its rising by described the second input has the integrator reference voltage signal that reaches the peaked rise time of tens of milliseconds of magnitudes.
11. D class A amplifier A circuit according to claim 9, further comprise:
Preamplifier circuit, it is configured to generate described input signal, and this preamplifier circuit has the first input that is configured to the signal from its derivation input signal to receive, and has the second input that is configured to reception amplifier reference voltage signal; And
Wherein said start-up circuit is further configured such that amplifier reference voltage signal is with than integrator reference voltage signal speed oblique ascension faster.
12. D class A amplifier A circuit according to claim 11, wherein said integrator is configured to receive by described the second input the integrator reference voltage signal that reaches the peaked rise time of the magnitude with tens of milliseconds, and described pre-amplification circuit is configured to receive by described the second input the amplifier reference voltage signal of the rise time with the peaked several microsecond magnitudes of reaching of several microsecond magnitudes.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201320139894.3U CN203457115U (en) | 2013-03-22 | 2013-03-22 | Mute-starting kind-D amplifier |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201320139894.3U CN203457115U (en) | 2013-03-22 | 2013-03-22 | Mute-starting kind-D amplifier |
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| CN203457115U true CN203457115U (en) | 2014-02-26 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104065353A (en) * | 2013-03-22 | 2014-09-24 | 意法半导体研发(深圳)有限公司 | Mute-starting class-D amplifier |
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2013
- 2013-03-22 CN CN201320139894.3U patent/CN203457115U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104065353A (en) * | 2013-03-22 | 2014-09-24 | 意法半导体研发(深圳)有限公司 | Mute-starting class-D amplifier |
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Address after: 5 / F East B501, South B502, North B503, 6th floor, block B, TCL Industrial Research Institute building, No. 006, Gaoxin South 1st Road, Nanshan District, Shenzhen City, Guangdong Province Patentee after: STMicroelectronics (Shenzhen) R&D Co.,Ltd. Address before: 518057, 4/5 building, B block, South SKYWORTH building, South Zone, Shenzhen hi tech Zone, Nanshan District science and Technology Park, Guangdong, China Patentee before: STMicroelectronics (Shenzhen) R&D Co.,Ltd. |
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Granted publication date: 20140226 |