WO2010098090A1

WO2010098090A1 - Voltage polarity discrimination circuit and electrical load measuring circuit

Info

Publication number: WO2010098090A1
Application number: PCT/JP2010/001247
Authority: WO
Inventors: 井上敦雄; 松野則昭
Original assignee: パナソニック株式会社
Priority date: 2009-02-25
Filing date: 2010-02-24
Publication date: 2010-09-02

Abstract

A voltage polarity discrimination circuit (1) is provided with an integration circuit (10), a switch (SW0), and a time measuring circuit (12). The integration circuit (10) is constructed by using an operational amplifier circuit (100) having an input offset voltage (Vosa) which is greater than the maximum value or less than the minimum value of the input voltage (Vin) of the integration circuit (10). The switch (SW0) switches the input voltage (Vin) to the integration circuit (10) to the voltage of the polarity discrimination target (voltage Rin between the terminals) or to a reference voltage (GND). The time measuring circuit (12) measures the time until the output voltage (V10) of the integration circuit (10) reaches a set voltage. The polarity of the input voltage (Vin) to the integration circuit (10) is discriminated on the basis of the measurement result.

Description

Voltage polarity discrimination circuit and charge amount measurement circuit

The present invention relates to a circuit for determining the polarity of a target voltage. In addition, the present invention detects the remaining current of the secondary battery by detecting the consumption current and charge amount of the electronic device supplied with power by the secondary battery, and the charge current and accumulated charge amount when charging the secondary battery. Alternatively, the present invention relates to an estimation system, and particularly to a circuit that measures the charge / discharge charge amount of the secondary battery.

In recent years, portable electronic devices are driven by a rechargeable secondary battery, and many of them are equipped with an LSI having a function of displaying the remaining capacity of the secondary battery. This LSI detects the charge amount or current, adds the detected charge amount to the battery capacity after discharging during charging, and subtracts the detected charge amount from the charged battery capacity during discharging. The determination of addition and subtraction is performed by determining the polarity of the charge / discharge current whether the battery is in a charged state or a discharged state. The result of addition and subtraction is the remaining capacity (also referred to as remaining charge amount, remaining capacity, etc.), and the state of the secondary battery can be known by displaying this. Such a portion for detecting the charge amount or current is called a charge amount measurement circuit (also called a coulomb counter).

Hereinafter, a conventional example of charge / discharge current polarity discrimination and a conventional example of a charge amount measurement circuit will be described. In the charge amount measurement circuit, a detection resistor connected in series to a secondary battery and a load or a charger is used to detect the charge amount or current. This detection resistor has a resistance value as small as several tens of mΩ to several hundreds of mΩ in order to suppress the power consumption by itself and the influence on the load due to voltage drop.

The current flowing through the detection resistor depends on the consumption current and the charging current of the portable electronic device, and generally both the consumption current and the charging current are about several A. In the above case, for example, the detection resistance is 20 mΩ, the maximum charging current is −6.25 A (− sign indicates the direction of current during charging), the maximum current consumption is +6.25 A (+ sign is the current during discharging) The voltage appearing at both ends of the sensing resistor is ± 125 mV. In the conventional voltage polarity discrimination circuit and the conventional charge amount measurement circuit, a method of amplifying the input voltage by a differential amplifier circuit or integrating charges by an integration circuit using an operational amplifier circuit is used. In general, the differential amplifier circuit and the operational amplifier circuit have an input offset voltage that varies within a range of ± several mV for each product. For example, when the input offset voltage is ± 1 mV, it corresponds to ± 50 mA of the current flowing through the detection resistor. That is, in the conventional voltage polarity discrimination circuit and the conventional charge amount measurement circuit, for example, −6.25 A to −50 mA and +50 mA to +6.25 A are set as the measurement range.

FIG. 24 is a diagram showing a configuration of a conventional voltage polarity discrimination circuit 303 (see Non-Patent Document 1). The voltage polarity discrimination circuit 303 includes an integration circuit 300, an initialization circuit 331, first and

second comparison circuits

601, 602, and first and

second counters

603, 604. The integrating circuit 300 uses an operational amplifier circuit 300a designed to reduce the input offset voltage Vos. The initialization circuit 331 includes a voltage source that outputs the initial voltage Vc, and a switch SW3 that sets one end of the capacitor C1 used in the integration circuit 300 to the initial voltage Vc. The first comparison circuit 601 compares the output voltage V30 of the integration circuit 300 with the first reference voltage VH. The first counter 603 measures the time from when the switch SW3 is turned off and disconnected from the initial voltage Vc to when the output V31 of the first comparison circuit 601 is inverted. The second comparison circuit 602 compares the output voltage V30 of the integration circuit 300 with the second reference voltage VL. The second counter 604 measures the time from when the switch SW3 is turned off and disconnected from the initial voltage Vc to when the output V32 of the second comparison circuit 602 is inverted. In the integrating circuit 300, a capacitor C1 is connected in parallel between the output terminal e and the inverting input terminal c of the operational amplifier circuit 300a, and a resistor R1 is connected between the inverting input terminal c and the terminal a. The reference voltage GND is connected to the non-inverting input terminal d via the GND terminal b.

Next, the operation of the conventional voltage polarity discrimination circuit 303 configured as described above will be described with reference to FIGS. 25 (a) to 25 (d).

A charge / discharge current flows through the detection resistor Rin connected between the secondary battery and the reference voltage GND, and the input voltage Vin appears at both ends thereof. At this time, the output voltage V30 of the integrating circuit 300 is

And the slope with respect to time t is

It is represented by

25 (a) to 25 (d), in the case of the input offset voltage Vos> 0, each voltage waveform when the input voltage Vin> Vos (charge) and when the input voltage Vin <−Vos (discharge). Is shown.

First, in the charged state, when the input offset voltage Vos> 0 and the input voltage Vin> Vos, the slope of the output voltage V30 of the integrating circuit 300 is given by [Equation 2]

Thus, as shown in FIG. 25B, when the time t increases, the output voltage V30 of the integrating circuit 300 decreases. Therefore, the output voltage V30 reaches the reference voltage GND from the initial voltage Vc, and the output V32 of the second comparison circuit 602 that compares with the second reference voltage VL is inverted (FIG. 25 (d)), so that the charged state is obtained. Is determined.

Next, in the discharge state, when the input offset voltage Vos> 0 and the input voltage Vin <−Vos, the slope of the output voltage V30 of the integrating circuit 300 is expressed by [Equation 2]

Thus, as shown in FIG. 25B, when the time t increases, the output voltage V30 of the integrating circuit 300 increases. Therefore, the output voltage V30 reaches the reference voltage Vdd from the initial voltage Vc, and the output V31 of the first comparison circuit 601 that compares with the first reference voltage VH is inverted (FIG. 25 (c)), thereby causing a discharge state. Is determined.

Therefore, the input voltage Vin is

In this range, the polarity of the charge / discharge current can be correctly determined.

Also, in the case of the input offset voltage Vos <0, the same result as [Equation 5] can be obtained, so the description thereof is omitted here.

FIG. 26 is a diagram showing a configuration of a conventional charge amount measurement circuit 2 (see Patent Document 1). The conventional charge amount measurement circuit 2 includes a first switch 101, an integration circuit 200 using an operational amplifier circuit 200a designed to reduce the input offset voltage Vos, an output voltage V20 of the integration circuit 200, and a first voltage. The first comparison circuit 102 that compares the reference voltage VH, the second comparison circuit 103 that compares the output voltage V20 of the integration circuit 200 and the second reference voltage VL, the first comparison circuit 102 and the second comparison circuit A logic circuit 104 that inputs the output voltages V42 and V43 to and from the comparison circuit 103, a second switch 105 that is controlled to be turned on and off by the output voltage V44 of the logic circuit 104, and a first comparison circuit. 102 or the asynchronous counter 206 that counts the number of times the output voltage of the second comparison circuit 103 is inverted, and the first switch 101 is switched to the GND terminal b. When the time Tos until the output voltage of either the first comparison circuit 102 or the second comparison circuit 103 is inverted is measured and the first switch 101 is switched to the input terminal a, the time Tos And a register 108 that stores the measured value measured by the timer 207 and sets the measured value in the timer 207.

In the integrating circuit 200, the capacitor C and the second switch 105 are connected in parallel between the output terminal e and the inverting input terminal c of the operational amplifier circuit 200a, and between the inverting input terminal c and the input terminal a. A resistor R is connected to the non-inverting input terminal d, and a GND terminal b is connected to the non-inverting input terminal d.

Next, the operation of the conventional charge amount measuring circuit 2 configured as described above will be described. Here, in order to facilitate understanding of the operation, a case where the current is constant, that is, the case where the input voltage Vin is constant and the input offset voltage is generated such that Vos> 0 will be described as an example.

Before the charge amount at the time of charge / discharge is measured, a trimming step is provided as an information collection period for correcting the influence of the input offset voltage Vos of the operational amplifier circuit 200a.

FIGS. 27A to 27F show the operation of the trimming step. First, the first switch 101 is switched to the GND terminal b, and the input voltage is set to Vin = 0 V (FIG. 27A). At this time, the output voltage V20 of the integrating circuit 200 increases from the second reference voltage VL to the first reference voltage VH during the time Tos.

Holds (FIG. 27B). Here, when the power supply voltage is Vdd, Vdd>VH>VL> 0V.

From [Equation 6], the time Tos is

After this time Tos, the output voltage V42 of the first comparison circuit 102 is inverted as shown in FIG. As a result of the inversion of the output voltage V42, the logic circuit 104 outputs a signal for conducting the second switch 105 (FIG. 27E). When the second switch 105 is turned on, both ends of the capacitor C are short-circuited, so that the output voltage V20 of the integrating circuit 200 decreases (FIG. 27 (b)). When the output voltage V20 of the integration circuit 200 decreases and reaches the second reference voltage VL, the output voltage V43 of the second comparison circuit 103 is inverted (FIG. 27 (d)). By inversion of the output voltage V43, the logic circuit 104 outputs a signal for turning off the second switch 105 (FIG. 27E). When the second switch 105 is turned off, the output voltage V20 of the integrating circuit 200 increases again (FIG. 27 (b)). The timer 207 measures the time Tos until the output voltage V20 of the integration circuit 200 reaches the first reference voltage VH from the second reference voltage VL with the clock CLK having the cycle Tclk (FIG. 27 (f)). The measured time information Nos is stored in the register 108, and the stored time information Nos is set in the timer 207. This time information Nos represents a charge amount corresponding to the input offset voltage Vos. After the trimming step as described above, the process proceeds to the measurement step.

The measurement step has two states of charging and discharging. First, the operation during charging will be described with reference to FIGS. 28 (a) to 28 (g). Here, the condition under which the conventional charge amount measurement circuit 2 can output a correct result, that is, the operation when the input voltage Vin is larger than twice the input offset voltage Vos (Vin> 2Vos) will be described (FIG. 28A). ).

In the measurement step, the first switch 101 is switched to the input terminal a, and the input terminal a and the GND terminal b are connected to both ends of the detection resistor Rin. At this time, the output voltage V20 of the integrating circuit 200 decreases from the first reference voltage VH to the second reference voltage VL during the time Tm.

Holds (FIG. 28B).

Since the input voltage Vin is constant, the time Tm is

It is represented by Here, since the input voltage Vin is Vin> 2Vos, the time Tm is shorter than the time Tos measured in the trimming step. That is,

Holds.

After this time Tm, the output voltage V43 of the second comparison circuit 103 is inverted as shown in FIG. By inversion of the output voltage V43, the logic circuit 104 outputs a signal for conducting the second switch 105 (FIG. 28 (e)). At this time, the asynchronous counter 206 adds 1 count (FIG. 28 (g)). When the second switch 105 is turned on, both ends of the capacitor C are short-circuited, so that the output voltage V20 of the integrating circuit 200 increases (FIG. 28 (b)). When the output voltage V20 of the integration circuit 200 increases and reaches the first reference voltage VH, the output voltage V42 of the first comparison circuit 102 is inverted (FIG. 28 (c)). By inversion of the output voltage V42, the logic circuit 104 outputs a signal for turning off the second switch 105 (FIG. 28E). When the second switch 105 is turned off, the output voltage V20 of the integrating circuit 200 decreases again. When the second switch 105 reaches the second reference voltage VL (FIG. 28B), the asynchronous counter 206 adds 1 count (FIG. 28). 28 (g)). In these added values, the charge amount corresponding to the input offset voltage Vos is insufficient from the charge amount corresponding to the input voltage Vin generated at both ends of the detection resistor Rin. When the input voltage Vin continues to satisfy the condition of Vin> 2Vos, the above operation is repeated.

Timer 207 outputs an elapsed signal of time Tos stored in register 108. Each time the time Tos elapses, the asynchronous counter 206 is incremented by 1 (FIG. 28 (g)). The value to be added is a charge amount corresponding to the input offset voltage Vos measured in the trimming step, and the charge amount corresponding to the input offset voltage Vos is corrected.

Next, the operation during discharge will be described with reference to FIGS. 29 (a) to 29 (g). Here, the operation when the input voltage is Vin <0 V (FIG. 29A) will be described.

As in the case of charging, in the measurement step, the first switch 101 is switched to the input terminal a, and the input terminal a and the GND terminal b are connected to both ends of the detection resistor Rin. At this time, the output voltage V20 of the integrating circuit 200 increases from the second reference voltage VL to the first reference voltage VH during the time Tm.

Holds (FIG. 29B).

Since the input voltage Vin is constant, the time Tm is

It is represented by Here, since the input voltage Vin is Vin <0 V, the time Tm is shorter than the time Tos measured in the trimming step as in the case of charging. That is,

Holds.

After this time Tm, the output voltage V42 of the first comparison circuit 102 is inverted as shown in FIG. Due to the inversion of the output voltage V42, the logic circuit 104 outputs a signal for conducting the second switch 105 (FIG. 29E). At this time, the asynchronous counter 206 adds 1 count (FIG. 29 (g)). When the second switch 105 is turned on, both ends of the capacitor C are short-circuited, so that the output voltage V20 of the integrating circuit 200 decreases (FIG. 29 (b)). When the output voltage V20 of the integration circuit 200 decreases and reaches the second reference voltage VL, the output voltage V43 of the second comparison circuit 103 is inverted (FIG. 29 (d)). By inversion of the output voltage V43, the logic circuit 104 outputs a signal for turning off the second switch 105 (FIG. 29 (e)). When the second switch 105 becomes non-conductive, the output voltage V20 of the integrating circuit 200 increases again, and when the first reference voltage VH is reached (FIG. 29B), the asynchronous counter 206 adds 1 count ( FIG. 29 (g)). These added values include a charge amount corresponding to the input voltage Vin generated at both ends of the detection resistor Rin and a charge amount corresponding to the input offset voltage Vos. When the input voltage Vin continues to satisfy the condition of Vin <0V, the above operation is repeated.

Timer 207 outputs an elapsed signal of time Tos stored in register 108. Every time the time Tos elapses, the asynchronous counter 206 is decremented by one count (FIG. 29 (g)). The value to be subtracted is a charge amount corresponding to the input offset voltage Vos measured in the trimming step, and the charge amount corresponding to the input offset voltage Vos is corrected.

From the above, in the conventional charge amount measurement circuit 2, as in [Equation 10] and [Equation 13] for both charging and discharging,

In this case, the influence of the input offset voltage Vos is corrected.

JP 2000-241515 A

In the conventional voltage polarity discrimination circuit 303, since the unintended input offset voltage Vos exists in the operational amplifier circuit 300a used in the integration circuit 300, the state of the output voltage V30 of the integration circuit 300 depends on the condition of the input voltage Vin. There are two problems: the problem that the polarity of the charge / discharge current cannot be determined without change, and the problem that there is an input voltage range that cannot be accurately determined.

The first problem is that when the input voltage Vin and the input offset voltage Vos are equal, in [Equation 1], the time from the initial voltage Vc to the second reference voltage VL, and the initial voltage Vc to the first reference voltage. When the time to the voltage VH is represented by Tc,

Accordingly, there is a possibility that none of the output voltages V31 and V32 of the first and

second comparison circuits

601 and 602 is inverted and the polarity of the charge / discharge current cannot be determined.

The second problem is that the polarity of the charge / discharge current may be erroneously determined depending on the conditions of the input voltage Vin and the input offset voltage Vos.

Here, the case of the input offset voltage Vos> 0 is compared with the determination result of the conventional voltage polarity determination circuit 303 by examining the slope of the output voltage V30 of the integration circuit 300 for each voltage range of the input voltage Vin.

When Vos> 0, the output voltage V30 of the integrating circuit 300 is

And the slope is

It is represented by

Vin> Vos, that is, when charging,

Thus, the discrimination result of the conventional voltage polarity discrimination circuit 303 indicates charging and is a correct result.

0 <Vin <Vos, that is, when charging

Thus, the discrimination result of the conventional voltage polarity discrimination circuit 303 indicates discharge, which is an incorrect result.

When Vin <0, that is, when discharging,

Thus, the discrimination result of the conventional voltage polarity discrimination circuit 303 indicates a discharge and is a correct result.

Similarly, when Vos <0, the output voltage V30 of the integrating circuit 300 is

And the slope is

It is represented by

Vin> 0, that is, when charging,

-Vos <Vin <0, ie, when discharging

Thus, the discrimination result of the conventional voltage polarity discrimination circuit 303 indicates charging and is an incorrect result.

When Vin <−Vos, that is, when discharging,

30 (a) to 30 (d) show the conventional voltage polarities when the input offset voltage Vos> 0 and the input voltage Vin is in a charged state of 0 <Vin <Vos and a discharged state of Vin <0. 7 shows an operation example of a determination circuit 303. The output voltage V30 of the integration circuit 300 reaches the first reference voltage VH in both the charged state and the discharged state, and only one output V31 of the first and

second comparison circuits

601 and 602 is inverted. And misjudgment in the state of charge.

FIG. 31 is a diagram showing the correctness of the discrimination result of the conventional voltage polarity discrimination circuit 303 with respect to the input offset voltage Vos and the input voltage range of the input voltage Vin. As is clear from FIG. 31, the conventional voltage polarity discrimination circuit 303 has a range in which the input voltage range is erroneously discriminated.

As described above, the voltage polarity discrimination circuit 303 according to the related art has one of the output voltages V31 and V32 of the first and

second comparison circuits

601 and 602 depending on the input offset voltage Vos of the operational amplifier circuit 300a used in the integration circuit 300. In some cases, the polarity of the charging / discharging current cannot be discriminated, and the polarity of the charging / discharging current is misjudged in the input voltage range.

In the conventional charge amount measurement circuit 2, the trimming step time becomes long when the input offset voltage Vos is close to 0 V, and there is a range in the input voltage range that cannot be measured due to an input condition called a dead zone. There was a problem.

The first problem is that, when the input offset voltage Vos is close to 0 V in the trimming step,

Thus, both the first and

second comparison circuits

102 and 103 can take a long time until the output voltage is inverted. That is, since the trimming step time is long, it is not suitable for mass production of products. Further, if the trimming step is lengthened, the timer 207 for measuring information for a long time and the register 108 for storing the information each require a large number of bits, so that the circuit scale increases and the area increases accordingly. Also grows.

The second problem is that the conventional charge measurement circuit 2 has a dead zone. In the measurement step, when the input voltage Vin is within the dead band range, the measurement time becomes longer than the time Tos measured in the trimming step, the output voltage V20 of the integration circuit 200 does not increase, and the asynchronous counter 206 is not added. The charge / discharge charge amount may not be measured.

32A and 32B are diagrams showing the distribution of the input offset voltage Vos and the range of the input voltage Vin of the amplification arithmetic circuit 200a of the integrating circuit 200 provided in the conventional charge amount measuring circuit 2. FIG. is there. The input offset voltage Vos of the operational amplifier circuit 200a cannot be set to 0 V for all products in mass production, and variations always occur (FIG. 32 (a)). For example, when the input offset voltage of a certain product is + Vos, the time until the output voltage V20 of the integrating circuit 200 reaches the first reference voltage VH from the second reference voltage VL in the conventional charge amount measurement circuit 2 Tm is expressed by the above [Equation 9].

Since Vin <0V and Vin> 2Vos, Tm <Tos, the conventional charge amount measurement circuit 2 can correct the influence of the input offset voltage Vos.

However, when the input voltage Vin is in the range of 0V ≦ Vin ≦ 2Vos,

It becomes. Since the conventional charge amount measurement circuit 2 does not have a correction function for the influence of the input offset voltage Vos under this input condition, it cannot measure the correct charge amount. Similarly, when the input offset voltage of the product including the conventional charge amount measurement circuit 2 is −Vos, the conventional charge amount measurement circuit 2 determines the correct charge amount when −2 Vos ≦ Vin <0V. It cannot be measured.

Accordingly, when the variation range of the input offset voltage Vos when the product is mass-produced is −Vos to + Vos, there is a range in which the charge amount cannot be measured correctly such as −2 Vos to +2 Vos, that is, a dead zone (FIG. 32 (b)). )). For example, if the input offset voltage is ± 1.5 mV, this corresponds to ± 150 mA of the current flowing through the detection resistor Rin. The conventional charge amount measurement circuit 2 has a measurement range of −2.0 A to −300 mA and +300 mA to +2.0 A, and has a dead zone of −300 mA to +300 mA.

Considering the case where the standby current of a portable electronic device having a secondary battery capacity of 2400 mAh is 15 mA, the charge amount (electric amount) of 2400 mAh is consumed in about one week, and the actual remaining capacity becomes zero. Since the conventional charge amount measuring circuit 2 has a dead zone, the remaining capacity of 2400 mAh is displayed.

As described above, when the input offset voltage Vos of the operational amplifier circuit 200a used in the integrating circuit 200 is close to 0V, the conventional charge amount measuring circuit 2 takes a trimming step, and the timer 207 that measures long-time information. In addition, the circuit scale of each of the registers 108 for storing the information increases, and the area increases accordingly. Further, there is a problem that there is an input voltage range that has a dead zone and cannot be measured correctly.

An object of the present invention is to provide a voltage polarity determination circuit that can accurately determine the polarity of a target voltage.

Another object of the present invention is to make it possible to measure the charge amount or the current value without having a dead zone in the entire measurement range of the input voltage.

The voltage polarity discrimination circuit of the present invention includes an integration circuit, a switch, and a time measurement circuit. The integration circuit is configured using an operational amplifier circuit having an input offset voltage that is greater than the maximum value or less than the minimum value of the input voltage of the integration circuit. The switch switches the input voltage to the integration circuit to a voltage for polarity discrimination or a reference voltage. The time measurement circuit measures the time until the output voltage of the integration circuit reaches a set voltage, and determines the polarity of the input voltage to the integration circuit based on the measurement result.

In the voltage polarity discrimination circuit, the input offset voltage of the operational amplifier circuit used in the integration circuit is set larger than the absolute value of the input voltage of the integration circuit, so the input voltage range is a continuous range smaller than the input offset voltage. In the range, it is possible to accurately determine the polarity of the input voltage, that is, the polarity of the voltage to be subjected to polarity determination. Further, since the input voltage and the input offset voltage are not equal, it is possible to always determine the polarity of the input voltage, that is, the polarity of the voltage to be subjected to polarity determination.

Preferably, the time measurement circuit includes a first comparison circuit, a second comparison circuit, a logic circuit, a counter, and a determination circuit. The first comparison circuit compares the output voltage of the integration circuit with the first reference voltage and outputs the comparison result. The second comparison circuit compares the output voltage of the integration circuit with a second reference voltage and outputs the comparison result. The logic circuit outputs a voltage that is set and reset in response to inversion of the output voltage of the first comparison circuit and inversion of the output voltage of the second comparison circuit. The counter measures the output of the logic circuit up to a set value. The determination circuit measures a time from when the input voltage to the integration circuit is switched by the switch until the measurement value by the counter reaches the set value, and based on the measurement result, inputs to the integration circuit Determine the polarity of the voltage. The voltage polarity determination circuit further includes an initialization circuit that initializes the output voltage of the integration circuit in response to the output of the logic circuit.

Furthermore, even in a system that measures time by measuring the number of clocks with a counter, the polarity can be accurately determined in the entire input voltage range.

Preferably, the voltage of the polarity discrimination target is a voltage across a detection resistor connected in series to a predetermined power source. In this way, the polarity of the current flowing through the detection resistor can be determined.

The charge amount measurement circuit of the present invention includes a voltage charge conversion circuit for converting an input voltage into a pulse corresponding to the charge amount, a charge measurement circuit and a discharge measurement circuit for counting output pulses of the voltage charge conversion circuit, In a charge amount measurement circuit having a storage circuit that holds a count value of the charge measurement circuit when the input voltage is 0 V and sets the count value in the charge measurement circuit, the count of the charge measurement circuit overflows Is configured to subtract the count value of the discharge measurement circuit when the count reaches the overflow, subtract the count value of the charge measurement circuit when the count of the discharge measurement circuit reaches an overflow, and the voltage charge conversion circuit, And an integrating circuit using an operational amplifier circuit having an input offset voltage larger than the maximum value of the input voltage or smaller than the minimum value. It is obtained by and.

Another charge amount measurement circuit of the present invention includes a voltage charge conversion circuit that converts an input voltage into a pulse corresponding to a charge amount, a charge measurement circuit that counts output pulses of the voltage charge conversion circuit, and the input voltage. A time measurement circuit that measures the time until the charge measurement circuit overflows when the voltage is 0 V, and indicates the passage of the measurement time when measuring the charge amount, and each of the charge measurement circuit and the time measurement circuit A charge integrating circuit that counts the number of clocks corresponding to an overflow time difference, a storage circuit that holds a count value of the time measurement circuit when the input voltage is 0 V, and sets the count value in the time measurement circuit; The voltage charge conversion circuit has an input offset voltage that is greater than the maximum value of the input voltage or less than the minimum value. It is obtained by a further comprising an integrating circuit including an operational amplifier circuit that.

According to the present invention, since the input offset voltage of the operational amplifier circuit used in the integrating circuit is made larger than the absolute value of the input voltage, the charge amount during charging / discharging can be reduced in a continuous input voltage range smaller than the input offset voltage. It can be measured.

According to the voltage polarity discriminating circuit of the present invention, the polarity of the input voltage, that is, the polarity of the voltage to be polarity discriminated can be accurately discriminated in the entire input voltage range.

According to the charge amount measurement circuit of the present invention, the charge amount or the current value can be measured without having a dead zone in the entire measurement range of the input voltage.

It is a figure which shows the voltage polarity discrimination circuit by 1st Embodiment. (A) is an input voltage waveform diagram to the voltage polarity discrimination circuit, (b) is an output voltage waveform diagram of the integration circuit, and (c) is an output voltage waveform diagram of the comparison circuit. FIG. 2 is a block diagram illustrating an internal configuration example of a determination circuit in FIG. 1. It is a figure which shows the voltage polarity discrimination circuit by 2nd Embodiment. (A) is an input voltage waveform diagram to the voltage polarity discrimination circuit, (b) is an output voltage waveform diagram of the integration circuit, (c) and (d) are output voltage waveform diagrams of the comparison circuit, and (e) is a logic circuit diagram. The output voltage waveform diagram, (f) is the output voltage waveform diagram of the counter, and (g) is the clock waveform diagram. FIG. 5 is a block diagram illustrating an internal configuration example of a determination circuit in FIG. 4. It is a block diagram which shows the structure of the electric charge amount measurement circuit which concerns on the 3rd Embodiment of this invention. FIG. 8 is a waveform diagram showing an operation at the trimming step of the charge amount measurement circuit of FIG. 7, (a) is an input voltage to the charge amount measurement circuit, (b) is an output voltage of the integration circuit, (c). Is the output voltage of the first comparison circuit, (d) is the output voltage of the second comparison circuit, (e) is the output voltage of the logic circuit, (f) is the state of the charge counter, (g) is (H) is a diagram showing the state of the measurement counter. FIG. 8 is a waveform diagram showing an operation at the time of charging of the charge amount measurement circuit of FIG. 7, (a) is an input voltage to the charge amount measurement circuit, (b) is an output voltage of the integration circuit, and (c) is an output voltage. (D) is a charge counter state, (e) is a clock voltage, (f) is a measurement counter state, and (g) is a charge counter state. . FIG. 8 is a waveform diagram showing an operation of the charge amount measurement circuit of FIG. 7 during discharging, where (a) shows the input voltage to the charge amount measurement circuit, (b) shows the output voltage of the integration circuit, and (c) shows (D) is the state of the charge counter, (e) is the state of the discharge counter, (f) is the state of the measurement counter, and (g) is the voltage of the clock. . It is the figure which represented the time in a measurement counter and an electric charge counter with a number line, (a) is the time relationship in a trimming step, (b) is the time relationship at the time of charge, (c) is the time at the time of discharge. It is a figure which shows each time relationship. It is a block diagram which shows the structure of the electric charge amount measurement circuit which concerns on the 4th Embodiment of this invention. FIG. 13 is a waveform diagram showing an operation at the trimming step of the charge amount measurement circuit of FIG. 12, where (a) shows an input voltage to the charge amount measurement circuit, (b) shows an output voltage of the integration circuit, and (c). Is the output voltage of the first comparison circuit, (d) is the output voltage of the second comparison circuit, (e) is the output voltage of the logic circuit, (f) is the state of the charge counter, (g) is (H) is a diagram showing the state of the measurement counter. FIG. 13 is a waveform diagram showing an operation at the time of charging of the charge amount measurement circuit of FIG. 12, where (a) shows an input voltage to the charge amount measurement circuit, (b) shows an output voltage of the integration circuit, and (c) shows The output voltage of the logic circuit, (d) the state of the charge counter, (e) the overflow signal of the charge counter, (f) the state of the measurement counter, (g) the overflow signal of the measurement counter, ( h) is an enable signal from the start / stop control circuit, (i) is a clock voltage, and (j) is a diagram showing the state of the integration counter. FIG. 13 is a waveform diagram showing the operation of the charge amount measurement circuit of FIG. 12 during discharging, where (a) shows the input voltage to the charge amount measurement circuit, (b) shows the output voltage of the integration circuit, and (c) shows the operation. The output voltage of the logic circuit, (d) the state of the charge counter, (e) the overflow signal of the charge counter, (f) the state of the measurement counter, (g) the overflow signal of the measurement counter, ( h) is an enable signal from the start / stop control circuit, (i) is a clock voltage, and (j) is a diagram showing the state of the integration counter. It is the figure which represented the time in a measurement counter, an electric charge counter, and an integration counter with a number line, (a) is a time relation in a trimming step, (b) is a time relation at the time of charge, (c) is a discharge. It is a figure which shows the time relationship at the time of, respectively. (A) And (b) is a figure which shows distribution of the input offset voltage and input voltage range of the integration circuit in FIG.8 and FIG.12. It is a figure which shows the example of application of embodiment of this invention. FIG. 3 is a circuit diagram of an operational amplifier circuit in which an input offset voltage is set by making a difference in the size of a pair of transistors in a differential input stage according to an embodiment of the present invention. FIG. 4 is a circuit diagram of an operational amplifier circuit in which an input offset voltage is set with a difference in the amount of current of a current source according to an embodiment of the present invention. FIG. 3 is a circuit diagram of an operational amplifier circuit in which an input offset voltage is set by making a difference between resistance values of offset resistors connected to a pair of transistors in a differential input stage according to an embodiment of the present invention. FIG. 4 is a circuit diagram of an operational amplifier circuit in which an input offset voltage is set by making a difference between resistance values of offset resistors connected to a current source according to an embodiment of the present invention. It is a circuit diagram of the operational amplifier circuit which set the input offset voltage by the bias voltage which concerns on embodiment of this invention. It is a figure which shows the conventional voltage polarity discrimination circuit. It is a voltage waveform diagram when the input voltage to the conventional voltage polarity discrimination circuit is larger than the input offset voltage, (a) is an input voltage waveform diagram to the voltage polarity discrimination circuit, (b) is an output voltage waveform diagram of the integration circuit , (C) is an output voltage waveform diagram of the comparison circuit, and (d) is an output voltage waveform diagram of the comparison circuit. It is a block diagram which shows the structure of the conventional charge amount measurement circuit. It is a wave form diagram which shows the operation | movement at the time of the trimming step of the electric charge measurement circuit of FIG. 26, (a) is the input voltage to the said electric charge measurement circuit, (b) is the output voltage of an integration circuit, (c). FIG. 4 is a diagram showing an output voltage of the first comparison circuit, (d) is an output voltage of the second comparison circuit, (e) is an output voltage of the logic circuit, and (f) is a voltage of the clock. It is a wave form diagram which shows the operation | movement at the time of charge of the charge amount measurement circuit of FIG. 26, (a) is the input voltage to the said charge amount measurement circuit, (b) is the output voltage of an integration circuit, (c) is The output voltage of the first comparison circuit, (d) the output voltage of the second comparison circuit, (e) the output voltage of the logic circuit, (f) the clock voltage, and (g) the asynchronous counter. It is a figure which shows each of these states. FIG. 27 is a waveform diagram showing an operation during discharging of the charge amount measurement circuit of FIG. 26, where (a) shows the input voltage to the charge amount measurement circuit, (b) shows the output voltage of the integration circuit, and (c) shows The output voltage of the first comparison circuit, (d) the output voltage of the second comparison circuit, (e) the output voltage of the logic circuit, (f) the clock voltage, and (g) the asynchronous counter. It is a figure which shows each of these states. It is a voltage waveform diagram when the input voltage to the conventional voltage polarity discrimination circuit is smaller than the input offset voltage, (a) is the input voltage waveform diagram to the voltage polarity discrimination circuit, (b) is the output voltage waveform diagram of the integration circuit , (C) is an output voltage waveform diagram of the comparison circuit, and (d) is an output voltage waveform diagram of the comparison circuit. It is a figure which shows the right / wrong of the polarity discrimination | determination result of the charging / discharging current with respect to the input offset voltage of the conventional voltage polarity discrimination | determination circuit and the input range of input voltage. (A) And (b) is a figure which shows distribution of the input offset voltage and input voltage range of the integration circuit in FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<< First Embodiment >>
FIG. 1 is a configuration diagram of a voltage polarity determination circuit 301 according to the first embodiment. The voltage polarity determination circuit 301 includes a switch SW 0, an integration circuit 100, an initialization circuit 311, and a time measurement circuit 312.

The integration circuit 100 includes an operational amplifier circuit 100a, a capacitor C1, and a resistor R1. The capacitor C1 is connected between the output terminal e and the inverting input terminal c of the operational amplifier circuit 100a. The resistor R1 is connected between the inverting input terminal c of the operational amplifier circuit 100a and the switch SW0. The non-inverting input terminal d of the operational amplifier circuit 100a is connected to the reference voltage GND through the GND terminal b. The operational amplifier circuit 100a has an input offset voltage Vosa whose level is outside the input voltage range. Here, “outside the input voltage range” is a region that is larger than the maximum value or smaller than the minimum value of the input voltage Vin of the integration circuit 100. The input offset voltage Vosa is preferably set at a level outside the input voltage range of the input voltage Vin, but may be set in a region close to the maximum value or the minimum value where the frequency of occurrence of the input voltage Vin is low.

The switch SW0 switches the connection destination of the inverting input terminal c of the operational amplifier circuit 100a to the input terminal a or the GND terminal b. The input terminal a is connected to a node between the negative electrode of the secondary battery and the detection resistor Rin.

The initialization circuit 311 includes a switch SW1. The switch SW1 is connected in parallel with the capacitor C1 between the output terminal e and the inverting input terminal c of the operational amplifier circuit 100a.

The time measurement circuit 312 includes a comparison circuit 401 and a determination circuit 402. The comparison circuit 401 compares the output voltage V10 of the integration circuit 100 with the reference voltage VH and outputs the result. The determination circuit 402 measures a time (Tdis or Tch) from when the connection destination of the inverting input terminal c is switched to the input terminal a or the GND terminal b by the switch SW0 until the output voltage V11 of the comparison circuit 401 is inverted. .

Next, the operation of the voltage polarity discrimination circuit 301 configured as described above will be described with reference to FIGS. 2 (a) to 2 (c). Here, in order to simplify the understanding of the operation, a case of a constant current, that is, a case where the input voltage Vin is constant and a case where the input offset voltage Vosa> 0 will be described as an example.

First, the switch SW0 is switched to the reference voltage GND (= 0V) side, the input voltage Vin = 0V as shown in FIG. 2A, and the reference time for charge / discharge determination is measured. At this time, the output voltage V10 of the integrating circuit 100 reaches the reference voltage VH from the reference voltage GND. If this time is Tosa,

Holds. From [Equation 28], the time Tosa is

When the time Tosa elapses, the output voltage V11 of the comparison circuit 401 is inverted as shown in FIG. This time Tosa is used as a reference time for determining the polarity of charge / discharge.

Next, switch SW0 is switched to the input terminal a side, and the time corresponding to the state of charge or discharge is measured. At this time, an input voltage Vin having a different polarity is applied depending on charging and discharging of the secondary battery.

When the secondary battery is charged, the current flows into the positive electrode of the battery and flows out from the negative electrode of the battery through the reference voltage GND (= 0 V), so that the input voltage Vin> 0 V (charge in FIG. 2A). The output voltage V10 of the integrating circuit 100 at this time is set so that the time from the reference voltage GND to the reference voltage VH is Tch (charge in FIG. 2B), and the input offset voltage Vosa is larger than the input voltage range (Vosa> Vin). Therefore, for the input voltage range (0V <Vin <Vosa) during charging,

Holds. From [Equation 30], the time Tch is

When this time Tch elapses, the output voltage V11 of the comparison circuit 401 is inverted (charging in FIG. 2 (c)). At this time, the time Tch is longer than the time Tosa.

When the secondary battery is discharged, the current flows from the positive electrode of the battery through the reference voltage GND (= 0V) to the negative electrode of the battery, so that the input voltage Vin <0V (discharge in FIG. 2 (a)). The output voltage V10 of the integration circuit 100 at this time is such that the time from the reference voltage GND to the reference voltage VH is Tdis (discharge in FIG. 2B), and the input offset voltage Vosa is larger than the input voltage range (Vosa> Vin). Therefore, for the input voltage range (−Vosa <Vin <0V) during discharge,

Holds. From [Equation 32], the time Tdis is

When the time Tdis elapses, the output voltage V11 of the comparison circuit 401 is inverted (discharge in FIG. 2C). At this time, the time Tdis is shorter than the time Tosa.

Therefore, in the input voltage range of the input voltage Vin (−Vosa <Vin <Vosa),

The relationship holds. Therefore, it is possible to determine the state of charge / discharge by measuring the time Tosa first or periodically or irregularly, and then measuring the time Tdis or Tch and comparing it with the time Tosa. .

This comparison is performed in the determination circuit 402 by holding the measurement results of the respective times Tosa, Tdis, and Tch in a storage circuit such as a register and performing an operation such as subtraction on the time Tosa. For example, as shown in FIG. 3, the determination circuit 402 is a timer that measures the time from when the input voltage to the integration circuit 100 is switched by the switch SW0 until the output voltage V11 of the comparison circuit 401 is inverted using the clock CLK. 701, a storage circuit 702 that stores the measurement result of the timer 701, and an arithmetic circuit 703 that compares the measurement result. The determination circuit 402 may be processed by a down counter in which the measurement result of the time Tosa is set. This process may be performed by a microcomputer outside the voltage polarity determination circuit 301 or a dedicated arithmetic circuit.

As described above, according to the present embodiment, since the input offset voltage Vosa given to the operational amplifier circuit 100a used in the integrating circuit 100 is made larger than the input voltage Vin, the input voltage Vin is a continuous value of −Vosa <Vin <Vosa. The polarity of the charge / discharge current can be accurately determined within the range. Further, since the input voltage value Vin and the input offset voltage value Vosa satisfy the condition of Vin <Vosa and an appropriate difference is not established, the state of Vin = Vosa is not obtained. Is inverted, and the polarity of the charge / discharge current can be determined.

In the present embodiment, an example in which the polarity of the charge / discharge current is determined by comparing the time to reach the reference voltage VH of the output voltage V10 of the integration circuit 100 with respect to the input voltage Vin is shown, but the reference time is set. The level of the output voltage V10 of the integrating circuit 100 that has reached that time is measured and compared with the level of the output voltage V10 of the integrating circuit 100 when the input voltage Vin = 0V. An effect is obtained.

<< Second Embodiment >>
FIG. 4 is a configuration diagram of the voltage polarity determination circuit 302 according to the second embodiment. The voltage polarity determination circuit 302 includes a switch SW0, an integration circuit 100, an initialization circuit 321 and a time measurement circuit 322.

The integration circuit 100 includes an operational amplifier circuit 100a, a capacitor C1, and a resistor R1. The capacitor C1 is connected between the output terminal e and the inverting input terminal c of the operational amplifier circuit 100a. The resistor R1 is connected between the inverting input terminal c of the operational amplifier circuit 100a and the switch SW0. The non-inverting input terminal d of the operational amplifier circuit 100a is connected to the reference voltage GND through the GND terminal b. The operational amplifier circuit 100a has an input offset voltage Vosa whose level is outside the input voltage range. Here, as in the first embodiment, “outside of the input voltage range” is a region larger than the maximum value or smaller than the minimum value of the input voltage Vin of the integration circuit 100. The input offset voltage Vosa is preferably set to a level outside the input voltage range of the input voltage Vin, but may be set to a region close to the maximum value or the minimum value where the frequency of occurrence of the input voltage Vin is low.

The time measurement circuit 322 includes first and

second comparison circuits

401 and 502, a logic circuit 503, a counter 504, and a determination circuit 505. The first comparison circuit 401 compares the output voltage V10 of the integration circuit 100 with the first reference voltage VH and outputs the result. The second comparison circuit 502 compares the output voltage V10 of the integration circuit 100 with the second reference voltage VL and outputs the result. The logic circuit 503 receives the output voltage V11 of the first comparison circuit 401 and the output voltage V22 of the second comparison circuit 502, and outputs a voltage V23. The output voltage V23 of the logic circuit 503 is reset in response to the fall of the voltage V11 (Vdd → 0) (V23 = 0V), and is set in response to the fall of the voltage V22 (Vdd → 0) (V23). = Vdd). The counter 504 measures the output voltage V23 of the logic circuit 503 up to a set value. The determination circuit 505 measures the time from when the connection destination of the inverting input terminal c is switched to the input terminal a or the GND terminal b by the switch SW0 until the measurement value of the counter 504 reaches the set value, and the polarity of the charge / discharge current Is determined. V24 is a measurement value of the counter 504, and CLK is a clock input to the determination circuit 505.

The initialization circuit 321 includes a switch SW2. The switch SW2 is connected in parallel with the capacitor C1 between the output terminal e and the inverting input terminal c of the operational amplifier circuit 100a. The switch SW2 switches between a conductive state and a nonconductive state in response to the output voltage V23 of the logic circuit 503.

Next, the operation of the voltage polarity determination circuit 302 configured as described above will be described with reference to FIGS. 5 (a) to 5 (g). Here, in order to easily understand the operation, the case where the current is constant, that is, the case where the input voltage Vin is a constant value and the input offset voltage Vosa> 0 will be described as an example.

First, the switch SW0 is switched to the reference voltage GND (= 0V) side, the input voltage Vin = 0V as shown in FIG. 5A, and the reference time for charge / discharge determination is measured. At this time, the output voltage V10 of the integrating circuit 100 reaches the first reference voltage VH from the second reference voltage VL as shown in FIG. If this time is Tosa,

Holds. From [Equation 35], the time Tosa is

When the time Tosa elapses, the output voltage V11 of the first comparison circuit 401 is inverted as shown in FIG. 5C (Vdd → 0). In response to this, the output voltage V23 of the logic circuit 503 is reset as shown in FIG. 5E (V23 = 0V), and the switch SW2 of the initialization circuit 321 becomes conductive. As a result, the capacitor C1 is discharged, and the output voltage V10 of the integrating circuit 100 reaches the second reference voltage VL (FIG. 5B). If the time to reach the second reference voltage VL from the first reference voltage VH is Trst,

Holds. From [Equation 37], the time Trst is

When the time Trst elapses, the output voltage V22 of the second comparison circuit 502 is inverted as shown in FIG. 5D (Vdd → 0). In response to this, the output voltage V23 of the logic circuit 503 is set as shown in FIG. 5E (V23 = Vdd), and the switch SW2 of the initialization circuit 321 is turned off. As a result, the output voltage V10 of the integration circuit 100 reaches the first reference voltage VH from the second reference voltage VL again. Thereafter, the process is repeated up to the set number of times.

The time of one cycle of the output voltage V10 of the integrating circuit 100 is

Therefore, if the set number of times is 2 N times, the time Tosn until the set number of times is (FIG. 5 (f)).

It becomes.

In the case of a system in which the time is measured by measuring the number of clocks CLK with a counter, a time error of a maximum of one clock due to a timing shift from the clock CLK is included (FIG. 5 (g)). That is,

But

When the set number of times N is set so as to satisfy, the influence of one cycle Tclk of the clock CLK is reduced, and the accuracy can be improved. This time Tosn is used as a reference time for discriminating the polarity of charge / discharge.

Next, when the switch SW0 is switched to the input terminal a side, the input voltage Vin having a different polarity is applied depending on the charging and discharging of the secondary battery.

In these charge and discharge cases, the circuit operation is the same as in FIGS. 5 (a) to 5 (g), and only the measurement time differs between charge and discharge. Is omitted.

When the time when the secondary battery is discharged is Tdisn, and the time when the secondary battery is charged is Tchn, Tosn in FIG. 5 (f) is set to Tdisn when discharging, and FIG. 5 (f) is set when charging. Tosn is replaced with Tchn.

Therefore, if an error due to the clock CLK is included,

In the case of charging,

And

The relationship holds.

Therefore, it is possible to accurately determine the charge / discharge state by measuring the time Tosn first, or periodically or irregularly, and then measuring the time Tdisn or Tchn and comparing it with the time Tosn. It becomes.

This comparison is performed in the determination circuit 505 by holding the measurement results of the respective times Tosn, Tdisn, Tchn in a storage circuit such as a register and performing an operation such as subtraction on the time Tosn. For example, as shown in FIG. 6, the determination circuit 505 measures the time from when the input voltage to the integration circuit 100 is switched by the switch SW0 until the measurement value V24 by the counter 504 reaches the set value using the clock CLK. Timer 801, a storage circuit 802 for storing the measurement result of the timer 801, and an arithmetic circuit 803 for comparing the measurement result. The determination circuit 505 may be processed by a down counter in which the measurement result of the time Tosn is set. This process may be performed by a microcomputer outside the voltage polarity determination circuit 302 or a dedicated arithmetic circuit.

As described above, according to the present embodiment, even in a system that measures time by measuring the number of clocks with a counter, it is possible to accurately determine the polarity with respect to the entire range of charge / discharge current. In addition, since the input voltage value Vin and the input offset voltage value Vosa satisfy the condition of Vin <Vosa, and an appropriate difference is not made, the state of Vin = Vosa is not obtained. The output voltages V11 and V22 of the

circuits

401 and 502 are inverted, and the polarity of the charge / discharge current can be determined.

<< Third Embodiment >>
FIG. 7 is a configuration diagram of the charge amount measuring circuit 1 according to the third embodiment of the present invention. The charge amount measurement circuit 1 counts the first switch 101, the voltage charge conversion circuit 10 that converts the input voltage into a pulse corresponding to the charge amount, and the output pulses of the voltage charge conversion circuit 10. Charge measurement circuit 30 that subtracts the count value, discharge measurement circuit 20 that counts the output pulse of the voltage charge conversion circuit 10 and subtracts the count value of the charge measurement circuit 30, and a charge measurement circuit when the input voltage Vin is 0V The storage circuit 50 holds the count value of 30 and sets the count value in the charge measurement circuit 30, and the voltage charge conversion circuit 10 is larger than the maximum value or smaller than the minimum value of the input voltage Vin. An integrating circuit 100 using an operational amplifier circuit 100a having an input offset voltage Vosa is provided.

The voltage-to-charge converter circuit 10 includes an integrating circuit 100 configured using an operational amplifier circuit 100a having an input offset voltage Vosa, and a first that switches an input voltage Vin to the integrating circuit 100 to an input terminal a or a GND terminal b. , The first comparison circuit 102 that compares the output voltage V10 of the integration circuit 100 and the first reference voltage VH and outputs the comparison result, the output voltage V10 of the integration circuit 100 and the second reference voltage Set in response to the second comparison circuit 103 that compares VL and outputs the comparison result, and the inversion of the output voltage V12 of the first comparison circuit 102 or the inversion of the output voltage V13 of the second comparison circuit 103 , A logic circuit 104 that outputs a reset voltage, and a second switch 105 that is controlled to be turned on and off by the output voltage V14 of the logic circuit 104. It is constructed from.

When the first switch 101 is switched to the GND terminal b, that is, in the trimming step, the charge measuring circuit 30 measures the time Tosa until the charge counter 106 reaches an overflow (O / F) with the clock CLK. In addition, when the first switch 101 is connected to the input terminal a, that is, when the measurement counter 107 indicating the passage of the measurement time based on the clock CLK and the measurement counter 107 overflow in the measurement step. A charge counter 109 that adds 1 count and decrements 1 count when the charge counter 106 overflows.

The discharge measurement circuit 20 counts the number of times the output voltage of the first comparison circuit 102 or the second comparison circuit 103 is inverted, and adds 1 count when the charge counter 106 overflows. And a discharge counter 110 that subtracts one count when the battery overflows.

In the integrating circuit 100, a capacitor C and a second switch 105 are connected in parallel between the output terminal e and the inverting input terminal c of the operational amplifier circuit 100a, and between the inverting input terminal c and the input terminal a. A resistor R is connected to the non-inverting input terminal d, and a GND terminal b is connected to the non-inverting input terminal d. The operational amplifier circuit 100a has an input offset voltage Vosa whose level is outside the input voltage range. Here, “outside the input voltage range” is a region that is larger than the maximum value or smaller than the minimum value of the input voltage Vin of the integration circuit 100. The input offset voltage Vosa is preferably set at a level outside the input voltage range of the input voltage Vin, but may be set in a region close to the maximum value or the minimum value where the frequency of occurrence of the input voltage Vin is low.

Next, the operation of the charge amount measuring circuit 1 according to the embodiment of the present invention configured as described above will be described. Here, in order to facilitate understanding of the operation, a case where the current is constant, that is, the case where the input voltage Vin is constant and the input offset voltage is set such that Vosa> 0 will be described as an example.

Before the charge amount at the time of charging / discharging is measured, a trimming step is provided as an information collection period for correcting the influence of the input offset voltage Vosa set in the operational amplifier circuit 100a.

FIGS. 8A to 8H show the operation of the trimming step when the set input offset voltage Vosa> 0V. First, the first switch 101 is switched to the GND terminal b, and the input voltage is set to Vin = 0 V (FIG. 8A). At this time, the output voltage V10 of the integrating circuit 100 increases from the second reference voltage VL to the first reference voltage VH during the time Tosa.

Holds (FIG. 8B).

From [Equation 46], the time Tosa is

After this time Tosa, the output voltage V10 of the integration circuit 100 reaches the first reference voltage VH, and the output voltage V12 of the first comparison circuit 102 is inverted as shown in FIG. By inversion of the output voltage V12, the logic circuit 104 outputs a signal for conducting the second switch 105 (FIG. 8E). When the second switch 105 is turned on, both ends of the capacitor C are short-circuited, so that the output voltage V10 of the integrating circuit 100 decreases (FIG. 8B). When the output voltage V10 of the integration circuit 100 decreases and reaches the second reference voltage VL, the output voltage V13 of the second comparison circuit 103 is inverted (FIG. 8 (d)). By inversion of the output voltage V13, the logic circuit 104 outputs a signal for turning off the second switch 105 (FIG. 8E). When the second switch 105 becomes non-conductive, the output voltage V10 of the integration circuit 100 increases again (FIG. 8B). The measurement counter 107 determines the time Tosan (FIG. 8 (f)) until the number of inversions of the output voltage V14 of the logic circuit 104 reaches the N count of the set value of the charge counter 106, and the clock CLK (FIG. 8). (G)) to measure (FIG. 8 (h)). The time information Nosa is stored in the register 108, and the stored time information Nosa is set in the measurement counter 107. This time information Nosa represents a charge amount corresponding to the set input offset voltage Vosa.

When the second switch 105 is turned on and the output voltage V10 of the integration circuit 100 changes from the first reference voltage VH to the second reference voltage VL, the second switch 105 has a resistance, so that the time Trst (Refer to FIG. 27 (b)) occurs, but since its value is generally small, it is ignored here. If the resistance when the second switch 105 is conductive is large, the time Trst may be measured and corrected.

After the above trimming step, move to the measurement step. The measurement step has two states of charging and discharging. First, the operation at the time of charging will be described with reference to FIGS. 9 (a) to 9 (g). Here, the operation in the case of 0V <Vin <Vosa (FIG. 9A) will be described.

In the measurement step, the first switch 101 is switched to the input terminal a, and the input terminal a and the GND terminal b are connected to both ends of the detection resistor Rin. At this time, the output voltage V10 of the integration circuit 100 increases from the second reference voltage VL to the first reference voltage VH during the time Tm.

Holds (FIG. 9B).

Since the input voltage Vin is constant, the time Tm is

It is represented by Here, since the input voltage Vin is 0V <Vin <Vosa, the time Tm is longer than the time Tosa measured in the trimming step. That is,

Holds.

After this time Tm, the output voltage V10 of the integration circuit 100 reaches the first reference voltage VH, and the output voltage V12 of the first comparison circuit 102 is inverted. By inversion of the output voltage V12, the logic circuit 104 outputs a signal for conducting the second switch 105 (FIG. 9C). At this time, the charge counter 106 adds 1 count (FIG. 9D). When the second switch 105 is turned on, both ends of the capacitor C are short-circuited, so that the output voltage V10 of the integrating circuit 100 decreases (FIG. 9B). When the output voltage V10 of the integration circuit 100 decreases and reaches the second reference voltage VL, the output voltage V13 of the second comparison circuit 103 is inverted. By inversion of the output voltage V13, the logic circuit 104 outputs a signal for turning off the second switch 105 (FIG. 9C). When the second switch 105 becomes non-conductive, the output voltage V10 of the integrating circuit 100 increases again. When the second switch 105 reaches the first reference voltage VH (FIG. 9B), the charge counter 106 adds 1 count (FIG. 9). 9 (d)). When the input voltage Vin is continuously applied, the above operation is repeated.

The measurement counter 107 counts the time information Nosa stored in the register 108 (FIG. 9 (f)). The charge counter 109 adds 1 count each time the measurement counter 107 counts the time information Nosa, that is, every time the time Tosan passes, and when the charge counter 106 overflows the set value N, the charge counter 109 One count is subtracted from the count value of 109 (FIG. 9 (g)). This added value includes a charge amount corresponding to the input voltage Vin generated at both ends of the detection resistor Rin and a charge amount corresponding to the set input offset voltage Vosa. The value to be subtracted is a charge amount corresponding to the set input offset voltage Vosa measured in the trimming step. By subtracting from the count value of the charge counter 109, the value to be subtracted corresponds to the set input offset voltage Vosa. The charge amount is corrected.

Next, the operation during discharging will be described with reference to FIGS. 10 (a) to 10 (g). Here, the operation when the input voltage Vin is −Vosa <Vin <0 V (FIG. 10A) will be described.

As in the case of charging, in the measurement step, the first switch 101 is switched to the input terminal a, and the input terminal a and the GND terminal b are connected to both ends of the detection resistor Rin. At this time, the output voltage V10 of the integration circuit 100 increases from the second reference voltage VL to the first reference voltage VH during the time Tm.

Holds (FIG. 10B).

Since the input voltage Vin is constant, the time Tm is

It is represented by Here, since the input voltage Vin is Vin <0V, the time Tm is shorter than the time Tosa measured in the trimming step. That is,

Holds.

After this time Tm, the output voltage V10 of the integration circuit 100 reaches the first reference voltage VH, and the output voltage V12 of the first comparison circuit 102 is inverted. By inversion of the output voltage V12, the logic circuit 104 outputs a signal for conducting the second switch 105 (FIG. 10C). At this time, the charge counter 106 adds 1 count (FIG. 10D). When the second switch 105 is turned on, both ends of the capacitor C are short-circuited, so that the output voltage V10 of the integrating circuit 100 decreases (FIG. 10B). When the output voltage V10 of the integration circuit 100 decreases and reaches the second reference voltage VL, the output voltage V13 of the second comparison circuit 103 is inverted. Due to the inversion of the output voltage V13, the logic circuit 104 outputs a signal for turning off the second switch 105 (FIG. 10C). When the second switch 105 becomes non-conductive, the output voltage V10 of the integrating circuit 100 increases again. When the second switch 105 reaches the first reference voltage VH (FIG. 10B), the charge counter 106 adds 1 count (FIG. 10). 10 (d)). When the input voltage Vin is continuously applied, the above operation is repeated as in the charged state.

The measurement counter 107 counts the time information Nosa stored in the register 108 (FIG. 10 (f)). The discharge counter 110 adds 1 count every time the charge counter 106 counts the set value N, and when the measurement counter 107 overflows the set value Nosa, 1 count is subtracted from the count value of the discharge counter 110 ( FIG. 10 (e)). This added value includes a charge amount corresponding to the input voltage Vin generated at both ends of the detection resistor Rin and a charge amount corresponding to the set input offset voltage Vosa. The value to be subtracted is the amount of charge corresponding to the set input offset voltage Vosa measured in the trimming step. By subtracting from the count value of the discharge counter 110, the value to be subtracted corresponds to the set input offset voltage Vosa. The charge amount is corrected.

Next, how to obtain the charge amount from the charge amount measurement circuit 1 according to the embodiment of the present invention that operates as described above will be described.

In the trimming step, the charge amount qosa per count of the charge counter 106 and the charge amount qclk per clock of the measurement counter 107 are detected.

First, the charge amount qosa per count of the charge counter 106 is obtained.

The time Tosa when the output voltage V10 of the integration circuit 100 changes from the first reference voltage VH to the level of the second reference voltage VL is expressed by the above-mentioned [Equation 47]. Here, if a virtual current Iosa flows through the detection resistor Rin and a voltage Vosa is generated at both ends,

And [Equation 47] is

It becomes. The product of the time Tosa and the current Iosa represents the amount of charge.

Thus, the charge amount qosa can be considered as a charge amount corresponding to the set input offset voltage Vosa. The element constants (C, R, Rin) in [Equation 56] are values that can be measured by a measuring instrument such as an impedance analyzer. When the voltage levels (VH, VL) are integrated in the LSI, a test mode may be provided so that these terminal voltages can be observed with an oscilloscope or the like. Therefore, the charge amount qosa represented by [Equation 56] can be easily obtained.

Next, a charge amount qclk per clock of the measurement counter 107 is obtained.

FIG. 11A shows a time relationship in the measurement counter 107 and the charge counter 106 in the trimming step. Since the charge amount qosa is a charge amount for one count of the charge counter 106, if the set amount N is counted, that is, the charge amount when the charge counter 106 overflows is Qosa,

It becomes.

The time Tosan when the charge counter 106 reaches the set value N count and reaches the charge amount Qosa is measured by the measurement counter 107 using the clock CLK. The count number at this time is Nosa and is stored in the register 108.

The charge amount qclk for one clock of the measurement counter 107 is calculated using this count number Nosa.

It can be expressed as. Since the count number N, Nosa and the charge amount qosa in [Formula 58] are both known, the charge amount qclk can be easily obtained.

In the charged state of the measurement step, the charge amount is obtained using the charge amounts qosa and qclk obtained in the trimming step.

FIG. 11B shows the time relationship in the measurement counter 107 and the charge counter 106 during charging. The time Tmc of the charge counter 106 is a time when the charge counter 106 overflows after N counts due to the influence of the input voltage Vin and the set input offset voltage Vosa. At this time, the charge amount has reached Qosa.

On the other hand, in the measurement counter 107, when the charge counter 106 reaches the time Tmc,

The time has passed.

The time Tosan of the measurement counter 107 is a time when the charge counter 106 reaches an overflow after N counts due to the influence of only the set input offset voltage Vosa.

Therefore, the time Tch related only to the input voltage Vin is a time obtained by subtracting the time Tosan from the time Tmc.

It is. The charge amount Qch corresponding to this time Tch is

Can be obtained as

Therefore, in the charge measurement circuit 1 of FIG. 7, the count counter 107 and the charge counter 109 remain in the count value Nch obtained by subtracting the count value Nosa corresponding to the charge amount Qosa, and the count value Nch is trimmed. By multiplying the obtained charge amount qclk, the charge amount Qch at the time of charging can be obtained as represented by [Equation 61].

Similarly, in the discharge state of the measurement step, the charge amount is obtained using the charge amounts qosa and qclk obtained in the trimming step.

FIG. 11C shows a time relationship in the measurement counter 107 and the charge counter 106 during discharge. When the measurement counter 107 reaches time Tosan, that is, when overflowing after counting Nosa, the charge counter 106

The time has passed.

The time Tmd of the charge counter 106 is a time when the charge counter 106 overflows after N counts due to the influence of the input voltage Vin and the set input offset voltage Vosa. At this time, the charge amount has reached Qosa.

Therefore, the time Tdis relating only to the input voltage Vin is a time obtained by subtracting the time Tmd from the time Tosan of the measurement counter 107.

It is. The charge amount Qdis corresponding to this time Tdis is

Can be obtained as

Therefore, in the charge measurement circuit 1 of FIG. 7, the state of the charge counter 106 and the discharge counter 110 remains as a count value Ndis obtained by subtracting the count value Nosa corresponding to the charge amount Qosa, and the count value Ndis is obtained by trimming. By multiplying the charge amount qosa, the charge amount Qdis at the time of discharge can be obtained as represented by [Equation 64].

Further, since the current is obtained by dividing the amount of change in the charge amount by the elapsed time, it can be easily obtained using the charge amount obtained by charging and discharging.

For example, the charging current Ich is

It is obtained by Also, the discharge current Idis is

It is obtained by

<< Fourth Embodiment >>
FIG. 12 is a configuration diagram of the charge amount measuring circuit 1 according to the fourth embodiment of the present invention. The charge amount measurement circuit 1 includes a first switch 101, a voltage charge conversion circuit 10 that converts an input voltage Vin into a pulse corresponding to the charge amount, and a charge measurement circuit 25 that counts output pulses of the voltage charge conversion circuit 10. The time until the charge measurement circuit 25 overflows when the input voltage Vin is 0 V is measured by the clock CLK, and the time measurement circuit 35 indicating the passage of the measurement time at the time of charge amount measurement, the charge measurement circuit 25 and the time measurement. The charge integration circuit 40 that counts the number of clocks CLK corresponding to each overflow time difference from the circuit 35, and the count value of the time measurement circuit 35 when the input voltage Vin is 0V, and the count value The voltage / charge conversion circuit 10 is configured to be larger than the maximum value of the input voltage Vin. And a integrating circuit 100 including an operational amplifier circuit 100a having the minimum value is less than the input offset voltage Vosa.

The charge measurement circuit 25 includes a charge counter 106 that counts the number of times the output voltage of the first comparison circuit 102 or the second comparison circuit 103 is inverted.

When the first switch 101 is switched to the GND terminal b, that is, in the trimming step, the time measuring circuit 35 measures a time Tosa until the charge counter 106 overflows with the clock CLK, and first time When the switch 101 is connected to the input terminal a, that is, at the time of the measurement step, a measurement counter 107 that indicates the passage of measurement time based on the clock CLK is provided.

The charge integrating circuit 40 detects an overflow signal (first overflow signal) OF1 of the charge counter 106 and an overflow signal (second overflow signal) OF2 of the measurement counter 107 from any overflow signal previously input. And a start / stop control circuit 111 for generating an enable signal EN indicating a period until another overflow signal inputted later, and an integration counter 112 controlled to be counted or stopped by the enable signal EN of the start / stop control circuit 111. Has been.

The storage circuit 50 includes a register 108 that stores a measurement value measured by the measurement counter 107 when the input voltage Vin is 0 V and sets the measurement value in the measurement counter 107.

FIGS. 13A to 13H show the operation of the trimming step when the set input offset voltage Vosa> 0V. First, the first switch 101 is switched to the GND terminal b, and the input voltage is set to Vin = 0 V (FIG. 13A). At this time, the output voltage V10 of the integrating circuit 100 increases from the second reference voltage VL to the first reference voltage VH during the time Tosa.

Holds (FIG. 13B).

From [Equation 67], the time Tosa is

After this time Tosa, the output voltage V10 of the integration circuit 100 reaches the first reference voltage VH, and the output voltage V12 of the first comparison circuit 102 is inverted as shown in FIG. Due to the inversion of the output voltage V12, the logic circuit 104 outputs a signal for conducting the second switch 105 (FIG. 13E). When the second switch 105 is turned on, both ends of the capacitor C are short-circuited, so that the output voltage V10 of the integrating circuit 100 decreases (FIG. 13 (b)). When the output voltage V10 of the integration circuit 100 decreases and reaches the second reference voltage VL, the output voltage V13 of the second comparison circuit 103 is inverted (FIG. 13 (d)). By inversion of the output voltage V13, the logic circuit 104 outputs a signal for turning off the second switch 105 (FIG. 13E). When the second switch 105 is turned off, the output voltage V10 of the integrating circuit 100 increases again (FIG. 13 (b)). The measurement counter 107 determines the time Tosan (FIG. 13 (f)) until the number of inversions of the output voltage V14 of the logic circuit 104 reaches the N count of the set value of the charge counter 106, and the clock CLK (FIG. 13). (G)) to measure (FIG. 13 (h)). The time information Nosa is stored in the register 108, and the stored time information Nosa is set in the measurement counter 107. This time information Nosa represents a charge amount corresponding to the set input offset voltage Vosa.

After the above trimming step, move to the measurement step. There are two measurement steps, charging and discharging. First, the operation during charging will be described with reference to FIGS. 14 (a) to 14 (j). Here, the operation in the case of 0V <Vin <Vosa (FIG. 14A) will be described.

Holds (FIG. 14B).

Since the input voltage Vin is constant, the time Tm is

Holds.

After this time Tm, the output voltage V10 of the integration circuit 100 reaches the first reference voltage VH, and the output voltage V12 of the first comparison circuit 102 is inverted. By inversion of the output voltage V12, the logic circuit 104 outputs a signal for conducting the second switch 105 (FIG. 14C). At this time, the charge counter 106 adds 1 count (FIG. 14D). When the second switch 105 is turned on, both ends of the capacitor C are short-circuited, so that the output voltage V10 of the integrating circuit 100 decreases (FIG. 14B). When the output voltage V10 of the integration circuit 100 decreases and reaches the second reference voltage VL, the output voltage V13 of the second comparison circuit 103 is inverted. Due to the inversion of the output voltage V13, the logic circuit 104 outputs a signal for turning off the second switch 105 (FIG. 14C). When the second switch 105 becomes non-conductive, the output voltage V10 of the integrating circuit 100 increases again. When the second switch 105 reaches the first reference voltage VH (FIG. 14B), the charge counter 106 adds one count (FIG. 14). 14 (d)). When the input voltage Vin is continuously applied, the above operation is repeated.

The charge counter 106 outputs the first overflow signal OF1 every time it counts to the set value N (FIG. 14 (d)) (FIG. 14 (e)). On the other hand, the measurement counter 107 outputs the second overflow signal OF2 every time it counts up to the time information Nosa stored in the register 108 (FIG. 14 (f)), that is, every time the time Tosan elapses (FIG. 14). 14 (g)). The start / stop control circuit 111 starts from the second overflow signal OF2 (FIG. 14 (g)) of the measurement counter 107 and stops at the first overflow signal OF1 (FIG. 14 (e)) of the charge counter 106. EN is output (FIG. 14 (h)). The integration counter 112 counts the number of clocks CLK (FIG. 14 (i)) during which the enable signal EN is output from the start / stop control circuit 111 (FIG. 14 (j)). The length of the period in which the integration counter 112 is stopped represents the amount of charge corresponding to the set input offset voltage Vosa, and the length of the period from the start to the stop is the input voltage generated at both ends of the detection resistor Rin. It represents the amount of charge corresponding to Vin. Therefore, only the charge amount to be measured corresponding to the input voltage Vin is cumulatively added to the integration counter 112.

Next, the operation during discharging will be described with reference to FIGS. 15 (a) to 15 (j). Here, the operation when the input voltage Vin is −Vosa <Vin <0 V (FIG. 15A) will be described.

Holds (FIG. 15B).

Since the input voltage Vin is constant, the time Tm is

Holds.

After this time Tm, the output voltage V10 of the integration circuit 100 reaches the first reference voltage VH, and the output voltage V12 of the first comparison circuit 102 is inverted. By inversion of the output voltage V12, the logic circuit 104 outputs a signal for conducting the second switch 105 (FIG. 15C). At this time, the charge counter 106 adds 1 count (FIG. 15D). When the second switch 105 is turned on, both ends of the capacitor C are short-circuited, so that the output voltage V10 of the integrating circuit 100 decreases (FIG. 15 (b)). When the output voltage V10 of the integration circuit 100 decreases and reaches the second reference voltage VL, the output voltage V13 of the second comparison circuit 103 is inverted. By inversion of the output voltage V13, the logic circuit 104 outputs a signal for turning off the second switch 105 (FIG. 15C). When the second switch 105 becomes non-conductive, the output voltage V10 of the integrating circuit 100 increases again, and when the first reference voltage VH is reached (FIG. 15B), the charge counter 106 adds 1 count (FIG. 15). 15 (d)). When the input voltage Vin is continuously applied, the above operation is repeated as in the charged state.

The charge counter 106 outputs the first overflow signal OF1 every time it counts to the set value N (FIG. 15 (d)) (FIG. 15 (e)). On the other hand, the measurement counter 107 outputs the second overflow signal OF2 every time it counts up to the time information Nosa stored in the register 108 (FIG. 15 (f)), that is, every time the time Tosan elapses (FIG. 15). 15 (g)). The start / stop control circuit 111 starts from the first overflow signal OF1 (FIG. 15 (e)) of the charge counter 106 and stops at the second overflow signal OF2 (FIG. 15 (g)) of the measurement counter 107. EN is output (FIG. 15 (h)). The integration counter 112 counts the number of clocks CLK (FIG. 15 (i)) during which the enable signal EN is output from the start / stop control circuit 111 (FIG. 15 (j)). The length of the period in which the integration counter 112 is stopped represents the amount of charge corresponding to the set input offset voltage Vosa, and the length of the period from the start to the stop is the input voltage generated at both ends of the detection resistor Rin. It represents the amount of charge corresponding to Vin. Therefore, only the charge amount to be measured corresponding to the input voltage Vin is cumulatively added to the integration counter 112.

In charge and discharge, only the start and stop by the overflow signals OF1 and OF2 of the charge counter 106 and the measurement counter 107 are reversed, and the other operations may be the same.

First, the charge amount qosa per count of the charge counter 106 is obtained.

The time Tosa when the output voltage V10 of the integrating circuit 100 changes from the first reference voltage VH to the level of the second reference voltage VL is expressed by the above-described [Equation 68]. Here, if a virtual current Iosa flows through the detection resistor Rin and a voltage Vosa is generated at both ends,

And [Equation 68] is

Thus, the charge amount qosa can be considered as a charge amount corresponding to the set input offset voltage Vosa. The element constants (C, R, Rin) in [Equation 77] are values that can be measured by a measuring instrument such as an impedance analyzer. When the voltage levels (VH, VL) are integrated in the LSI, a test mode may be provided so that these terminal voltages can be observed with an oscilloscope or the like. Therefore, the charge amount qosa expressed by [Equation 77] can be easily obtained.

FIG. 16A shows a time relationship in the measurement counter 107 and the charge counter 106 in the trimming step. Since the charge amount qosa is a charge amount for one count of the charge counter 106, if the set amount N is counted, that is, the charge amount when the charge counter 106 overflows is Qosa,

It becomes.

It can be expressed as. Since the count number N, Nosa and the charge amount qosa in [Equation 79] are both known, the charge amount qclk can be easily obtained.

In the charge state of the measurement step, the charge amount is obtained using the charge amount qclk obtained in the trimming step.

FIG. 16B shows a time relationship in the measurement counter 107, the charge counter 106, and the integration counter 112 during charging. The time Tmc of the charge counter 106 is a time when the charge counter 106 overflows after N counts due to the influence of the input voltage Vin and the set input offset voltage Vosa. At this time, the charge amount has reached Qosa. The time Tosan of the measurement counter 107 is a time when the charge counter 106 reaches an overflow after N counts due to the influence of only the input offset voltage Vosa set in the trimming step. The integration counter 112 starts counting after the second overflow signal OF2 of the measurement counter 107 is output, and stops counting when the first overflow signal OF1 of the charge counter 106 is output. The time Tch counted by the integration counter 112 is a time difference between the time Tmc and the time Tosan corresponding to the time affected only by the input voltage Vin. During this time difference Tch, the integration counter 112 counts the number of clocks CLK (Nch). Therefore, the time Tch is

It is represented by The charge amount Qch corresponding to this time Tch is

Can be obtained as

Therefore, in the state of the integration counter 112 in the charge measurement circuit 1 of FIG. 12, the number of clocks CLK corresponding to the overflow time difference Tch between the charge counter 106 and the measurement counter 107 is counted. When this count value Nch is multiplied by the charge amount qclk obtained in the trimming step, the charge amount Qch at the time of charging is obtained as represented by [Equation 81].

Similarly, in the discharge state of the measurement step, the charge amount is obtained using the charge amount qclk obtained in the trimming step.

FIG. 16C shows the time relationship in the measurement counter 107, the charge counter 106, and the integration counter 112 during discharge.

The time Tmd of the charge counter 106 is a time when the charge counter 106 overflows after N counts due to the influence of the input voltage Vin and the set input offset voltage Vosa. At this time, the charge amount has reached Qosa. The time Tosan of the measurement counter 107 is a time when the measurement counter 107 reaches an overflow after counting Nosa, under the influence of only the set input offset voltage Vosa. The integration counter 112 starts counting after the first overflow signal OF1 of the charge counter 106 is output, and stops counting when the second overflow signal OF2 of the measurement counter 107 is output. The time Tdis counted by the integration counter 112 is a time difference between the time Tosan and the time Tmd, which corresponds to a time affected only by the input voltage Vin. During this time difference Tdis, the integration counter 112 counts the number of clocks CLK (Ndis). Therefore, the time Tdis is

It is represented by The charge amount Qdis corresponding to this time Tdis is

Can be obtained as

Therefore, the state of the integration counter 112 in the charge measurement circuit 1 of FIG. 12 is the number of clocks CLK corresponding to the overflow time difference Tdis between the charge counter 106 and the measurement counter 107. By multiplying the count value Ndis by the charge amount qclk obtained in the trimming step, the charge amount Qdis at the time of discharge is obtained as represented by [Equation 83].

For example, the charging current Ich is

It is obtained by Also, the discharge current Idis is

It is obtained by

17A and 17B show the distribution of the input offset voltage Vosa and the input voltage of the amplification operation circuit 100a of the integration circuit 100 provided in the charge amount measurement circuit 1 of the third and fourth embodiments. It is a figure which shows the range of Vin.

Also in the embodiment of the present invention, as in the prior art, variations in the input offset voltage Vosa of the operational amplifier circuit 100a occur during mass production of products. In the embodiment of the present invention, the input offset voltage Vosa is set outside the input voltage range in a state where the variation of the input offset voltage exists (FIG. 17A).

When −Vmin ≦ Vin <0 V, Tm <Tosa, and the influence of the input offset voltage Vosa can be corrected and the correct charge amount can be measured as in the conventional charge amount measurement circuit 2.

On the other hand, when 0 V <Vin ≦ + Vmax, Tm> Tosa. Even in such a case, the charge amount measuring circuit 1 of the present invention corrects the influence of the input offset voltage Vosa as described in the operation during charging. The correct charge amount can be measured.

As described above, according to the third and fourth embodiments, by setting the input offset voltage Vosa in the operational amplifier circuit 100a used in the integrating circuit 100, the entire measurement range of the input voltage Vin flows to the detection resistor Rin. The amount of charge can be measured. Further, since the input voltage Vin and the set input offset voltage Vosa satisfy the condition of Vin <Vosa and an appropriate difference is not established, the state of Vin = Vosa is not obtained. The output voltage V12 is always inverted, and the amount of charge flowing through the detection resistor Rin can be measured.

FIG. 18 shows an application example to the portable electronic device 3 to which the third and fourth embodiments are applied. The portable electronic device 3 includes a detection resistor Rin that converts a current that flows during charging and discharging of the secondary battery into an input voltage Vin, and a charge amount measurement circuit 1 that measures the amount of charge or current flowing from the input voltage Vin to the detection resistor Rin. And an arithmetic circuit (microcomputer) 4 for calculating the remaining capacity of the secondary battery from the charge amount measured by the charge amount measuring circuit 1, and a display circuit 5 for displaying the calculation processing result of the microcomputer 4. ing.

As in the third and fourth embodiments, the charge amount measurement circuit 1 includes an integration circuit 100 using an operational amplifier circuit 100a having an input offset voltage Vosa that is larger than the maximum value of the input voltage Vin or smaller than the minimum value. I have. Therefore, such a portable electronic device 3 can measure the amount of charge or the amount of current without having a dead zone in the entire measurement range of the input voltage Vin.

FIGS. 19 to 23 are examples of realizing the input offset voltage Vosa of the operational amplifier circuit 100a according to the first to fourth embodiments.

FIG. 19 shows an example in which the input offset voltage Vosa is set with a difference in the size of a pair of transistors in a differential input stage often used in an operational amplifier circuit. Here, the transistor size is differentiated by connecting a plurality of transistors in one of the differential input stages in parallel. I0 is a current source, MP1-3 are P-channel MOS transistors, and MN1-2 are N-channel MOS transistors. FIG. 20 shows an example in which the input offset voltage Vosa is set with a difference in the amount of current of a current source often used in an operational amplifier circuit. Here, by connecting one of a pair of transistors constituting a current mirror as a current source in parallel, a difference is made in the size of the transistor, and the current amount is made different. I0 is a current source, MP1 and MP2 are P-channel MOS transistors, and MN1 and MN3 are N-channel MOS transistors.

FIG. 21 shows an example in which the input offset voltage Vosa is set by making a difference between the resistance values of offset resistors connected to a pair of transistors in a differential input stage often used in an operational amplifier circuit. Here, the resistance value is differentiated by connecting the offset resistor Rof to only one transistor of the differential input stage. FIG. 22 shows an example in which the input offset voltage Vosa is set by adding a difference to the resistance value of an offset resistor connected to a current source often used in an operational amplifier circuit. Here, the resistance value is differentiated by connecting the offset resistor Rof to only one current source.

In FIGS. 19 to 22, description has been made using a general operational amplifier circuit. However, other differentials such as a folded cascode differential amplifier circuit (folded cascode amplifier circuit or Rail-to-Rail amplifier circuit) may be used. It goes without saying that the same effect can be obtained even with an operational amplifier circuit.

FIG. 23 is a circuit diagram of an operational amplifier circuit in which the input offset voltage Vosa is set by applying a bias voltage to the amplifier AMP.

In the first to fourth embodiments, the input offset voltage Vosa is set on the non-inverting input side of the operational amplifier circuit 100a. However, the input offset voltage Vosa is set on the inverting input side to obtain a desired operation. However, the same effects as those of the first to fourth embodiments can be obtained.

Furthermore, in the first to fourth embodiments, the input offset voltage Vosa is set in the operational amplifier circuit 100a. However, the same effect can be obtained even when a bias voltage is applied from the outside of the operational amplifier circuit 100a. Needless to say.

In the first and second embodiments, the charge / discharge determination using the secondary battery is described as an example. However, the first and second embodiments can be used for determining the current polarity in current detection using a general power source. The same effect as in the second embodiment can be obtained.

In the third embodiment, an example using the discharge measurement circuit 20, the charge measurement circuit 30, and the storage circuit 50 is used. In the fourth embodiment, the charge measurement circuit 25, the time measurement circuit 35, the charge integration circuit 40, and the storage are stored. Although examples using the circuit 50 are shown, the same effect can be obtained even if these functions are processed by a microcomputer or a dedicated arithmetic circuit. Further, addition and subtraction processing may be performed by an up / down counter.

The voltage polarity discrimination circuit of the present invention is useful for portable electronic devices such as mobile phones, digital cameras, and game machines equipped with secondary batteries, electric vehicles, and the like. It can also be applied to current detectors and the like. For example, the current consumption and charge amount of an electronic device supplied with power by the secondary battery, and the charge current and accumulated charge amount when charging the secondary battery are detected, and the remaining capacity of the secondary battery is detected or estimated. It is useful as a circuit for discriminating the polarity of the charge / discharge current in the system.

In addition, the charge amount measurement circuit of the present invention is useful for portable electronic devices such as mobile phones, digital cameras, and game machines equipped with secondary batteries, and electric vehicles. It can also be applied to ammeters and the like.

1, 2 Charge measurement circuit 3 Portable electronic device 4 Arithmetic circuit (microcomputer)
5 Display Circuit 10 Voltage Charge Conversion Circuit 20 Discharge Measurement Circuit 25 Charge Measurement Circuit 30 Charge Measurement Circuit 35 Time Measurement Circuit 40 Charge Integration Circuit 50 Storage Circuit 100, 200, 300 Integration Circuit 100a, 200a, 300a Operational Amplification Circuit 101, 105 Switch 102, 103 Comparison circuit 104 Logic circuit 106 Charge counter 107 Measurement counter 108 Register 109 Charge counter 110 Discharge counter 111 Start / stop control circuit 112 Integration counter 206 Asynchronous counter 207 Timer 301, 302, 303 Voltage polarity discrimination circuit 311, 321, 331 Initial Circuit 312, 322 time measurement circuit 401, 502, 601, 602 comparison circuit 402, 505 determination circuit 503 logic circuit 504, 603, 604 counter 701, 801 timer 702, 8 2 Storage circuits 703, 803 Arithmetic circuit AMP Amplifier C, C1 Capacitor CLK Clock EN Enable signal GND Reference voltage OF1, OF2 Overflow signal R, R1, Rin, Rof Resistance SW0, SW1, SW2, SW3 Switch V10, V20, V30 Integration circuit Output voltage V11, V12, V13, V22 Comparison circuit output voltage V14, V44 Logic circuit output voltage V23 Logic circuit output voltage V24 Counter output voltage V31, V32, V42, V43 Comparison circuit output voltage Vc Initial voltage Vdd Power supply voltage VH First reference voltage Vin Input voltage VL Second reference voltage Vos, Vosa Input offset voltage a Input terminal b GND terminal c Inverted input terminal d of operational amplifier circuit Non-inverted input terminal e of operational amplifier circuit Operational amplifier circuit Output terminal

Claims

An integration circuit;
A switch for switching the input voltage to the integration circuit to a voltage for discrimination of polarity or a reference voltage;
A time measuring circuit for measuring the time until the output voltage of the integrating circuit reaches a set voltage, and determining the polarity of the input voltage to the integrating circuit based on the measurement result;
The voltage polarity discriminating circuit, wherein the integrating circuit is configured using an operational amplifier circuit having an input offset voltage that is larger than a maximum value or smaller than a minimum value of an input voltage of the integrating circuit.
In the voltage polarity discrimination circuit according to claim 1,
The time measuring circuit is
A comparison circuit that compares the output voltage of the integration circuit with a first reference voltage and outputs the comparison result;
The time from when the input voltage to the integration circuit is switched by the switch until the output voltage of the comparison circuit is inverted is measured, and the polarity of the input voltage to the integration circuit is determined based on the measurement result. A voltage polarity discrimination circuit including a determination circuit.
In the voltage polarity discrimination circuit according to claim 2,
The determination circuit includes a timer for measuring a time from when the input voltage to the integration circuit is switched by the switch to when the output voltage of the comparison circuit is inverted.
In the voltage polarity discrimination circuit according to claim 3,
The voltage polarity determination circuit, wherein the determination circuit further includes a storage circuit that stores a measurement result of the timer.
In the voltage polarity discrimination circuit according to claim 4,
The voltage determination circuit according to claim 1, wherein the determination circuit further includes an arithmetic circuit for comparing the measurement results.
In the voltage polarity discrimination circuit according to claim 4,
The voltage polarity discrimination circuit, wherein the memory circuit is an up counter or a down counter.
In the voltage polarity discrimination circuit according to claim 1,
The time measuring circuit includes a time from when the input voltage to the integrating circuit is switched to the reference voltage by the switch until the output voltage of the integrating circuit reaches the first reference voltage, and the switch by the switch. By comparing the time until the output voltage of the integration circuit reaches the first reference voltage after the input voltage to the integration circuit has been switched to the voltage to be polarity-determined, A voltage polarity discrimination circuit for discriminating the polarity of an input voltage.
In the voltage polarity discrimination circuit according to claim 1,
The time measuring circuit is
A first comparison circuit that compares the output voltage of the integration circuit with a first reference voltage and outputs the comparison result;
A second comparison circuit that compares the output voltage of the integration circuit with a second reference voltage and outputs the comparison result;
A logic circuit that outputs a voltage that is set and reset in response to inversion of the output voltage of the first comparison circuit and inversion of the output voltage of the second comparison circuit;
A counter for measuring the output of the logic circuit up to a set value;
The time from when the input voltage to the integration circuit is switched by the switch until the measurement value by the counter reaches the set value is measured, and the polarity of the input voltage to the integration circuit is determined based on the measurement result. A determination circuit for determining,
The voltage polarity discrimination circuit further comprises an initialization circuit that initializes an output voltage of the integration circuit in response to an output of the logic circuit.
In the voltage polarity discrimination circuit according to claim 8,
The initialization circuit includes a switch that is turned on or off according to the output of the logic circuit and sets the output voltage of the integrating circuit to the second reference voltage. .
In the voltage polarity discrimination circuit according to claim 8,
The determination circuit includes a timer for measuring a time from when the input voltage to the integration circuit is switched by the switch until the measurement value by the counter reaches the set value. .
In the voltage polarity discrimination circuit according to claim 10,
The voltage polarity determination circuit, wherein the determination circuit further includes a storage circuit that stores a measurement result of the timer.
In the voltage polarity discrimination circuit according to claim 11,
The voltage determination circuit according to claim 1, wherein the determination circuit further includes an arithmetic circuit for comparing the measurement results.
In the voltage polarity discrimination circuit according to claim 11,
The voltage polarity discrimination circuit, wherein the memory circuit is an up counter or a down counter.
In the voltage polarity discrimination circuit according to claim 8,
The determination circuit includes a time from when the input voltage to the integration circuit is switched to the reference voltage by the switch until the measurement value by the counter reaches the set value, and an input to the integration circuit by the switch. The polarity of the input voltage to the integration circuit is determined by comparing the time from when the voltage is switched to the polarity determination target voltage until the value measured by the counter reaches the set value. Voltage polarity discrimination circuit.
In the voltage polarity discrimination circuit according to claim 1,
The operational amplifier circuit generates the input offset voltage by making a difference between the sizes of a pair of transistors in a differential input stage.
In the voltage polarity discrimination circuit according to claim 1,
The operational amplifier circuit generates the input offset voltage by making a difference in a current amount of a current source connected to a pair of transistors in a differential input stage.
In the voltage polarity discrimination circuit according to claim 1,
The operational amplifier circuit generates the input offset voltage by making a difference between resistance values of offset resistors connected to a pair of transistors in a differential input stage.
In the voltage polarity discrimination circuit according to claim 1,
The operational amplifier circuit generates the input offset voltage by differentiating a resistance value of an offset resistor connected to a current source connected to a pair of transistors of a differential input stage. Discrimination circuit.
In the voltage polarity discrimination circuit according to claim 1,
In the operational amplifier circuit, a bias voltage greater than the maximum value or less than the minimum value of the input voltage of the integration circuit is applied to either the inverting input terminal or the non-inverting input terminal. .
In the voltage polarity discrimination circuit according to claim 1,
The voltage polarity discrimination circuit, wherein the voltage for polarity discrimination is a voltage between both ends of a detection resistor connected in series to a predetermined power source.
A voltage charge conversion circuit that converts an input voltage into a pulse corresponding to the amount of charge; and
A charge measuring circuit and a discharge measuring circuit, each counting an output pulse of the voltage-to-charge converter circuit;
A charge amount measurement circuit having a storage circuit that holds a count value of the charge measurement circuit when the input voltage is 0 V and sets the count value in the charge measurement circuit;
The count value of the discharge measurement circuit is subtracted when the count of the charge measurement circuit reaches an overflow, and the count value of the charge measurement circuit is subtracted when the count of the discharge measurement circuit reaches an overflow, And,
2. The charge amount measuring circuit according to claim 1, wherein the voltage-to-charge converter circuit includes an integrating circuit using an operational amplifier circuit having an input offset voltage that is greater than a maximum value or less than a minimum value of the input voltage.
The charge amount measuring circuit according to claim 21,
The voltage to charge conversion circuit is
A first switch for switching an input voltage to the integration circuit to a voltage to be measured or a reference voltage;
A first comparison circuit that compares the output voltage of the integration circuit with a first reference voltage and outputs the comparison result;
A second comparison circuit that compares the output voltage of the integration circuit with a second reference voltage and outputs the comparison result;
A logic circuit that outputs a voltage that is set and reset in response to inversion of the output voltage of the first comparison circuit or inversion of the output voltage of the second comparison circuit;
A charge amount measuring circuit, further comprising: a second switch that controls conduction and non-conduction by an output voltage of the logic circuit to initialize the integration circuit.
The charge amount measuring circuit according to claim 21,
The charge measurement circuit includes a measurement counter and a charge counter, and the discharge measurement circuit includes a charge counter and a discharge counter,
The measurement counter measures the time until the charge counter overflows when the first switch is switched to the reference voltage, and the first switch is connected to the voltage to be measured. Is configured to show the passage of measurement time,
The charge amount measurement circuit according to claim 1, wherein the charge counter adds 1 count when the measurement counter overflows and subtracts 1 count when the charge counter overflows.
The charge amount measurement circuit according to claim 23,
The charge counter counts the number of times the output voltage of the first comparison circuit or the output voltage of the second comparison circuit is inverted,
The charge amount measurement circuit according to claim 1, wherein the discharge counter adds 1 count when the charge counter overflows and subtracts 1 count when the measurement counter overflows.
The charge amount measurement circuit according to claim 23,
The charge amount measurement circuit, wherein the storage circuit is a register that stores a measurement value measured by the measurement counter when the input voltage is 0 V and sets the measurement value in the measurement counter.
The charge amount measurement circuit according to claim 25,
The charge amount measuring circuit, wherein the register is an up counter or a down counter.
The charge amount measuring circuit according to claim 21,
The charge amount measuring circuit, wherein the operational amplifier circuit generates the input offset voltage by making a difference between the sizes of a pair of transistors in a differential input stage.
The charge amount measuring circuit according to claim 21,
The charge amount measuring circuit, wherein the operational amplifier circuit generates the input offset voltage by making a difference in a current amount of a current source connected to a pair of transistors in a differential input stage.
The charge amount measuring circuit according to claim 21,
The charge amount measuring circuit, wherein the operational amplifier circuit generates the input offset voltage by making a difference between resistance values of offset resistors connected to a pair of transistors in a differential input stage.
The charge amount measuring circuit according to claim 21,
The operational amplifier circuit generates the input offset voltage by differentiating a resistance value of an offset resistor connected to a current source connected to a pair of transistors in a differential input stage. Measuring circuit.
The charge amount measuring circuit according to claim 21,
In the operational amplifier circuit, a charge voltage measuring circuit, wherein a bias voltage larger than a maximum value or smaller than a minimum value of the input voltage of the integrating circuit is applied to either an inverting input terminal or a non-inverting input terminal. .
The charge amount measuring circuit according to claim 21,
The charge amount measuring circuit, wherein the memory circuit is an up counter or a down counter.
The charge amount measuring circuit according to claim 21,
The charge amount measuring circuit, wherein the input voltage is a voltage across a sensing resistor connected in series to a predetermined power source.
A sensing resistor connected in series to the secondary battery;
The charge amount measuring circuit according to claim 21, wherein a voltage generated by a current flowing through the detection resistor is input, and a charge amount corresponding to the current flowing through the detection resistor is output.
An arithmetic circuit for calculating the remaining capacity of the secondary battery from the charge amount measured by the charge amount measurement circuit;
A portable electronic device comprising a display circuit for displaying a calculation result of the arithmetic circuit.
The portable electronic device according to claim 34,
A portable electronic device, wherein the arithmetic circuit is a microcomputer.
A voltage charge conversion circuit that converts an input voltage into a pulse corresponding to the amount of charge; and
A charge measuring circuit for counting output pulses of the voltage-to-charge converter circuit;
A time measurement circuit that measures the time until the charge measurement circuit overflows when the input voltage is 0 V with a clock and indicates the passage of the measurement time when measuring the charge amount; and
A charge integrating circuit that counts the number of clocks corresponding to the time difference of overflow between the charge measuring circuit and the time measuring circuit;
A storage circuit that holds a count value of the time measurement circuit when the input voltage is 0 V and sets the count value in the time measurement circuit;
2. The charge amount measuring circuit according to claim 1, wherein the voltage-to-charge converter circuit includes an integrating circuit using an operational amplifier circuit having an input offset voltage that is greater than a maximum value or less than a minimum value of the input voltage.
The charge amount measuring circuit according to claim 36,
The voltage to charge conversion circuit is
A first switch for switching an input voltage to the integration circuit to a voltage to be measured or a reference voltage;
A first comparison circuit that compares the output voltage of the integration circuit with a first reference voltage and outputs the comparison result;
A second comparison circuit that compares the output voltage of the integration circuit with a second reference voltage and outputs the comparison result;
A logic circuit that outputs a voltage that is set and reset in response to inversion of the output voltage of the first comparison circuit or inversion of the output voltage of the second comparison circuit;
A charge amount measuring circuit, further comprising: a second switch that controls conduction and non-conduction by an output voltage of the logic circuit to initialize the integration circuit.
The charge amount measurement circuit according to claim 37,
The charge measurement circuit includes a charge counter that counts the number of times the output voltage of the first comparison circuit or the output voltage of the second comparison circuit is inverted.
The charge amount measurement circuit according to claim 37,
When the first switch is switched to the reference voltage, the time measurement circuit measures a time until the charge counter reaches an overflow, and the first switch is set to the voltage to be measured. A charge amount measurement circuit comprising a measurement counter indicating the passage of measurement time when connected.
The charge amount measurement circuit according to claim 39,
The charge amount measurement circuit, wherein the measurement counter is an up counter or a down counter.
The charge amount measuring circuit according to claim 36,
The charge integrating circuit is
Start / stop that generates an enable signal indicating a period from one of the previously input overflow signals to another overflow signal that is input later, based on the overflow signal of the charge measuring circuit and the overflow signal of the time measuring circuit A control circuit;
A charge amount measuring circuit comprising: an integration counter whose counting or stopping is controlled by the enable signal of the start / stop control circuit.
The charge amount measuring circuit according to claim 41,
The charge amount measuring circuit, wherein the integration counter is an up counter or a down counter.
The charge amount measuring circuit according to claim 36,
The charge amount measurement circuit, wherein the storage circuit stores a measurement value measured by the time measurement circuit when the input voltage is 0 V, and sets the measurement value in the time measurement circuit.
The charge amount measurement circuit according to claim 43,
The charge amount measuring circuit, wherein the memory circuit is a register.
The charge amount measurement circuit according to claim 43,
The charge amount measuring circuit, wherein the memory circuit is an up counter or a down counter.
The charge amount measuring circuit according to claim 36,
The charge amount measuring circuit, wherein the operational amplifier circuit generates the input offset voltage by making a difference between the sizes of a pair of transistors in a differential input stage.
The charge amount measuring circuit according to claim 36,
The charge amount measuring circuit, wherein the operational amplifier circuit generates the input offset voltage by making a difference in a current amount of a current source connected to a pair of transistors in a differential input stage.
The charge amount measuring circuit according to claim 36,
The charge amount measuring circuit, wherein the operational amplifier circuit generates the input offset voltage by making a difference between resistance values of offset resistors connected to a pair of transistors in a differential input stage.
The charge amount measuring circuit according to claim 36,
The operational amplifier circuit generates the input offset voltage by differentiating a resistance value of an offset resistor connected to a current source connected to a pair of transistors in a differential input stage. Measuring circuit.
The charge amount measuring circuit according to claim 36,
In the operational amplifier circuit, a charge voltage measuring circuit, wherein a bias voltage larger than a maximum value or smaller than a minimum value of the input voltage of the integrating circuit is applied to either an inverting input terminal or a non-inverting input terminal. .
The charge amount measuring circuit according to claim 36,
The charge amount measuring circuit, wherein the input voltage is a voltage across a sensing resistor connected in series to a predetermined power source.
A sensing resistor connected in series to the secondary battery;
The charge amount measuring circuit according to claim 36, wherein a voltage generated by a current flowing through the detection resistor is input, and a charge amount corresponding to the current flowing through the detection resistor is output.
An arithmetic circuit for calculating the remaining capacity of the secondary battery from the charge amount measured by the charge amount measurement circuit;
A portable electronic device comprising a display circuit for displaying a calculation result of the arithmetic circuit.
The portable electronic device according to claim 52,
A portable electronic device, wherein the arithmetic circuit is a microcomputer.