WO2010083744A1 - 一种低功耗控制电路及其工作方式 - Google Patents

一种低功耗控制电路及其工作方式 Download PDF

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Publication number
WO2010083744A1
WO2010083744A1 PCT/CN2010/070231 CN2010070231W WO2010083744A1 WO 2010083744 A1 WO2010083744 A1 WO 2010083744A1 CN 2010070231 W CN2010070231 W CN 2010070231W WO 2010083744 A1 WO2010083744 A1 WO 2010083744A1
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WIPO (PCT)
Prior art keywords
circuit
control
signal
receiving
control chip
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PCT/CN2010/070231
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English (en)
French (fr)
Inventor
王金友
王学星
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深圳市博孚机电有限公司
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Publication date
Application filed by 深圳市博孚机电有限公司 filed Critical 深圳市博孚机电有限公司
Priority to US13/142,401 priority Critical patent/US9134718B2/en
Priority to EP10733217.3A priority patent/EP2381323A4/en
Priority to CA2749517A priority patent/CA2749517A1/en
Publication of WO2010083744A1 publication Critical patent/WO2010083744A1/zh

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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H04B1/1607—Supply circuits
    • H04B1/1615—Switching on; Switching off, e.g. remotely
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/02—Details
    • H04L12/12—Arrangements for remote connection or disconnection of substations or of equipment thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/02—Power saving arrangements
    • H04W52/0209—Power saving arrangements in terminal devices
    • H04W52/0225—Power saving arrangements in terminal devices using monitoring of external events, e.g. the presence of a signal
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/25—Pc structure of the system
    • G05B2219/25289—Energy saving, brown out, standby, sleep, powerdown modus for microcomputer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H04B1/26—Circuits for superheterodyne receivers
    • H04B1/28—Circuits for superheterodyne receivers the receiver comprising at least one semiconductor device having three or more electrodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/2803—Home automation networks
    • H04L2012/2847—Home automation networks characterised by the type of home appliance used
    • H04L2012/285—Generic home appliances, e.g. refrigerators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/02—Power saving arrangements
    • H04W52/0209—Power saving arrangements in terminal devices
    • H04W52/0212—Power saving arrangements in terminal devices managed by the network, e.g. network or access point is master and terminal is slave
    • H04W52/0216—Power saving arrangements in terminal devices managed by the network, e.g. network or access point is master and terminal is slave using a pre-established activity schedule, e.g. traffic indication frame
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
    • H04W52/02—Power saving arrangements
    • H04W52/0209—Power saving arrangements in terminal devices
    • H04W52/0261—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level
    • H04W52/0287—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level changing the clock frequency of a controller in the equipment
    • H04W52/0293—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level changing the clock frequency of a controller in the equipment having a sub-controller with a low clock frequency switching on and off a main controller with a high clock frequency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the present invention relates to control circuits, and more particularly to a low power control circuit and a method of operating the same. Background technique
  • control circuits such as: electric curtains, electric windows and doors, electric lights, etc.
  • These control circuits generally include a receiving circuit, a control chip, a receiving circuit signal connection control chip, a control chip connection actuator (the actuators described herein may be electric gates, power windows, electric curtains, lights, etc.), and receiving circuits for receiving Command information, the control chip is used to issue various execution commands to the actuator.
  • a power supply circuit is provided to supply power to the receiving circuit and the control chip. Since the receiving circuit and the control chip are always in operation, both the receiving circuit and the control chip need to consume power, but in reality, there is no command information for most of the time.
  • the receiving circuit, the control chip, and the actuator are all powered by the battery, most of the power of the battery is consumed on the receiving circuit and the control chip, instead of being consumed on the actuator, so that the battery power can be quickly After consumption, it is necessary to constantly replace the battery.
  • DC tubular motor control circuit under normal circumstances, the receiving circuit operating current is about 7 mA, the operating current of the control chip is usually about 7 mA, if the battery is 1800 mAh battery block, can be used
  • the receiving circuit and the control chip work for more than 100 hours, which means that the power consumption can be exhausted within 5 days.
  • the 1800 mAh battery block can make a 380 mA motor (the motor usually runs for 30 seconds at a time) and can run 570 times. If it is operated twice a day, it can be used for almost one year. It can be seen from this that the energy consumed is mainly used in the usual receiving circuit and control chip.
  • FIG. 200580009297.7 discloses a low power Rf control system which is essentially a low power control circuit.
  • the patent uses a dual-frequency control chip. Under normal circumstances, the control chip is in a low-frequency control state. The low-frequency state is generally consumed at about 20-30 microamperes, and at high frequencies, it is about 7 milliamps.
  • the receiving module also has two states. , sleep state and working state, 2 in sleep state Around microamperes, it is about 7 mA in working condition.
  • the control chip periodically turns on the receiving module to make it work for about 1 millisecond. Generally, the receiving circuit is turned on once every several tens of milliseconds, so that the power consumption rate of the receiving circuit can be saved by several times.
  • control chip Since the control chip is in a low frequency state for many times, it also saves a lot of power compared to the original control chip at a high frequency state. However, since the control chip is in a low frequency state, it still consumes about 20-30 microamperes. So still consume a lot of energy. Summary of the invention
  • One of the technical problems to be solved by the present invention is to provide a low power control circuit which can reduce the power consumption of the control chip and thereby save power to the control circuit.
  • the low-power control circuit of the present invention comprises a receiving circuit, a control chip, a receiving circuit signal connection control chip, and a control chip connection executing mechanism, characterized in that it further comprises a clock generation control circuit, and the clock generation control circuit respectively receives the signal connection and receives Circuit and control chip.
  • the clock generation control circuit comprises a switch circuit, an RC bridge, a clock generation control power supply circuit, an oscillation enable control circuit, the switch circuit is electrically connected to the RC bridge, and the clock generation control power supply circuit supplies power to the switch circuit and the RC bridge.
  • the control chip signal is connected to the oscillation enable control circuit, and the oscillation enable control circuit signal is connected to the switch circuit. This is an implementation of a clock generation control circuit.
  • the switching circuit is a wide value oscillation analog switching circuit. This circuit can reduce power consumption.
  • the power supply circuit is a step-down circuit. This reduces the power consumption of the switching circuit, which further reduces the power consumption of the clock generation control circuit.
  • the step-down circuit is a diode series step-down circuit. This step-down circuit is more accurate in step-down.
  • the receiving circuit is a wireless receiving circuit, and the circuit comprises: a high frequency receiving frequency selective circuit, a superheterodyne receiving circuit, an intermediate frequency filter, a crystal local resonant circuit, a receiving data squelch circuit, and electrical connection between the above circuits. This can reduce the noise coming out of the signal from the superheterodyne receiving circuit.
  • the receiving data squelch circuit comprises two parts: an analog integral proportional circuit, a logic processing circuit, a received signal strength level output of the superheterodyne receiving circuit to the analog integral proportional circuit, and a data processing loop data of the superheterodyne receiving circuit and The output data of the unit is output to the logic processing circuit to simulate the integral ratio
  • the analog signal is output to a logic processing circuit, and the logic processing circuit outputs a low noise signal.
  • This design can determine whether the received analog signal is an approved carrier frequency band by analog integral proportional circuit. If it is, the logic processing circuit is allowed to process the signal; if not, the logic processing circuit is not allowed to process the signal. It is possible to shield the output signal of the non-working state, so that the zero-noise output of the infinite receiving circuit can be realized.
  • the second technical problem to be solved by the present invention is to provide a method for enabling a control circuit to achieve low power consumption.
  • the method of the present invention comprises the following steps:
  • control chip is in a sleep state, and the timing circuit works
  • the clock generation control circuit generates a timing timing signal, and turns on or off the receiving circuit periodically;
  • step C When the receiving circuit is in the open state, if there is the same frequency signal, the output port will produce data change, go to step E; if there is no same frequency signal, the output port will remain high;
  • step E after the control chip is woken up, the control chip directly outputs a control command to make the receiving circuit be in a working state within a time set by the control chip, and if the signal is an invalid signal during the working time period (and internal control chip) If the stored ID code is different, the receiving circuit is turned off, the timing circuit is turned on, the control chip enters the sleep state, and the process goes to step B; if the signal is a valid signal, the corresponding command is executed, and the receiving circuit is directly controlled to be turned on. After the execution of the command is completed, the receiving circuit is turned off, the timing circuit is turned on, the control chip enters the sleep state, and the process proceeds to step ⁇ .
  • This method is to control the chip to connect the receiving circuit, and directly control the receiving circuit to be in an open state under certain conditions.
  • the control chip outputs a command to the clock generation control circuit, and the clock generation control circuit causes the receiving circuit to be in a working state within a time set by the control chip, and if the signal is in the working time period
  • the receiving circuit is turned off, the timing circuit is turned on, the control chip enters the sleep state, and the process goes to step B; if the signal is a valid signal, the corresponding command is executed, and The output command is given to the clock generation control circuit, and the receiving circuit is always turned on by the clock generation control circuit.
  • the receiving circuit is closed, the timing circuit is turned on, the control chip enters the sleep state, and the process proceeds to step ⁇ .
  • This method is to control the chip.
  • the receiving circuit is not directly connected, but the receiving circuit is turned on under certain conditions by the clock generation control circuit.
  • the control chip since the clock generation control circuit periodically turns on the receiving circuit, and only when the receiving circuit has an output signal, the control chip can be woken up, so the control chip is generally in a sleep state (or standby state), and the control chip is in standby state.
  • the power consumption is generally around a few micro-amps at zero, which is far less than the power consumption of the control chip (a few milliamps), and far less than the power consumption of the dual-frequency control chip in the low-frequency state (tens of microamps). Left and right), so the invention can greatly reduce the power consumption of the control chip, thereby enabling the control circuit to save power.
  • Fig. 1 is a block diagram showing the circuit configuration of a control circuit in the embodiment.
  • Fig. 2 is a block diagram showing the configuration of a clock generation control circuit in the embodiment.
  • Fig. 3 is a circuit diagram of a clock generation control circuit in the embodiment.
  • Fig. 4 is a block diagram showing the configuration of a receiving circuit in the embodiment.
  • Fig. 5 is a circuit diagram showing the structure of a receiving circuit in the embodiment.
  • Figure 6 is a block diagram showing the structure of a received data squelch circuit in the embodiment.
  • Fig. 7 is a circuit diagram showing the structure of a receiving data squelch circuit in the embodiment.
  • Figure 8 is a flow chart showing the operation of the control chip in the embodiment.
  • Fig. 9 is a timing chart showing the operation of the clock generation control circuit in the embodiment.
  • Fig. 10 is a timing chart showing the operation of the receiving circuit in the embodiment.
  • Fig. 11 is a timing chart showing the operation of the control chip in the embodiment.
  • Fig. 12 is a timing chart showing the operation of the receiving circuit in the embodiment. detailed description
  • the low-power control circuit described in the embodiment is used for controlling the DC motor of the automatic curtain, and includes a receiving circuit 101, a control chip 102 (multi-chip microcomputer), a clock generation control circuit 104, a memory 107, and a receiving circuit.
  • the 101 signal is connected to the control chip 102.
  • the control chip 102 is connected to the memory 107, the DC motor 103 (i.e., one of the actuators), and the clock generation control circuit 104 is connected to the receiving circuit 101 and the control chip 102, respectively.
  • there is a dry battery 105 of dry 15V and the power circuit 106 supplies the voltage of 15V output from the dry battery 105 to 5V to supply power to each circuit.
  • the clock generation control circuit 104 includes a switch circuit 2, an RC bridge 3, a clock generation control power supply circuit 1, an oscillation enable control circuit 4, the switch circuit 2 is electrically connected to the RC bridge 3, and the clock generation control power supply circuit 1 is
  • the switching circuit and the RC bridge provide power, the control chip 102 is connected to the oscillation enable control circuit 4, and the oscillation enable control circuit 4 is connected to the switch circuit 2; the timing delay of the oscillation circuit and the proportional coefficient of the duty ratio are provided, and the oscillation is made.
  • the control circuit can be used to control the opening/closing of the low-power timing generator circuit to cooperate with the overall circuit.
  • the switching circuit is a wide-value oscillation analog switching circuit, which provides the necessary threshold value comparison of the entire circuit.
  • the power circuit is a two diode series step-down circuit.
  • the input voltage of the power supply circuit is 3V.
  • the operating voltage supplied to the wide-value oscillation analog switch circuit is 1.6V, and the output voltage of the wide-value oscillation analog switch circuit is still 3V, which can reduce the switching circuit.
  • Power consumption the power consumption of this clock generation control circuit is very low, typically 0.1 microamps. Since the oscillation enable control circuit 4 and the RC bridge 3 are known circuits, they will not be described in detail. See Figure 4, Figure 5
  • the receiving circuit is a wireless receiving circuit, and the used carrier frequency band is near 433.42 MHz, which includes: a high frequency receiving LC frequency selecting circuit (also referred to as a high frequency receiving frequency selecting circuit) 5 , Function: used for matching 1/ 4 wavelength receiving antenna, and through LC loop parameters, high Q resonance near the 433.42MHz carrier frequency band to provide high receiver sensitivity; pre-low noise high-discharge circuit 6, function: receive the pre-stage circuit 5
  • the high frequency signal near the 433.42 MHz carrier frequency band of the nanovolt is amplified to enhance the receiver sensitivity and compensate for the insertion attenuation of the lower stage circuit 7; the acoustic surface narrowband filter circuit 7, function: the high level of the preamplifier circuit 6 received and amplified
  • the frequency carrier signal is accurately filtered to intercept a carrier frequency modulated signal of a fundamental frequency (433.42 MHz) ⁇ 1 , and input to the lower level circuit 8;
  • the high frequency receiving LC frequency selection circuit signal is output to the front low noise high discharge circuit 6, the front low noise high discharge circuit 6 signal is output to the acoustic surface narrow band filter circuit 7, and the acoustic surface narrow band filter circuit 7 signal is output to the superheterodyne reception.
  • the memory 14 and the crystal oscillator 15 are electrically connected to the single chip circuit 13, respectively.
  • the received data squelch circuit 12 includes two parts: an analog integral proportional circuit 16, a logic processing circuit 17, and a received signal strength level RSSI of the super-heterodyne receiving circuit 8 is output to the analog integral proportional circuit 16, superheterodyne reception
  • the data processing loop data IF/DATA and the local output data DATA of the circuit 8 are output to the logic processing circuit 17, and the analog-scale analog analog signal is output to the logic processing circuit 17, which outputs a low-noise signal.
  • the analog integral proportional circuit 16 includes an integrating resistor R8, a discharging resistor R9, an integrating capacitor C19, a discharging resistor R9 and an integrating capacitor C19 in parallel, and one end of the discharging resistor R9 and the integrating capacitor C19 in parallel is grounded, and the other end is respectively connected to the logic processing.
  • An input of the circuit 17 and an output of the integrating resistor R8, the received signal strength level output of the superheterodyne receiving circuit 8 is connected to the input of the integrating resistor R8.
  • the logic processing circuit 17 is a logic processing chip.
  • the noise in the signal output from the superheterodyne receiving circuit 8 can be completely shielded, so that the zero-noise output of the infinite receiving circuit can be realized.
  • the control chip is in a sleep state, and the timing circuit works
  • the clock generation control circuit 104 (i.e., the timing circuit described in Fig. 8) generates a timing timing signal to the receiving circuit every 330 seconds (i.e., ms) (i.e., the reception described in FIG.
  • the machine sends an instruction to open the receiving circuit for 2 seconds, and after 2 seconds, the receiving circuit is turned off;
  • 902 determine if 200 milliseconds is up, if it is to go to 903, if not, go to 908;
  • the timing circuit 104 is issued a command, the timing circuit starts working according to its working sequence, enters 905;
  • control chip enters a sleep state, all circuits operate at low power, enter 906;
  • the receiver is powered, the main program runs, and the received signal is decoded and judged within 200 milliseconds of working time. If the signal is invalid (different from the ID code stored in the chip itself), To 902; if the signal is a valid signal, the corresponding command is executed, and after the execution of the command ends, the receiving circuit is turned off, and the process goes to step 902.
  • the power consumption of the clock generation control circuit 104 during normal operation is about 0.1 microamperes, and the power consumption of the control chip is about 0.8 microamperes. It is far less than the power consumption of the dual frequency control chip in the low frequency state (about several tens of microamps), so the invention can greatly reduce the power consumption of the control chip, thereby saving the control circuit power.

Description

一种低功耗控制电路及其工作方式 技术领域
本发明涉及控制电路， 尤其是涉及一种低功耗控制电路及其工作方法。 背景技术
随着科技的发展， 越来越多的设备的执行依靠电路控制， 如： 电动窗帘、 电动门窗、 电灯等。 这些控制电路一般包括接收电路、 控制芯片， 接收电路信 号连接控制芯片， 控制芯片连接执行机构（这里所述的执行机构可以是电动门、 电动窗、 电动窗帘、 电灯等）， 接收电路用于接收命令信息， 控制芯片用于向执 行机构发出各种执行命令。 此外还配有电源电路向接收电路和控制芯片提供电 源， 由于接收电路和控制芯片一直处于工作状态， 而接收电路和控制芯片工作 时都需要消耗电能， 但是实际上大部分时间内是没有命令信息输入的， 因此在 没有命令输入的情况下， 接收电路和控制芯片消耗的电能都是无用的， 这样就 造成了电能的浪费。 尤其是接收电路、 控制芯片、 执行机构全部釆用电池供电 的情况下， 电池的电能大部分是消耗在接收电路、 控制芯片上， 而不是消耗在 执行机构上， 使得电池的电能很快就能消耗完， 从而要不断地更换电池。 如： 直流管状电机的控制电路， 一般情况下接收电路工作电流为 7 个毫安左右， 控 制芯片的工作电流也通常为 7个毫安左右， 如果电池是 1800毫安时的电池块， 可以供接收电路和控制芯片工作 100多个小时， 也就是说 5天内就可以将电能 消耗殆尽。 但是 1800毫安的电池块可以使 380毫安电机（电机一般一次的运行 时间为 30秒）， 可以运行 570次， 如果一天两次操作， 几乎可以用一年。 从此 可以看出， 所消耗的能量主要是用在平时的接收电路、 控制芯片上。
现在中国专利 200580009297.7公开了一种低功率 Rf控制系统，其实质上是 一种低功耗控制电路。 该专利釆用双频率控制芯片， 一般情况下控制芯片处于 低频控制状态，低频状态一般消耗在 20-30微安左右， 高频的时候为 7个毫安左 右， 同时， 接收模块也有两种状态， 休眠状态和工作状态， 休眠状态下为 2个 微安左右， 工作状态下为 7 个毫安左右。 控制芯片定时打开接收模块使其处于 工作状态 1 毫秒左右。 一般几十个毫秒打开一次接收电路， 这样， 接收电路的 耗电率可以节省几十倍。 控制芯片由于在很多时候处于低频状态下， 所以也比 原来的控制芯片一直处于高频状态下大大节省了电能， 但是， 由于控制芯片处 于低频状态的情况下依然要消耗 20-30微安左右， 所以仍然要消耗不少能量。 发明内容
本发明的所要解决的技术问题之一是提供一种低功耗控制电路， 釆用这种 控制电路可以降低控制芯片的电能消耗， 从而使控制电路节约电能。
本发明所述的低功耗控制电路， 包括接收电路、 控制芯片， 接收电路信号 连接控制芯片， 控制芯片连接执行机构， 其特征在于， 还包括时钟发生控制电 路， 时钟发生控制电路分别信号连接接收电路和控制芯片。
所述的时钟发生控制电路包括开关电路、 RC桥路、时钟发生控制电源电路、 振荡使能控制电路，开关电路与 RC桥路电连接， 时钟发生控制电源电路向开关 电路、 RC桥路提供电源， 控制芯片信号连接振荡使能控制电路， 振荡使能控制 电路信号连接开关电路。 这是一种时钟发生控制电路的实施方式。
所述的开关电路为阔值振荡模拟开关电路。 这种电路可以减少功耗。
所述的电源电路为降压电路。 这样可以降低开关电路功耗， 从而进一步降 低时钟发生控制电路功耗。
所述的降压电路为二极管串联降压电路。 这种降压电路降压比较准确。 所述接收电路为无线接收电路， 该电路包括： 高频接收选频电路、 超外差 接收电路、 中频滤波器、 晶体本机谐振电路、 接收数据静噪电路， 上述电路之 间电连接。 这样可以降低超外差接收电路出来的信号中出来的噪声。
所述接收数据静噪电路包括两个部分： 模拟积分比例电路、 逻辑处理电路， 超外差接收电路的接收信号强度电平输出到模拟积分比例电路， 超外差接收电 路的数据处理回路数据和本机输出数据输出到逻辑处理电路， 模拟积分比例的 模拟量信号输出到逻辑处理电路， 逻辑处理电路输出低噪声信号。 这种设计可 以通过模拟积分比例电路来判断收到的模拟信号是否为认可的载波频段， 如果 是就允许逻辑处理电路对信号进行处理； 如果不是， 就不允许逻辑处理电路对 信号进行处理， 这样就可以将非工作状态的输出信号屏蔽掉， 从而可以实现无 限接收电路零噪声输出。
本发明所要解决的技术问题之二是提供一种可以使控制电路实现低功耗的 方法。
本发明所述的方法包括以下步骤：
A、 控制芯片处于休眠状态， 定时电路工作；
B、 时钟发生控制电路产生定时时序信号， 定时打开或关闭接收电路；
C、接收电路处于打开状态时， 如果有同频信号， 输出端口就会产生数据变 化， 转到步骤 E; 如果没有同频信号， 输出端口一直维持高电平；
D、 接收电路处于关闭状态时， 接收电路不工作；
E、 唤醒控制芯片，控制芯片输出控制命令使接收电路在控制芯片设定的时 间内处于工作状态（例如 200毫秒 ), 在该段工作时间内， 对接收的信号做出解 码判断， 如果该信号为无效信号 （和自己控制芯片内部储存的 ID码不同 ), 就 关闭接收电路， 打开定时电路， 控制芯片进入休眠状态， 转到步骤 B; 如果该信 号为有效信号， 就执行相应的命令， 命令执行结束后， 关闭接收电路， 打开定 时电路， 进入休眠状态， 转到步骤^
所述步骤 E中， 唤醒控制芯片后， 控制芯片直接输出控制命令使接收电路 在控制芯片设定的时间内处于工作状态， 在该段工作时间内如果该信号为无效 信号 （和自己控制芯片内部储存的 ID码不同 ), 就关闭接收电路， 打开定时电 路， 控制芯片进入休眠状态， 转到步骤 B; 如果该信号为有效信号， 就执行相应 的命令， 并直接控制接收电路一直处于打开状态， 命令执行结束后， 关闭接收 电路， 打开定时电路， 控制芯片进入休眠状态， 转到步骤^ 这种方法是控制芯 片连接接收电路， 在一定条件下直接控制接收电路处于打开状态。 所述步骤 E中， 唤醒控制芯片后，控制芯片输出命令给时钟发生控制电路， 通过时钟发生控制电路使接收电路在控制芯片设定的时间内处于工作状态， 在 该段工作时间内如果该信号为无效信号 （和自己控制芯片内部储存的 ID码不 同）， 就关闭接收电路， 打开定时电路， 控制芯片进入休眠状态， 转到步骤 B; 如果该信号为有效信号， 就执行相应的命令， 并输出命令给时钟发生控制电路， 通过时钟发生控制电路控制接收电路一直处于打开状态， 命令执行结束后， 关 闭接收电路， 打开定时电路， 控制芯片进入休眠状态， 转到步骤^ 这种方法是 控制芯片不直接连接接收电路， 而是通过时钟发生控制电路使接收电路在一定 条件下处于打开状态。
本发明由于釆用时钟发生控制电路定时打开接收电路， 而只有在接收电路 有输出信号时， 才能唤醒控制芯片， 所以控制芯片一般都在休眠状态 （或称待 机状态）， 而控制芯片待机时的功耗一般在零点几个微安左右， 既远远小于控制 芯片工作时的功耗（几个毫安左右）， 也远远小于双频率控制芯片在低频状态的 功耗（几十个微安左右）， 所以本发明可以大大降低控制芯片的电能消耗， 从而 使控制电路节约电能。 附图说明
图 1是实施例中的控制电路的电路结构框图。
图 2是实施例中的时钟发生控制电路的结构框图。
图 3是实施例中的时钟发生控制电路的电路图。
图 4是实施例中的接收电路结构方框图。
图 5是实施例中的接收电路的电路结构示意图。
图 6是实施例中的接收数据静噪电路结构方框图。
图 7是实施例中的接收数据静噪电路的电路结构示意图。
图 8是实施例中的控制芯片的工作流程图。
图 9是实施例中的时钟发生控制电路工作时序图。 图 10是实施例中的接收电路工作时序图。
图 11是实施例中的控制芯片工作时序图。
图 12是实施例中的接收电路工作时序图。 具体实施方式
实施例
参看图 1
实施例中所述的低功耗控制电路是用在自动窗帘的直流电机的控制上， 包 括接收电路 101、 控制芯片 102 (多釆用单片机）、 时钟发生控制电路 104、 储存 器 107 , 接收电路 101信号连接控制芯片 102, 控制芯片 102连接储存器 107、 直流电机 103 (也就是执行机构中的一类 ), 时钟发生控制电路 104分别信号连 接接收电路 101和控制芯片 102。 此外， 还配有干 15V的干电池 105 , 电源电路 106将干电池 105输出的 15V的电压变压为 5V后给各个电路供电。
参看图 2、 图 3
所述的时钟发生控制电路 104包括开关电路 2、 RC桥路 3、 时钟发生控制 电源电路 1、 振荡使能控制电路 4, 开关电路 2与 RC桥路 3电连接， 时钟发生 控制电源电路 1向开关电路、 RC桥路提供电源， 控制芯片 102信号连接振荡使 能控制电路 4, 振荡使能控制电路 4信号连接开关电路 2; 提供振荡电路的时序 延时及占空比的比例系数， 振荡使能控制电路,功能:用于控制低功耗时序发生器 电路的开启 /关闭,从而配合整体电路工作， 所述的开关电路为阔值振荡模拟开关 电路， 提供整个电路所必须的阔值比较及逻辑状态转换； 所述的电源电路为两 个二极管串联降压电路。 电源电路的输入电压为 3V, 经过两个二极管串联降压 后， 提供给阔值振荡模拟开关电路的工作电压为 1.6V, 而阔值振荡模拟开关电 路的输出电压还是 3V, 这样可以降低开关电路功耗， 这种时钟发生控制电路的 功耗很低， 一般在 0.1微安。 在此由于振荡使能控制电路 4、 RC桥路 3都是已 知的电路， 就不对它们进行具体描述。 参看图 4、 图 5
所述接收电路为无线接收电路， 釆用的载波频段为 433.42MHz附近， 其包 括： 高频接收 LC选频电路（也可以称为高频接收选频电路） 5 , 功能： 用于匹 配 1/4波长接收天线， 并通过 LC回路参数， 高 Q值的谐振于 433.42MHz载波 频段附近， 以提供高的接收机灵敏度； 前置低噪声高放电路 6, 功能： 将前级电 路 5接收到的毫微伏的 433.42MHz载波频段附近得高频信号进行放大，以增强接 收机灵敏度及补偿下级电路 7的插入衰减； 声表面窄带滤波电路 7, 功能： 将前 级电路 6接收并放大后的高频载波信号进行精确过滤， 以截取基频 (433.42MHz) ± 1ΚΗζ的载波数据调制信号， 并输入至下级电路 8中； .超外差接收电路 8, 功 能： 接收机电路主功能芯片， 用于对前级电路 7接收到的高频载波信号的选频 放大， 外差式载波数据解调， 基带数据恢复， 数据滤波及放大整形功能， 并将 处理后的接收数据输入至下级电路 12; 中频滤波器 9, 功能： 10.7 MHz声表面 波中频滤波器， 其为电路 8部分的 IF中频限副放大器提供低噪声输入回路； 晶 体本机谐振电路 10, 功能： 晶体振荡器串联谐振回路， 其为电路 8部分的 PLL 本振电路提供谐振基准， 使其准确接收于 433.42MHz载波频段； 接收机低功耗 控制端口 11 , 功能： 用于电路 8部分的接收状态 /待机状态切换， 从而控制电路 8部分功耗； 接收数据静噪电路 12, 功能： 接收电路 8的信号强度电平 （英文 缩写 RSSI )、 数据处理回路（英文 IF/DATA )、 本机输出数据（英文 DATA )、 三 路信号进行模拟比例及逻辑静噪处理， 从而实现接收机零噪声输出， 并将处理 后的数据输入至下级电路 13; 单片机电路 13 , 功能： 将前级电路 12输入的数 据进行数字解码处理； 存储器 14, 功能： 其为电路 13的外设辅件， 用于存储电 路 13程序运行中的常量配置数据； 晶振 15, 功能： 其为电路的外设辅件， 用 于产生电路 13运行所必须的时钟脉冲。
高频接收 LC选频电路信号输出到前置低噪声高放电路 6,前置低噪声高放 电路 6信号输出到声表面窄带滤波电路 7,声表面窄带滤波电路 7信号输出到超 外差接收电路 8, 超外差接收电路 8信号输出到接收数据静噪电路 12, 接收数 据静噪电路 12信号输出到单片机电路 13 , 单片机电路 13信号输出到电机； 中 频滤波器 9、晶体本机谐振电路 10和接收机低功耗控制端口 11分别与超外差接 收电路 8电连接； 存储器 14和晶振 15分别与单片机电路 13电连接。
参看图 6、 图 7
所述的接收数据静噪电路 12包括两个部分：模拟积分比例电路 16、逻辑处 理电路 17,超外差接收电路 8的接收信号强度电平 RSSI输出到模拟积分比例电 路 16, 超外差接收电路 8的数据处理回路数据 IF/DATA和本机输出数据 DATA 输出到逻辑处理电路 17, 模拟积分比例的模拟量信号输出到逻辑处理电路 17 , 逻辑处理电路 17输出低噪声信号。 所述的模拟积分比例电路 16包括积分电阻 R8、 放电电阻 R9、 积分电容 C19, 放电电阻 R9和积分电容 C19并联， 放电电 阻 R9和积分电容 C19并联后的一端接地， 另一端分别连接到逻辑处理电路 17 的一个输入端和积分电阻 R8的输出端，超外差接收电路 8的接收信号强度电平 输出端连接积分电阻 R8的输入端。 所述的逻辑处理电路 17是一个逻辑处理芯 片。
釆用实施例中的这种电路设计， 可以使超外差接收电路 8输出的信号中的 噪声完全屏蔽掉， 从而可以实现无限接收电路零噪声输出。
下面结合附图简介一下实施例中的低功耗控制电路的工作过程。
参看图 8-图 12
1、 开始；
2、 控制芯片处于休眠状态， 定时电路工作；
3、 参看图 9、 图 12, 时钟发生控制电路 104 (即图 8中所述的定时电路） 产生定时时序信号， 每隔 330秒（即 ms )向接收电路（即图 8中所述的接收机） 发出指令打开接收电路 2秒钟， 2秒钟以后接收电路处于关闭状态；
4、 接收电路处于打开状态时， 如果有同频信号， 输出端口就会产生数据变 化， 转到步骤 6; 如果没有同频信号， 输出端口一直维持高电平；
5、 接收电路处于关闭状态时， 接收电路不工作； 6、 参看图 8 , 唤醒控制芯片， 执行以下步骤：
901、 唤醒控制芯片， 控制芯片的定时器开始 200毫秒计时；
902、 判断 200毫秒是否到时， 如果是转到 903 , 如果不是， 转到 908;
903、 切断接收机和其他电路电源， 电路进入低功耗状态， 进入 904;
904、向定时电路 104发出命令，定时电路按其工作时序开始工作，进入 905;
905、 控制芯片进入休眠状态， 所有电路低功耗运行， 进入 906;
906、 判断相应的口线是否为低， 为高一直休眠， 为低单片机会被唤醒， 进 入 901 ;
908、 接收机通电， 主程序各项功能运行， 在 200毫秒工作时间内， 对接收 的信号做出解码判断， 如果该信号为无效信号 （和自己控制芯片内部储存的 ID 码不同）， 就转到 902; 如果该信号为有效信号， 就执行相应的命令， 命令执行 结束后， 才关闭接收电路， 转到步骤 902。
这样设计的控制电路，时钟发生控制电路 104正常工作时的功耗是 0.1微安 左右， 控制芯片的功耗为为 0.8微安左右。远远地小于双频率控制芯片在低频状 态的功耗（几十个微安左右）， 所以本发明可以大大降低控制芯片的电能消耗， 从而使控制电路节约电能。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明， 不 能认定本发明的具体实施只局限于这些说明。 对于本发明所属技术领域的普通 技术人员来说， 在不脱离本发明构思的前提下， 还可以做出若干简单推演或替 换， 如： 所述的时钟发生控制电路 104 中的电源电路也可以釆用三个以上的二 极管串联或其他降压电路； 执行机构也可以是电灯等其他部件等， 都应当视为 属于本发明的保护范围。

Claims

权 利 要求
1、 一种低功耗控制电路， 包括接收电路、 控制芯片， 接收电路信号连接控 制芯片， 控制芯片连接执行机构， 其特征在于， 还包括时钟发生控制电路， 时 钟发生控制电路分别信号连接接收电路和控制芯片。
2、 根据权利要求 1所述的一种低功耗控制电路， 其特征在于， 所述时钟发 生控制电路， 包括开关电路、 RC桥路、 时钟发生控制电源电路、 振荡使能控制 电路， 开关电路与 RC桥路电连接， 时钟发生控制电源电路向开关电路、 RC桥 路提供电源， 控制芯片信号连接振荡使能控制电路， 振荡使能控制电路信号连 接开关电路。
3、 根据权利要求 2所述的一种低功耗控制电路， 其特征在于， 所述的开关 电路为阔值振荡模拟开关电路。
4、 根据权利要求 2或 3所述的一种低功耗控制电路， 其特征在于， 所述的 电源电路为降压电路。
5、 根据权利要求 4所述的一种低功耗控制电路， 其特征在于， 所述的降压 电路为二极管串联降压电路。
6、 根据权利要求 1或 2或 3所述的一种低功耗控制电路， 其特征在于， 所 述接收电路为无线接收电路， 该电路包括： 高频接收选频电路、 超外差接收电 路、 中频滤波器、 晶体本机谐振电路、 接收数据静噪电路， 上述电路之间电连 接。
7、 根据权利要求 6所述的一种低功耗控制电路， 其特征在于， 所述接收数 据静噪电路包括两个部分： 模拟积分比例电路、 逻辑处理电路， 超外差接收电 路的接收信号强度电平输出到模拟积分比例电路， 超外差接收电路的数据处理 回路数据和本机输出数据输出到逻辑处理电路， 模拟积分比例的模拟量信号输 出到逻辑处理电路， 逻辑处理电路输出低噪声信号。
8、 一种低功耗控制电路的工作方法， 包括以下步骤： A、 控制芯片处于休眠状态， 定时电路工作；
B、 时钟发生控制电路产生定时时序信号， 定时打开或关闭接收电路；
C、 接收电路处于打开状态时， 如果有同频信号， 输出端口就会产生数据变 化， 转到步骤 E; 如果没有同频信号， 输出端口一直维持高电平；
D、 接收电路处于关闭状态时， 接收电路不工作；
E、 唤醒控制芯片， 控制芯片输出控制命令使接收电路在控制芯片设定的时 间内处于工作状态（例如 200毫秒 ), 在该段工作时间内， 对接收的信号做出解 码判断， 如果该信号为无效信号 （和自己控制芯片内部储存的 ID码不同 ), 就 关闭接收电路， 打开定时电路， 控制芯片进入休眠状态， 转到步骤 B; 如果该信 号为有效信号， 就执行相应的命令， 命令执行结束后， 关闭接收电路， 打开定 时电路， 进入休眠状态， 转到步骤^
9、 根据权利要求 8所述的一种低功耗控制电路的工作方法， 其特征在于， 所述步骤 E 中， 唤醒控制芯片后， 控制芯片直接输出控制命令使接收电路在控 制芯片设定的时间内处于工作状态， 在该段工作时间内如果该信号为无效信号
(和自己控制芯片内部储存的 ID码不同）， 就关闭接收电路， 打开定时电路， 控制芯片进入休眠状态， 转到步骤 B; 如果该信号为有效信号， 就执行相应的命 令， 并直接控制接收电路一直处于打开状态， 命令执行结束后， 关闭接收电路， 打开定时电路， 控制芯片进入休眠状态， 转到步骤^
10、 根据权利要求 8所述的一种低功耗控制电路的工作方法， 其特征在于， 所述步骤 E 中， 唤醒控制芯片后， 控制芯片输出命令给时钟发生控制电路， 通 过时钟发生控制电路使接收电路在控制芯片设定的时间内处于工作状态， 在该 段工作时间内如果该信号为无效信号（和自己控制芯片内部储存的 ID码不同 ), 就关闭接收电路， 打开定时电路， 控制芯片进入休眠状态， 转到步骤 B; 如果该 信号为有效信号， 就执行相应的命令， 并输出命令给时钟发生控制电路， 通过 时钟发生控制电路控制接收电路一直处于打开状态， 命令执行结束后， 关闭接 收电路， 打开定时电路， 控制芯片进入休眠状态， 转到步骤^
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