WO2010079530A1

WO2010079530A1 - Circuit and method for digital-analog conversion

Info

Publication number: WO2010079530A1
Application number: PCT/JP2009/000028
Authority: WO
Inventors: 小島昭二
Original assignee: 株式会社アドバンテスト
Priority date: 2009-01-07
Filing date: 2009-01-07
Publication date: 2010-07-15
Also published as: JP5226085B2; JPWO2010079530A1

Abstract

A reference voltage generating circuit (10) applies an upper reference voltage (VRH) to a first reference voltage terminal (P1), and a lower reference voltage (VRL) to a second reference voltage terminal (P2) in a first state (S1), and the reference voltage generating circuit applies the voltages by opposite polarities in a second state (S2). A first switch group (SWG1) selects one tap, which corresponds to a digital input signal (DIN) from among a plurality of taps (T₁-T_n+1) in the first state, and in the second state, the first switch group selects a tap at a position symmetrical to the tap selected in the first state.

Description

Digital / analog conversion circuit and method

The present invention relates to a digital / analog conversion circuit (DAC), and more particularly to a resistor string type DAC.

In order to convert a digital signal into an analog signal, various DACs including a resistor string type, an R-2R type, and a segment R-2R type are used. The resistor string type DAC includes a plurality of resistors directly connected between two reference voltages, and a switch group that selects one of voltages generated at a connection point (tap) between adjacent resistors. The resistor string type DAC controls a switch group according to the value of the digital input signal, and outputs an analog voltage according to the value of the digital signal.
US Pat. No. 5,343,199 US Pat. No. 4,462,021 US Pat. No. 5,014,054 US Pat. No. 5,343,199

When a resistor string type DAC is integrated as an LSI on a semiconductor substrate, variations in the accuracy of individual resistors become a problem. In this case, the resistance accuracy is
1. Random variation Classified as position-dependent variation. The position-dependent variation tends to have monotonic increase (or monotonic decrease) with respect to the coordinates. Due to such an error in resistance value, the resistance string type DAC is excellent in differential non-linearity (DNL) but poor in integral non-linearity (INL). Have

In order to improve the INL of the resistor string type DAC, several techniques for devising the layout of a plurality of resistors have been proposed (see Patent Documents 2 to 4), but there is room for further improvement.

The present invention has been made in view of such a situation, and an object thereof is to provide a highly accurate resistor string type DAC.

An embodiment of the present invention relates to a digital / analog conversion circuit that outputs an analog voltage corresponding to a digital input signal. The digital / analog conversion circuit includes a first reference voltage terminal, a second reference voltage terminal, an output terminal, a resistor string, a plurality of taps, a reference voltage generation circuit, a first switch group, an output unit, Is provided. The resistor string includes a plurality of resistors provided in series between the first and second reference voltage terminals. A plurality of taps are provided for each connection point of each resistor, and are provided for extracting a voltage generated in the corresponding resistor. The reference voltage generation circuit generates a predetermined upper reference voltage and a predetermined lower reference voltage, and applies the upper reference voltage to the first reference voltage terminal and the lower reference voltage to the second reference voltage terminal in the first state. In the second state, the lower reference voltage is applied to the first reference voltage terminal, and the upper reference voltage is applied to the second reference voltage terminal. The first switch group selects one of the plurality of taps according to the digital input signal in the first state, and selects a tap at a position symmetrical to the tap selected in the first state in the second state. . The output unit averages and outputs the output voltage of the first switch group in the first state and the output voltage of the first switch group in the second state.

According to this aspect, the two reference voltage terminals of the resistor string type DAC are exchanged for one digital input signal to perform D / A conversion twice, and the analog voltage generated in each is averaged. Therefore, it is possible to suitably cancel the in-plane variation of the resistance and realize high-precision digital / analog conversion.

The output unit may include a first capacitor having a fixed potential at one end, a second capacitor having a fixed potential at one end, and a second switch group. The second switch group has a state in which the first capacitor is charged by the voltage of the tap selected by the first switch group in the first state, and a second capacitor by the voltage of the tap selected by the first switch group in the second state. And a state in which a voltage obtained by averaging the voltage of the first capacitor and the voltage of the second capacitor is output from the output terminal may be switched.

The output unit includes a first sample and hold circuit that samples and holds the output voltage of the first switch group in the first state, a second sample and hold circuit that samples and holds the output voltage of the first switch group in the second state, 1 and an averaging circuit that averages the output voltage of the second sample and hold circuit.

The digital / analog conversion circuit according to an aspect may further include a buffer that receives the output voltage of the first switch group and outputs the output voltage to the output unit. According to this aspect, the processing can be speeded up when the output impedance of the first switch group is high or when the load of the output unit is heavy.

A digital / analog conversion circuit according to an aspect controls a first switch group according to a first control signal having a predetermined relationship with a digital input signal in a first state, and 2 of the digital input signal in a second state. A decoder circuit for controlling the first switch group in accordance with a second control signal having a predetermined relationship with the complement of each other may be further provided.
By providing a circuit for generating the 2's complement of the digital input signal, the position of the tap to be selected by the first switch group can be easily inverted.

In one aspect, the second switch group includes a first switch provided between the output of the first switch group and the first capacitor, and a second switch provided between the output of the first switch group and the second capacitor. And a third switch provided between the first capacitor and the output terminal, and a fourth switch provided between the second capacitor and the output terminal.

In one aspect, the second switch group includes a first switch provided between the output of the first switch group and the first capacitor, and a second switch provided between the output of the first switch group and the second capacitor. And a fifth switch provided between the output of the first switch group and the output terminal. In this case, the number of switches can be reduced.

In one aspect, the second switch group includes a sixth switch having a first capacitor connected to one output terminal and a second capacitor connected to the other output terminal, an output of the first switch group, A seventh switch provided between the input terminal of the switch, a third switch provided between the first capacitor and the output terminal, a fourth switch provided between the second capacitor and the output terminal, May be included.

When the digital input signal is m bits (m is a natural number), the first switch group may include a plurality of switch elements arranged in a tournament of m stages starting from a plurality of taps. The switch element of the i-th stage (1 ≦ i ≦ m) is controlled according to the lower i-th bit of the digital input signal in the first state and according to the inverted signal of the lower i-th bit of the digital input signal in the second state. May be.

When the digital input signal is m bits (m is a natural number), the resistors of the resistor string form a matrix of α rows and β columns (α = 2 ^K , β = 2 ^L , K + L = m, all natural numbers). In this way, it may be arranged in a folded manner. The first switch group includes α row lines associated with the matrix rows, β column lines associated with the matrix columns, a plurality of output switches, and a plurality of switch elements. But you can.
The plurality of output switches may be provided in association with α row lines, and each may be provided between the corresponding row line and the output terminal of the first switch group. The plurality of switch elements are arranged in a matrix in association with the plurality of resistors, and one end of each switch element is connected to the corresponding resistor, and the other end of the switch element in the i-th row (1 ≦ i ≦ α). May be connected to the i-th row line, and the control terminal of the switch element in the j-th column (1 ≦ i ≦ β) may be connected to the j-th column line. On / off of the plurality of output switches may be controlled according to the upper K bits of the digital input signal in the first state and according to the two's complement of the upper K bits of the digital input signal in the second state. On / off of the plurality of switch elements may be controlled according to the lower L bits of the digital input signal in the first state and according to the two's complement of the lower L bits of the digital input signal in the second state.

In one embodiment, the digital / analog conversion circuit may include a multi-channel output. A plurality of output units may be provided for each of a plurality of channels. The digital / analog conversion circuit may alternately use a plurality of output units for each digital input signal data in a time-sharing manner.
In this case, the output voltage of the digital / analog conversion circuit can be continuously held, and a hold circuit or the like is not required in the subsequent stage.

It should be noted that an arbitrary combination of the above-described constituent elements and those in which constituent elements and expressions of the present invention are mutually replaced between methods and apparatuses are also effective as an aspect of the present invention.

According to an aspect of the present invention, a highly accurate digital / analog conversion circuit can be realized.

1 is a circuit diagram showing a configuration of a digital / analog conversion circuit according to a first embodiment. FIG. 2 is a time chart illustrating an operation of the digital / analog conversion circuit of FIG. 1. It is a figure which shows the input-output characteristic of the digital / analog converting circuit of FIG. It is a circuit diagram which shows the structure of the digital / analog converting circuit which concerns on a 1st modification. 5 is a time chart illustrating an operation of the digital / analog conversion circuit of FIG. 4. It is a circuit diagram which shows the structure of the digital / analog converting circuit which concerns on a 2nd modification. 7 is a time chart illustrating the operation of the digital / analog conversion circuit of FIG. 6. It is a circuit diagram which shows the structure of the digital / analog converting circuit which concerns on a 3rd modification. It is a circuit diagram which shows the structure of the digital / analog converting circuit based on a 4th modification. 10 is a time chart illustrating an operation of the digital / analog conversion circuit of FIG. 9. It is a circuit diagram which shows the structure of the digital / analog converting circuit based on a 5th modification. It is a circuit diagram which shows the structure of the digital / analog converting circuit based on a 6th modification. It is a circuit diagram which shows the structure of the digital / analog converting circuit based on a 7th modification. It is a circuit diagram which shows the structure of the digital / analog converting circuit based on 2nd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 2 ... Resistor string, 10 ... Reference voltage generation circuit, 20 ... Decoder circuit, 30 ... Control part, SWG1 ... 1st switch group, SWG2 ... 2nd switch group, P1 ... 1st reference voltage terminal, P2 ... 2nd reference voltage Terminal, P3 ... output terminal, C1 ... first capacitor, C2 ... second capacitor, 100 ... digital / analog conversion circuit, SW1 ... first switch, SW2 ... second switch, SW3 ... third switch, SW4 ... fourth switch , SW5, fifth switch, SW6, sixth switch, SW7, seventh switch, OUT, output section, SH1, first sample and hold circuit, SH2, second sample and hold circuit SH2, and averaging circuit 40.

Hereinafter, the present invention will be described based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. The case where it is indirectly connected through another member that does not affect the state is also included. Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

In this specification, alphabets i, j, n, m, s, t, K, L, Greek letters α, β, and the like indicate integers. In addition, “#” represents logical inversion or two's complement.

(First embodiment)
FIG. 1 is a circuit diagram showing a configuration of a digital / analog conversion circuit 100 according to the first embodiment. The digital / analog conversion circuit 100 converts the digital input signal DIN into an analog voltage DACOUT and outputs it from the output terminal P3. The digital input signal DIN is m-bit binary data [Bm-1: B0], and the case where m = 3 is illustrated in the figure.

The digital / analog conversion circuit 100 includes a resistor string (R ₁ to R _n ), a plurality of voltage taps T ₁ to T _{n + 1} , a reference voltage generation circuit 10, a decoder circuit 20, a first switch group SWG1, a second switch group SWG2, An output unit OUT is provided. In FIG. 1, the relationship n = 2 ^m −1 is satisfied.

A plurality of resistors R ₁ to R _n provided in series between the first reference voltage terminal P 1 and the second reference voltage terminal P 2 form a resistor string 2. The connection point between the adjacent resistors R _i and R _{i + 1} (i = 1, 2,..., N−1) and the first reference voltage terminal P1 and the second reference voltage terminal P2 have (n + 1) pieces for taking out the voltage. Taps T ₁ to T _{n + 1} are provided. The plurality of resistors R ₁ to R _n are regularly arranged on the semiconductor chip in order, and more specifically, the plurality of resistors R ₁ to R _n are arranged with symmetry (point symmetry or line symmetry).

The reference voltage generation circuit 10 generates a predetermined upper reference voltage VRH and a lower reference voltage VRL. In the first state S1, the reference voltage generation circuit 10 applies the upper reference voltage VRH to the first reference voltage terminal P1 and the lower reference voltage VRL to the second reference voltage terminal P2. In the second state S2, the lower reference voltage VRL is applied to the first reference voltage terminal P1, and the upper reference voltage VRH is applied to the second reference voltage terminal P2. That is, it is possible to apply voltages having opposite polarities between the first reference voltage terminal P1 and the second reference voltage terminal P2 in the first state S1 and the second state S2.

The reference voltage generation circuit 10 includes two-input one-output switches SWI1 and SWI2. Each of the switches SWI1 and SWI2 receives a control signal φ1 that takes different values in the first state S1 and the second state S2. Specifically, φ1 = 0 in the first state S1, and φ1 = 1 in the second state S2. The upper reference voltage VRH is input to one input terminal of the switch SWI1, and the lower reference voltage VRL is input to the other input terminal. The same applies to the switch SWI2.

The switch SWI1 selects the upper reference voltage VRH in the first state S1 (φ1 = 0), selects the lower reference voltage VRL in the second state S2 (φ1 = 1), and selects the selected voltage as the first reference. Apply to voltage terminal P1. Similarly, the switch SWI2 selects the lower reference voltage VRL in the first state S1 (φ1 = 0), selects the upper reference voltage VRH in the second state S2 (φ1 = 1), and selects the selected voltage. This is applied to the second reference voltage terminal P2.

The 2-input 1-output switch shown in each drawing in this specification indicates a state in which 0 is input as a control signal. When 1 is input, it conducts to the input node side opposite to the figure.

The first switch group SWG1 selects _one of the voltages (tap voltages) V ₁ to V _{n + 1} generated in the plurality of taps T ₁ to T _{n + 1} according to the digital input signal DIN, and outputs it from the intermediate terminal P4.

Specifically, in the first state S1, the first switch group SWG1 selects one T _s (1 ≦ s ≦ n + 1) corresponding to the digital input signal DIN from the plurality of taps T ₁ to T _{n + 1} . In the second state S2, a tap T _t (1 ≦ t ≦ n + 1) at a position symmetrical to the tap T _s selected in the first state S1 is selected. Here, (t + s) / 2 = (n + 1) / 2 is established.

The topology of the first switch group SWG1 is arbitrary, but in the embodiment of FIG. 1, for example, the switch elements SW connected in a tree shape for selecting the tap voltages V ₁ to V _{n + 1} in a tournament manner in m stages. [0, 1], SW [0, 2], SW [0, 3], SW [0, 4], SW [1, 1], SW [1, 2], SW [2, 1]. Each switch element SW [i, j] has two inputs and one output.

The connection state of the switch SW [i, j] is controlled by the control signal Ci corresponding to the bit Bi of the digital input signal DIN.

The two input terminals of the switch SW [0, j] are connected to the taps T _2j-1 and T _2j , respectively.
The two input terminals of the switch SW [i, j] (i ≠ 0) are connected to the switches SW [i−1,2j−1] and SW [i−1,2j], respectively.

The decoder circuit 20 generates control signals C0 to C2 for controlling the first switch group SWG1. Specifically, in the first state S1, the decoder circuit 20 controls the first switch group SWG1 according to the control signal [C2: C0] having a predetermined relationship with the digital input signal DIN (= [B2: B0]). To do. In the second state S2, the first switch group SWG1 is controlled in accordance with the second control signal [C2: C0] having a predetermined relationship with the two's complement (#DIN) of the digital input signal DIN.
In the first state S1, Ci = Bi, and in the second state S2, Ci = # Bi.

The decoder circuit 20 of FIG. 1 includes a plurality of exclusive OR gates XOR0 to XOR2 associated with each bit [B2: B0] of the digital input signal DIN.
The gate XORi outputs an exclusive OR of the bit Bi and the control signal φ1 as the control signal Ci. With this configuration, the value of the digital input signal DIN can be converted to 2's complement in the second state S2.

The output unit OUT averages the output voltage of the first switch group SWG1 in the first state S1 and the output voltage of the first switch group SWG1 in the second state S2, and outputs it as an analog voltage DACOUT.

The output unit OUT can be configured by using the property of a capacitor that stores electric charge according to voltage. The output unit OUT includes a first capacitor C1, a second capacitor C2, and a second switch group SWG2.

The potential of one end of the first capacitor C1 is fixed. The same applies to the second capacitor C2. The voltages generated in the first capacitor C1 and the second capacitor C2 are referred to as a first capacitor voltage VC1 and a second capacitor voltage VC2. The capacitance values of the first capacitor C1 and the second capacitor C2 are designed to be equal.

The second switch group SWG2 is configured so that the following three states can be switched.
1. 1. State in which the first capacitor C1 is charged by the output voltage of the first switch group SWG1 in the first state S1. 2. State in which the second capacitor C2 is charged by the output voltage of the first switch group SWG1 in the second state S2. A state in which the charges of the first capacitor C1 and the second capacitor C2 are averaged, and the average voltage of the first capacitor voltage VC1 and the second capacitor voltage VC2 is applied to the output terminal P3.

If the above three functions can be switched, the configuration of the second switch group SWG2 is arbitrary. For example, the second switch group SWG2 in FIG. 1 includes a first switch SW1, a second switch SW2, a third switch SW3, and a fourth switch SW4.

The first switch SW1 is provided between the output terminal (intermediate terminal) P4 of the first switch group SWG1 and the first capacitor C1. The second switch SW2 is provided between the intermediate terminal P4 and the second capacitor C2. The third switch SW3 is provided between the first capacitor C1 and the output terminal P3 of the digital / analog conversion circuit 100. The fourth switch SW4 is provided between the second capacitor C2 and the output terminal P3 of the digital / analog conversion circuit 100. The first switch SW1 to the fourth switch SW4 are switches with one input and one output. When 0 is input as a control signal, the first switch SW1 to the fourth switch SW4 are turned off (shut off). In each figure, a switch with 1 input and 1 output shows a state in which 0 is input as a control signal. The first switch SW1 is controlled according to the control signal φ2, the second switch SW2 is controlled according to the control signal φ3, and the third switch SW3 and the fourth switch SW4 are controlled according to the common control signal φ4.

The control unit 30 generates control signals φ1 to φ4.

The buffer BUF1 receives the potential of the intermediate terminal P4 and outputs it to the output unit OUT. When the capacitances of the first capacitor C1 and the second capacitor C2 are large, or when the output impedance of the first switch group SWG1 is high (current supply capability is low), the charging time of the first capacitor C1 and the second capacitor C2 is long. There is a problem of becoming. Therefore, the charging time can be shortened by providing the buffer BUF1. The buffer BUF1 may be a voltage follower circuit having a gain of 1 using an operational amplifier, an amplifier having a gain larger than 1, or an attenuator having a gain smaller than 1. That is, any circuit having an output impedance sufficient to charge the first capacitor C1 and the second capacitor C2 may be used.

Two buffers BUF1 may be provided in the charging paths of the first capacitor C1 and the second capacitor C2, respectively.

On the other hand, when the capacitance values of the first capacitor C1 and the second capacitor C2 are small or the output impedance of the first switch group SWG1 is sufficiently low (the current supply capability is high), the buffer BUF1 may be omitted. . Alternatively, even when the charging time of the first capacitor C1 and the second capacitor C2 becomes long, the signal processing can be omitted.

Also in the digital / analog conversion circuit shown in the other figures, it is needless to say that the buffer BUF1 can be provided as necessary, but for the sake of simplicity of explanation, the buffer BUF1 is omitted in the following figures.

The above is the configuration of the digital / analog conversion circuit 100. Next, the operation will be described. FIG. 2 is a time chart illustrating the operation of the digital / analog conversion circuit 100 of FIG.

A period t0 to t7 indicates one cycle of D / A conversion. At time t0, the value of the digital input signal DIN changes. The value is “4” in decimal. At time t0, the control signal φ1 becomes low level (0), and the reference voltage generation circuit 10 is set to the first state S1. In this state, the decoder circuit 20 generates control signals C0 to C2 according to the digital input signal DIN. At this time, the voltage selected by the first switch group SWG1 is an analog voltage corresponding to the digital input signal DIN, and ideally coincides with the value 4. However, in reality, the resistances R ₁ to R _n vary. Thus, the voltage deviates from 4. After the value of the digital input signal DIN is determined, when the control signal φ2 becomes high level at time t1 and the first switch SW1 is turned on, the first capacitor C1 is charged with the voltage selected by the first switch group SWG1, 1 capacitor voltage VC1 rises. The first capacitor voltage VC1 coincides with the output voltage of the first switch group SWG1 in the first state S1 after a certain period of time. At time t2, the control signal φ2 becomes low level, and the first switch SW1 is turned off.

Subsequently, at time t3, the control signal φ1 becomes high level (1), and the reference voltage generation circuit 10 is set to the second state S2. In this state, the decoder circuit 20 supplies the 2's complement of the digital input signal DIN as the control signals C0 to C2 to the first switch group SWG1. Also in the second state S2, the voltage selected by the first switch group SWG1 is an analog voltage corresponding to the digital input signal DIN and ideally matches the value 4, but in reality, the resistors R ₁ to R due to variations in R _n, it becomes a voltage shifted from 4. At time t4, when the control signal φ3 becomes a high level and the second switch SW2 is turned on, the second capacitor C2 is charged with the voltage selected by the first switch group SWG1, and the second capacitor voltage VC2 rises. The second capacitor voltage VC2 coincides with the output voltage of the first switch group SWG1 in the second state S2 after a certain time. When the second capacitor voltage VC2 is stabilized, the control signal φ3 becomes low level at time t5, and the second switch SW2 is turned off.

When the control signal φ4 becomes high level at the subsequent time t6, both the third switch SW3 and the fourth switch SW4 are turned on, and the charges of the first capacitor C1 and the second capacitor C2 are smoothed. As a result, the first capacitor voltage VC1 and the second capacitor voltage VC2 are averaged, and the respective voltages converge to the average value voltage (VC1 + VC2) / 2.

The average voltage is output from the output terminal P3 as an analog voltage DACOUT corresponding to the digital input signal DIN.

The above is the operation of the digital / analog conversion circuit 100. FIG. 3 is a diagram showing input / output characteristics of the digital / analog conversion circuit 100 of FIG. The horizontal axis represents the digital input signal DIN. The first capacitor voltage VC1 indicates a conversion characteristic in the first state S1, and the second capacitor voltage VC2 indicates a conversion characteristic in the second state S2. The variation in resistance values of the resistors R ₁ to R _n of the digital / analog conversion circuit 100 of FIG. 1 shows in-plane dependence. In the first state S1 and the second state S2, the high potential side and low potential of the DAC The side is reversed and used. As a result, the first capacitor voltage VC1 and the second capacitor VC2 have contrasting errors with respect to ideal linear characteristics. In the digital / analog conversion circuit 100 of FIG. 1, the same digital input signal DIN is subjected to D / A conversion in two states, and the output voltages VC1 and VC2 in each state are averaged, thereby causing an error in resistance value. Cancel in-plane variation. As a result, the averaged output voltage DACOUT has a high linearity with respect to the digital input signal DIN.

Thus, according to the digital / analog conversion circuit 100 of FIG. 1, errors that cannot be removed by the conventional layout device can be reduced, and the accuracy can be improved.

In the digital / analog conversion circuit 100 shown in FIG. 1, the output voltage DACOUT is valid only during the period when the control signal φ4 is at a high level. Therefore, a hold circuit that holds the output voltage DACOUT may be provided as necessary. .

FIG. 4 is a circuit diagram showing a configuration of the digital / analog conversion circuit 100a according to the first modification. The digital / analog conversion circuit 100a differs from the digital / analog conversion circuit 100 of FIG. 1 in the topology of the first switch group SWG1a and the second switch group SWG2a, and accordingly, the configuration of the decoder circuit 20a is different. ing.

Focusing on the first switch group SWG1a, the switch elements SW [0,1], SW [0,2], SW [0,3], SW [0,4], SW [1,1], SW [1, 2] is connected in the same manner as in FIG.

In FIG. 4, the configuration of the switch controlled by the control signal Cm-1 (= C2) corresponding to the most significant bit Bm-1 of the digital input signal DIN is different. Specifically, instead of the switch element SW [m−1, 1] of FIG. 1, switch elements SW [m−1, 1] and SW [m−1, 2] having one input and one output are provided. Yes. The switch element SW [m−1, 1] is provided between the output terminal of the switch element SW [m−2, 1] and the intermediate terminal P4. The switch element SW [m-1, 2] is provided between the output terminal of the switch element SW [m-2, 2] and the intermediate terminal P4. It fulfills a part of the function of the second switch group SWG2 of FIG.

The decoder circuit 20a further includes AND gates AND1 and AND2 in addition to the decoder circuit 20 of FIG. The gate AND1 generates a logical product of the control signal φ2 and the control signal C2, and outputs the logical product as the control signal C21 of the switch element SW [m−1, 1]. The gate AND2 generates a logical product of the inversion # C2 of the control signal C2 and the control signal φ2, and outputs the logical product as the control signal C22 of the switch element SW [m−1, 2].

The second switch group SWG2a includes a first switch SW1, a second switch SW2, and a fifth switch SW5. The switch elements SW [m−1, 1] and SW [m−1, 2] described above are also part of the second switch group SWG2a.

The fifth switch SW5 is provided between the intermediate terminal P4 and the output terminal P3 of the digital / analog conversion circuit 100a.

The above is the configuration of the digital / analog conversion circuit 100a in FIG. Next, the operation will be described. FIG. 5 is a time chart illustrating the operation of the digital / analog conversion circuit 100a of FIG.

A period t0 to t9 indicates one cycle of D / A conversion. At time t0, the value of the digital input signal DIN changes. At time t1, the control signal φ1 becomes low level, and the reference voltage generation circuit 10 is set to the first state S1. In this state, the decoder circuit 20 generates control signals C0, C1, C21, and C22 according to the digital input signal DIN. After the value of the digital input signal DIN is determined, when the control signal φ2 becomes high level at time t2, one of the control signals C21 and C22 becomes high level, and any of the taps T ₁ to T _{n + 1} is applied to the intermediate terminal P4. Voltage is generated.

When the control signal φ3 becomes high level at time t2, the first switch SW1 is turned on, the first capacitor C1 is charged with the voltage selected by the first switch group SWG1, and the first capacitor voltage VC1 rises. At time t3, the control signal φ3 becomes low level, and the first switch SW1 is turned off.

Subsequently, at time t4, the control signal φ1 becomes high level, and the reference voltage generation circuit 10 is set to the second state S2. In this state, the decoder circuit 20 generates control signals C0, C1, C21, and C22 corresponding to the two's complement #DIN of the digital input signal DIN, and supplies the control signals C0, C1, C21, and C22 to the first switch group SWG1a. At time t5, when the control signal φ4 becomes high level and the second switch SW2 is turned on, the second capacitor C2 is charged with the voltage selected by the first switch group SWG1, and the second capacitor voltage VC2 rises. When the second capacitor voltage VC2 is stabilized, the control signal φ2 becomes low level at time t6, and both the switch elements SW [2,1] and SW [2,2] are turned off.

When the control signal φ3 becomes high level again at the subsequent time t7, the first capacitor C1 and the second capacitor C2 are coupled via the first switch SW1 and the second switch SW2, and the first capacitor voltage VC1 and the second capacitor are coupled. The voltage VC2 is averaged. When the control signal φ5 becomes high level at time t8, the fifth switch SW5 is turned on, and the analog voltage DACOUT corresponding to the digital input signal DIN is output from the output terminal P3.

The above is the operation of the digital / analog conversion circuit 100a. According to the digital / analog conversion circuit 100a of FIG. 4, the number of switches can be reduced as compared with the digital / analog conversion circuit 100 of FIG. 1, which is advantageous in terms of cost and circuit area.

FIG. 6 is a circuit diagram showing a configuration of a digital / analog conversion circuit 100b according to a second modification. The digital / analog conversion circuit 100b differs from the digital / analog conversion circuit 100 of FIG. 1 in the topology of the second switch group SWG2b.

The second switch group SWG2b includes a third switch SW3, a fourth switch SW4, a sixth switch SW6, and a seventh switch SW7.
The sixth switch SW6 has one input and two outputs, and one output terminal is connected to the first capacitor C1, and the other output terminal is connected to the second capacitor C2. The seventh switch SW7 is provided between the input terminal of the sixth switch SW6 and the intermediate terminal P4. The sixth switch SW6 is controlled according to the control signal φ1, and the seventh switch SW7 is controlled according to the control signal φ2.

FIG. 7 is a time chart illustrating the operation of the digital / analog conversion circuit 100b of FIG.

Period t0 to t8 represents one cycle of D / A conversion. At time t0, the value of the digital input signal DIN changes. At time t1, the control signal φ1 becomes low level, and the reference voltage generation circuit 10 is set to the first state S1. In this state, the decoder circuit 20 generates control signals C0 to C2 corresponding to the digital input signal DIN. After the value of the digital input signal DIN is confirmed, when the control signal φ2 becomes high level at time t2, the seventh switch SW7 is turned on, and the output voltage of the first switch group SWG1 is applied to the input terminal of the sixth switch SW6. It is done. At this time, since the control signal φ1 is at the low level, the sixth switch SW6 is conductive to the first capacitor C1 side. As a result, the first capacitor C1 is charged with the voltage selected by the first switch group SWG1. At time t3, the control signal φ2 becomes low level, and the seventh switch SW7 is turned off.

Subsequently, at time t4, the control signal φ1 becomes high level, and the reference voltage generation circuit 10 is set to the second state S2. In this state, the decoder circuit 20 generates control signals C0 to C2 based on the 2's complement of the digital input signal DIN. At subsequent time t5, the control signal φ2 becomes high level again, and the seventh switch SW7 is turned on. At this time, since the control signal φ1 is at a high level, the sixth switch SW6 is electrically connected to the second capacitor C2. As a result, the second capacitor C2 is charged with the voltage selected by the first switch group SWG1. At time t6, the control signal φ2 becomes low level, and the seventh switch SW7 is turned off.

At the subsequent time t7, when the control signal φ3 becomes high level, both the third switch SW3 and the fourth switch SW4 are turned on, the first capacitor C1 and the second capacitor C2 are coupled, and the first capacitor voltage VC1 and the second capacitor SW2 are coupled. An average voltage of the capacitor voltage VC2 is output from the output terminal P3.

FIG. 8 is a circuit diagram showing a configuration of a digital / analog conversion circuit 100c according to a third modification. The digital / analog conversion circuit 100c differs from the digital / analog conversion circuit 100 of FIG. 1 in the topology of the first switch group SWG1.

In FIG. 8, a plurality of resistors R ₁ to R _n are provided in a ninety-nine fold shape so as to form a matrix of α rows and β columns. Specifically, the resistor strings R ₁ to R _n connected in series are arranged so as to be folded back for each row. Here, α = 2 ^K , β = 2 ^L , and K + L = m are established.

Switches MOS ₁ to MOS _n are provided in association with the resistors R ₁ to R _n . In addition, α row lines RL ₁ to RL _α and output switches (transfer gates) TG ₁ to TG _{α associated} with the matrix rows, and β column lines CL ₁ to CL associated with the matrix columns. CL _β is provided. The plurality of switches MOS ₁ to MOS _n and the plurality of output switches TG ₁ to TG _α constitute a first switch group SWG1c.

One end of the i-th (i ≠ n) switch MOS _i is connected to a connection point between the resistors R _i and R _{i + 1} . One end of the n-th switch MOS _n is connected to the connection point of the resistors _{R n} and the second reference voltage terminal P2.

The other end of the switch MOS connected to the i-th resistor R is connected to the i-th row line RL _i . The control terminal (gate) of the switch MOS connected to the resistor R in the j-th column is connected to the column line CL _{j in the} j-th column.

The row line and the column line can be understood as an analogy with the relationship between the row address and the column address in the memory or the relationship between the scanning line and the data line in the display device.

The i-th output switch TG _i is provided between the _i-th row line RL _i and the intermediate terminal P4.

The upper decoder circuit 20U generates signals to be given to the output switches TG ₁ to TG _α based on the upper K bits of the control signals Cm−1 to C0 from the decoder circuit 20. The upper decoder circuit 20U turns on the output switch TG _{x + 1} in the (x + 1) -th row, where x is a value representing the upper K bits of the control signals Cm−1 to C0 in decimal. The configuration of the upper decoder circuit 20U is not limited to the illustrated one.

The lower decoder circuit 20L generates signals to be applied to the column lines CL ₁ to CL _β based on the lower L bits of the control signals Cm−1 to C0 from the decoder circuit 20. The lower decoder circuit 20L turns on the switch MOS _{y + 1} in the (y + 1) -th column, where y is a value representing the lower L bits of the control signals Cm−1 to C0 in decimal. The configuration of the low-order decoder circuit 20L is not limited to that illustrated.

Other configurations are the same as those in FIG. In the digital / analog conversion circuit 100c of FIG. 8, the upper decoder circuit 20H and the lower decoder circuit 20L turn on a switch corresponding to the digital input signal DIN, so that the output terminal P3 of the digital / analog conversion circuit 100c has a digital signal. An analog voltage corresponding to the input signal DIN is generated.

Also by the digital / analog conversion circuit 100c of FIG. 8, the D / A conversion is performed in each of the first state and the second state, and the voltage generated in each is averaged, whereby the same principle as in the above-described embodiment is obtained. Thus, the variation in the resistances R ₁ to R _n can be preferably canceled.

FIG. 9 is a circuit diagram showing a configuration of a digital / analog conversion circuit 100d according to a fourth modification. The digital / analog conversion circuit 100d includes two capacitor pairs C1 and C2 for averaging two voltages generated in the first state and the second state. At the same time, the digital / analog conversion circuit 100d includes two second switch groups SWG2 ₁ and SWG2 ₂ and an output switch SWOUT for switching between the _two second switch groups SWG2 ₁ and SWG2 ₂ .

A set of capacitors C1 ₁ and C2 ₁ and a second switch group SWG2 ₁ (referred to as a first channel CH1), a set of capacitors C1 ₂ and C2 ₂ and a second switch group SWG2 ₂ (referred to as a second channel CH2), Are used alternately in a time-sharing manner.

The control unit 30d generates control signals φ1 to φ8. The switch SW1 ₁ on the first channel side is controlled by a control signal φ2, SW2 ₁ by φ3, and SW3 ₁ and SW4 ₁ by φ4. Switch SW1 ₂ of the second channel side, the control signal .phi.5, SW2 ₂ by .phi.6, SW3 ₂ and SW4 ₂ are controlled by .phi.7. The output switch SWOUT is controlled by a control signal φ8.

FIG. 10 is a time chart illustrating the operation of the digital / analog conversion circuit 100d of FIG. In the period t0 to t7, the first channel side is used, and in the period t7 to t8, the second channel side is used. At each transition of the digital input signal DIN, the level of the control signal φ8 is switched. In the period t0 to t7, the control signal φ8 is at a high level, and the output switch SWOUT is conducted to the second channel CH2 side.

The period t0 to t7 in FIG. 10 corresponds to the period t0 to t7 in FIG.

When the subsequent digital input signal DIN is input at time t7, the control signal φ8 becomes low level, and the first channel CH1 side becomes valid. In the period t7 to t8, the same processing as that in the period t0 to t7 is performed using the second channel CH2. The control signal φ5 transitions at a timing corresponding to φ2, φ6 corresponds to φ3, and φ7 corresponds to φ4.

The effect of the digital / analog conversion circuit 100d of FIG. 9 becomes clear by comparing the time chart of FIG. 10 with other time charts (FIGS. 2, 5, and 7).
For example, referring to the time chart of FIG. 2, the output voltage DACOUT of the digital / analog conversion circuit 100 takes a correct value according to the digital input signal DIN only during the period t6 to t8, and fluctuates during other periods. Depending on the situation in which the digital / analog conversion circuit 100 is used, it is necessary to provide a hold circuit after the digital / analog conversion circuit 100. This has been described above.

On the other hand, referring to the time chart of FIG. 10, two capacitor pairs (C1 ₁ , C2 ₁ ) and (C1 ₂ , C2 ₂ ) are alternately used for each symbol of the digital input signal DIN. Thus, while the capacitor pair C1 ₁ , C2 ₁ of _one channel is used, the charge of the other capacitor pair C1 ₂ , C2 ₂ can be held. In other words, the output voltage DACOUT of the digital / analog conversion circuit 100d can be stabilized for a long time, so that there is an advantage that a hold circuit is unnecessary.

In the digital / analog conversion circuits 100 to 100d described above, potential holding and voltage averaging are performed using capacitors. On the other hand, in the digital / analog conversion circuits 100e to 100g of FIGS. 11 to 13 described below, an equivalent process is performed using a sample and hold circuit.

FIG. 11 is a circuit diagram showing a configuration of a digital / analog conversion circuit 100e according to a fifth modification.

The digital / analog conversion circuit 100e includes a first sample hold circuit SH1, a second sample hold circuit SH2, and an averaging circuit 40 in place of the first capacitor C1, the second capacitor C2, and the second switch group SWG2 in FIG. . The first sample hold circuit SH1 and the second sample hold circuit SH2 respectively sample the potential of the intermediate terminal P4 in synchronization with the control signals φ2 and φ3. The output voltage Vsh1 of the first sample hold circuit SH1 and the output voltage Vsh2 of the second sample hold circuit SH2 are voltages corresponding to the capacitor voltages VC1 and VC2 in FIG. The configurations of the first sample hold circuit SH1 and the second sample hold circuit SH2 are not limited.

The averaging circuit 40 averages the output voltages Vsh1 and Vsh2 of the first sample hold circuit SH1 and the second sample hold circuit SH2 and outputs them as an analog voltage DACOUT from the output terminal P3. Although the configuration of the averaging circuit 40 is not limited, for example, resistance voltage division can be used.

The digital / analog conversion circuit 100e can perform the same processing as the digital / analog conversion circuit 100 of FIG. Further, the analog voltage DACOUT has a merit that it always takes an effective value.

FIG. 12 is a circuit diagram showing a configuration of a digital / analog conversion circuit 100f according to a sixth modification. The digital / analog conversion circuit 100f of FIG. 12 is provided with output terminals P31 to P3M of M channels (M is an integer of 2 or more). For each channel, a first sample hold circuit SH1 and a second sample hold circuit SH2 are provided. A set of averaging circuits 40 (output units OUT1 to OUTM) is also provided.

The control signal φ2i is input to the first sample hold circuit SH1 of the i-th channel, and the control signal φ3i is input to the second sample hold circuit SH2. The control unit 30f asserts the control signals φ2i and φ3i for the channels to be valid in a time division manner at a predetermined timing.

According to the digital / analog conversion circuit 100f of FIG. 12, a single resistor string 2 can be used in a time-sharing manner by a plurality of output units OUT1 to OUTM.

FIG. 13 is a circuit diagram showing a configuration of a digital / analog conversion circuit 100g according to a seventh modification. Similar to the digital / analog conversion circuit 100f of FIG. 12, the digital / analog conversion circuit 100g includes M-channel output terminals P31 to P3M. For each channel, the output sections OUT1 to OUTM and the first switch group SWG11 to SWG1M is provided.

The plurality of first switch groups SWG11 to SWG1M are connected to a common resistor string 2. The i-th channel first switch group SWG1i is controlled by i-channel control signals C0i to C2i generated by a decoder circuit 20 (not shown).

According to the digital / analog conversion circuit 100g in FIG. 13, multi-channel digital / analog conversion can be realized by using a single resistor string 2 in the same manner as the digital / analog conversion circuit 100f in FIG. Further, the time division processing required in the circuit of FIG. 12 becomes unnecessary, and each channel can perform digital / analog conversion simultaneously and in parallel.

(Second Embodiment)
Next, a technique for canceling the resistance variation of the digital / analog conversion circuit by devising the resistor layout based on a concept different from the above embodiment will be described.

FIG. 14 is a circuit diagram showing a configuration of a digital / analog conversion circuit 200 according to the second embodiment. The digital / analog conversion circuit 200 converts the digital input signal DIN into an analog voltage DACOUT and outputs it from the output terminal P3. The digital input signal DIN is binary data [Bm-1: B0] of m bits (m is an integer), and the case where m = 6 is illustrated.

The digital / analog conversion circuit 200 includes a plurality of resistors R ₁ to R _n , switches SW ₀ to SW _n , α row lines RL ₁ to RL _α , β column lines CL ₁ to CL _β , and an output switch SWO. ₁ to SWO _α , an X decoder 210, and a Y decoder 220.

n = 2 ^m , and n = 64 in FIG. The plurality of resistors R ₁ to R _n are connected in series and arranged in a spiral shape. The resistor strings R ₁ to R _n form a matrix of α rows and β columns. An upper reference voltage VRH and a lower reference voltage VRL are applied to both ends of the resistor strings R ₁ to R _n .

Switches

_SW 0 ~ SW _n each end is connected to corresponding resistors _{_R} 1 ~ _R _n. One end of the switch SW arranged in the i-th row is connected to the _i-th row line RL _i . The i-th row output switch SWO _i is provided between the _i-th row line RL _i and the output terminal P3.

The X decoder 210 generates a signal to be given to the switches SW ₀ to SW _n based on the lower L (= 3) bits [B2: B0] in the digital input signal DIN. The X decoder 210 turns on the switch SW in the (y + 1) th column, where y is a value representing the lower L bits in decimal.

The Y decoder 220 generates a signal to be given to the output switches SWO ₁ to SWO _α based on the upper K (= 3) bits [B5: B3] in the digital input signal DIN. The Y decoder 220 turns on the switch SWO _{x + 1} in the (x + 1) -th row, where x is a value representing the upper K bits in decimal.

The functions of the X decoder 210 and the Y decoder 220 may be a logic circuit configured in hardware, or may be realized using software operations.

The above is the configuration of the digital / analog conversion circuit 200. According to the digital / analog conversion circuit 200 of FIG. 14, by arranging the resistor strings R ₁ to R _n in a spiral shape, the influence of the in-plane variation of the resistance value can be preferably canceled, and nonlinearity is improved. can do.

Although the present invention has been described based on the embodiments, the embodiments merely show the principle and application of the present invention, and the embodiments depart from the idea of the present invention defined in the claims. Many modifications and arrangements can be made without departing from the scope.

The present invention can be used for electronic circuits.

Claims

A digital / analog conversion circuit that outputs an analog voltage corresponding to a digital input signal,
A first reference voltage terminal;
A second reference voltage terminal;
An output terminal;
A resistor string including a plurality of resistors provided in series between the first and second reference voltage terminals;
A plurality of taps provided for each connection point of each resistor;
Generating a predetermined upper reference voltage and a predetermined lower reference voltage, and applying the upper reference voltage to the first reference voltage terminal and the lower reference voltage to the second reference voltage terminal in a first state; A reference voltage generating circuit for applying the lower reference voltage to the first reference voltage terminal and the upper reference voltage to the second reference voltage terminal in a second state;
A first tap is selected from the plurality of taps according to the digital input signal in the first state, and a tap at a position symmetrical to the tap selected in the first state is selected in the second state. 1 switch group,
An output unit that averages and outputs the output voltage of the first switch group in the first state and the output voltage of the first switch group in the second state;
A digital / analog conversion circuit comprising:
The output unit is
A first capacitor having a fixed potential at one end;
A second capacitor having a fixed potential at one end;
A state in which the first capacitor is charged by the voltage of the tap selected by the first switch group in the first state, and a state of the second capacitor by the voltage of the tap selected by the first switch group in the second state A second switch group configured to be able to switch between a state in which the first capacitor voltage and a voltage obtained by averaging the voltage of the first capacitor and the voltage of the second capacitor are output from the output terminal;
The digital / analog conversion circuit according to claim 1, comprising:
The output unit is
A first sample and hold circuit that samples and holds an output voltage of the first switch group in the first state;
A second sample-and-hold circuit that samples and holds the output voltage of the first switch group in the second state;
An averaging circuit for averaging the output voltages of the first and second sample and hold circuits;
The digital / analog conversion circuit according to claim 1, comprising:
4. The digital / analog conversion circuit according to claim 1, further comprising a buffer that receives an output voltage of the first switch group and outputs the output voltage to the output unit.
In the first state, the first switch group is controlled according to a first control signal having a predetermined relationship with the digital input signal, and in the second state, the two's complement of the digital input signal and the 4. The digital / analog conversion circuit according to claim 1, further comprising a decoder circuit that controls the first switch group in accordance with a second control signal having a predetermined relationship.
The second switch group includes:
A first switch provided between the output of the first switch group and the first capacitor;
A second switch provided between the output of the first switch group and the second capacitor;
A third switch provided between the first capacitor and the output terminal;
A fourth switch provided between the second capacitor and the output terminal;
The digital / analog conversion circuit according to claim 2, comprising:
The second switch group includes:
A first switch provided between the output of the first switch group and the first capacitor;
A second switch provided between the output of the first switch group and the second capacitor;
A fifth switch provided between the output of the first switch group and the output terminal;
The digital / analog conversion circuit according to claim 2, comprising:
The second switch group includes:
A sixth switch having one output terminal connected to the first capacitor and the other output terminal connected to the second capacitor;
A seventh switch provided between the output of the first switch group and the input terminal of the sixth switch;
A third switch provided between the first capacitor and the output terminal;
A fourth switch provided between the second capacitor and the output terminal;
The digital / analog conversion circuit according to claim 2, comprising:
When the digital input signal is m bits (m is a natural number)
The first switch group includes a plurality of switch elements arranged in an m-stage tournament starting from the plurality of taps, and the i-th (1 ≦ i ≦ m) switch elements are in the first state. 4. The control according to claim 1, wherein control is performed in accordance with a lower i-th bit of the digital input signal in accordance with an inverted signal of the lower i-th bit of the digital input signal in the second state. The digital / analog conversion circuit described.
When the digital input signal is m bits (m is a natural number)
The plurality of resistors of the resistor string are arranged in a folded manner so as to form a matrix of α rows and β columns (α = 2 K , β = 2 L , K + L = m, all natural numbers),
The first switch group includes:
Α row lines associated with rows of the matrix;
Β column lines associated with columns of the matrix;
A plurality of output switches provided in association with the α row lines, each provided between a corresponding row line and an output terminal of the first switch group;
A plurality of switch elements arranged in a matrix in association with the plurality of resistors, wherein one end of each switch element is connected to the corresponding resistor, and the i-th row (1 ≦ i ≦ α) The other end of the switch element is connected to the i-th row line, and the control terminal of the switch element in the j-th column (1 ≦ i ≦ β) is connected to the j-th column line. When,
Including
On / off of the plurality of output switches is controlled according to the upper K bits of the digital input signal in the first state and according to the two's complement of the upper K bits of the digital input signal in the second state. The on / off of the plurality of switch elements is controlled according to the lower L bits of the digital input signal in the first state and according to the two's complement of the lower L bits of the digital input signal in the second state. The digital / analog conversion circuit according to claim 1, wherein:
This digital / analog converter circuit has a multi-channel output,
A plurality of the output units are provided for each of a plurality of channels,
4. The digital / analog conversion circuit according to claim 1, wherein a plurality of the output units are alternately used in a time division manner for each data of the digital input signal.
A method of converting a digital input signal into an analog voltage,
A first step of applying an upper reference voltage to one end of a resistor string including a plurality of resistors provided in series and applying a lower reference voltage to the other end;
A second step of selecting one corresponding to the digital input signal from a plurality of taps provided for each connection point of each resistor;
Applying a lower reference voltage to the one end of the resistor string and applying an upper reference voltage to the other end;
A fourth step of selecting a tap at a position symmetrical to the tap selected in the second step from the plurality of taps;
A fifth step of averaging and outputting the two voltages selected in each of the second step and the fourth step;
A method comprising the steps of: