WO2010074537A2 - Convolutional turbo coding method and device for implementing the coding method - Google Patents

Convolutional turbo coding method and device for implementing the coding method Download PDF

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WO2010074537A2
WO2010074537A2 PCT/KR2009/007791 KR2009007791W WO2010074537A2 WO 2010074537 A2 WO2010074537 A2 WO 2010074537A2 KR 2009007791 W KR2009007791 W KR 2009007791W WO 2010074537 A2 WO2010074537 A2 WO 2010074537A2
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bit
sequences
bits
information bits
subblock
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French (fr)
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WO2010074537A3 (en
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Zhao ZHENG
Seung-Hoon Choi
Sung-Eun Park
Chi-Woo Lim
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/23—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using convolutional codes, e.g. unit memory codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/258—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with turbo codes, e.g. Turbo Trellis Coded Modulation [TTCM]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H03M13/296—Particular turbo code structure
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/3988—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes for rate k/n convolutional codes, with k>1, obtained by convolutional encoders with k inputs and n outputs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6522—Intended application, e.g. transmission or communication standard
    • H03M13/6544—IEEE 802.16 (WIMAX and broadband wireless access)
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0059—Convolutional codes
    • H04L1/006—Trellis-coded modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H04L1/0066—Parallel concatenated codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving

Definitions

  • the present invention relates to a coding method in a wireless mobile communication system. More particularly, the present invention relates to a Convolutional Turbo Coding (CTC) method and a device for implementing the method.
  • CTC Convolutional Turbo Coding
  • WiMAX Mobile Worldwide Interoperability for Microwave Access
  • IEEE Institute of Electrical and Electronics Engineers
  • the mobile WiMAX standard was proposed after the IEEE 802.16d fixed WiMAX standard was proposed.
  • the mobile WiMAX aims to support mobility of the broadband access by building on research started during the standardization of the fixed WiMAX standard.
  • Convolutional Turbo Code is a class of Turbo code using several convolution coding schemes.
  • the CTC is incorporated into the IEEE 802.16 and Digital Video Broadcasting - Return Channel via Satellite (DVB-RCS) standards because of its high error correction performance.
  • DVD-RCS Digital Video Broadcasting - Return Channel via Satellite
  • FIG. 1 illustrates a CTC encoder according to the related art. Referring to FIG. 1, the
  • CTC encoder may comprise a 1/3 CTC encoder 101, an interleaver 102 and a puncturing unit 103.
  • input information bits are input to the 1/3 CTC encoder 101.
  • the number of encoded output information bits and parity bits is three times the number of information bits.
  • the encoded data is then interleaved by the interleaver 102.
  • the puncturing unit 103 punctures the interleaved data based on the transmission rate, i.e., it chooses the data bits to be transmitted and obtains the encoded bit sequence so as to complete the encoding process.
  • the 1/3 CTC encoder 101 may comprise a CTC interleaver 105 and a constituent encoder 104.
  • the inputs A and B to the CTC interleaver 105 represent the input information bits, which are encoded twice.
  • the duo binary CRSC coding is performed on the in- formation bits A and B. That is, a set of information bits A 1 and B 1 are simultaneously input to the constituent encoder 104 for encoding, and parity sequences Y 1 and Wi are obtained.
  • the information bits A and B are also interleaved by the CTC interleaver 105.
  • the second constituent encoding process is then performed to the interleaved sequences.
  • interleaved information bits A j and B j are simultaneously input to the constituent encoder 104 so as to obtain parity sequences Y 2 and W 2 .
  • the interleaver 102 may comprise a symbol separation module, a subblock interleaving module and a symbol grouping module.
  • the symbol separation module is used to allocate the information bits and the encoded bits to 6 subblocks, which are in turn A, B, Y 1 , Y 2 , Wi and W 2 described above.
  • the subblock interleaving module is used to interleave these 6 subblocks respectively within each of the subblocks. The interleaving order is the same for each subblock.
  • FIG. 2 illustrates subblock interleaving operations according to the related art.
  • a symbol separation module separates encoded bits into subblocks A, B, Yi, Y 2 , Wi and W 2 in step 201.
  • a subblock interleaving performs an interleaving operation to the subblocks A, B, Yi, Y 2 , Wi and W 2 in step 202 and a symbol grouping module groups the interleaved subblocks in step 203.
  • subblocks A and B are output by the symbol grouping module, and the two subblocks Yi and Y 2 and the two subblocks Wi and W 2 are alternately output.
  • the output sequences are A' o , A' ls , A' N-1 ; B' o , B' ls , B' N- i; Y'1,0, Y'2,0, Y' 1,1. Y'2,1, ,
  • the reliability refers to an average distance between a constellation point of which a certain mapped bit is "0" and a constellation point of which this mapped bit is "1" in a modulation constellation. The larger the distance, the greater the reliability of the mapped bit.
  • M-QAM Quadrature Amplitude Modulation
  • high order modulation is an unequal error protection modulation.
  • BERs Bit Error Rates
  • Inner points of the constellation have less energy and thus may be subject to fading more easily. Accordingly, the bits constituting these symbols are less reliable. In contrast, the bits constituting the points outside the constellation are more reliable.
  • FIG. 3 illustrates reliability of bit mapping of high order modulation according to the related art.
  • FIG. 4 illustrates a constituent encoder of a 1/3 CTC encoder implementing duo binary CRSC coding according to the related art.
  • the input bit A 1 401 and the input bit B 1 402 are used as a set of inputs to the 1/3 CTC encoder, and the parity bits Y 1 and W 1 embody the combined information of the information bit A 1 and the information bit B 1 .
  • the bit A 1 and the bit B 1 should be considered as a whole and treated like a group unit.
  • the bit A 1 is mapped to a bit with high reliability
  • the bit B 1 is also mapped to a bit with high reliability.
  • bit A 1 is mapped to a bit with low reliability
  • bit Bi is also mapped to a bit with low reliability.
  • the information bits in the sequence A and the information bits in the sequence B that are simultaneously input to the constituent encoder are said to constitute a bit group. Therefore, from the perspective of the group unit (A 1 , B 1 ), different group units have unequal bit reliability. Some group units have high reliability whereas some have low reliability.
  • An aspect of the present invention is to address at least the above-mentioned problems and/or disadvantages and to provide at least the advantages described below.
  • a Convolutional Turbo Coding (CTC) method is provided. The method includes the steps of encoding information bits A and B using a constituent encoder, and outputting parity sequences Yi and Wi, interleaving the information bits A and B using a CTC interleaver to obtain information bits C and D, and encoding the interleaved information bits C and D using the constituent encoder to obtain parity sequences Y 2 and W 2 , interleaving the information bits A and B, the parity sequences Y 1 and Wi and the parity sequences Y 2 and W 2 , respectively, wherein the bits in at least one of a bit group constituted of the information bits A and B, a bit group constituted of the sequences Y 1 and Wi, and a bit group constituted of the sequences Y 2 and W 2 are alternately mapped to bits
  • an apparatus for CTC includes a constituent encoder for encoding information bits A and B and outputting parity sequences Y 1 and W 1 , a CTC interleaver for interleaving the information bits A and B to obtain new information bits C and D, and for providing the interleaved information bits C and D to the constituent encoder for encoding to obtain parity sequences Y 2 and W 2 , an interleaver for interleaving the information bits A and B, the parity sequences Y 1 and W 1 and the parity sequences Y 2 and W 2 , respectively, wherein the bits in at least one of a bit group constituted of the information bits A and B, a bit group constituted of the sequences Y 1 and W 1 , and a bit group constituted of the sequences Y 2 and W 2 are alternately mapped to bits of constellation points with high reliability and low reliability, and a puncturing unit for puncturing the output sequences from the interleaver
  • an apparatus for a turbo encoder includes an interleaved information subblock A, an interleaved information subblock B, wherein information subblocks A and B are bypassed, a bit-by-bit multiplexed parity sequence of interleaved Y 1 and Y 2 subblock sequences, the bit-by-bit multiplexed sequence of interleaved Y 1 and Y 2 subblock sequences consisting of a first output bit from a Y 1 subblock interleaver, a first output bit from a Y 2 subblock interleaver, a second output bit from the Y 1 subblock interleaver, and a second output bit from the Y 2 subblock interleaver, and a bit-by-bit multiplexed parity sequence of the interleaved W 2 and W 1 subblock sequences, the bit- by-bit multiplexed sequence of interleaved W 2 and W 1 subblock sequences
  • a 1 and B 1 are combined for bit mapping. Furthermore, the bit reliability of high order modulation is taken into account during the mapping so that the reliability of the coding is improved.
  • FIG. 1 illustrates a Convolutional Turbo Code (CTC) according the related art
  • FIG. 2 illustrates subblock interleaving operations according to the related art
  • FIG. 3 illustrates reliability of bit mapping of high order modulation according to the related art
  • FIG. 4 illustrates a constituent encoder of a 1/3 CTC encoder implementing duo binary Circular Recursive Systematic Convolutional (CRSC) coding according to the related art
  • FIG. 5 illustrates remapping operations according to a first exemplary embodiment of the present invention
  • FIG. 6 illustrates remapping operations according to a second exemplary embodiment of the present invention.
  • FIG. 7 illustrates remapping operations according to a third exemplary embodiment of the present invention.
  • Exemplary embodiments of the present invention provide improvements in a symbol grouping module, such as the interleaver 102 of the Convolutional Turbo Code (CTC) illustrated in FIG. 1.
  • CTC Convolutional Turbo Code
  • sequence A' is mapped first. Then, the corresponding bit in sequence B' that is input to the CTC encoder simultaneously with each bit in sequence A' is found.
  • the bit that is input to the CTC encoder simultaneously with A ⁇ is denoted as B' r B' j is referred to as a group unit corresponding bit of A ⁇ .
  • sequence B' is mapped. If A ⁇ is mapped to a bit with high reliability, its group unit corresponding bit B' j should be mapped to a bit with low reliability. Also, if A ⁇ is mapped to a bit with low reliability, its group unit corresponding bit B' j should be mapped to a bit with high reliability.
  • sequence Y'i may be mapped first. Then, the corresponding bit in sequence W i that is output from the CTC encoder simultaneously with each bit in sequence Y'i is found.
  • the parity bit that is output from the CTC encoder simultaneously with Y'i 4 is denoted as Wi 0 .
  • W'i j is referred to as a group unit corresponding unit of Y' I 1 . Then, sequence W'i is mapped. If Y' I 1 is mapped to a bit with high reliability, its group unit corresponding bit Wi 0 should be mapped to a bit with low reliability.
  • sequence Y' 2 can also be mapped first. Then, the corresponding bit in sequence W 2 that is output from the CTC encoder simultaneously with each bit in sequence Y' 2 is found.
  • the parity bit that is output from the CTC encoder simultaneously with Y' 2il is denoted as W' 2j .
  • W 2j is referred to as a group unit corresponding bit of Y' 2 l . Then, sequence W 2 is mapped. If Y' 2il is mapped to a bit with high reliability, its group unit corresponding bit W' 2j should be mapped to a bit with low reliability.
  • Y' 2il is mapped to a bit with low reliability
  • its group unit corresponding bit W 2j should be mapped to a bit with high reliability.
  • the parity bits in sequence Y' 2 and the bits in sequence W 2 which are simultaneously output from the constituent encoder, constitute a bit group.
  • the above three exemplary schemes can be implemented independently, by combining any two of them together, or by combining all of them together. According to a result of a simulation, the least performance gain is obtained by only applying the second or third schemes. If both the second and third schemes are applied, the per- formance gain increases a little. When only the first scheme is applied, the performance is superior to that obtained by applying both the second and third schemes. If the first, second, and third schemes are applied, the best performance would generally be obtained.
  • FIG. 5 illustrates remapping operations according to a first exemplary embodiment of the present invention.
  • the outputs from a subblock interleaving module in an interleaver are sequences A', B', Y' ls Y' 2 , W 1 ,W 2 .
  • A', B', Y' ls Y' 2 , W 1 ,W 2 are specifically arranged as A' o , A'i, , A' N-1 ; B' o , B'i, , B' N-1 ; YV Y'u, , Y' I,N-I; Y' 2 ,O, Y' 2 ,I, , YVi; W' !,0, Wu, , WV -1 ; w' 2 ,o, wv , w
  • sequence A' is mapped first. Based on the IEEE 802.16e standard, the corresponding bit in sequence B' that is input to the CTC encoder simultaneously with A ⁇ is B ⁇ . Then, sequence B' is mapped. If A ⁇ is mapped to a bit with high reliability, its group unit corresponding bit B ⁇ should be mapped to a bit with low reliability. Also, if A ⁇ is mapped to a bit with low reliability, its group unit corresponding bit B ⁇ should be mapped to a bit with high reliability.
  • FIG. 6 illustrates remapping operations according to a second exemplary embodiment of the present invention.
  • sequence Y'i is mapped first.
  • the parity bit that is output from the CTC encoder simultaneously with Y' !4 is W 1 1 .
  • sequence W 1 is mapped. If Y' l4 is mapped to a bit with high reliability, its group unit corresponding bit W 1 1 should be mapped to a bit with low reliability. Also, if Y' !4 is mapped to a bit with low reliability, its group unit corresponding bit Wi 4 should be mapped to a bit with high reliability.
  • sequence Y' 2 is mapped.
  • the parity bit that is output from the CTC encoder simultaneously with Y' 24 is W 24 .
  • sequence W 2 is mapped. If Y' 24 is mapped to a bit with high reliability, its group unit corresponding bit W 24 should be mapped to a bit with low reliability. Also, if Y' 24 is mapped to a bit with low reliability, its group unit corresponding bit W 24 should be mapped to a bit with high reliability.
  • alternate mapping may be performed first to the bits in the bit group constituted of sequences A' and B', and then to the bit group constituted of sequences Y'i and W'i or the bit group constituted of sequences Y' 2 and W 2 , respectively.
  • a third exemplary embodiment of the present invention that combines the first and second exemplary embodiments of the present invention is described below with reference to FIG. 7.
  • FIG. 7 illustrates remapping operations according to a third exemplary embodiment of the present invention.
  • sequence A' can be mapped first.
  • the corresponding bit in sequence B' that is input to the CTC encoder simultaneously with A ⁇ is B ⁇ .
  • sequence B' is mapped. If A ⁇ is mapped to a bit with high reliability, its group unit corresponding bit B ⁇ should be mapped to a bit with low reliability. Also, if the A ⁇ is mapped to a bit with low reliability, its group unit corresponding bit B ⁇ should be mapped to a bit with high reliability.
  • sequence Y'i is mapped. In the IEEE 802.16e standard, the parity bit that is output from the CTC encoder simultaneously with Y'i 4 is Wi 11 . Then, sequence Wi is mapped.
  • Y' I 1 is mapped to a bit with high reliability
  • its group unit corresponding bit Wi 4 should be mapped to a bit with low reliability.
  • the Y'i 4 is mapped to a bit with low reliability
  • its group unit corresponding bit Wi 11 should be mapped to a bit with high reliability.
  • sequence Y' 2 is mapped.
  • the parity bit that is output from the CTC encoder simultaneously with Y' 24 is W 24 .
  • sequence W 2 is mapped. If Y' 24 is mapped to a bit with high reliability, its group unit corresponding bit W 24 should be mapped to a bit with low reliability. Also, if the Y' 24 is mapped to a bit with low reliability, its group unit corresponding bit W 24 should be mapped to a bit with high reliability.
  • the bits with high reliability are indicated by the bits to which arrows point. If the bits with high reliability are odd number bits and the bits with low reliability are even number bits as shown in FIG. 7, then the output sequences are A' o , A' N-1 5 -D 0? J -D N l ? ⁇ 5 N-2? 1 1,0? i 2,0? JL 1,1 ? JL 2,1 ? ? JL 1 ,N-I ? JL 2,N-I ?

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  • Detection And Prevention Of Errors In Transmission (AREA)
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PCT/KR2009/007791 2008-12-26 2009-12-24 Convolutional turbo coding method and device for implementing the coding method Ceased WO2010074537A2 (en)

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EP2683087A3 (en) 2014-04-30
HK1140066A1 (en) 2010-09-30
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US20100169748A1 (en) 2010-07-01
EP2683087A2 (en) 2014-01-08
MY161322A (en) 2017-04-14
US8788919B2 (en) 2014-07-22
RU2514088C2 (ru) 2014-04-27
CN101710850B (zh) 2013-10-30
KR20100076893A (ko) 2010-07-06
WO2010074537A3 (en) 2010-10-07

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