WO2010058994A2 - Appareil de codage/de décodage de canal et procédé utilisant des codes de contrôle de parité de faible densité - Google Patents
Appareil de codage/de décodage de canal et procédé utilisant des codes de contrôle de parité de faible densité Download PDFInfo
- Publication number
- WO2010058994A2 WO2010058994A2 PCT/KR2009/006860 KR2009006860W WO2010058994A2 WO 2010058994 A2 WO2010058994 A2 WO 2010058994A2 KR 2009006860 W KR2009006860 W KR 2009006860W WO 2010058994 A2 WO2010058994 A2 WO 2010058994A2
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- WO
- WIPO (PCT)
- Prior art keywords
- parity
- column group
- column
- check matrix
- positions
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 74
- 239000011159 matrix material Substances 0.000 claims abstract description 158
- 230000009977 dual effect Effects 0.000 claims description 5
- 238000004891 communication Methods 0.000 description 21
- 238000010586 diagram Methods 0.000 description 13
- 238000013461 design Methods 0.000 description 10
- 239000000284 extract Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000011160 research Methods 0.000 description 4
- 230000003044 adaptive effect Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 3
- 125000004122 cyclic group Chemical group 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 238000005562 fading Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000032683 aging Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
- H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
- H03M13/6516—Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
Abstract
L'invention concerne un appareil de codage/de décodage et procédé utilisant un code de contrôle de parité de faible densité (code LDPC). Des informations de base de groupe de colonnes, servant comme ensemble d'informations concernant la position des rangées de poids 1, sont extraites d'une colonne de référence dans chaque groupe de colonnes d'une matrice de contrôle de parité prédéterminée. Les informations de groupe de colonnes transforment la position des rangées de poids 1 en une position dont la longueur respecte une longueur de parité requise. Une matrice de contrôle de parité est générée selon les informations de groupe de colonnes générées. Les données sont codées ou décodées sur la base de la matrice de contrôle de parité générée.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP09827759.3A EP2351230B1 (fr) | 2008-11-24 | 2009-11-20 | Appareil de codage/de décodage de canal et procédé utilisant des codes de contrôle de parité de faible densité |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2008-0117008 | 2008-11-24 | ||
KR1020080117008A KR20100058260A (ko) | 2008-11-24 | 2008-11-24 | 저밀도 패리티 검사 부호를 사용하는 통신 시스템에서 채널부호/복호 장치 및 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2010058994A2 true WO2010058994A2 (fr) | 2010-05-27 |
WO2010058994A3 WO2010058994A3 (fr) | 2010-09-10 |
Family
ID=42198686
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/KR2009/006860 WO2010058994A2 (fr) | 2008-11-24 | 2009-11-20 | Appareil de codage/de décodage de canal et procédé utilisant des codes de contrôle de parité de faible densité |
Country Status (4)
Country | Link |
---|---|
US (1) | US8495459B2 (fr) |
EP (1) | EP2351230B1 (fr) |
KR (1) | KR20100058260A (fr) |
WO (1) | WO2010058994A2 (fr) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7474608B2 (en) | 2004-01-12 | 2009-01-06 | Intel Corporation | Method for signaling information by modifying modulation constellations |
KR20120088369A (ko) * | 2011-01-31 | 2012-08-08 | 삼성전자주식회사 | 방송 및 통신시스템에서 송?수신 방법 및 장치 |
US8839069B2 (en) | 2011-04-08 | 2014-09-16 | Micron Technology, Inc. | Encoding and decoding techniques using low-density parity check codes |
KR101477925B1 (ko) * | 2013-10-08 | 2014-12-30 | 세종대학교산학협력단 | Ldpc 복호기를 이용한 데이터 경로 설정 방법 및 이를 위한 ldpc 복호기 |
US10784901B2 (en) | 2015-11-12 | 2020-09-22 | Qualcomm Incorporated | Puncturing for structured low density parity check (LDPC) codes |
WO2017091018A1 (fr) | 2015-11-24 | 2017-06-01 | Samsung Electronics Co., Ltd. | Procédé et appareil de codage/décodage de canal dans un système de communication ou de diffusion |
KR20170060562A (ko) | 2015-11-24 | 2017-06-01 | 삼성전자주식회사 | 통신 또는 방송 시스템에서 채널 부호화/복호화 방법 및 장치 |
US10268539B2 (en) * | 2015-12-28 | 2019-04-23 | Intel Corporation | Apparatus and method for multi-bit error detection and correction |
US10469104B2 (en) | 2016-06-14 | 2019-11-05 | Qualcomm Incorporated | Methods and apparatus for compactly describing lifted low-density parity-check (LDPC) codes |
EP3264610A1 (fr) * | 2016-06-27 | 2018-01-03 | Alcatel Lucent | Correction d'erreurs sans voie de retour avec taux de codage variable |
CN109565289A (zh) * | 2016-08-11 | 2019-04-02 | 瑞典爱立信有限公司 | 基于目标信息长度和目标奇偶校验长度的纠错码选择 |
US10340949B2 (en) * | 2017-02-06 | 2019-07-02 | Qualcomm Incorporated | Multiple low density parity check (LDPC) base graph design |
US10606697B2 (en) * | 2018-06-21 | 2020-03-31 | Goke Us Research Laboratory | Method and apparatus for improved data recovery in data storage systems |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100922956B1 (ko) * | 2003-10-14 | 2009-10-22 | 삼성전자주식회사 | 저밀도 패리티 검사 코드의 부호화 방법 |
US7685497B2 (en) * | 2004-03-31 | 2010-03-23 | Nxp B.V. | Method and apparatus for efficient computation of check equations in periodical low density parity check (LDPC) codes |
US7581157B2 (en) * | 2004-06-24 | 2009-08-25 | Lg Electronics Inc. | Method and apparatus of encoding and decoding data using low density parity check code in a wireless communication system |
US7506238B2 (en) * | 2004-08-13 | 2009-03-17 | Texas Instruments Incorporated | Simplified LDPC encoding for digital communications |
US7343548B2 (en) | 2004-12-15 | 2008-03-11 | Motorola, Inc. | Method and apparatus for encoding and decoding data |
KR100941680B1 (ko) * | 2005-07-01 | 2010-02-12 | 삼성전자주식회사 | 준순환 저밀도 패리티 검사 부호의 생성 방법 및 장치 |
US8103935B2 (en) * | 2005-08-10 | 2012-01-24 | Mitsubishi Electric Corporation | Test matrix generating method, encoding method, decoding method, communication apparatus, communication system, encoder and decoder |
KR100842597B1 (ko) * | 2005-10-17 | 2008-07-01 | 삼성전자주식회사 | 저밀도 패리티 검사 부호의 패리티 검사 행렬 설계 방법 |
EP1966897A4 (fr) | 2005-12-27 | 2012-05-30 | Lg Electronics Inc | Appareils et procedes de decodage et codage en utilisant un code de canal ou lpdc |
KR101147768B1 (ko) * | 2005-12-27 | 2012-05-25 | 엘지전자 주식회사 | 채널 코드를 이용한 복호화 방법 및 장치 |
JP4601675B2 (ja) * | 2006-02-09 | 2010-12-22 | 富士通株式会社 | Ldpc検査行列生成方法及び検査行列生成器並びに符号再送方法 |
FR2900294B1 (fr) * | 2006-04-19 | 2008-07-04 | St Microelectronics Sa | Chargement de la memoire d'entree d'un decodeur ldpc avec des donnees a decoder |
-
2008
- 2008-11-24 KR KR1020080117008A patent/KR20100058260A/ko not_active Application Discontinuation
-
2009
- 2009-11-20 EP EP09827759.3A patent/EP2351230B1/fr not_active Not-in-force
- 2009-11-20 WO PCT/KR2009/006860 patent/WO2010058994A2/fr active Application Filing
- 2009-11-23 US US12/624,098 patent/US8495459B2/en active Active
Non-Patent Citations (1)
Title |
---|
See references of EP2351230A4 * |
Also Published As
Publication number | Publication date |
---|---|
EP2351230A2 (fr) | 2011-08-03 |
US8495459B2 (en) | 2013-07-23 |
US20100138720A1 (en) | 2010-06-03 |
EP2351230B1 (fr) | 2019-02-20 |
WO2010058994A3 (fr) | 2010-09-10 |
EP2351230A4 (fr) | 2012-09-12 |
KR20100058260A (ko) | 2010-06-03 |
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