WO2010058693A1

WO2010058693A1 - Packet transmission device, inter-processor communication system, parallel processor system, and packet transmission method

Info

Publication number: WO2010058693A1
Application number: PCT/JP2009/068674
Authority: WO
Inventors: 健加納
Original assignee: 日本電気株式会社
Priority date: 2008-11-21
Filing date: 2009-10-30
Publication date: 2010-05-27
Also published as: JPWO2010058693A1; JP5310735B2

Abstract

A packet transfer device receives a predetermined number of packets which have been successively transmitted one by one from a first processor to a second processor and transfers the packets to a communication path set as a transfer destination among a plurality of communication paths leading to the second processor. The packet transfer device includes: a storage unit which stores communication-in-progress information when the first processor has transmitted one or more of the plurality of packets and not yet transmitted all of the packets; and a control unit. Upon reception of a transfer destination switching instruction while the communication-in-progress information is stored in the storage unit, the control unit switches the transfer destination to another communication path among the communication paths after all of the packets have been transferred to the communication path set as the transfer destination.

Description

Packet transfer device, inter-processor communication system, parallel processor system, and packet transfer method

The present invention relates to a packet transfer device, an inter-processor communication system, a parallel processor system, and a packet transfer method, for example, a packet transfer device, an inter-processor communication system, a parallel processor system, and a packet transfer method used in a parallel computer.

In inter-processor communication in a parallel computer, transmission data is divided into a plurality of packets, and each packet is transferred to a destination processor through an inter-processor network. An inter-processor data transfer device such as a crossbar switch exists in the inter-processor network.

In inter-processor communication, there is communication in which the order of a plurality of packets must be guaranteed, that is, communication in which packets must be received in the order of packet transmission. Hereinafter, communication in which the order of a plurality of packets must be guaranteed is referred to as “order guaranteed communication”.

In one example of order-guaranteed communication, a transmission side assigns a sequence number to a packet generated by dividing transmission data and transmits the packet, and a reception side receives a predicted value of the sequence number and a packet that arrives when the packet is received. Is a communication for detecting an error by comparing the sequence number assigned to the.

In this case, if the order of packets in the inter-processor network changes, the receiving side receives a packet with a sequence number different from the predicted value, and determines that it is an error.

Another example of order-guaranteed communication is communication in which the receiving side receives a packet having the last part of transmission data and determines that reception of the entire transmission data is completed when the last part is written. .

In this case, if the order of the packets is changed in the inter-processor network, the reception side determines that the reception is completed before receiving all of the plurality of packets generated from one transmission data. read out. For this reason, the value before all of one transmission data is written is read.

Thus, it is important to guarantee the order of packets within the interprocessor network.

Communication that requires order guarantee is communication in which a plurality of packets generated by dividing one transmission data are transmitted from the same processor to the same destination processor. Note that even in the case of communication in which packets are transmitted from the same processor to the same destination processor, it is not necessary to guarantee the order between packets generated from different transmission data.

Patent Document 1 discloses a technique for changing a data transfer path based on failure information and bypassing a failure switch in a network between parallel processors.

Patent Document 2 discloses an interprocessor data communication method in which a partial network used in place of a failed crossbar switch is determined in advance.

Japanese Patent No. 2960454 JP-A-8-77127

In the failure processing for isolating the failure location when a failure occurs in the network between the processors of the parallel computer, as described in

Patent Documents

1 and 2, simply changing the transfer path and bypassing the failure location is not necessary. There is a problem that the order of packets that need to be guaranteed cannot be guaranteed.

This is because the route through which the preceding packet passes differs from the detour route through which the subsequent packet passes, and the arrival order of the packets may be reversed depending on the difference in the degree of congestion between the routes.

An object of the present invention is to provide a packet transfer apparatus, an interprocessor communication system, a parallel processor system, and a packet transfer method that can solve the above-described problems.

The packet transfer apparatus of the present invention receives a plurality of predetermined packets addressed to the second processor, which are sequentially transmitted from the first processor one by one, and transmits the packets among the plurality of communication paths leading to the second processor. A packet transfer apparatus for transferring to a communication path set as a transfer destination, wherein the first processor has transmitted one or more packets of the plurality of packets, and all of the plurality of packets are transmitted. A storage unit that stores in-communication information indicating that communication is in progress when not transmitting, and in a situation where the in-communication information is stored in the storage unit, the transfer destination switching instruction is received, After all of the plurality of packets are transferred to the communication path set as the transfer destination, the transfer destination is switched to another communication path among the plurality of communication paths. It includes a control unit, a.

The inter-processor communication system of the present invention includes the packet transfer device and the plurality of communication paths.

The parallel processor system of the present invention includes the inter-processor communication system, the first processor, and the second processor.

The packet transfer method of the present invention receives a plurality of predetermined packets addressed to the second processor, which are sequentially transmitted from the first processor one by one, and transmits the packets to the second processor among the plurality of communication paths. A packet transfer method performed by a packet transfer apparatus that transfers to a communication path set as a transfer destination, wherein the first processor has transmitted one or more packets of the plurality of packets, and the plurality When not transmitting all of the packets, the communication information indicating that communication is in progress is stored in the storage unit, and the transfer destination is switched in a situation where the communication information is stored in the storage unit. When receiving the instruction, after all of the plurality of packets are transferred to the communication path set as the transfer destination, the transfer destination is changed to another of the plurality of communication paths. Switch to the communication path.

The packet transfer method of the present invention receives a plurality of predetermined packets addressed to the second processor, which are sequentially transmitted from the first processor one by one, and transmits the packets to the second processor among the plurality of communication paths. A packet transfer method performed by an inter-processor communication system including a packet transfer apparatus configured to transfer to a communication path set as a transfer destination and the plurality of paths, wherein the packet transfer apparatus is configured such that the first processor includes the plurality of the plurality of paths. The communication unit stores in-communication information indicating that communication is in progress when one or more packets have been transmitted and all of the plurality of packets have not been transmitted, and the packet transfer apparatus However, in a situation where the information during communication is stored in the storage unit, when the transfer destination switching instruction is received, all of the plurality of packets are After being transferred to the set communication path as the transfer destination, the transfer destination to switch to another communication path among the plurality of communication paths.

The packet transfer method according to the present invention includes a first processor, a second processor, a plurality of communication paths that communicate with the second processor, and a predetermined address addressed to the second processor that is sequentially transmitted from the first processor. A packet transfer method performed by a parallel computer system that includes a packet transfer apparatus that receives a plurality of packets and transfers the packets to a communication path set as a transfer destination among the plurality of communication paths. The packet transfer apparatus is in communication when the first processor has transmitted one or more of the plurality of packets and has not transmitted all of the plurality of packets. Is stored in the storage unit, and the packet transfer device is in a state where the communication information is stored in the storage unit. When the transfer destination switching instruction is accepted, after all of the plurality of packets are transferred to the communication path set as the transfer destination, the transfer destination is changed to another of the plurality of communication paths. Switch to the communication path.

According to the present invention, it is possible to guarantee the order of a plurality of packets even when a communication path is switched.

1 is a block diagram illustrating a configuration of a parallel processor system according to a first embodiment of this invention. It is explanatory drawing for demonstrating the format of the packet 200 communicated in the network 2 between processors. It is explanatory drawing which showed the detail of the crossbar 105 between planes. It is explanatory drawing which showed the data path of the direction to a processor in the crossbar 105 between planes. It is a flowchart for demonstrating the process in the data path of the direction to a network plane in the crossbar between planes. It is a figure explaining operation | movement of the crossbar between planes of the 1st Embodiment of this invention. It is a figure explaining operation | movement of the crossbar between planes of the 1st Embodiment of this invention. It is a figure explaining operation | movement of the crossbar between planes of the 1st Embodiment of this invention. It is a figure explaining operation | movement of the crossbar between planes of the 1st Embodiment of this invention. It is a figure explaining operation | movement of the crossbar between planes of the 1st Embodiment of this invention. It is explanatory drawing for demonstrating the format of the packet 700 used by the 2nd Embodiment of this invention. It is explanatory drawing which showed the data path of the network plane direction of the crossbar between planes of the 2nd Embodiment of this invention.

Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram illustrating a parallel processor system, an interprocessor communication system, and a packet transfer apparatus according to a first embodiment of this invention.

1, the parallel processor system 1 includes a plurality of network planes 101 to 104, a plurality of interplane crossbars (interplane crossbar switches) 105 to 112, and a plurality of processors 113 to 144.

In the parallel processor system 1, the processors 113 to 144 perform parallel operations in cooperation with each other. Each of processors 113-144 can generally be referred to as a first processor and a second processor.

When there is data to be transmitted to other processors (hereinafter referred to as “transmission data”), each of the processors 113 to 144 divides the transmission data and generates a plurality of packets addressed to the other processors.

When a plurality of packets require the order guarantee, each of the processors 113 to 144 adds information indicating that the order guarantee is necessary to each of the plurality of packets.

A plurality of packets requiring order guarantee can be generally called a predetermined plurality of packets. One communication command is constituted by the plurality of packets.

Each of the processors 113 to 144 transmits individual packets constituting one communication command to the inter-processor network 2 one by one in order.

The interprocessor network 2 can be generally called an interprocessor communication system.

The interprocessor network 2 is connected to each of the processors 113 to 144. The inter-processor network 2 includes a plurality of network planes 101 to 104 and a plurality of inter-plane crossbars 105 to 112.

The network planes 101 to 104 can generally be called a plurality of communication paths. The network planes 101 to 104 can be called independent partial networks that are not directly connected to each other.

Each of the network planes 101 to 104 is an 8-input 8-output network. Each of the network planes 101 to 104 includes three crossbars (crossbar switches) 145 to 147 having eight inputs and eight outputs.

Each of the interplane crossbars 105 to 112 can be generally called a packet transfer device.

Each of the interplane crossbars 105 to 112 is connected to the network planes 101 to 104.

The interplane crossbar 105 is also connected to the processors 113 to 116. The interplane crossbar 106 is also connected to the processors 117 to 120. The interplane crossbar 107 is also connected to the processors 121 to 124. The interplane crossbar 108 is also connected to the processors 125 to 128. The interplane crossbar 109 is also connected to the processors 129 to 132. The interplane crossbar 110 is also connected to the processors 133 to 136. The interplane crossbar 111 is also connected to the processors 137 to 140. The interplane crossbar 112 is also connected to the processors 141 to 144.

Each of the crossbars 105 to 112 between the planes is an 8-input 8-output crossbar.

Each of the interplane crossbars 105 to 112 receives a plurality of packets addressed to another processor (second processor), one by one, sequentially transmitted from the processor (first processor) connected thereto, and the packet Are transferred to the network plane set as the transfer destination among the network planes 101 to 104.

When each of the network planes 101 to 104 receives a packet from any of the interplane crossbars 105 to 112, the network plane 101 to 104 sends the packet to any one of the interplane crossbars 105 to 112 based on the routing information described in the packet. Forward to.

When each of the interplane crossbars 105 to 112 receives a packet from any one of the network planes 101 to 104, the interplane crossbars 105 to 112 send the packet to any of the processors connected to the packet based on the routing information described in the packet. Transfer to.

For this reason, the network planes 101 to 104 function as a plurality of communication paths leading to the packet destination processor.

Here, as an example of the parallel processor system 1, the configuration as shown in FIG. 1 is shown. However, the number of network planes as a partial network, the topology and configuration of the partial network, the number of ports and the number of crossbars between planes, In addition, the number of processors is arbitrary.

FIG. 2 is an explanatory diagram for explaining a format of the packet 200 communicated in the inter-processor network 2.

In FIG. 2, the packet 200 is generated by each of the processors 113 to 144. In the present embodiment, each of the processors 113 to 144 generates a plurality of packets 200 by dividing the transmission data. Each of the processors 113 to 144 transmits the individual packets 200 to the inter-processor network 2 one by one in order.

The packet 200 includes routing information 201, an order guarantee flag 202, a last packet flag 203, a packet length 204, and data 205.

The routing information 201 is used for routing in the inter-processor network 2. The route designation information 201 includes first route designation information 206, second route designation information 207, and third route designation information 208.

The first routing information 206 is used by the interplane crossbar (hereinafter referred to as “reception plane crossbar”) that has received the packet 200 from any of the processors 113 to 144 among the interplane crossbars 105 to 112.

The first route designation information 206 is information (information related to routing) for designating a network plane (hereinafter referred to as “destination network plane”) as a transmission destination from the crossbar between the reception planes among the network planes 101 to 104. It is.

In the present embodiment, the first route designation information 206 designates an output port (destination output port) connected to the transmission destination network plane among the output ports of the crossbar between the reception planes.

The second routing information 207 is used by the destination network plane. The second route designation information 207 is information (routing) for designating an interplane crossbar (hereinafter referred to as “destination plane crossbar”) that is a transmission destination from the transmission destination network plane among the interplane crossbars 105 to 112. Information).

In the present embodiment, the second route designation information 207 designates an output port connected to the crossbar between the transmission destination planes among the output ports of the transmission destination network plane.

The third routing information 208 is used by the crossbar between transmission destination planes. The third routing information 208 is information (information related to routing) for designating a processor (hereinafter referred to as “destination processor”) as a transmission destination from the crossbar between the transmission destination planes among the processors 113 to 144. .

In the present embodiment, the third route designation information 208 designates an output port connected to the destination processor among the output ports of the crossbar between the destination planes.

The order guarantee flag 202 indicates whether the packet 200 is a packet that requires order guarantee in the inter-processor network 2.

In the present embodiment, when the order guarantee flag 202 is “1”, it indicates that the packet 200 is a packet that requires order guarantee. On the other hand, when the order guarantee flag 202 is “0”, it indicates that the packet 200 is a packet that does not require the order guarantee.

The last packet flag 203 indicates whether or not the packet 200 is the last packet of one communication command.

In the present embodiment, when the last packet flag 203 is “0”, it indicates that the packet 200 is not the last packet of one communication command. On the other hand, when the last packet flag 203 is “1”, it indicates that the packet 200 is the last packet of one communication command.

Packet length 204 specifies the length of data 205.

FIG. 3 is an explanatory diagram showing details of the crossbar 105 between planes. 3, the same components as those shown in FIG. 1 are denoted by the same reference numerals.

3 illustrates the interplane crossbar 105 shown in FIG. 1, but the interplane crossbars 105 to 112 have the same configuration, except that the connected processor is changed. For this reason, the description about the other crossbar between planes is abbreviate | omitted.

FIG. 3 shows only the data path in the direction to the network plane at the crossbar 105 between the planes. The data path in the direction of the processor in the interplane crossbar 105 will be described with reference to FIG.

The interplane crossbar 105 includes four input ports 301 to 304 and four output ports 305 to 308 for the data path in the direction toward the network plane.

The number “0” is assigned to the output port 305. The output port 306 is numbered “1”. The output port 307 is numbered “2”. The output port 308 is numbered “3”. Note that the number can generally be referred to as identification information.

Each of the four input ports 301 to 304 is connected to one of the processors 113 to 116. In the present embodiment, the input port 301 is connected to the processor 113. The input port 302 is connected to the processor 114. The input port 303 is connected to the processor 115. The input port 304 is connected to the processor 116.

Each of the four output ports 305 to 308 is connected to one of the network planes 101 to 104. In the present embodiment, the output port 305 is connected to the network plane 101. The output port 306 is connected to the network plane 102. The output port 307 is connected to the network plane 103. The output port 308 is connected to the network plane 104.

The interplane crossbar 105 includes storage units 105a to 105d and a control unit 105e.

Each of the storage units 105a to 105d can be generally referred to as storage means.

The storage unit 105 a includes a switching status register 309, a switching destination register 310, a normal destination register 311, and a pending register 312. The storage unit 105 b includes a switching status register 313, a switching destination register 314, a normal destination register 315, and a pending register 316. The storage unit 105 c includes a switching status register 317, a switching destination register 318, a normal destination register 319, and a pending register 320. The storage unit 105 d includes a switching status register 321, a switching destination register 322, a normal destination register 323, and a pending register 324.

Control unit 105e can be generally referred to as control means.

The control unit 105e includes multiplexers 325 to 328, control circuits 329 to 332, and arbitration circuits 333 to 336.

The number “0” is assigned to the arbitration circuit 333. The arbitration circuit 334 is numbered “1”. The arbitration circuit 335 is numbered “2”. The arbitration circuit 336 is numbered “3”.

The input port 301 is associated with the storage unit 105a and the control circuit 329. The input port 302 is associated with the storage unit 105b and the control circuit 330. The input port 303 is associated with the storage unit 105c and the control circuit 331. The input port 304 is associated with the storage unit 105d and the control circuit 332.

The output port 305 is associated with the multiplexer 325 and the arbitration circuit 333. The output port 306 is associated with the multiplexer 326 and the arbitration circuit 334. The output port 307 is associated with the multiplexer 327 and the arbitration circuit 335. The output port 308 is associated with the multiplexer 328 and the arbitration circuit 336.

Each of the normal destination registers 311, 315, 319 and 323 stores the number of the arbitration circuit corresponding to the output port for each of the output ports 305 to 308 (numbers “0” to “3”).

In FIG. 3, the numbers 0 to 3 described above the switching status registers 309, 313, 317, and 321 correspond to the numbers “0” to “3” of the output ports 305 to 308, respectively.

Therefore, each of the normal destination registers 311, 315, 319 and 323 is output to a portion (register) existing in the number 0 column described above each of the switching status registers 309, 313, 317 and 321. The number of the arbitration circuit corresponding to the port 305 is stored.

In addition, each of the normal destination registers 311, 315, 319 and 323 has an output port in a portion (register) existing in the number 1 column described above each of the switching status registers 309, 313, 317 and 321. The number of the arbitration circuit corresponding to 306 is stored.

In addition, each of the normal destination registers 311, 315, 319 and 323 has an output port in a portion (register) existing in the number 2 column described above each of the switching status registers 309, 313, 317 and 321. The number of the arbitration circuit corresponding to 307 is stored.

In addition, each of the normal destination registers 311, 315, 319 and 323 has an output port in a part (register) existing in the column of number 3 described on each of the switching status registers 309, 313, 317 and 321. The number of the arbitration circuit corresponding to 308 is stored.

Each of the switching destination registers 310, 314, 318 and 322 stores the number of the arbitration circuit corresponding to the output port switched from the output port for each of the output ports 305 to 308 (numbers “0” to “3”). To do.

Each of the switching destination registers 310, 314, 318, and 322 has a portion (register) in the column of number 0 described above each of the switching status registers 309, 313, 317, and 321 in the output port 305. Stores the number of the arbitration circuit corresponding to the output port of the switching destination.

Each of the switching destination registers 310, 314, 318, and 322 is connected to a portion (register) that exists in the number 1 column described above each of the switching status registers 309, 313, 317, and 321. Stores the number of the arbitration circuit corresponding to the output port of the switching destination.

Each of the switching destination registers 310, 314, 318, and 322 has a portion (register) in the column of number 2 described above each of the switching status registers 309, 313, 317, and 321 in the output port 307. Stores the number of the arbitration circuit corresponding to the output port of the switching destination.

Each of the switch destination registers 310, 314, 318, and 322 is connected to the portion (register) of the output port 308 in a portion (register) existing in the number 3 column described above each of the switch state registers 309, 313, 317, and 321. Stores the number of the arbitration circuit corresponding to the output port of the switching destination.

In this embodiment, each of the switching destination registers 310, 314, 318, and 322 adds mod 1 to the output port number for each of the output ports 305 to 308 (numbers “0” to “3”). The calculated value is stored as the arbitration circuit number corresponding to the output port of the switching destination.

Each of the switching status registers 309, 313, 317 and 321 has switching status information (“0” to “0”) indicating the switching status of the output port for each of the output ports 305 to 308 (numbers “0” to “3”). Any one of “3”) is stored.

Each of the switching status registers 309, 313, 317, and 321 stores switching status information for the output port 305 in a portion (register) existing in the number 0 column described above.

Each of the switching status registers 309, 313, 317, and 321 stores the switching status information for the output port 306 in the portion (register) that exists in the column of number 1 described above.

Each of the switching status registers 309, 313, 317 and 321 stores the switching status information for the output port 307 in the part (register) existing in the column of number 2 described above.

Each of the switching status registers 309, 313, 317, and 321 stores switching status information for the output port 308 in a portion (register) that exists in the column of number 3 described above.

If there is no failure in the network plane connected to an output port, there is no need to switch the output port to another output port. When the output port is not switched, “0” is stored as the switching state information corresponding to the output port. When the switching status information is “0”, the number in the normal destination register is used.

When a failure occurs in a network plane connected to a certain output port and the other port is used to switch the output port to another output port, the switching state information is changed from “0” to “1”. Is changed.

When the switching state information is “1”, the packet 200 is in the normal destination register depending on whether the packet 200 is a packet that requires the order guarantee and the packet number of the packet that requires the order guarantee. Or the number in the switch destination register is used.

The method for determining the number to be used and the case where the switching status information changes from “1” to “2” will be described later with reference to FIG.

When the switching status information is “2”, the number in the switching destination register is always used.

When the switching status information of all the output ports connected to the network plane where the failure occurred among the output ports of the crossbars 105 to 112 between the planes changes from “1” to “2”, the network plane where the failure occurred is used. I will not be broken.

At this point, the network plane where the failure has occurred can be disconnected from the parallel processor system 1. Therefore, at this point, maintenance is performed for the network plane where the failure has occurred.

Then, the network plane in which the failure has occurred is repaired and incorporated into the parallel processor system 1 again. At this time, the switching state information of the output port connected to the network plane where the failure has occurred is changed from “2” to “3”.

When the switching state information is “3”, the packet 200 is in the normal destination register depending on whether the packet 200 is a packet that requires order guarantee and the number of the packet that requires the order guarantee. Or the number in the switch destination register is used.

The method of determining the number to be used and the case where the switching status information changes from “3” to “0” will be described later with reference to FIG.

The example shown in FIG. 3 shows a state where no failure has occurred yet. Therefore, all the switching state information is “0”.

Each of the in-process registers 312, 316, 320, and 324 has a processor connected to its corresponding input port having transmitted one or more packets out of a plurality of packets that require an order guarantee, and When all of the plurality of packets are not transmitted, communication information “1” indicating that communication is in progress is stored.

Packets that require an order guarantee guarantee the order in the inter-processor network 2 between a plurality of packets, and that the order of packets sent from the source processor and the arrival order at the destination processor are the same. It is a packet that needs to be guaranteed.

If the order of packets in the inter-processor network 2 is reversed, problems such as errors occur and the order of data writing to the memory (not shown) by the destination processor cannot be guaranteed.

When each of the control circuits 329 to 332 receives a packet transmitted first among a plurality of packets that require order guarantee from an input port corresponding to the control circuit 329 to 332, “1” (information during communication) is stored.

When each of the control circuits 329 to 332 receives from the input port corresponding to itself the last transmitted packet among the plurality of packets that require order guarantee, the in-process register corresponding to the same input port as that of itself "1" (information during communication) is deleted and "0" is stored.

Each of the control circuits 329 to 332 determines whether or not the packet 200 received from the input port corresponding to the control circuit 329 to 332 is the packet transmitted last among the plurality of packets that need the order guarantee. The state of the packet flag 202 is checked and determined.

When the last packet flag 202 is “0”, each of the control circuits 329 to 332 determines that the packet 200 is not the last packet transmitted among a plurality of packets that require order guarantee.

On the other hand, when the last packet flag 202 is “1”, each of the control circuits 329 to 332 determines that the packet 200 is the last packet transmitted among a plurality of packets that require order guarantee.

In addition, each of the control circuits 329 to 332 has an in-process register value corresponding to the same input port as that of itself, and when the packet 200 that requires the order guarantee arrives, the packet 200 is ordered. It is determined that the packet is the first packet transmitted out of a plurality of packets that need to be guaranteed.

When each of the control circuits 329 to 332 transfers the packet 200 to the output port 305 according to the first routing information 206 in the packet 200 and the information in the storage unit corresponding to the same input port as the self, the control circuits 329 to 332 Send a request for transmission.

When each of the control circuits 329 to 332 transfers the packet 200 to the output port 306 according to the first routing information 206 in the packet 200 and the information in the storage unit corresponding to the same input port as the self, the control circuits 329 to 332 Send a request for transmission.

When each of the control circuits 329 to 332 transfers the packet 200 to the output port 307 according to the first routing information 206 in the packet 200 and the information in the storage unit corresponding to the same input port as itself, the control circuits 329 to 332 Send a request for transmission.

When each of the control circuits 329 to 332 transfers the packet 200 to the output port 308 according to the first routing information 206 in the packet 200 and the information in the storage unit corresponding to the same input port as the self, the control circuits 329 to 332 Send a request for transmission.

When each of the control circuits 329 to 332 has the value of the in-process register corresponding to the same input port as “1” and the packet 200 that requires the order guarantee arrives, the destination (transfer destination) of the packet 200 Do not switch the output port.

This is because if two packets pass through different network planes, the order in the inter-processor network 2 cannot be guaranteed.

For example, if the network plane through which the earlier packet passes is congested and the network plane through which the later packet passes is free, the arrival order at the destination processor is reversed.

Each of the multiplexers 325 to 328 selects one input port from the four input ports 301 to 304 based on an instruction from the arbitration circuit corresponding to the same output port as itself. Each of the multiplexers 325 to 328 forwards the packet 200 from the selected input port to the output port corresponding to itself.

When each of the arbitration circuits 333 to 336 receives a request from any of the control circuits 329 to 332, each of the arbitration circuits 333 to 336 sends an instruction to select an input port corresponding to the control circuit that transmitted the request to the same output port as itself. Output to the corresponding multiplexer.

In each of the storage units 105a to 105b, the processor connected to the input port corresponding to the storage unit 105a to 105b has already transmitted one or more packets out of a predetermined plurality of packets (for example, a plurality of packets requiring order guarantee). And, when all of the plurality of packets have not been transmitted, communication information indicating that communication is in progress is stored.

It should be noted that the predetermined plurality of packets are preferably a plurality of packets that require the order guarantee, but other packets may be included in addition to the plurality of packets that require the order guarantee. In this case, the order can be guaranteed including other packets.

When the control unit 105e receives individual packets constituting a predetermined plurality of packets from a certain input port, the control unit 105e transfers the packets to the network plane set as the transfer destination.

The control unit 105e switches the packet transfer destination from the input port in a situation where the storage unit corresponding to one input port among the storage units 105a to 105b stores communication information. When the instruction is accepted, all of the predetermined packets sent to the input port are transferred to the network plane set as the transfer destination, and then the transfer destination is transferred to another network plane among the plurality of network planes. Switch.

FIG. 4 is an explanatory diagram showing only the data path in the direction of the processor in the crossbar 105 between the planes. In FIG. 4, the same components as those shown in FIG.

FIG. 4 illustrates the interplane crossbar 105 shown in FIG. 1, but the interplane crossbars 105 to 112 have the same configuration except that the connected processor is changed. For this reason, the description about the other crossbar between planes is abbreviate | omitted.

Interplane crossbar 105 includes four input ports 401 to 404 and four output ports 405 to 408 for the data path in the direction to the processor.

The interplane crossbar 105 includes multiplexers 409 to 412, control circuits 413 to 416, and arbitration circuits 417 to 420.

In this embodiment, the arbitration circuit 417 is numbered “4”. The arbitration circuit 418 is numbered “5”. The arbitration circuit 419 is numbered “6”. The arbitration circuit 420 is numbered “7”.

Each of the four input ports 401 to 404 is connected to one of the network planes 101 to 104. In the present embodiment, the input port 401 is connected to the network plane 101. The input port 402 is connected to the network plane 102. The input port 403 is connected to the network plane 103. The input port 404 is connected to the network plane 104.

The input port 401 is associated with the control circuit 413. The input port 402 is associated with the control circuit 414. The input port 403 is associated with the control circuit 415. The input port 404 is associated with the control circuit 416.

Each of the four output ports 405 to 408 is connected to one of the processors 113 to 116. In the present embodiment, the output port 405 is connected to the processor 113. The output port 406 is connected to the processor 114. The output port 407 is connected to the processor 115. The output port 408 is connected to the processor 116.

The output port 405 is associated with the multiplexer 409 and the arbitration circuit 417. The output port 406 is associated with the multiplexer 410 and the arbitration circuit 418. The output port 407 is associated with the multiplexer 411 and the arbitration circuit 419. The output port 408 is associated with the multiplexer 412 and the arbitration circuit 420.

When each of the control circuits 413 to 416 transfers the packet 200 from the input port corresponding to itself to the output port 405 according to the third routing information 208 in the packet 200, the control circuit 413 to 416 sends a request for transmission to the arbitration circuit 417. Send.

When each of the control circuits 413 to 416 transfers the packet 200 from the input port corresponding to the control circuit 413 to the output port 406 according to the third routing information 208 in the packet 200, the control circuit 413 to 416 sends a request for transmission to the arbitration circuit 418. Send.

When each of the control circuits 413 to 416 transfers the packet 200 from the input port corresponding to the control circuit 413 to the output port 407 according to the third routing information 208 in the packet 200, the control circuit 413 to 416 sends a request for transmission to the arbitration circuit 419. Send.

When each of the control circuits 413 to 416 transfers the packet 200 from the input port corresponding to the control circuit 413 to the output port 408 according to the third routing information 208 in the packet 200, the control circuit 413 to 416 sends a request for transmission to the arbitration circuit 420. Send.

Each of the multiplexers 409 to 412 selects one input port from the four input ports 401 to 404 based on an instruction from the arbitration circuit corresponding to the same output port as itself. Each of the multiplexers 409 to 412 transfers the packet 200 from the selected input port to the output port corresponding to itself.

When each of the arbitration circuits 417 to 420 receives a request from any of the control circuits 413 to 416, each of the arbitration circuits 417 to 420 issues an instruction to select an input port corresponding to the control circuit that transmitted the request to the same output port as itself. Output to the corresponding multiplexer.

Next, the operation will be described.

FIG. 5 is a flowchart for explaining processing in the data path in the direction toward the network plane in the crossbar between planes.

Hereinafter, a case where the processor 113 transmits the packet 200 to the input port 301 will be described as an example. When another processor transmits the packet 200, the input port to which the packet 200 is input, the control circuit that executes the process, and the storage unit that is used are different, and the description thereof is omitted.

When receiving the packet 200 from the input port 301, the control circuit 329 first confirms the destination output port indicated by the first routing information 206 in the packet 200, and among the switching state information in the switching state register 309, The switching state information corresponding to the destination output port (hereinafter referred to as “corresponding switching state information”) is checked (step 501).

First, when the correspondence switching state information is “0” or “2”, that is, in the case of step 502, the control circuit 329 checks whether or not the packet 200 is a packet that requires order guarantee (step 503). .

When the order guarantee flag 202 of the packet 200 is “1”, that is, in the case of step 504, the control circuit 329 checks the value of the in-process register 312 (step 505).

When the in-process register 312 stores “1”, that is, in the case of step 506, the control circuit 329 checks the last packet flag 203 of the packet 200 (step 507).

If the last packet flag 203 indicates “1”, that is, the last packet, that is, in the case of step 508, the control circuit 329 changes the value of the in-process register 312 from “1” to “0”. (Step 509).

When the last packet flag 203 indicates “0”, that is, it is not the last packet, that is, in the case of Step 510, the control circuit 329 does not change the value of the in-process register 312.

When the in-process register 312 stores “0”, that is, in the case of step 511, it means that the first packets of a plurality of packets that require order guarantee have arrived. Therefore, the control circuit 329 stores “1” in the in-progress register 312 (step 512).

When the order guarantee flag 202 of the packet 200 is “0”, that is, in the case of step 513, the control circuit 329 does not change the value of the in-process register 312.

The control circuit 329 checks whether the correspondence switching state information is “0” or “2” following

Step

509, 510, 512 or 513 (Step 514).

When the correspondence switching state information is “0”, that is, in the case of step 515, the control circuit 329 specifies a number corresponding to the destination output port from the numbers in the normal destination register 311, and the number is A request is sent to the added arbitration circuit (step 516).

When the correspondence switching state information is “2”, that is, in the case of step 517, the control circuit 329 specifies the number corresponding to the destination output port from the numbers in the switching destination register 310, and the number is A request is sent to the added arbitration circuit (step 518).

Next, when the correspondence switching state information is “1”, that is, in the case of step 519, a failure occurs in the network plane connected to the destination output port, and the control circuit 329 accepts a transfer destination switching instruction. In this state, “1” is stored in the correspondence switching state information.

In this case, the control circuit 329 first checks whether the packet 200 is a packet that requires order guarantee (step 520).

When the order guarantee flag 202 of the packet 200 is “1”, that is, in the case of step 521, the control circuit 329 checks the value of the in-process register 312 (step 522).

When the in-process register 312 stores “1”, that is, in the case of step 523, the control circuit 329 checks the last packet flag 203 of the packet 200 (step 524).

When the last packet flag 203 indicates “1”, that is, the last packet, that is, in the case of step 525, the control circuit 329 changes the value of the in-process register 312 from “1” to “0”. (Step 526).

Subsequently, the control circuit 329 specifies a number corresponding to the destination output port from the numbers in the normal destination register 311 and sends a request to the arbitration circuit to which the number is added (step 527).

When the last packet flag 203 indicates “0”, that is, not the last packet, that is, in the case of step 528, the control circuit 329 executes step 527 without changing the value of the in-process register 312. To do.

When the in-process register 312 stores “0”, that is, in the case of step 529, it means that the first packets of a plurality of packets that require the order guarantee have arrived. For this reason, the control circuit 329 can send all of the plurality of packets that require the order guarantee to the network plane of the switching destination.

Therefore, the control circuit 329 changes the correspondence switching state information from “1” to “2” (step 530), and stores “1” in the in-progress register 312 (step 531).

Subsequently, the control circuit 329 specifies a number corresponding to the destination output port from the numbers in the switching destination register 310, and sends a request to the arbitration circuit to which the number is added (step 532).

When the order guarantee flag 202 of the packet 200 is “0”, that is, in the case of step 533, the control circuit 329 executes step 532.

Finally, when the correspondence switching state information is “3”, that is, in the case of step 534, the network plane connected to the destination output port is restored and the network plane can be used.

In this case, the control circuit 329 first checks whether the packet 200 is a packet that requires order guarantee (step 535).

When the order guarantee flag 202 of the packet 200 is “1”, that is, in the case of step 536, the control circuit 329 checks the value of the in-process register 312 (step 537).

When the in-process register 312 stores “1”, that is, in the case of step 538, the control circuit 329 checks the last packet flag 203 of the packet 200 (step 539).

When the last packet flag 203 indicates “1”, that is, the last packet, that is, in the case of step 540, the control circuit 329 changes the value of the in-process register 312 from “1” to “0”. (Step 541).

Subsequently, the control circuit 329 specifies a number corresponding to the destination output port from the numbers in the switching destination register 310, and sends a request to the arbitration circuit to which the number is added (step 542).

When the last packet flag 203 indicates “0”, that is, it is not the last packet, that is, in the case of step 543, the control circuit 329 executes step 542 without changing the value of the in-process register 312. To do.

When the in-process register 312 stores “0”, that is, in the case of step 544, it means that the first packets of a plurality of packets that require order guarantee have arrived. For this reason, the control circuit 329 can send all of a plurality of packets that require an order guarantee to the normal destination network plane.

Therefore, the control circuit 329 changes the correspondence switching state information from “3” to “0” (step 545), and stores “1” in the in-progress register 312 (step 546).

Subsequently, the control circuit 329 specifies a number corresponding to the destination output port from the numbers in the normal destination register 311 and sends a request to the arbitration circuit to which the number is added (step 547).

When the order guarantee flag 202 of the packet 200 is “0”, that is, in the case of step 548, the control circuit 329 executes step 547.

Next, the operation of the crossbar between planes according to the embodiment of the present invention will be described with reference to FIGS. 6A to 6E. 6A to 6E, the same components as those shown in FIG. 3 are denoted by the same reference numerals.

FIG. 6A is an explanatory diagram showing a state immediately before a failure occurs in the network plane 102. All of the switching status registers 309, 313, 317 and 321 store “0” as the switching status information.

FIG. 6B is an explanatory diagram showing a state immediately after a failure occurs in the network plane 102. In all of the switching status registers 309, 313, 317, and 321, registers 601 to 604 corresponding to the output port 306 (number “1”) store “1” as switching status information.

FIG. 6C is an explanatory diagram showing a situation in which a packet arrives at the

input ports

301 and 303 and is processed.

First, the packet 605 addressed to the output port 306 that requires the order guarantee arrives at the input port 301 from the processor 113.

At this time, the in-process register 312 corresponding to the input port 301 stores “1”. For this reason, even if the register 601 in the switching status register 309 stores “1”, the control circuit 329 selects the number “1” 606 corresponding to the output port 306 from the numbers in the normal destination register 311. The request is sent to the arbitration circuit 334 assigned with the number “1”, and the packet 605 is sent to the network plane 102.

Next, a packet 607 addressed to the output port 306 that requires the order guarantee arrives at the input port 303 from the processor 115.

At this time, the in-process register 320 corresponding to the input port 303 stores “0”. For this reason, the control circuit 331 determines that the packet 607 is the first packet of a plurality of packets that require order guarantee.

Therefore, the control circuit 331 changes the value of the register 603 in the switching status register 317 from “1” to “2”, changes the value of the in-progress register 320 from “0” to “1”, and switches the switching destination register. The number “2” 608 corresponding to the output port 306 is identified from the numbers in 318, the request is sent to the arbitration circuit 335 to which the number “2” is assigned, and the packet 607 is sent to the network plane 103. .

FIG. 6D is an explanatory diagram showing a state immediately after the network plane 102 that has been disconnected due to a failure has been recovered. In all of the switching status registers 309, 313, 317, and 321, the registers 601 to 604 corresponding to the output port 306 (number “1”) store “3” as the switching status information.

FIG. 6E is an explanatory diagram showing a situation where a packet arrives at the

input ports

301 and 304 and is processed.

First, a packet 609 addressed to the output port 306 that requires the order guarantee arrives at the input port 301 from the processor 113.

At this time, the in-process register 312 corresponding to the input port 301 stores “0”. For this reason, the control circuit 329 determines that the packet 609 is the first packet of a plurality of packets that require order guarantee.

Therefore, the control circuit 329 changes the value of the register 601 in the switching status register 309 from “3” to “0”, changes the value of the in-progress register 312 from “0” to “1”, and sets the normal destination register. A number “1” 606 corresponding to the output port 306 is identified from the numbers in 311, a request is sent to the arbitration circuit 334 to which the number “1” is assigned, and a packet 609 is sent to the network plane 102. .

Next, the last packet 610 addressed to the output port 306 that requires the order guarantee arrives at the input port 304 from the processor 116.

At this time, the in-process register 324 corresponding to the input port 304 stores “1”. Therefore, the control circuit 332 changes the value of the in-process register 324 from “1” to “0”, and specifies the number “2” 611 corresponding to the output port 306 from the numbers in the switching destination register 322. Then, a request is sent to the arbitration circuit 335 to which the number “2” is assigned, and a packet 610 is sent to the network plane 103.

According to the present embodiment, each of the storage units 105a to 105b has a processor connected to an input port corresponding to the storage unit 105a to 105b having transmitted one or more packets among a plurality of predetermined packets, and In-communication information indicating that communication is in progress when all of the plurality of packets are not transmitted is stored.

The control unit 105e, in the situation where the storage unit corresponding to a certain input port among the storage units 105a to 105b stores communication information, instructs to switch the transfer destination of the packet from that input port. When all of the predetermined packets sent to the input port are transferred to the network plane set as the transfer destination, the transfer destination is transferred to the other network plane among the plurality of network planes. Switch.

For this reason, even if a switching instruction is accepted, it is possible to transfer all of a plurality of predetermined packets transmitted from one processor to the same network plane. Therefore, it becomes possible to guarantee the order of a plurality of predetermined packets.

In the present embodiment, a plurality of packets that require order assurance are used as the predetermined plurality of packets. In this case, the order can be guaranteed for a plurality of packets that need to be ordered.

In the present embodiment, the control unit 105e has the transfer destination switched to another network plane, and the storage unit corresponding to one input port among the storage units 105a to 105b stores the information during communication. When receiving an instruction to switch the communication path to the original network plane, all of a plurality of predetermined packets transmitted to the input port are transferred to other network planes. Switch from the other network plane to the original network plane.

In this case, for example, even when the failed network plane is repaired and then restored, a predetermined plurality of packets transmitted from one processor can be transferred to the same network plane. Therefore, it becomes possible to guarantee the order of a plurality of predetermined packets.

In this embodiment, a plurality of independent partial networks (network planes) that are not directly connected to each other are used as a plurality of communication paths.

In this case, when a plurality of partial networks are used as a plurality of communication paths, the order of a plurality of packets can be guaranteed.

In this embodiment, the interprocessor network 2 includes a plurality of network planes 101 to 104 and at least one interplane crossbar. In this case, it is possible to guarantee the order of a plurality of packets in the interprocessor network 2.

In this embodiment, the parallel processor system 1 includes a plurality of processors 113 to 144 and an interprocessor network 2. In this case, the parallel processor system 1 can guarantee the order of a plurality of packets.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to the drawings.

The configuration of the parallel processor system 1 of the second embodiment is the same as that of FIG. 1 of the first embodiment except that the configuration of the registers in each storage unit in each interplane crossbar is simplified. It is.

In the second embodiment, the interplane crossbars 105A to 112A in which the configuration of each register in each storage unit is simplified are used instead of the interplane crossbars 105 to 112.

In the second embodiment, the packet output destination in the normal case is determined in advance according to each input port of the interplane crossbar. In other words, the network plane that is normally used is determined by the processor.

All network planes 101 to 104 are connected to all interplane crossbars 105A to 112A. Therefore, each of the interplane crossbars 105A to 112A can transmit a packet to a destination interplane crossbar, more specifically, a destination processor, regardless of which network plane is used.

FIG. 7 is an explanatory diagram for explaining the format of the packet 700 used in the second embodiment. In FIG. 7, the same information as that shown in FIG.

Packet 700 is generated by each of processors 113-144. In the present embodiment, each of the processors 113 to 144 generates a plurality of packets 700 by dividing the transmission data. Each of the processors 113 to 144 transmits individual packets 700 to the inter-processor network 2 one by one in order.

The packet 700 includes routing information 701, an order guarantee flag 202, a last packet flag 203, a packet length 204, and data 205.

The routing information 701 is used for routing in the interprocessor network 2. The routing information 701 includes second routing information 207 and third routing information 208.

In this embodiment, the routing in the direction of the network plane in the interplane crossbars 105A to 112A has already been determined. For this reason, routing information for designating the direction to the network plane in the interplane crossbars 105A to 112A is not added to the packet 700.

FIG. 8 is an explanatory diagram showing details of the crossbar 105A between planes. In FIG. 8, the same components as those shown in FIG.

8 shows the interplane crossbar 105A, but the interplane crossbars 105A to 112A all have the same configuration, except that the connected processor is changed. For this reason, the description about the other crossbar between planes is abbreviate | omitted.

FIG. 8 shows only the data path in the direction toward the network plane in the cross-plane crossbar 105A. Note that the data path in the direction to the processor in the interplane crossbar 105A is the same as that shown in FIG. 4 in the first embodiment.

Hereinafter, the interplane crossbar 105 </ b> A will be described focusing on differences from the interplane crossbar 105.

The interplane crossbar 105A includes storage units 105aA to 105dA and a control unit 105eA.

Each of the storage units 105aA to 105dA can be generally referred to as storage means.

The storage unit 105aA includes a switching status register 801, a switching destination register 802, a normal destination register 803, and a pending register 804. The storage unit 105bA includes a switching status register 805, a switching destination register 806, a normal destination register 807, and a pending register 808. The storage unit 105cA includes a switching status register 809, a switching destination register 810, a normal destination register 811, and a pending register 812. The storage unit 105dA includes a switching status register 813, a switching destination register 814, a normal destination register 815, and a pending register 816.

Control unit 105eA can be generally referred to as control means.

The control unit 105eA includes multiplexers 325 to 328, control circuits 329A to 332A, and arbitration circuits 333 to 336.

The input port 301 is associated with the storage unit 105aA and the control circuit 329A. The input port 302 is associated with the storage unit 105bA and the control circuit 330A. The input port 303 is associated with the storage unit 105cA and the control circuit 331A. The input port 304 is associated with the storage unit 105dA and the control circuit 332A.

Each of the normal destination registers 803, 807, 811 and 815 stores the number of the arbitration circuit corresponding to the output port (hereinafter referred to as “corresponding output port”) determined by the input port corresponding to itself.

The normal destination register 803 stores the number “0”. The normal destination register 807 stores the number “1”. The normal destination register 811 stores the number “2”. The normal destination register 815 stores the number “3”.

Each of the switching destination registers 802, 806, 810, and 814 stores the number of the output port that is switched from the corresponding output port.

Each of the switching destination registers 802, 806, 810 and 814 stores the value calculated by adding 1 to the corresponding output port number as the number of the arbitration circuit corresponding to the output port of the switching destination.

Each of the switching status registers 801, 805, 809 and 813 stores switching status information (any one of “0” to “3”) indicating the switching status of the corresponding output port.

When the switching state information is “1”, the packet 700 is in the normal destination register depending on whether the packet 700 is a packet that requires order guarantee and the number of the packet that requires order guarantee. Or the number in the switch destination register is used.

In the second embodiment, the method for determining the number to be used and the operation when the switching state information changes from “1” to “2” are the same as the operations of the first embodiment described with reference to FIG. It is.

Among the output ports of the crossplanes 105A to 112A between the planes, when the switching status information of all output ports connected to the network plane where the failure has occurred changes from “1” to “2”, the network plane where the failure has occurred is used. I will not be broken.

When the switching state information is “3”, the packet 700 is in the normal destination register depending on whether the packet 700 is a packet that requires the order guarantee and the number of the packet that requires the order guarantee. Or the number in the switch destination register is used.

In the second embodiment, the method for determining the number to be used and the operation when the switching state information is changed from “3” to “0” are the same as those in the first embodiment described with reference to FIG. It is.

The example shown in FIG. 8 shows a state where a failure has not yet occurred. Therefore, all the switching state information is “0”.

Each of the in-process registers 804, 808, 812, and 816 has a processor connected to its corresponding input port having transmitted one or more packets out of a plurality of packets that require an order guarantee, and When all of the plurality of packets are not transmitted, communication information “1” indicating that communication is in progress is stored.

When each of the control circuits 329A to 332A receives a packet transmitted first among a plurality of packets that require an order guarantee from an input port corresponding to the control circuit 329A to 332A, “1” (information during communication) is stored.

When each of the control circuits 329A to 332A receives the last transmitted packet from the input ports corresponding to the control circuit 329A to 332A, the in-progress register corresponding to the same input port as that of the control circuit 329A to 332A is received. "1" (information during communication) is deleted and "0" is stored.

Each of the control circuits 329A to 332A determines whether or not the packet 700 received from the input port corresponding to the control circuit 329A to 332A is the last packet transmitted among a plurality of packets that require order guarantee. The state of the packet flag 202 is checked and determined.

When the last packet flag 202 is “0”, each of the control circuits 329A to 332A determines that the packet 700 is not the last packet transmitted among a plurality of packets that require order guarantee.

On the other hand, when the last packet flag 202 is “1”, each of the control circuits 329A to 332A determines that the packet 700 is the last packet transmitted among a plurality of packets that require order guarantee.

Further, each of the control circuits 329A to 332A, when the value of the in-process register corresponding to the same input port as that of itself is “0” and the packet 700 that requires the order guarantee arrives, It is determined that the packet is the first packet transmitted among a plurality of packets that need to be guaranteed.

Each of the control circuits 329A to 332A transmits a transmission request to the arbitration circuit 333 when transferring the packet 700 to the output port 305 according to the information in the storage unit corresponding to the same input port as the control circuit 329A to 332A.

When each of the control circuits 329A to 332A transfers the packet 700 to the output port 306 in accordance with the information in the storage unit corresponding to the same input port as itself, the control circuit 329A to 332A transmits a transmission request to the arbitration circuit 334.

Each of the control circuits 329A to 332A transmits a transmission request to the arbitration circuit 335 when transferring the packet 700 to the output port 307 according to the information in the storage unit corresponding to the same input port as the control circuit 329A to 332A.

When each of the control circuits 329A to 332A transfers the packet 700 to the output port 308 according to the information in the storage unit corresponding to the same input port as itself, the control circuit 329A to 332A transmits a transmission request to the arbitration circuit 336.

Each of the control circuits 329A to 332A has a destination register (transfer destination) of the packet 700 when the value of the in-process register corresponding to the same input port as that of the control circuit 329A to 332A arrives and the packet 700 that requires the order guarantee arrives. Do not switch the output port.

When each of the arbitration circuits 333 to 336 receives a request from any of the control circuits 329A to 332A, an instruction to select an input port corresponding to the control circuit that transmitted the request is sent to the same output port as itself. Output to the corresponding multiplexer.

In each of the storage units 105aA to 105bA, the processor connected to the input port corresponding to the storage unit 105aA to 105bA has already transmitted one or more packets out of a predetermined plurality of packets (for example, a plurality of packets requiring order guarantee). In addition, when all of the plurality of packets are not transmitted, in-communication information indicating that communication is in progress is stored.

When the control unit 105eA receives individual packets constituting a predetermined plurality of packets from a certain input port, the control unit 105eA transfers the packets to the network plane set as the transfer destination.

The control unit 105eA performs switching to switch the transfer destination of a packet from the input port in a situation where the storage unit corresponding to a certain input port among the storage units 105aA to 105bA stores information during communication. When the instruction is accepted, all of the predetermined packets transmitted to the input port are transferred to the network plane set as the transfer destination, and then the transfer destination is changed to another network plane of the plurality of network planes. Switch to.

According to the present embodiment, the output port, that is, the network plane that is normally used is determined by the interplane crossbar 105. For this reason, the same effects as those of the first embodiment can be obtained, and it is not necessary to describe the first routing information 206 in the packet.

Next, effects of the above embodiments will be described.

According to each of the embodiments described above, the interplane crossbar has, for each processor, the processor has already communicated one or more packets out of a plurality of packets requiring order guarantee, and the last packet is still communicated. If the last packet is communicated, the transfer destination of the packet is switched from the partial network where the failure has occurred to another predetermined partial network.

For this reason, when the packet transfer destination is switched from the failed partial network to another predetermined partial network, it is possible to guarantee the order of a plurality of packets requiring order guarantee.

Also, the packet that was scheduled to be sent to the failed partial network is sent to another predetermined partial network. For this reason, it becomes possible to predict the influence on the communication performance when the partial network is switched.

As mentioned above, although this invention was demonstrated with reference to each embodiment, this invention is not limited to the said embodiment. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

This application claims priority based on Japanese Patent Application No. 2008-297981, filed on November 21, 2008, the entire disclosure of which is incorporated herein.

101-104 Network plane 105-112 Crossbar between planes 113-144 Processor 145-147 Crossbar 105a-105d, 105aA-105dA Storage unit 105e, 105eA Control unit 200, 700

Packet

201, 701 Routing information 202 Order guarantee flag 203 Last packet Flag 204 Packet length 205 Data 206 First routing information 207 Second routing information 208 Third routing information 301 to 304 Input ports 305 to 308

Output ports

309, 313, 317, 321, 801, 805, 809, 813 Switching Status registers 310, 314, 318, 322, 802, 806, 810, 814 Switching destination registers 311, 315, 319, 323, 803, 807, 811, 815

Normal destination register

312, 316, 320, 324, 804, 808, 812, 816 In-progress register 325-328 Multiplexer 329-332, 329A-332A Control circuit 333-336 Arbitration circuit 401-404 Input Port 405 to 408 Output port 409 to 412 Multiplexer 413 to 416 Control circuit 417 to 420 Arbitration circuit 601 to 604

Register

605, 607, 609, 610

Packet

606, 608, 611 Number

Claims

A communication path which receives a plurality of predetermined packets addressed to the second processor, which are sequentially transmitted from the first processor, and is set as a transfer destination among the plurality of communication paths leading to the second processor. A packet transfer device for transferring to
When the first processor has transmitted one or more of the plurality of packets and has not transmitted all of the plurality of packets, communication information indicating that communication is in progress is stored. Storage means for
In a situation where the information during communication is stored in the storage unit, when receiving the transfer destination switching instruction, after all of the plurality of packets are transferred to the communication path set as the transfer destination, Control means for switching a transfer destination to another communication path among the plurality of communication paths.
The packet transfer apparatus according to claim 1, wherein the predetermined plurality of packets are a plurality of packets that require order guarantee.
The control means instructs to switch the communication path to the original communication path when the transfer destination is switched to the other communication path and the in-communication information is stored in the storage means. When all of the plurality of packets are transferred to the other communication path, the transfer destination is switched from the other communication path to the original communication path. Packet transfer device.
An interprocessor communication system including the packet transfer apparatus according to any one of claims 1 to 3 and the plurality of communication paths.
The inter-processor communication system according to claim 4, wherein the plurality of communication paths are a plurality of independent partial networks that are not directly connected to each other.
A parallel processor system comprising the interprocessor communication system according to claim 4, the first processor, and the second processor.
A communication path which receives a plurality of predetermined packets addressed to the second processor, which are sequentially transmitted from the first processor, and is set as a transfer destination among the plurality of communication paths leading to the second processor. A packet transfer method performed by a packet transfer apparatus for transferring to
In-communication information indicating that communication is being performed when the first processor has transmitted one or more packets of the plurality of packets and has not transmitted all of the plurality of packets, Store in storage means,
In a situation where the information during communication is stored in the storage unit, when receiving the transfer destination switching instruction, after all of the plurality of packets are transferred to the communication path set as the transfer destination, A packet transfer method for switching a transfer destination to another communication path among the plurality of communication paths.
The packet transfer method according to claim 7, wherein the predetermined plurality of packets are a plurality of packets that require order guarantee.
When the transfer destination is switched to the other communication path and the communication information is stored in the storage unit, an instruction to switch the communication path to the original communication path is received. The packet transfer method according to claim 7 or 8, wherein after all of a plurality of packets are transferred to the other communication path, the transfer destination is switched from the other communication path to the original communication path.
A communication path which receives a plurality of predetermined packets addressed to the second processor, which are sequentially transmitted from the first processor, and is set as a transfer destination among the plurality of communication paths leading to the second processor. A packet transfer method performed by an inter-processor communication system including a packet transfer device that transfers data to a plurality of paths,
The packet transfer device is in communication indicating that communication is in progress when the first processor has already transmitted one or more of the plurality of packets and has not transmitted all of the plurality of packets. Store information in storage means,
When the packet transfer apparatus accepts the transfer destination switching instruction in a situation where the communication information is stored in the storage unit, all of the plurality of packets are transferred to the communication path set as the transfer destination. A packet transfer method for switching the transfer destination to another communication path among the plurality of communication paths after being transferred.
The packet transfer method according to claim 10, wherein the plurality of communication paths are a plurality of independent partial networks that are not directly connected to each other.
Receiving a first processor, a second processor, a plurality of communication paths leading to the second processor, and a plurality of predetermined packets addressed to the second processor transmitted one by one from the first processor in sequence; A packet transfer method performed by a parallel computer system performed by a parallel processor system including a packet transfer device configured to transfer a packet to a communication path set as a transfer destination among the plurality of communication paths,
The packet transfer device is in communication indicating that communication is in progress when the first processor has already transmitted one or more of the plurality of packets and has not transmitted all of the plurality of packets. Store information in storage means,
When the packet transfer apparatus accepts the transfer destination switching instruction in a situation where the communication information is stored in the storage unit, all of the plurality of packets are transferred to the communication path set as the transfer destination. A packet transfer method for switching the transfer destination to another communication path among the plurality of communication paths after being transferred.