WO2010052682A2

WO2010052682A2 - Mems with poly-silicon cap layer

Info

Publication number: WO2010052682A2
Application number: PCT/IB2009/054992
Authority: WO
Inventors: Greja Johanna Adriana Verheijden; Gerhard Koops
Original assignee: Nxp B.V.
Priority date: 2008-11-10
Filing date: 2009-11-10
Publication date: 2010-05-14
Also published as: WO2010052682A3

Abstract

The present invention relates to a novel way of sealing a MEMS and the MEMS obtained thereby. MEMS resonators are being intensively studied in many research groups and some first products have recently been released. This type of device offers a high Q-factor, small size, high level of integration and potentially low cost. These devices are expected to replace bulky quartz crystals in high-precision oscillators and may also be used as RF filters. The oscillators are widely used in time-keeping and frequency reference applications such as RF modules in mobile phones, devices containing blue-tooth modules and other digital and telecommunication devices.

Description

MEMS with poly-silicon cap layer

FIELD OF THE INVENTION

The present invention relates to a novel way of sealing a MEMS and the MEMS obtained thereby.

BACKGROUND OF THE INVENTION

MEMS resonators are being intensively studied in many research groups and some first products have recently been released. This type of device offers a high Q-factor, small size, high level of integration and potentially low cost. These devices are expected to replace bulky quartz crystals in high-precision oscillators and may also be used as RF filters. The oscillators can be used in time-keeping and frequency reference applications such as RF modules in mobile phones, devices containing blue-tooth modules and other digital and telecommunication devices. Microelectromechanical systems (MEMS) are the technology of the very small, and merge at the nano-scale into nanoelectromechanical systems (NEMS) and nanotechnology. MEMS are also referred to as micromachines (in Japan), or Micro Systems Technology - MST (in Europe). MEMS are separate and distinct from the hypothetical vision of Molecular nanotechnology or Molecular Electronics. NEMS are made up of components between 1 to 100 μm in size (i.e. 0.001 to 0.1 mm) and MEMS devices generally range in size from a 20 μm to a millimeter. They usually consist of a central unit that processes data, the microprocessor and several components that interact with the outside such as microsensors. At these size scales, the standard constructs of classical physics do not always hold true. Due to MEMS' large surface area to volume ratio, surface effects such as electrostatics and wetting dominate volume effects such as inertia or thermal mass.

A MEMS device can be protected for dicing and molding by a wafer level encapsulating process. Because MEMS devices are fragile, e.g. due to moving parts typically being present, and the device performance is affected by impurities, they have to be protected during wafer dicing and bonding. Some MEMS structures (e.g. MEMS resonators) need to be hermetically sealed from the environment since gas pressure has a direct influence on the properties of the MEMS device. Other MEMS structures (e.g. MEMS switches) need a well-controlled gas environment in order to function optimally. This protection can be achieved by an integrated wafer level encapsulating process. This means that a MEMS structure is e.g. build inside a cavity with an encapsulation shell, e.g. by using state of the art processing steps. Fig. 1 shows a schematic diagram of a typical concept of an integrated encapsulation process. This process typically includes the following steps: a) Completion of a surface-micro machined device with a sacrificial spacer layer remaining on the wafer. b) Additional sacrificial layer deposition and patterning followed by a packaging cap layer deposition and patterning for the formation of an encapsulation shell with release etching channel holes. Removal of the sacrificial layer to release micro-mechanical structures and c) Sealing of release channels and holes by another or similar deposition process. One of the biggest problems of the above concept is that, during the sealing of the release holes and channels by another deposition process (step c in Fig. 1), typically some material (impurities) will be deposited inside the cavity. An example of this deposition can be seen in Fig. 2, which shows an X-section SEM picture of release holes, which is sealed by a PECVD deposition process. If these impurities are deposited on top of the MEMS structure the weight and shape thereof will change, which as a consequence has a big impact on the MEMS device performance. In a prior art option, this deposition might be avoided by designing the release holes next to the MEMS structure, and if it is necessary with horizontal etch channels. This option has as disadvantage that a cavity becomes larger, and more area means more cost. Moreover, a bigger cavity means that the capping layer has to be stronger and/or thicker. Another disadvantage is that the release etch time will increase due to the longer traveling distance of the release etchants. Further, still no guaranty is present that no deposition on the MEMS structure will take place, albeit being less extensive. The most difficult step of this encapsulation process is the sealing of the release holes, without leaving impurities inside the cavity.

Various documents disclose forming of MEMS structures. WO2008/034233 describes the use of barrier walls to prevent contaminants from reaching sensitive parts if the device. The method and structure are different from those presented in the present invention.

The above disclosure describes the provision of a barrier "wall" to prevent that the soldering layer of the CAP -wafer is contaminating a MEMS- structure. A separate cap-wafer is used. More-over, separate patterning steps are needed.

EP 1908727, US5090254 and WO2008/085779 describe additional state of the art methods to create encapsulated MEMS devices using release holes and sacrificial layers.

EP 1908727 discloses using long etch long etch channels to prevent that a sealing layer is deposited in-side the cavity on top of the MEMS-structure. These long etch channels increase the release etch time and introduce extra process steps.

US5090254 discloses an oxidation process to seal the cavity. This oxidation process will also oxidize the silicon resonator.

In WO2008/085779 it is not prevented that impurities are deposited inside the cavity. Design of the location of the release holes is such that the impurities will not impact the MEMS resonator. A disadvantage thereof is that the locations of the release holes are not designed to have an optimal release, which can increase the release time or result in an incomplete release.

US2007/0023890 and US2004/0121506 are examples of other MEMS devices with release structures.

In invention US2007/0023890 no special step is used to seal the release holes. Therein holes are sealed with a separate lid (for example glass), which is an expensive and time-consuming process step.

In invention US2004/0121506 a method is described to release a MEMS-structure and not an encapsulation process.

However, none of the above mentioned documents describes contamination problems or sealing problems arising from the growth of SiGe on poly- silicon when closing release holes. Further, a method for sealing the release holes without leaving impurities inside the cavity has been described, where migration of silicon atoms by H₂-anneal is used for closing release holes of a MEMS cavity. However, when the atoms of the poly-silicon cap are moving during the anneal, the atoms of the silicon resonator itself also become mobile. This should be avoided since it will change the parameters of the resonator. This migration of the silicon could be prevented by a protection layer, for example a thin LPCVD silicon nitride layer, such as has been mentioned. A disadvantage for using such a layer is that this layer has to be deposited before the sacrificial layer of the cavity is deposited and therefore the resonator has first to be released. This means that two release etches are necessary. Another disadvantage of this method is that, processing on top of the fragile released MEMS structures is needed, with a risk of destroying the characteristics of said MEMS. Another attention point of such protection layer is that it has to withstand high annealing temperatures and has to be resistant to sacrificial etch. The migration temperature can be lowered, so the resonator will not be damaged, by using SiGe instead of poly-silicon. But poly-silicon layers are much more used and therefore better known. So poly-silicon layers are preferred, because these are easier to tune with respect to various characteristics, like stress.

In the prior art a method is described where spacers made of PoIy- silicon or SiGe inside a release hole are used for the sealing process with Fb-anneal, instead of making a full cap layer of poly-silicon or SiGe. To have the advantage of a poly-silicon cap layer, but with a low SiGe annealing temperature, spacers of SiGe in a poly-silicon cap layer are proposed. Unfortunately, SiGe is mixing with the poly- silicon during the Fb-anneal. This gives a sealing behavior, which is depended on e.g. release holes density and is therefore proven unreliable. This can be seen on the SEM pictures displayed in Fig. 3. This picture shows two cavities, after H^-anneal on the same wafer, with on the left side a dense release holes pattern and on the right side an isolated pattern.

The present invention describes a method to overcome one or more of the above mentioned problems.

SUMMARY OF THE INVENTION

The present invention relates to a method for forming a MEMS in a cavity, comprising the step of: forming spacers and openings and closing said openings by annealing said spacers, the use of spacers for encapsulating a MEMS device, and a MEMS with a poly-silicon cap layer, which poly-silicon cap layer comprises spacers.

To have the advantage using H2-anneal for sealing the release holes of a MEMS cavity with a poly-silicon cap layer but with the low SiGe annealing temperatures, spacers of SiGe in a poly-silicon cap layer are proposed. However, SiGe is mixing with the poly-silicon during the ϊb-anneal, which gives a sealing behavior depending on the release holes density, and this is therefore unreliable. The solution to overcome this problem is a separation layer between the poly-silicon and SiGe. This separation layer can be LPCVD-nitiride for instance.

DETAILED DESCRIPTION OF THE INVENTION

In a first aspect the invention relates to a method for forming a MEMS in a cavity, comprising the step of: forming spacers and openings in a surface and closing said openings by annealing said spacers.

The present method provides a well controlled way of sealing, without a risk of destroying characteristics of the MEMS, and without the above drawbacks of the prior art.

In a preferred embodiment the present method comprises the steps of: providing a surface micromachined device (resonator), depositing a sacrificial layer and patterning said layer, depositing a cap-layer, preferably a Poly-silicon layer, - patterning and etching release holes in the cap-layer, optionally depositing a protection layer, depositing a further layer, such as a Si or a SiGe layer, exposing the further layer to an etch step, preferably a dry-etch plasma step, creating spacers and openings, - optionally opening the protection layer at the bottom during said etch step, and thereby removing the sacrificial layer, emptying the cavity by an etch step, preferably a sacrificial etch step, thereby releasing the MEMS structure, and annealing the spacer layer, preferably by H₂-anneal, in order to seal the cavity.

Typically the micromachined device relates to a resonator.

The sacrificial layer is typically a silicon oxide or silicon nitride layer. The cap (or capping) layer can be any layer, which hermitically seals the underlying device. A preferred layer is silicon, such as poly silicon. Such a layer is easily incorporated in a standard process flow. The thickness of the cap layer should be large enough to provide said hermitic sealing and give enough strength to the cavity so this will not collapse during further processing. Patterning of release holes is done by standard lithographic processes.

Etching of the release holes is done by standard etch techniques, such as dry etch techniques.

A protection layer is optionally provided. Such a layer provides a separation between subsequent deposited or formed layers and underlying layers. A further layer is deposited. Said layer will form spacers. Therefore such a layer may comprise any material capable of forming spacers. However, Si and SiGe are preferred. These, or similar materials, can easily be integrated in standard process techniques for manufacturing the present device, such as CMOS.

The further layer is then exposed to an etch step, in order to form spacers. At the same time openings are created in the optional protecting layer, if present.

Subsequently the sacrificial layer is removed by an etch step, such as a dry etch step. This dry etch step typically is a standard dry etch step for removing a sacrificial layer. The protection layer has to be opened at the bottom of the release holes in order to allow the sacrificial etch to remove the sacrificial layer to empty the cavity and release the MEMS structure.

The opening of the protection layer can be done by the same or another etch chemistry as the spacer etch, however not with the same chemistry as the sacrificial layer etch, because this will cause that the entire protection layer is removed during this etch, and it will also remove the spacers.

The spacers formed are subsequently annealed, thereby sealing the cavity hermetically. Preferably an H₂ anneal is used, as it is a well controlled anneal, and further does not require high temperatures. In the present invention it has been found that no electrical interference can take place between cap layer and MEMS device if the cap layer is made of an isolating material, such as a dielectric material. This is not the case for the prior art, where the whole cap layer is made of poly-silicon or SiGe. A disadvantage of said electrical interference is that it limits the minimum distance between cap and MEMS- device. Therefore, as an advantage, the present cavity can be made smaller and is therefore better suited for applications where thin MEMS devices are required. So preferably the present invention relates to thin MEMS devices, such as those having a thickness of less than 1.0 μm. Dimensions of the spacers are typically in the order of 0.2 - 2.0 μm high, such as 1.0 μm, and from 0.05 - 0.5 μm wide, such as from 0.1-0.3 μm wide, such as 0.2 μm. Dimensions of the cap layer are typically from 0.3 -3.0 μm thick, such as 1.0 μm thick. Density of the holes is typically from 0.01 - 0.25 per μm², such as from 0.05 - 0.1 per μm². Preferably the release holes are situated above the MEMS structure, thereby saving space.

Moreover, if a conductive cap layer is used, as above, an extra mask is needed to isolate bondpads being provided.

Thus, the present inventors have found a solution of to the above problems, namely to make spacers of poly-silicon or SiGe inside release holes, forming an isolating cap layer, e.g. by LPCVD silicon nitride. During a subsequent thermal H₂ anneal, atoms in the SiGe or poly-silicon spacer will become mobile and start moving and close the hole. In this way the biggest part of the cap layer can be made of an isolating, e.g. dielectric material and only a small part of this cap layer will be conductive and so the electrical interference is less or negligible compared to a fully conducting cap.

Thereby e.g. the following advantages are provided:

1. The providing of spacers is a mask- less process step. So cost increase of a process is low. Moreover, a spacer etch is commonly used in most fabs.

2. An isolated capping layer can be used, and as the space between a cap and MEMS device is thus only limited by the moving parts of the MEMS structure, the encapsulation shell can be made small. Moreover, no extra mask is needed for isolating subsequent bond-pads. 3. During sealing no impurities are deposited inside the cavity, so the release holes can be designed above the resonator. This limits release etch time, and also decreases cavity size.

It is noted that a cap layer made of poly-silicon has advantages of being strong, being hermetic, and being well known in the art and therefore tunable.

In order to have the advantage of a strong poly-silicon cap layer but still having the low annealing temperatures used by SiGe reflow, the present inventors suggested to make SiGe spacers inside the release holes of a poly-silicon cap layer. Unfortunately SiGe is mixing with poly-silicon during an H₂-anneal. It has been found that this gives a sealing behavior, which is depended on the release holes density and therefore unreliable or not applicable in all instances. After thorough research it has been found that to overcome this problem a separation or protection layer between the poly-silicon and SiGe is preferably present. Such a separation layer is preferably a dielectric layer, such as a silicon nitride layer. As such, advantages of a poly-silicon cap layer are used, combined with the advantage of the low annealing temperature of SiGe.

Further advantages of this embodiment of the present invention are e.g.:

The provision of spacers is a mask- less process step. So cost increase of a process is low. Moreover, it is noted that a spacer etch is commonly used in most fabs.

The resonator does not need to be protected for high annealing temperatures. So, there is no need for an extra release step and difficult processing on released (fragile) resonators. During sealing no impurities are deposited inside the cavity, so the release holes can be designed above the resonator. This limits the release etch time and also decreases the cavity size.

Poly-silicon is a well known material in all fabs. This means that the tuning of the layer is also known SiGe is not mixed with the poly-silicon-cap, due to the protection layer.

This makes the process less sensitive for mask-density variations.

In a further preferred embodiment the present method relates to a surface wherein the density of the openings is from l%-50% of the surface available, preferably from 5-40% of the surface, such as from 10-25%. The amount of openings or holes should be high enough to enable etching of underlying layers, yet not too large to jeopardize integrity of the cap layer.

In a further preferred embodiment the present method relates spacers wherein the size of the spacer is from 5-80% of the opening, preferably from 10-70%, such as from 25-60% of the opening.

The size of the spacer should not be to small, as then not enough material is provided to secure a hermitic sealing and/or to maintain integrity of the cap, whereas the spacers should not be to large, as then an etching step is hindered too much. Such variations vary on the material used for the spacer, as well as on the specific chemicals used in the etching step and material of the sacrificial layer.

In a second aspect the present invention relates to use of a spacer for encapsulating a MEMS device.

The use of a spacer for encapsulating offers the advantage of a well controlled etching step and a well controlled encapsulation, as mentioned above. In a preferred embodiment the spacer comprises silicon, preferably poly-silicon, or wherein the spacer comprises SiGe.

In a third aspect the present invention relates to a MEMS with poly- silicon cap layer, which poly-silicon cap layer comprises spacers, preferably SiGe spacers, which MEMS further optionally comprises a protection layer between the poly-silicon cap and spacers.

Such a MEMS offers the advantages as mentioned above. In a preferred embodiment the MEMS in a cavity comprises a poly- silicon cap layer with spacers, preferably poly-silicon or SiGe spacers.

The present invention is further elucidated by the following Figures and examples, which are not intended to limit the scope of the invention. The person skilled in the art will understand that various embodiments may be combined.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 shows a schematic drawing of a typical process-concept of an integrated encapsulation process.

Fig. 2 shows a X-section SEM picture of a release hole after sealing by depositing of a PECVD layer. Fig. 3 shows top view SEM pictures of cavities of lμm release holes with a SiGe spacer in a poly-silicon cap layer after an H₂-anneal. On the left side, a cavity with a dense pattern of release holes. On the right side, a cavity with an isolated release hole. Figs. 4a-h show a Schematic drawing of a possible process route for the encapsulating of a MEMS device by using spacers of SiGe inside the release holes of a poly-silicon cap layer, to seal the cavity with H₂-anneal.

Fig. 5 shows a X-section SEM pictures of a created spacer. Fig. 6 shows a X-section SEM pictures after sealing (H^-anneal)

DETAILED DESCRIPTION OF THE DRAWINGS

Fig. Ia shows a schematic drawing of a typical process-concept of an integrated encapsulation process, showing a silicon substrate (100), a sacrificial layer (HO) and a micro mechanical structure (120). Thereon an encapsulation shell (140) is deposited wherein one or more release holes (130) are formed, and wherein a channel is formed by removing the sacrificial layer (Fig. Ib). Then the one or more release holes and channel are sealed by layer (141) (Fig. Ic).

Fig. 2 shows a X-section SEM picture of a release hole after sealing by depositing of a PECVD layer, showing a release hole, a capping layer, a sealing layer and unwanted material deposited under the release hole, inside the cavity.

Fig. 3 shows top view SEM pictures of cavities of lμm release holes with a SiGe spacer in a poly-silicon cap layer after an H₂-anneal. On the left side, a cavity with a dense pattern of release holes. On the right side, a cavity with an isolated release hole.

Figs. 4a-h show a schematic drawing of a possible process route for the encapsulating of a MEMS device by using spacers of SiGe inside the release holes of a poly-silicon cap layer, to seal the cavity with H₂-anneal.

Fig. 4a shows the completion of a surface micromachined device (resonator), having a substrate (100), a sacrificial layer (110) and a micromachined device (120).

Fig. 4b shows a sacrificial layer (130) that is deposited and patterned. The thickness of this layer is typically from 0.5 Dm to 5.0 Dm. Typically it is deposited by LPCVD. Fig. 4c shows a cap-layer (140) that is deposited, typically a Poly- silicon layer. The thickness of this layer is typically from 0.5 Dm to 10.0 Dm. Typically it is deposited by LPCVD.

Fig. 4d shows release holes (150) that are patterned in the cap-layer. Typically patterning takes place by a wet or dry etch, preferably an anisotropic dry etch. Such an etch results in straight profiles, making it easier to form spacers.

Fig. 4e shows two alternatives. Fig. 4el shows that the layer (170) where the spacers have to be made of (poly-silicon or SiGe) is deposited. Fig. 4e2 shows that the protection layer (170) and the SiGe layer (160) are deposited. The protection layer is typically made of a dielectric layer, such as silicon nitride. The thickness of these layers is typically from 5-500 nm. Typically it is deposited by LPCVD. The layer does not have to be thick; it can be as thin as deposition allows. Thinner layers have as an advantage that smaller release holes can be used. Also thinner layer are easier to open at the bottom of the hole and save spacer material. Fig. 4f shows two alternatives. Fig. 4fl shows that the wafer is exposed to dry-etch plasma to create the spacers (171). The spacers are created (see also X- section SEM picture in Fig. 3). Fig. 4f2 shows that the wafer is exposed to dry-etch plasma to create the spacers (171). Also during this plasma the protection layer is opened at the bottom. The spacers are created (see also X-section SEM picture in Fig. 5). Typically etching takes place an an-isotropic dry etch. Such an etch is not isotropic and forms good spacers.

Fig. 4gl and g2 show a sacrificial etch (180), to empty the cavity and release the MEMS structure. Typically etching takes place by an isotropic wet or dry etch. Dry etch is less sensitive for stiction and further no critical CO₂ dryer is needed. Typical release etches are Vapor HF for oxide like materials and XeF₂ for Silicon type materials.

Fig. 4hl and h2 show H₂-anneal to seal the cavity by a cap (171) (X- section SEM pictures of sealed release holes are displayed in Fig. 6).

Typical conditions for the H₂-anneal process are: Temperature between 800 and 1150 deg C (depending on the melting point of material used)

Total pressure preferably being a low pressure. The process will, however, also work at atmospheric pressure. Typical pressure range from mTorr to Atmospheric, depending on e.g. tool availability. The hydrogen gas purity is important. The gas may be eventually diluted in He or Ar. A purity of more than 99.9% is preferred, preferably of more than 99.99%, such as more than 99.999%.

Fig. 5 shows a X-section SEM picture of a created spacer.

Fig. 6 shows a X-section SEM pictures after sealing (H^-anneal).

Claims

CLAIMS:

1. Method for forming a MEMS in a cavity, comprising the step of : forming spacers and openings in a surface and closing said openings by annealing said spacers.

2. Method according to claim 1, comprising the steps of : providing a surface micromachined device, depositing a sacrificial layer and patterning said layer, depositing a cap-layer, patterning and etching release holes in the cap-layer, - depositing a further layer, exposing the further layer to an etch step, creating spacers and openings, emptying the cavity by an etch step, thereby releasing the MEMS structure, and - annealing the spacer layer in order to seal the cavity.

3. Method according to claim 1 or 2, wherein a surface density of the openings is from l%-50% of surface available.

4. Method according to any of claims 1-3, wherein the size of the spacer is from 5-80% of the opening.