WO2010039896A3 - Éléments de mémoire volatile à immunité à la perturbation par des erreurs logicielles - Google Patents

Éléments de mémoire volatile à immunité à la perturbation par des erreurs logicielles Download PDF

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Publication number
WO2010039896A3
WO2010039896A3 PCT/US2009/059116 US2009059116W WO2010039896A3 WO 2010039896 A3 WO2010039896 A3 WO 2010039896A3 US 2009059116 W US2009059116 W US 2009059116W WO 2010039896 A3 WO2010039896 A3 WO 2010039896A3
Authority
WO
WIPO (PCT)
Prior art keywords
power supply
memory elements
signal
soft error
signal strengths
Prior art date
Application number
PCT/US2009/059116
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English (en)
Other versions
WO2010039896A2 (fr
Inventor
Yanzhong Xu
Jeffrey T. Watt
Original Assignee
Altera Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Altera Corporation filed Critical Altera Corporation
Priority to CN200980143407.7A priority Critical patent/CN102203867B/zh
Publication of WO2010039896A2 publication Critical patent/WO2010039896A2/fr
Publication of WO2010039896A3 publication Critical patent/WO2010039896A3/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G11C11/4125—Cells incorporating circuit means for protecting against loss of information
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/0033—Radiation hardening

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)

Abstract

La présente invention concerne des éléments de mémoire volatile présentant une immunité aux événements de perturbation par des erreurs logicielles lorsqu’ils sont soumis à des frappes de particules à haute énergie atomique. Les éléments de mémoire peuvent avoir chacun dix transistors. Pour surmonter les difficultés lors de l’écriture de données dans les éléments de mémoire, des intensités de signal pour un ou plusieurs parmi les signaux fournis à la matrice peuvent être ajustées. On peut prévoir deux tensions d’alimentation positives qui sont utilisées dans l’alimentation de chaque élément de mémoire. Une des tensions d’alimentation peut être temporairement abaissée par rapport à l’autre tension d’alimentation pour améliorer la marge d’écriture lors d’opérations de chargement de données. D’autres intensités de signal qui peuvent être ajustées de cette manière comprennent d’autres signaux d’alimentation, des niveaux de signal de données, des grandeurs d’adresses et de signaux en clair, et des intensités de signal de masse. Un circuit d’alimentation réglable et un circuit de commande d’écriture-lecture de données peuvent être utilisés dans la production de ces ajustements d’intensité de signal.
PCT/US2009/059116 2008-10-01 2009-09-30 Éléments de mémoire volatile à immunité à la perturbation par des erreurs logicielles WO2010039896A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN200980143407.7A CN102203867B (zh) 2008-10-01 2009-09-30 具有软错误翻转抗扰性的易失性存储器元件

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10199808P 2008-10-01 2008-10-01
US61/101,998 2008-10-01

Publications (2)

Publication Number Publication Date
WO2010039896A2 WO2010039896A2 (fr) 2010-04-08
WO2010039896A3 true WO2010039896A3 (fr) 2010-05-27

Family

ID=42057307

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2009/059116 WO2010039896A2 (fr) 2008-10-01 2009-09-30 Éléments de mémoire volatile à immunité à la perturbation par des erreurs logicielles

Country Status (3)

Country Link
US (3) US8355292B2 (fr)
CN (2) CN102203867B (fr)
WO (1) WO2010039896A2 (fr)

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US9256266B1 (en) 2011-11-04 2016-02-09 Altera Corporation Negative bit line driver circuitry
US20130229858A1 (en) * 2012-03-02 2013-09-05 Maxwell Consulting Fault Tolerant Static Random-Access Memory
CN103366802B (zh) * 2013-06-26 2016-06-29 清华大学 一种静态随机存储单元
CN103746678B (zh) * 2014-01-10 2016-08-17 电子科技大学 基于保护门替代电路的set加固结构
KR20160047199A (ko) * 2014-10-22 2016-05-02 에스케이하이닉스 주식회사 래치 회로 및 이를 포함하는 래치 회로 어레이
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US10181851B2 (en) * 2017-03-20 2019-01-15 Vanderbilt University Dual interlocked logic circuits
US10242732B2 (en) 2017-05-15 2019-03-26 Intel Corporation Memory elements with soft-error-upset (SEU) immunity using parasitic components
US10269426B2 (en) * 2017-06-15 2019-04-23 Intel Corporation Integrated circuits with complementary non-volatile resistive memory elements
CN108183706B (zh) * 2018-01-29 2021-09-07 中国人民解放军国防科技大学 一种抗单粒子翻转的寄存器文件存储阵列写单元
US10528292B2 (en) * 2018-05-22 2020-01-07 Luca De Santis Power down/power-loss memory controller

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US20060023535A1 (en) * 2004-07-13 2006-02-02 Ki-Chul Chun Circuit and method of driving bitlines of integrated circuit memory using improved precharge scheme and sense-amplification scheme
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US20070041242A1 (en) * 2005-08-19 2007-02-22 Sony Corporation Nonvolatile memory cell, storage device and nonvolatile logic circuit

Also Published As

Publication number Publication date
WO2010039896A2 (fr) 2010-04-08
CN103778946A (zh) 2014-05-07
US20100080033A1 (en) 2010-04-01
CN102203867A (zh) 2011-09-28
CN102203867B (zh) 2014-02-26
US8873278B1 (en) 2014-10-28
US8077500B2 (en) 2011-12-13
US20100254203A1 (en) 2010-10-07
US8355292B2 (en) 2013-01-15
CN103778946B (zh) 2017-01-04

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