WO2010026663A1

WO2010026663A1 - Nonvolatile storage element and nonvolatile storage device

Info

Publication number: WO2010026663A1
Application number: PCT/JP2008/066192
Authority: WO
Inventors: 豪山口
Original assignee: 株式会社東芝
Priority date: 2008-09-08
Filing date: 2008-09-08
Publication date: 2010-03-11

Abstract

A nonvolatile storage element is provided with a conductive first layer, a conductive second layer, and a recording layer arranged between the first layer and the second layer for recording information by reversibly transiting between a high resistance state and a low resistance state. At least the first layer or the second layer is composed of at least a metal oxide or a metal nitride or a metal carbide, and contains a first noble metal.

Description

Nonvolatile memory element and nonvolatile memory device

The present invention relates to a nonvolatile memory element and a nonvolatile memory device.

In recent years, small portable devices have become widespread worldwide, and at the same time, with the rapid progress of high-speed information transmission networks, the demand for small-sized and large-capacity nonvolatile memories has been rapidly expanding. Among them, NAND flash memory and small HDD (hard disk drive) have achieved rapid development of recording density and formed a large market.

In this situation, several new memory ideas have been proposed aiming to greatly exceed the recording density limit.

Among them, a memory using a resistance change material having a low resistance state and a high resistance state has been proposed. When the resistance change material is caused to repeat the transition between the low resistance state and the high resistance state, the characteristics of the low resistance state and the high resistance state may vary. For this reason, it is desired to improve the stability of repeated operations.

At the same time, a technique for processing a variable resistance material and an electrode for applying a voltage thereto with high accuracy is desired.

Patent Document 1 discloses a memory element in which an intermediate layer made of HfO, ZnO, InZnO or ITO is formed on a lower electrode, a NiO layer is formed thereon, and a variable resistance material is formed thereon. Has been.
Patent Document 2 discloses a memory device having two layers containing Cu between two electrodes made of Pt, Ru, Ir, Au, Ag, Ti, or the like.
US Patent Application Publication No. 2008 / 0007988A1 US Patent Application Publication No. 2008 / 0002458A1

The present invention provides a non-volatile memory element and a non-volatile memory device having good processability, high accuracy, and high repetitive operation stability.

According to one embodiment of the present invention, the first layer having conductivity, the second layer having conductivity, the first layer and the second layer are provided between the high resistance state and the low resistance state. A recording layer capable of recording information by reversibly transitioning between the first layer and the second layer, wherein at least one of the first layer and the second layer includes a metal oxide, a metal nitride, and a metal There is provided a nonvolatile memory element comprising at least one of carbides and containing a first noble metal.

According to another aspect of the present invention, the non-volatile memory element, at least one of application of a voltage to the recording layer of the non-volatile memory element and energization of a current to the recording layer. There is provided a non-volatile memory device comprising: a drive unit that records information by causing the recording layer to transition between the high resistance state and the low resistance state.

1 is a schematic cross-sectional view illustrating the configuration of a nonvolatile memory element according to a first embodiment of the invention. 1 is a schematic view illustrating the configuration of a main part of a nonvolatile memory device to which a nonvolatile memory element according to a first embodiment of the invention is applied. FIG. 6 is a graph illustrating characteristics of the nonvolatile memory element according to the first embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating the configuration of a nonvolatile memory element according to a modification according to the first embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating the configuration of a nonvolatile memory element according to a second embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating the configuration of another nonvolatile memory element according to the second embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating the configuration of another nonvolatile memory element according to the second embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating the configuration of a nonvolatile memory element according to a third embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating the configuration of another nonvolatile memory element according to the third embodiment of the invention. FIG. 9 is a schematic perspective view illustrating the configuration of a nonvolatile memory device according to a fourth embodiment of the invention. FIG. 6 is a schematic circuit diagram illustrating the configuration of a nonvolatile memory device according to a fourth embodiment of the invention. FIG. 9 is a schematic perspective view illustrating the configuration of another nonvolatile memory device according to the fourth embodiment of the invention. FIG. 9 is a schematic perspective view illustrating the configuration of another nonvolatile memory device according to the fourth embodiment of the invention. FIG. 9 is a schematic perspective view illustrating the configuration of a nonvolatile memory device according to a fifth embodiment of the invention. FIG. 9 is a schematic plan view illustrating the configuration of a nonvolatile memory device according to a fifth embodiment of the invention. FIG. 9 is a schematic cross-sectional view illustrating the configuration of a main part of a nonvolatile memory device according to a sixth embodiment of the invention. FIG. 10 is a schematic cross-sectional view illustrating the operation of a nonvolatile memory device according to a sixth embodiment of the invention. It is a schematic diagram which illustrates the structure of the principal part of another non-volatile memory device which concerns on the 6th Embodiment of this invention. FIG. 10 is a schematic cross-sectional view illustrating the main part of another nonvolatile memory device according to the sixth embodiment of the invention. FIG. 26 is a schematic cross-sectional view illustrating the main part of a nonvolatile memory device according to a modification according to the sixth embodiment of the invention. FIG. 26 is a schematic cross-sectional view illustrating the main part of a nonvolatile memory device according to a modification according to the sixth embodiment of the invention. It is a schematic diagram which illustrates the structure of the principal part of another non-volatile memory device which concerns on the 6th Embodiment of this invention. FIG. 10 is a schematic cross-sectional view illustrating the main part of another nonvolatile memory device according to the sixth embodiment of the invention. It is a schematic diagram which illustrates the structure of the principal part of another non-volatile memory device which concerns on the 6th Embodiment of this invention. FIG. 10 is a schematic cross-sectional view illustrating the main part of another nonvolatile memory device according to the sixth embodiment of the invention. FIG. 26 is a schematic cross-sectional view illustrating the main part of a nonvolatile memory device according to a modification according to the sixth embodiment of the invention.

Explanation of symbols

12 Lower electrode (second layer)
12a Second interface 13 Recording layer 14 Upper electrode (first layer)
14a First interface 15 Third layer 21 First noble metal 22 Second noble metal 30 Substrate 31 Word line driver 32 Bit line driver 33 Memory cell 33B Protective layer 34 Rectifier 35 Heater layer 41 Semiconductor substrate 41a P-type semiconductor substrate 41b N-type well Region 41c P-type well region 42 N-type diffusion layer (diffusion layer)
43 Gate insulating layer 44 Nonvolatile memory element 45 Control gate electrode 47 P-

type semiconductor layer

210, 211, 212, 250, 260, 261 to 266 Nonvolatile memory device 261c NAND cell unit 264c NOR cell unit 265c 2

tracell unit

310, 311, 320 to 325, 330 to 333 Non-volatile memory element 515 Driver 516 XY scanner 520 Substrate 521 Electrode 523 Substrate 524 Probe 525 526 Multiplex driver 531 Data area 532 Servo area 600 Drive unit

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

(First embodiment)
FIG. 1 is a schematic cross-sectional view illustrating the configuration of the nonvolatile memory element according to the first embodiment of the invention.
As shown in FIG. 1, the nonvolatile memory element 310 according to the first embodiment of the present invention includes a conductive upper electrode 14 (first layer) and a conductive lower electrode 12 (second layer). ) And a recording layer 13 provided between the upper electrode 14 and the lower electrode 12 and capable of recording information by reversibly transitioning between a high resistance state and a low resistance state, At least one of the upper electrode 14 and the lower electrode 12 is made of at least one of a metal oxide, a metal nitride, and a metal carbide, and contains the first noble metal 21.

In this specific example, the upper electrode 14 and the lower electrode 12 are made of at least one of a metal oxide, a metal nitride, and a metal carbide, and contain the first noble metal 21.

The recording layer 13 exhibits a phase change between a high resistance state phase and a low resistance state phase depending on the voltage applied to the recording layer 13 or the current flowing through the recording layer 13. That is, for example, due to the potential difference applied to the recording layer 13 via the upper electrode 14 and the lower electrode 12 or the current passed through the recording layer 13 via the upper electrode 14 and the lower electrode 12, the recording layer 13 is It exhibits a plurality of phases with different resistivity.

The nonvolatile memory element 310 according to this embodiment can be applied to, for example, a nonvolatile memory such as a cross point type, a probe memory type, and various flash memory types. As an example, a configuration of the nonvolatile memory element 310 when the nonvolatile memory element 310 is used in a cross-point nonvolatile memory device will be described.

FIG. 2 is a schematic view illustrating the configuration of the main part of a nonvolatile memory device to which the nonvolatile memory element according to the first embodiment of the invention is applied.
1A is a schematic perspective view, and FIG. 1B is a schematic cross-sectional view.
As shown in FIGS. 2A and 2B, in the cross-point type nonvolatile memory device 210, for example, between the word line WL _i and the bit line BL _j , the memory cell 33 and the rectifying element 34 are used. Is provided. The upper and lower arrangement relationship between the word line WL _i and the bit line BL _j is arbitrary. The arrangement relationship between the memory cell 33 and the rectifying element 34 between the word line WL _i and the bit line BL _j is also arbitrary. That is, in the specific example illustrated in FIG. 2, the memory cell 33 is disposed on the bit line BL _j side with respect to the rectifying element 34, but the memory cell 33 is disposed on the word line WL _i side with respect to the rectifying element 34. May be.

As shown in FIG. 2, the memory cell 33 includes the nonvolatile memory element 310 according to the present embodiment. The nonvolatile memory element 310 includes a lower electrode 12, an upper electrode 14, and a recording layer 13 provided between the lower electrode 12 and the upper electrode 14. As described above, the memory cell 33 includes the nonvolatile memory element 310. Here, the upper electrode 14 and the lower electrode 12 have convenient names and can be interchanged.

In addition to the nonvolatile memory element 310, the memory cell 33 can include a protective layer 33B and a heater layer 35 provided between the nonvolatile semiconductor memory device 310 and the protective layer 33B. In this specific example, the protective layer 33B is provided on the bit line BL _j side of the nonvolatile memory element 310, but the protective layer 33B is provided on the word line WL _i side of the nonvolatile memory element 310. Alternatively, it may be provided between the rectifying element 34 and the word line WL _i . Further, the heater layer 35 and the protective layer 33B are provided as necessary and can be omitted.

A plurality of these word lines WL _i , rectifying elements 34, memory cells 33, and bit lines BL _j are provided, and an insulating layer is provided between them to be insulated from each other.

Note that at least one of the lower electrode 12 and the upper electrode 14 of the nonvolatile memory element 310 is adjacent to the nonvolatile memory element 310, for example, a word line WL _i , a rectifier element 34, a heater layer 35, a protective layer 33B, a bit line. It may also be used as at least one of BL _j . In this case, the layer that is also used as at least one of the lower electrode 12 and the upper electrode 14 is regarded as at least one of the lower electrode 12 and the upper electrode 14.

Here, referring back to FIG. 1, in the nonvolatile memory element 310 according to the present embodiment, the upper electrode 14 and the lower electrode 12 are made of at least one of a metal oxide, a metal nitride, and a metal carbide, and the first noble metal. 21 is contained.

The first noble metal 21 can be at least one selected from the group consisting of Ag, Pt and Pd.

On the other hand, in the recording layer 13, all materials exhibiting a phase change between a high resistance state phase and a low resistance state phase due to a voltage applied to the recording layer 13 or a current flowing through the recording layer 13. Can be used.

Specifically, for example, the recording layer 13 has a spinel structure represented by A _x B _y X ₄ (0.1 ≦ x ≦ 2.2, 1.5 ≦ y ≦ 2), A _x B _y X ₂ (0.1 ≦ x ≦ 1.1, 0.9 ≦ y ≦ 1.1), a delafossite structure, A _x B _y X ₄ (0.5 ≦ x ≦ 1.1, 0. Any of a wolframite structure represented by 7 ≦ y ≦ 1.1 and an ilmenite structure represented by A _x B _y X ₃ (0.5 ≦ x ≦ 1.1, 0.9 ≦ y ≦ 1) A material having the following can be used.

The element A is a typical element and can be at least one selected from the group consisting of Zn, Cd, and Hg.
The element B is a transition element and can be at least one selected from the group consisting of Cr and Mn.
More specifically, the element A is at least one selected from the group consisting of Zn, Cd and Hg, and the element B is at least one selected from the group consisting of Cr and Mn. be able to.

And, for example, the above “X” can be oxygen. That is, various oxides are used for the recording layer 13.

The material used for the upper electrode 14 and the lower electrode 12 in contact with the recording layer 13 greatly affects the electrical characteristics of the nonvolatile memory element 310. Specifically, as the recording layer 13 is repeatedly switched between the high resistance state and the low resistance state, the resistance in the high resistance state and the resistance in the low resistance state vary. Further, the applied voltage or energizing current that becomes a high resistance state and the applied voltage or energizing current that becomes a low resistance state vary. Such resistance fluctuations and voltage and current fluctuations greatly depend on the materials used for the upper electrode 14 and the lower electrode 12.

According to the inventors' experiment, it has been found that when noble metals are used for the upper electrode 14 and the lower electrode 12, fluctuations in resistance, fluctuations in voltage and current are suppressed, and repeated operational stability is improved.

However, when a noble metal is used as the upper electrode 14 and the lower electrode 12, the workability of the noble metal is poor and the workability when forming the upper electrode 14 and the lower electrode 12 is poor. The processing accuracy of the recording layer 12 is poor, and in some cases, the characteristics of the recording layer 13 sandwiched between them are deteriorated.

On the other hand, when a conductive material such as a metal oxide, a metal nitride, and a metal carbide is used as the upper electrode 14 and the lower electrode 12, the workability is good. However, when the recording layer 13 is repeatedly switched, , Fluctuations in voltage and current increase. That is, repeated operation stability is poor.

At this time, in the nonvolatile memory element 310 according to the present embodiment, the upper electrode 14 and the lower electrode 12 are made of at least one of a metal oxide, a metal nitride, and a metal carbide, and contain the first noble metal 21.

For this reason, the upper electrode 14 and the lower electrode 12 can have good workability substantially similar to that of the metal oxide, metal nitride, and metal carbide.
For example, when the nonvolatile memory element 310 is manufactured, a film to be the lower electrode 12, a film to be the recording layer 13, and a film to be the upper electrode 14 are stacked, and these films are then dried using a mask. The lower electrode 12, the recording layer 13, and the upper electrode 14 are formed by processing such as etching. At this time, the recording layer 13 is, for example, an oxide, and the upper electrode 14 and the lower electrode 12 include a metal oxide, a metal nitride, and a metal carbide. Therefore, the recording layer 13, the upper electrode 14, the lower electrode 12, The processability is similar, and the processability is substantially the same. As a result, the nonvolatile memory element 310 is processed with high accuracy with good processability.

Since the upper electrode 14 and the lower electrode 12 have the first noble metal 21, fluctuations in the characteristics of the recording layer 13 can be suppressed, and repeated operational stability can be improved.

As described above, according to the nonvolatile memory element 310 according to the present embodiment, it is possible to provide a nonvolatile memory element with good processability, high accuracy, and high repetitive operation stability.

FIG. 3 is a graph illustrating characteristics of the nonvolatile memory element according to the first embodiment of the invention.
That is, this figure illustrates the relationship between the first noble metal 21 in the upper electrode 14 and the lower electrode 12 and the repetitive operation stability and workability of the nonvolatile memory element. The horizontal axes of FIGS. 9A and 9B show the concentration C1 of the first noble metal 21 in the upper electrode 14 and the lower electrode 12. The vertical axis in FIG. 5A shows the stability of repeated operation of the nonvolatile memory element 310. The vertical axis in FIG. 5B is the workability of the film that becomes the upper electrode 14 and the lower electrode 12.

As shown in FIG. 3A, as the concentration C1 of the first noble metal 21 in the upper electrode 14 and the lower electrode 12 increases, the repetitive operation stability of the nonvolatile memory element 310 is improved.

On the other hand, as shown in FIG. 3B, as the concentration C1 of the first noble metal 21 in the upper electrode 14 and the lower electrode 12 increases, the workability of the film that becomes the upper electrode 14 and the lower electrode 12 deteriorates.

Accordingly, the concentration C1 of the first noble metal 21 in the upper electrode 14 and the lower electrode 12 is good in the repetitive operation stability of the nonvolatile memory element 310 and the workability of the film that becomes the upper electrode 14 and the lower electrode 12 is good. A range is desirable.

Specifically, the concentration C1 of the first noble metal 21 in the upper electrode 14 and the lower electrode 12 is desirably 2 atomic percent or more and 40 atomic percent or less.
That is, when the concentration C1 is lower than 2 atomic percent, the effect of improving the repeated operation stability is lowered. On the other hand, when the concentration C1 is higher than 40 atomic percent, the workability deteriorates.

Further, as illustrated in FIG. 1, it is desirable that the first noble metal 21 is dispersed and contained in the upper electrode 14 and the lower electrode 12 in the upper electrode 14 and the lower electrode 12. That is, the first noble metal 21 is not contained as an alloy or a solid solution in the metal oxide, metal nitride, and metal carbide to be the upper electrode 14 and the lower electrode 12, but is dispersed as a region of only the first noble metal 21. It is desirable to be contained. As described above, the first noble metal 21 is dispersed and contained as a region of only the first noble metal 21, thereby providing a nonvolatile memory element with better workability, high accuracy, and high repeated operation stability. .

For example, the first noble metal 21 may be deposited on the inside and / or the surface of the upper electrode 14 and the lower electrode 12. In particular, it may be deposited on the interface side of the upper electrode 14 and the lower electrode 12 with the recording layer 13.
That is, the first noble metal 21 may be precipitated in at least one of the inside and the surface of the metal oxide, metal nitride, and metal carbide that become the upper electrode 14 and the lower electrode 12.

The first noble metal 21 can be precipitated as a plurality of first grains in at least one of the inside and the surface of the upper electrode 14 and the lower electrode 12.
The particle diameter of the first grains can be set to 0.5 nm to 10 nm, for example.
That is, when it is smaller than 0.5 nm, the effect of improving the repeated operation stability is low, and when it is larger than 10 nm, the workability deteriorates.
The particle diameter of the first grain is more preferably 1.0 nm to 10 nm. By setting the thickness to 1.0 nm or more, it is easier to obtain the effect of improving the repeated operation stability.

At that time, the average of the interval between the first grains is preferably set larger than the diameter of the first grains.
Thereby, the space | interval of 1st grains becomes wide and workability improves. Thereby, the space | interval of 1st grains spreads and workability improves. However, when the interval between the first grains is too wide, as a result, the content of the first noble metal 21 is reduced, and the effect of improving the repeated operation stability is lowered.

As described above, the first noble metal 21 is deposited, and more specifically, the first precious metal 21 is deposited as a plurality of first grains, so that the upper electrode 14 is maintained while maintaining the repetitive operation stability of the nonvolatile memory element 310. And the workability of the film to be the lower electrode 12 can be further improved.

Then, by setting the average of the interval between the first grains larger than the diameter of the first grains, the interval between the first grains, that is, the metal oxide that becomes the upper electrode 14 and the lower electrode 12 The regions of metal nitride and metal carbide and the region of the first grains are solidified as individual regions, so that the workability is further improved.

In addition, when both the upper electrode 14 and the lower electrode 12 have the 1st noble metal 21 like this specific example, with the upper electrode 14 and the lower electrode 12, the kind of noble metal to contain, content, concentration distribution, The dispersion state, the precipitation state, the diameter of the first grains, the interval between the first grains, and the like may be different.

FIG. 4 is a schematic cross-sectional view illustrating the configuration of a nonvolatile memory element according to a modification according to the first embodiment of the invention.
As shown in FIG. 4, in the nonvolatile memory element 311 of the modification according to the first embodiment of the present invention, the upper electrode 14 and the lower electrode 12 are made of conductive metal oxide, metal nitride, and It consists of at least one of metal carbide. Only the upper electrode 14 contains the first noble metal 21. That is, the lower electrode 12 does not contain the first noble metal 21.

In this case, the upper electrode 14 is relatively less workable than the lower electrode, and on the contrary, the repeated operation stability is better.

For example, a film to be the lower electrode 12, a film to be the recording layer 13, and a film to be the upper electrode 14 are laminated on the substrate, and then these laminated films are collectively processed by, for example, etching or the like. In some cases, the film to be the upper electrode 14 is exposed to etching longer than the film to be the lower electrode 12. For this reason, the upper electrode 14 can be set so as to be relatively less workable than the lower electrode.

As described above, either the upper electrode 14 or the lower electrode 12 may be made of at least one of a metal oxide, a metal nitride, and a metal carbide, and may contain the first noble metal 21.

Depending on the processing method, on the contrary, only the lower electrode 12 may contain the first noble metal 21 and the upper electrode 14 may not contain the first noble metal 21.

In the nonvolatile memory element according to this embodiment, the upper electrode 14 and the lower electrode 12 may be made of at least one of a metal oxide, a metal nitride, and a metal carbide, and contain the first noble metal 21. Depending on the material configuration and processing method of these films, for example, the upper electrode 14 is made of at least one of a metal oxide, a metal nitride, and a metal carbide, contains the first noble metal 21, and the lower electrode 12 has a noble metal. You may comprise with the film | membrane which consists of. Conversely, the lower electrode 12 may be made of at least one of a metal oxide, a metal nitride, and a metal carbide, contain the first noble metal 21, and the upper electrode 14 may be made of a film made of a noble metal. .

(Second Embodiment)
FIG. 5 is a schematic cross-sectional view illustrating the configuration of the nonvolatile memory element according to the second embodiment of the invention.
As shown in FIG. 5A, in the nonvolatile memory element 320 according to the second embodiment of the present invention, the upper electrode 14 and the lower electrode 12 are at least one of metal oxide, metal nitride, and metal carbide. It contains the first noble metal 21.

The concentration of the first noble metal 21 on the side closer to the recording layer 13 of the upper electrode 14 and the lower electrode 12 is the concentration of the first noble metal 21 on the side farther from the recording layer 13 than the closer side of the upper electrode 14 and lower electrode 12. Higher than.

That is, the concentration of the first noble metal 21 is high in the region close to the first interface 14a that is the interface between the upper electrode 14 and the recording layer 13, and the concentration of the first noble metal 21 is high in the region far from the first interface 14a. Relatively low. On the other hand, the concentration of the first noble metal 21 is high in the region close to the second interface 12a that is the interface between the lower electrode 12 and the recording layer 13, and the concentration of the first noble metal 21 is high in the region far from the second interface 12a. Relatively low.

In the upper electrode 14 and the lower electrode 12, the stability of the repetitive operation of the recording layer 13 can be ensured by increasing the concentration of the first noble metal 21 on the side closer to the recording layer 13.

On the other hand, in the upper electrode 14 and the lower electrode 12, on the side far from the recording layer 13, the workability of the film to be the upper electrode 14 and the lower electrode 12 is improved as a whole by reducing the concentration of the first noble metal 21. The

As described above, according to the nonvolatile memory element 320 according to the present embodiment, it is possible to provide a nonvolatile memory element that has better workability, higher accuracy, and higher repeated operation stability.

Further, as shown in FIG. 5B, in another nonvolatile memory element 321 according to the second embodiment of the present invention, the upper electrode 14 is made of at least one of a metal oxide, a metal nitride, and a metal carbide. The first noble metal 21 is contained, and the concentration of the first noble metal 21 on the side closer to the recording layer 13 of the upper electrode 14 is set to be higher on the side farther from the recording layer 13 than the closer side of the upper electrode 14. It is set higher than the concentration of one noble metal 21. As described above, even when the first noble metal 21 is contained in at least one of the upper electrode 14 and the lower electrode 12 and the concentration of the first noble metal 21 is provided with a gradient, both the repeated operation stability and the workability are further improved. Highly compatible.

Thus, at least one of the upper electrode 14 and the lower electrode 12 is made of at least one of a metal oxide, a metal nitride, and a metal carbide, contains the first noble metal 21, and the at least one of the records By setting the concentration of the first noble metal 21 on the side close to the layer 13 higher than the concentration of the first noble metal 21 on the side farther from the recording layer 13 than the at least any one of the close sides, Both the workability and the workability can be made more compatible.

FIG. 6 is a schematic cross-sectional view illustrating the configuration of another nonvolatile memory element according to the second embodiment of the invention.
As shown in FIG. 6A, in another nonvolatile memory element 322 according to the second embodiment of the present invention, the upper electrode 14 and the lower electrode 12 are made of metal oxide, metal nitride, and metal carbide. It consists of at least one and contains the first noble metal 21.

The first noble metal 21 is localized in a portion of the first interface 14 a with the recording layer 13 of the upper electrode 14 and a portion of the second interface 12 a with the recording layer 13 of the lower electrode 12.
Also in this case, the concentration of the first noble metal 21 is an example of a state in which the side closer to the recording layer 13 of the upper electrode 14 and the lower electrode 12 is higher than the side farther from the recording layer 13.

As described above, even when the first noble metal 21 is localized at the portion of the first interface 14 a with the recording layer 13 of the upper electrode 14 and the portion of the second interface 12 a with the recording layer 13 of the lower electrode 12. The stability of the repetitive operation of the recording layer 13 can be ensured.

On the other hand, in the upper electrode 14 and the lower electrode 12, the concentration of the first noble metal 21 is low on the side far from the recording layer 13, so that the workability of the film to be the upper electrode 14 and the lower electrode 12 is improved as a whole.

As described above, according to the nonvolatile memory element 322 according to the present embodiment, it is possible to provide a nonvolatile memory element with better workability, higher accuracy, and higher repeated operation stability.

In addition, as illustrated in FIG. 6B, in another nonvolatile memory element 323 according to the second embodiment of the present invention, the upper electrode 14 is at least one of metal oxide, metal nitride, and metal carbide. The first noble metal 21 is contained in the first interface 14 a with the recording layer 13. Thus, even when at least one of the upper electrode 14 and the lower electrode 12 is localized at the interface with the recording layer 13 and contains the first noble metal 21, both repeated operation stability and workability are further improved. Highly compatible.

As described above, at least one of the upper electrode 14 and the lower electrode 12 is made of at least one of metal oxide, metal nitride, and metal carbide, and is localized at the interface between the at least one and the recording layer 13. By including one noble metal 21, both repeated operation stability and workability can be made more highly compatible.

FIG. 7 is a schematic cross-sectional view illustrating the configuration of another nonvolatile memory element according to the second embodiment of the invention.
As shown in FIG. 7A, in another nonvolatile memory element 324 according to the second embodiment of the present invention, the upper electrode 14 and the lower electrode 12 are made of metal oxide, metal nitride, and metal carbide. It consists of at least one and contains the first noble metal 21.

The first noble metal 21 is continuously formed as a thin film on the portion of the first interface 14a with the recording layer 13 of the upper electrode 14 and the portion of the second interface 12a with the recording layer 13 of the lower electrode 12. Are localized. For example, this thin film is a thin film having a film thickness of 1.0 nm to 20 nm. If the film thickness is less than 1.0 nm, the effect of improving the repeated operation stability is low, and if the film thickness is more than 20 nm, the workability deteriorates.
As described above, the first noble metal 21 having a low workability as a material is formed in a portion of the first interface 14a with the recording layer 13 of the upper electrode 14 and a portion of the second interface 12a with the recording layer 13 of the lower electrode 12. Even when the thin film is provided continuously, the poor workability is not substantially a problem because the film thickness is thin.

Since the first noble metal 21 exists in the portion of the first interface 14a with the recording layer 13 of the upper electrode 14 and the portion of the second interface 12a with the recording layer 13 of the lower electrode 12, the recording layer 13 The stability of the repeated operation can be ensured.

As described above, the non-volatile memory element 324 according to this embodiment can provide a non-volatile memory element with better workability, higher accuracy, and higher repeated operation stability.

Further, as shown in FIG. 7B, in another nonvolatile memory element 325 according to the second embodiment of the present invention, the upper electrode 14 includes at least one of a metal oxide, a metal nitride, and a metal carbide. Thus, the first interface 14a with the recording layer 13 contains the first noble metal 21 continuously localized as a thin film. Thus, even if at least one of the upper electrode 14 and the lower electrode 12 includes the first noble metal 21 that is continuously localized as a thin film at the interface with the recording layer 13, repeated operation stability and processing are achieved. It is possible to achieve a higher degree of compatibility with both sex.

As described above, at least one of the upper electrode 14 and the lower electrode 12 is made of at least one of a metal oxide, a metal nitride, and a metal carbide, and is continuously formed as a thin film at the interface between the at least one and the recording layer 13. By including the first noble metal 21 that is localized, both repetitive operation stability and workability can be achieved at a higher level.

In the nonvolatile memory elements according to the first and second embodiments described above, the method of including the first noble metal 21 in at least one of the upper electrode 14 and the lower electrode 12 is arbitrary.

For example, when forming the film to be at least one of the upper electrode 14 and the lower electrode 12, at least one of the metal oxide, metal nitride, and metal carbide to be the at least one of the upper electrode 14 and the lower electrode 12 A method of forming a film using a target including the first noble metal 21 can be used. Alternatively, a method of forming a film using another target including at least one of a metal oxide, a metal nitride, and a metal carbide and the first noble metal 21 can be used. In addition, any method can be used.

Further, in at least one of the upper electrode 14 and the lower electrode 12, the concentration of the first noble metal 21 is provided with a gradient, or the first noble metal 21 is localized at the first interface 14a or the second interface 12a. For example, another target including at least one of a metal oxide, a metal nitride, and a metal carbide and the first noble metal 21 is used, and the amount formed from the target during film formation is changed. A control method can be used. Further, a first film formation using a target including at least one of a metal oxide, a metal nitride, and a metal carbide, and the first noble metal 21, and at least one of a metal oxide, a metal nitride, and a metal carbide A method of combination with the second film formation using the target can be used. At this time, after the film formation, the first noble metal 21 can also be diffused by heat treatment or the like.

As described above, the first noble metal 21 can be dispersed in the metal oxide, the metal nitride, and the metal carbide, which are at least one of the upper electrode 14 and the lower electrode 12, depending on the film forming conditions and subsequent processing. .

Further, the first noble metal 21 can be deposited on at least one of the inside and / or the surface of the upper electrode 14 and the lower electrode 12.

At this time, the first noble metal 21 can be precipitated as a plurality of first grains in at least one of the inside and / or the surface of the upper electrode 14 and the lower electrode 12.
And the average of the space | interval of 1st grains can be made larger than the diameter of said 1st grain.

(Third embodiment)
FIG. 8 is a schematic cross-sectional view illustrating the configuration of the nonvolatile memory element according to the third embodiment of the invention.
As shown in FIG. 8, the nonvolatile memory element 330 according to the third embodiment of the present invention includes the third layer 15 provided between the upper electrode 14, the lower electrode 12, and the recording layer 13. Further prepare. Except this, since it can be the same as the various nonvolatile memory elements 310 according to the first embodiment, the description thereof will be omitted.

The third layer 15 includes at least one of a metal, a metal oxide, a metal nitride, and a metal carbide, and includes a second noble metal 22 of a type different from the first noble metal 21.
The second noble metal is at least one selected from the group consisting of Ag, Pt, and Pd, and is a different type of metal from the first noble metal 21.

At this time, as in this specific example, when both the upper electrode 14 and the lower electrode 12 have the first noble metal 21 and the kinds of noble metals contained as the first noble metal are different, The third layer 15 provided between the electrode 14 and the recording layer 13 contains a second noble metal 22 of a type different from the first noble metal 21 contained in the upper electrode 14, and the lower electrode 12 and the recording layer 13. The third layer 15 provided between the first and second layers contains a second noble metal 22 of a type different from the first noble metal 21 contained in the lower electrode 12.

As described above, by providing the second noble metal 22, which is a metal different from the first noble metal 21, between the upper electrode 14, the lower electrode 12, and the recording layer 13, the repeated operation stability by the first noble metal 21 is compensated. Therefore, the stability of the repeated operation can be further improved as compared with the case where only the first noble metal 21 is used.

Since the third layer 15 includes the second noble metal 22 that is generally low in workability, the concentration of the second noble metal 22 in the third layer 15 is desirably 2 atomic percent or more and 50 atomic percent or less. .
When the concentration of the second noble metal 22 is lower than 2 atomic percent, the degree of improvement in repeated operation stability is low, and when it is lower than 50 atomic percent, workability is low.

Further, the thickness of the third layer 15 can be set to 0.5 nm or more and 10 nm or less.
When the thickness of the third layer 15 is less than 0.5 nm, the effect of improving the repeated operation stability is low, and when it is thicker than 10 nm, the workability deteriorates.
The thickness of the third layer 15 is more preferably 1.0 nm to 5 nm. By setting the thickness to 1.0 nm or more, it is easier to obtain the effect of improving the repetitive operation stability. By setting the thickness to 5 nm or less, the workability is improved, and the repetitive operation stability and the workability are more highly compatible. be able to.

Various combinations of materials can be used for the first noble metal 21 and the second noble metal 22. For example, the second noble metal 22 on the memory layer 13 side has a more stable operation stability than the first noble metal 21. It is possible to select materials that are important. Further, the concentration of the second noble metal 22 in the third layer 15 may be made higher than the concentration of the first noble metal 21 in the upper electrode 14 and the lower electrode. By using these techniques as appropriate, higher repeated operation stability can be ensured. At this time, the thickness of the third layer 15 having the second noble metal 22 is made relatively thin to compensate for the low workability of the second noble metal 22, and the workability and the repeated operation stability are further enhanced. Can be compatible.

The third layer 15 can include at least one of metal, metal oxide, metal nitride, and metal carbide, and the second noble metal 22 includes these metal, metal oxide, metal nitride, and metal. The second metal 22 may be contained in the third layer 15 as a solid body of these metals, metal oxides, metal nitrides and metal carbides, and the second metal 22. It may be contained.

Further, the second noble metal 22 may be precipitated in at least one of the inside and the surface of the third layer 15.

For example, the second noble metal 22 may be precipitated as a plurality of second grains in at least one of the inside and the surface of the third layer 15.
The particle size of the second grains can be set to 0.5 nm to 10 nm, for example.
That is, when it is smaller than 0.5 nm, the effect of improving the repetitive operation stability is low, and when it is larger than 10 nm, the workability deteriorates.
The particle diameter of the second grains can be more preferably 1.0 nm to 10 nm. By setting the thickness to 1.0 nm or more, it is easier to obtain the effect of improving the repeated operation stability.

At this time, the average of the interval between the second grains can be set larger than the diameter of the second grains.
Thereby, the space | interval of 2nd grains spreads and workability improves. However, if the interval between the second grains is too wide, as a result, the content of the second noble metal 22 is reduced, and the effect of improving the repeated operation stability is lowered.

This makes it possible to achieve both higher workability and stability of repeated operation.

The non-volatile memory element 330 according to this embodiment can provide a non-volatile memory element with better workability, higher accuracy, and higher repeated operation stability.

FIG. 9 is a schematic cross-sectional view illustrating the configuration of another nonvolatile memory element according to the third embodiment of the invention.
As shown in FIG. 9A, in another nonvolatile memory element 331 according to the third embodiment of the present invention, both the upper electrode 14 and the lower electrode 12 contain the first noble metal 21, and the upper electrode A third layer 15 is provided between the recording layer 14 and the recording layer 13.

Thus, the third layer 15 can be provided between at least one of the upper electrode 14 and the lower electrode 12.

As shown in FIG. 9B, in another nonvolatile memory element 332 according to the third embodiment of the present invention, the upper electrode 14 contains the first noble metal 21, and the upper electrode 14, the recording layer 13, A third layer 15 is provided therebetween.

As shown in FIG. 9C, in another nonvolatile memory element 333 according to the third embodiment of the present invention, the upper electrode 14 contains the first noble metal 21, and the lower electrode 12, the recording layer 13, A third layer 15 is provided therebetween.

Thus, the third layer 15 can be provided between at least one of the upper electrode 14 and the lower electrode 12. At this time, the third layer 15 is arbitrarily disposed between at least one of the upper electrode 14 and the lower electrode 12 independently of which of the upper electrode 14 and the lower electrode 12 contains the first noble metal 21. Can be provided.

(Fourth embodiment)
A non-volatile memory device according to a fourth embodiment of the present invention is a cross-point type non-volatile memory device, and uses the non-volatile memory element according to the first to third embodiments. It is.

FIG. 10 is a schematic perspective view illustrating the configuration of the nonvolatile memory device according to the fourth embodiment of the invention.
FIG. 11 is a schematic circuit diagram illustrating the configuration of the nonvolatile memory device according to the fourth embodiment of the invention.
As shown in FIGS. 10 and 11, in the nonvolatile memory device 210 according to the present embodiment, a strip-shaped first wiring (word line WL) extending in the X-axis direction on the main surface of the substrate 30. _i−1 , WL _i , WL _{i + 1} ). Then, the strip-like second wiring (bit lines BL _j−1 , BL _j , BL _{j + 1} ) extending in the Y-axis direction orthogonal to the X-axis in a plane parallel to the substrate 30 is connected to the first wiring (word Lines WL _i−1 , WL _i , WL _{i + 1} ).
In the above example, the first wiring and the second wiring are orthogonal to each other. However, the first wiring and the second wiring may be crossed (non-parallel).
As described above, the plane parallel to the main surface of the substrate 30 is the XY plane, the direction in which the first wiring extends is the X axis, and the axis orthogonal to the X axis is in the XY plane. Is the Y axis, and the direction perpendicular to the X and Y axes is the Z axis.

In the above, the subscript i and the subscript j are arbitrary. That is, FIG. 10 and FIG. 11 show examples in which three each of the first wiring and the second wiring are provided, but the present invention is not limited to this, and the first wiring and the second wiring are not limited thereto. The number of the two wirings is arbitrary. In this specific example, the first wiring is a word and the second wiring is a bit line. However, the first wiring may be a bit line and the second wiring may be a word line. In the following description, it is assumed that the first wiring is a word line and the second wiring is a bit.

As shown in FIGS. 10 and 11, the memory cell 33 is sandwiched between the first wiring and the second wiring. That is, in the nonvolatile memory device 210, the memory cell 33 is provided at an intersection formed by three-dimensionally intersecting a bit line and a word line.

As shown in FIG. 11, for example, one end of each of the word lines WL _i−1 , WL _i , WL _{i + 1} is connected to a word line driver 31 having a decoder function via a MOS transistor RSW as a selection switch, One end of each of the bit lines BL _j−1 , BL _j , BL _{j + 1} is connected to a bit line driver 32 having a decoder and a read function via a MOS transistor CSW as a selection switch.

Selection signals R _i−1 , R _i and R _{i + 1} for selecting one word line (row) are input to the gate of the MOS transistor RSW, and one bit line is input to the gate of the MOS transistor CSW. Selection signals C _i−1 , C _i , and C _{i + 1} for selecting (column) are input.

The memory cell 33 is arranged at the intersection of the word lines WL _i−1 , WL _i , WL _{i + 1} and the bit lines BL _j−1 , BL _j , BL _{j + 1} . This is a so-called cross-point cell array structure.

A rectifying element 34 for preventing a sneak current during recording / reproduction can be added to the memory cell 33.

It should be noted that the feature of such a cross-point cell array structure is that it is advantageous for high integration because it is not necessary to individually connect a MOS transistor to the memory cell 33.

As already described with reference to FIG. 2, the memory cell 33 and the rectifying element 34 are provided between the word line WL _i and the bit line BL _j . The upper and lower arrangement relationship between the word line WL _i and the bit line BL _j is arbitrary. The arrangement relationship between the memory cell 33 and the rectifying element 34 between the word line WL _i and the bit line BL _j is also arbitrary.

As described above, any one of the nonvolatile memory elements according to the first to third embodiments can be used as the memory cell 33.

That is, the recording layer 13, the lower electrode 12, and the upper electrode 14 of the nonvolatile memory element of the memory cell 33 are respectively provided with the recording layer 13, the lower electrode 12, and the upper electrode 14 described in the first to third embodiments. Can be used.

In the nonvolatile memory device 210 according to the present embodiment having such a configuration, the word line driver 31 and the bit line driver 32 serving as a driving unit are connected to the memory cell 33 via the word line WL _i and the bit line BL _j . At least one of application of a voltage to the recording layer 13 of the nonvolatile memory element and energization of a current to the recording layer 13 is performed. Accordingly, the drive unit records information by causing the recording layer 13 to transition between the high resistance state and the low resistance state. The drive unit can read information recorded on the recording layer 13.

That is, the nonvolatile memory device 210 according to the present embodiment applies any one of the nonvolatile memory elements according to the first to third embodiments, the application of voltage to the recording layer 13 of the nonvolatile memory element, and recording. A drive unit that records information by causing the recording layer 13 to transition between a high-resistance state and a low-resistance state by at least one of supplying a current to the layer 13;

The non-volatile memory device 210 further includes a word line WL _i and a bit line BL _j provided so as to sandwich a non-volatile memory element, and the driving unit is configured to record the recording layer via the word line WL _i and the bit line BL _j. At least one of application of a voltage to 13 and current application to the recording layer 13 is performed.

The non-volatile memory device 210 according to this embodiment having such a configuration can provide a non-volatile memory device with good processability, high accuracy, and high repetitive operation stability.

FIG. 12 is a schematic perspective view illustrating the configuration of another nonvolatile memory device according to the fourth embodiment of the invention.
FIG. 13 is a schematic perspective view illustrating the configuration of another nonvolatile memory device according to the fourth embodiment of the invention.
As shown in FIG. 12, a three-dimensional non-volatile memory device 211 can be configured by stacking two layers of a stacked structure including word lines, bit lines, and memory cells 33 sandwiched between them. .
Furthermore, as shown in FIG. 13, a three-dimensional stacked nonvolatile memory device 212 is configured by stacking three layers of stacked structures including word lines, bit lines, and memory cells 33 sandwiched between them. You can also.

As described above, a non-volatile memory device having a three-dimensional structure can be configured by stacking a plurality of stacked structures including word lines, bit lines, and memory cells 33 sandwiched between the word lines, bit lines, and the number of stacked layers. Is optional.

(Fifth embodiment)
The fifth embodiment of the present invention is a probe memory type nonvolatile memory device.
FIG. 14 is a schematic perspective view illustrating the configuration of the nonvolatile memory device according to the fifth embodiment of the invention.
FIG. 15 is a schematic plan view illustrating the configuration of the nonvolatile memory device according to the fifth embodiment of the invention.
As shown in FIGS. 14 and 15, in the nonvolatile memory device 250 according to the fifth embodiment of the present invention, the recording layer 13 provided on the electrode 521 is disposed on the XY scanner 516. ing. Then, a probe array is disposed so as to face the recording layer 13. A protective layer 521a (not shown) is provided on the recording layer 13.

The probe array includes a substrate 523 and a plurality of probes (heads) 524 arranged in an array on one surface side of the substrate 523. Each of the plurality of probes 524 is composed of a cantilever, for example, and is driven by

multiplex drivers

525 and 526.
Each of the plurality of probes 524 can be individually operated using the microactuator in the substrate 523. However, all the probes 524 are collectively operated to access the data area 531 of the storage medium (recording layer 13). It can also be done.

First, by using the

multiplex drivers

525 and 526, all the probes 524 are reciprocated in the X direction at a constant period, and the position information in the Y direction is read from the storage medium (recording layer 13) 532. The position information in the Y direction is transferred to the driver 515.
The driver 515 drives the XY scanner 516 based on the position information, moves the storage medium (recording layer 13) in the Y direction, and positions the storage medium (recording layer 13) and the probe.
When the positioning of both is completed, data reading or writing is performed simultaneously and continuously on all the probes 524 on the data area 531.
Data reading and writing are continuously performed because the probe 524 reciprocates in the X direction. Data reading and writing are performed line by line in the data area 531 by sequentially changing the position of the recording layer 13 in the Y direction.
Note that the recording layer 13 may be reciprocated in the X direction at a constant period to read position information from the storage medium (recording layer 13), and the probe 524 may be moved in the Y direction.

The recording layer 13 has a plurality of data areas 531 and servo areas 532 arranged at both ends of the plurality of data areas 531 in the X direction. The plurality of data areas 531 occupy the main part of the recording layer 13.

A servo burst signal is stored in the servo area 532. The servo burst signal indicates position information in the Y direction within the data area 531.

In addition to these pieces of information, an address area for storing address data and a preamble area for synchronization are arranged in the recording layer 13.
The data and servo burst signal are stored in the recording layer 13 as storage bits (electrical resistance fluctuation). The “1” and “0” information of the storage bit is read by detecting the electrical resistance of the recording layer 13.

In this specific example, one probe (head) is provided corresponding to one data area 531, and one probe is provided for one servo area 532.
The data area 531 is composed of a plurality of tracks. The track of the data area 531 is specified by the address signal read from the address area. The servo burst signal read from the servo area 532 is for moving the probe 524 to the center of the track and eliminating the reading error of the stored bits.
Here, by making the X direction correspond to the down-track direction and the Y direction correspond to the track direction, for example, it is possible to use the head position control technology of the HDD.

Each probe 524 is connected to the drive unit 600 via, for example,

multiplex drivers

525 and 526. The drive unit 600 supplies each probe 524 with at least one of voltage and current for information recording. Then, the recording layer 13 transitions between the high resistance state and the low resistance state by the voltage and current applied via the probe 524. The drive unit 600 detects the high resistance state and the low resistance state recorded on the recording layer 13 and reads the recorded information.

In the nonvolatile memory device 250 having such a configuration, any of the recording layers 13 of the nonvolatile memory elements described in the first to third embodiments can be used as the recording layer 13. As the electrode 521, the upper electrode 14 or the lower electrode 12 of any of the nonvolatile memory elements described in the first to third embodiments can be used.

When the electrode 521 is the lower electrode 12 of any of the nonvolatile memory elements described in the first to third embodiments, the protective layer on the probe 524 side has been described in the first to third embodiments. It can be regarded as any upper electrode 14 of the nonvolatile memory element.
In this case, as described in the first to third embodiments, the electrode 521 is made of at least one of a metal oxide, a metal nitride, and a metal carbide, and contains the first noble metal. On the other hand, a layer of any material can be used for the protective layer regarded as the upper electrode 14.

That is, the nonvolatile memory device 250 according to this embodiment includes any one of the nonvolatile memory elements described in the first to third embodiments, the application of a voltage to the recording layer 13 of the nonvolatile memory element, and And a drive unit 600 that records information by causing the recording layer 13 to transition between a high resistance state and a low resistance state by at least one of energization of a current to the recording layer 13.

The nonvolatile memory device 250 further includes a probe 524 provided alongside the nonvolatile memory element including the recording layer 13 and the electrode 521, and the drive unit 600 passes through the probe 524 and the recording layer 13 of the nonvolatile memory element. At least one of application of the voltage and energization of the current is performed for each recording unit.

Note that the driving unit 600 may include the driver 515 and the XY scanner 516, and conversely, the driving unit may be included in the driver 515 and the XY scanner 516.

Thereby, also in the probe memory type nonvolatile memory device 250 according to the present embodiment, the workability is high and the precision is high due to the effects described with respect to the nonvolatile memory elements according to the first to third embodiments already described. Thus, it is possible to provide a non-volatile memory device having high repeated operation stability.

(Sixth embodiment)
The sixth embodiment of the present invention is a flash memory type nonvolatile memory device.
FIG. 16 is a schematic cross-sectional view illustrating the configuration of the main part of the nonvolatile memory device according to the sixth embodiment of the invention.
FIG. 17 is a schematic cross-sectional view illustrating the operation of the nonvolatile memory device according to the sixth embodiment of the invention.
As shown in FIG. 16, the nonvolatile memory device 260 according to the present embodiment has a flash memory type memory cell, and this memory cell is configured by a MIS (metal-insulator-semiconductor) transistor.

That is, the diffusion layer 42 is formed in the surface region of the semiconductor substrate 41. A gate insulating layer 43 is formed on the channel region between the diffusion layers 42. On the gate insulating layer 43, the nonvolatile memory element 44 according to the embodiment of the present invention is formed. A control gate electrode 45 is formed on the nonvolatile memory element 44.

Here, any one of the nonvolatile memory elements according to the first to third embodiments can be used as the nonvolatile memory element 44.
That is, although not shown in FIG. 16, the nonvolatile memory element 44 includes the recording layer 13, the upper electrode 14, and the lower electrode 12 described in the nonvolatile memory elements according to the first to third embodiments.

That is, the nonvolatile memory device 260 according to this embodiment applies a voltage to at least one of the nonvolatile memory elements described in the first to third embodiments and the recording layer 13 of the nonvolatile memory element, or A drive unit (not shown) that records information by energizing a current to cause the recording layer 13 to transition between the high resistance state and the low resistance state.
In this case, the driving unit is connected to the control gate electrode 45, and the driving unit is at least one of applying a voltage to the recording layer 13 and supplying a current to the recording layer 13 via the control gate electrode 45. Do something.

That is, the nonvolatile memory device 260 according to this embodiment further includes a MIS transistor having a gate electrode (control gate electrode 45) and a gate insulating film (gate insulating layer 43). The nonvolatile memory element 44 is provided between the gate electrode of the MIS transistor and the gate insulating layer.

In the above, any one of the upper electrode 14 and the lower electrode 12 of the nonvolatile memory element 44 may be used as the control gate electrode 45, for example.

The semiconductor substrate 41 may be a well region, and the semiconductor substrate 41 and the diffusion layer 42 have opposite conductivity types. The control gate electrode 45 becomes a word line and is made of, for example, conductive polysilicon.

As shown in FIG. 17, in the set (write) operation SO, the potential V <b> 1 is applied to the control gate electrode 45 and the potential V <b> 2 is applied to the semiconductor substrate 41.
The difference between the potential V1 and the potential V2 is large enough for the recording layer 13 of the nonvolatile memory element 44 to transition between the high resistance state and the low resistance state. However, the polarity of the potential difference is not particularly limited. That is, either V1> V2 or V1 <V2 may be used.

For example, assuming that the recording layer 13 is in the high resistance state phase HR in the initial state (reset state), the gate insulating layer 43 is substantially thickened, so the threshold value of the memory cell (MIS transistor) is , Get higher.

When the potentials V1 and V2 are applied from this state to change the recording layer 13 to the low resistance state phase LR, the gate insulating layer 43 is substantially thinned. Therefore, the threshold value of the memory cell (MIS transistor) is Lower.

Although the potential V2 is applied to the semiconductor substrate 41, the potential V2 may be transferred from the diffusion layer 42 to the channel region of the memory cell instead.
In the figure, arrow Ae represents the movement of electrons, and arrow Ai represents the movement of ions.

On the other hand, in the reset (erase) operation RO, the potential V1 ′ is applied to the control gate electrode 45, the potential V3 is applied to one of the diffusion layers 42, and the potential V4 (<V3) is applied to the other of the diffusion layers 42.
The potential V1 ′ is set to a value exceeding the threshold value of the memory cell in the set state.

At this time, the memory cell is turned on, electrons flow from one side of the diffusion layer 42 to the other side, and hot electrons are generated. Since the hot electrons are injected into the recording layer 13 through the gate insulating layer 43, the temperature of the recording layer 13 rises.

Accordingly, since the recording layer 13 changes from the low resistance state phase LR to the high resistance state phase, the gate insulating layer 43 is substantially thickened, and the threshold value of the memory cell (MIS transistor) is increased. .

As described above, the threshold value of the memory cell can be changed based on a principle similar to that of the flash memory, which can be used as a nonvolatile memory device.
At this time, in the nonvolatile memory device 260 according to this embodiment, since any one of the nonvolatile memory elements described in the first to third embodiments is used as the nonvolatile memory element 44, the workability is good. A nonvolatile memory device with high accuracy and high repetitive operation stability can be provided.

FIG. 18 is a schematic view illustrating the configuration of the main part of another nonvolatile memory device according to the sixth embodiment of the invention.
FIG. 19 is a schematic cross-sectional view illustrating the main part of another nonvolatile memory device according to the sixth embodiment of the invention.
That is, another nonvolatile memory device 261 according to the present embodiment is a NAND flash memory. FIG. 18 illustrates the NAND cell unit 261c and the driving unit 600 connected thereto, and FIG. The structure of the cell unit 261c is illustrated.

As shown in FIGS. 18 and 19, an N-type well region 41b and a P-type well region 41c are formed in the P-type semiconductor substrate 41a. A NAND cell unit 261c is formed in the P-type well region 41c.
The NAND cell unit 261c includes a NAND string composed of a plurality of memory cells MC connected in series, and a total of two select gate transistors ST connected to both ends of the NAND string unit 261c.

The memory cell MC and the select gate transistor ST have the same structure. Specifically, these include an N-type diffusion layer 42, a gate insulating layer 43 on a channel region between the N-type diffusion layers 42, a nonvolatile memory element 44 on the gate insulating layer 43, and a nonvolatile memory element 44 and a control gate electrode 45 (CG) on 44.

Each control gate electrode 45 (CG) is electrically connected to the drive unit 600. Note that the driving unit 600 may be provided on a substrate on which the NAND cell unit 261c is provided, or may be provided on a different substrate.

Further, at least one of the nonvolatile memory elements according to the first to third embodiments is used for the nonvolatile memory element 44. That is, although not shown in these drawings, the nonvolatile memory element 44 is provided with the recording layer 13, the upper electrode 14, and the lower electrode 12 described in the first to third embodiments.

The state (high resistance state phase HR and low resistance state phase LR) of the recording layer 13 of the nonvolatile memory element 44 that is the memory cell MC can be changed by the above-described basic operation. On the other hand, the recording layer 13 of the select gate transistor ST is fixed to the set state, that is, the low resistance state phase LR.

One of the select gate transistors ST is connected to the source line SL, and the other one is connected to the bit line BL.
It is assumed that all memory cells in the NAND cell unit 261c are in a reset state (resistance is large) before the set (write) operation SO.
The set (write) operation SO is sequentially performed one by one from the memory cell MC on the source line SL side toward the memory cell on the bit line BL side.
Giving V1 (positive potential) to the selected word line (control gate electrode) WL as a write voltage, gives a V _pass as a transfer potential to the unselected word lines WL (potential memory cell MC is turned on).
The select gate transistor ST on the source line SL side is turned off, the select gate transistor ST on the bit line BL side is turned on, and program data is transferred from the bit line BL to the channel region of the selected memory cell MC.

For example, when the program data is “1”, a write inhibit potential (for example, the same potential as V1) is transferred to the channel region of the selected memory cell MC, and the recording layer 13 of the selected memory cell MC is transferred. The resistance value should not change from a high state to a low state.

When the program data is “0”, V2 (<V1) is transferred to the channel region of the selected memory cell MC, and the resistance value of the recording layer 13 of the selected memory cell MC is changed from a high state to a low state. To change.

On the other hand, in the reset (erase) operation RO, for example, V1 'is applied to all the word lines (control gate electrodes) WL, and all the memory cells MC in the NAND cell unit 261c are turned on. Further, the two select gate transistors ST are turned on, V3 is applied to the bit line BL, and V4 (<V3) is applied to the source line SL.

At this time, since hot electrons are injected into the recording layers 13 of all the memory cells MC in the NAND cell unit 261c, the reset operation is collectively executed for all the memory cells MC in the NAND cell unit 261c. .

In the read operation, a read potential (positive potential) is applied to the selected word line (control gate electrode) WL, and the memory cell MC receives data “0”, “1” on the unselected word line (control gate electrode) WL. A potential to be turned on without fail is given.
Further, the two select gate transistors ST are turned on to supply a read current to the NAND string.
When the read potential is applied, the selected memory cell MC is turned on or off according to the value of the data stored in the selected memory cell MC. For example, data can be read by detecting a change in the read current. it can.

In the structure illustrated in FIG. 19, the select gate transistor ST has the same structure as the memory cell MC, but may be modified as follows.
FIG. 20 is a schematic cross-sectional view illustrating the main part of a nonvolatile memory device according to a modification according to the sixth embodiment of the invention.
As shown in FIG. 20, in the nonvolatile memory device 262 of the modification according to this embodiment, the select gate transistor ST can be a normal MIS transistor without forming a recording layer.

FIG. 21 is a schematic cross-sectional view illustrating the main part of a nonvolatile memory device according to a modification according to the sixth embodiment of the invention.
As shown in FIG. 21, in the nonvolatile memory device 263 of the modification according to this embodiment, the gate insulating layers of the plurality of memory cells MC configuring the NAND string are replaced with the P-type semiconductor layer 47.

When the high integration progresses and the memory cell MC is miniaturized, the P-type semiconductor layer 47 is filled with a depletion layer without applying a voltage.
In the set (write) operation SO, a positive write potential (for example, 3.5 V) is applied to the control gate electrode 45 of the selected memory cell MC, and the control gate electrode 45 of the non-selected memory cell MC is positive. Transfer potential (for example, 1 V).
At this time, the surface of the P-type well region 41c of the plurality of memory cells MC in the NAND string is inverted from P-type to N-type, and a channel is formed.

Therefore, as described above, the set operation can be performed by turning on the select gate transistor ST on the bit line BL side and transferring the program data “0” from the bit line BL to the channel region of the selected memory cell MC. it can.

On the other hand, in the reset (erase) operation RO, for example, a negative erase potential (for example, −3.5 V) is applied to all control gate electrodes 45, and the ground potential (P-type well region 41c and P-type semiconductor layer 47 are grounded). 0V), all the memory cells MC constituting the NAND string can be collectively processed.

At the time of reading, a positive read potential (for example, 0.5 V) is applied to the control gate electrode 45 of the selected memory cell MC, and the memory cell MC receives the data “ A transfer potential (for example, 1 V) that always turns on regardless of 0 ”or“ 1 ”is applied.
However, the threshold voltage Vth “1” of the memory cell MC in the “1” state is in the range of 0V <Vth “1” <0.5 V, and the threshold voltage Vth of the memory cell MC in the “0” state “0” is assumed to be in the range of 0.5 V <Vth “0” <1 V.
Further, the two select gate transistors ST are turned on to supply a read current to the NAND string.
In such a state, since the amount of current flowing through the NAND string changes according to the value of the data stored in the selected memory cell MC, data can be read by detecting this change.

In this modification, the hole doping amount of the P-type semiconductor layer 47 is larger than that of the P-type well region 41c, and the Fermi level of the P-type semiconductor layer 47 is 0 than that of the P-type well region 41c. It is desirable that the depth is about 5V.
This is because when a positive potential is applied to the control gate electrode 45, inversion from the P-type to N-type starts from the surface portion of the P-type well region 41c between the N-type diffusion layers 42, and a channel is formed. It is to make it.
Thus, for example, at the time of writing, the channel of the non-selected memory cell MC is formed only at the interface between the P-type well region 41c and the P-type semiconductor layer 47, and at the time of reading, a plurality of memories in the NAND string is formed. The channel of the cell MC is formed only at the interface between the P-type well region 41 c and the P-type semiconductor layer 47.
That is, even if the recording layer 13 of the nonvolatile memory element 44 used in the memory cell MC is in the low resistance state phase LR, the diffusion layer 42 and the control gate electrode 45 are not short-circuited.

FIG. 22 is a schematic view illustrating the configuration of the main part of another nonvolatile memory device according to the sixth embodiment of the invention.
FIG. 23 is a schematic cross-sectional view illustrating the main part of another nonvolatile memory device according to the sixth embodiment of the invention.
That is, another nonvolatile memory device 264 according to the present embodiment is a NOR flash memory. FIG. 22 illustrates the NOR cell unit 264c and the drive unit 600 connected thereto, and FIG. The structure of the cell unit 264c is illustrated.

As shown in FIGS. 22 and 23, an N-type well region 41b and a P-type well region 41c are formed in the P-type semiconductor substrate 41a. A NOR cell is formed in the P-type well region 41c.
The NOR cell is composed of one memory cell (MIS transistor) MC connected between the bit line BL and the source line SL.
The memory cell MC includes an N-type diffusion layer 42, a gate insulating layer 43 on a channel region between the N-type diffusion layers 42, a non-volatile storage element 44 on the gate insulating layer 43, and a non-volatile storage element 44. And the control gate electrode 45.

Each control gate electrode 45 (CG) is electrically connected to the drive unit 600. Note that the driving unit 600 may be provided on a substrate on which the NOR cell unit 264c is provided, or may be provided on a different substrate.

The state (high resistance state phase HR and low resistance state phase LR) of the recording layer 13 of the nonvolatile memory element 44 used in the memory cell MC can be changed by the above-described basic operation.

FIG. 24 is a schematic view illustrating the configuration of the main part of another nonvolatile memory device according to the sixth embodiment of the invention.
FIG. 25 is a schematic cross-sectional view illustrating the main part of another nonvolatile memory device according to the sixth embodiment of the invention.
That is, another nonvolatile memory device 265 according to the present embodiment is a two-tra type flash memory. FIG. 24 illustrates a two-tracell unit 265c and a driving unit 600 connected thereto, and FIG. The structure of the 2 tracell unit 265c is illustrated.

As shown in FIG. 24 and FIG. 25, the 2-tra cell unit 265c has a cell structure having both the characteristics of the NAND cell unit and the characteristics of the NOR cell.

In the P-type semiconductor substrate 41a, an N-type well region 41b and a P-type well region 41c are formed. In the P-type well region 41c, a 2-tracell unit 265c is formed.

The 2-tra cell unit 265c includes one memory cell MC and one select gate transistor ST connected in series.
The memory cell MC and the select gate transistor ST have the same structure. Specifically, these include an N-type diffusion layer 42, a gate insulating layer 43 on a channel region between the N-type diffusion layers 42, a nonvolatile memory element 44 on the gate insulating layer 43, and a nonvolatile memory element And a control gate electrode 45 on the upper side 44.

Each control gate electrode 45 (CG) is electrically connected to the drive unit 600. In addition, the drive part 600 may be provided in the board | substrate with which the 2 trcell unit 265c is provided, and may be provided in another board | substrate.

The state (high resistance state phase HR and low resistance state phase LR) of the recording layer 13 of the nonvolatile memory element 44 used in the memory cell MC can be changed by the above-described basic operation. On the other hand, the recording layer 13 of the select gate transistor ST is fixed to the set state, that is, the low resistance state phase LR.

The select gate transistor ST is connected to the source line SL, and the memory cell MC is connected to the bit line BL.

The recording layer 13 state (high resistance state phase HR and low resistance state phase LR) of the nonvolatile memory element 44 used in the memory cell MC can be changed by the basic operation described above.

In the structure illustrated in FIG. 25, the select gate transistor ST has the same structure as the memory cell MC, but may be modified as follows.
FIG. 26 is a schematic cross-sectional view illustrating the main part of a nonvolatile memory device according to a modification according to the sixth embodiment of the invention.
As shown in FIG. 26, in the nonvolatile memory device 266 of the modification according to the present embodiment, the select gate transistor ST can be a normal MIS transistor without forming the nonvolatile memory element 44. It is.

The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, regarding the specific configuration of each element constituting the nonvolatile memory element and the nonvolatile memory device, those skilled in the art can implement the present invention in the same manner by appropriately selecting from a known range, and obtain the same effect. Is included in the scope of the present invention as long as possible.
Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

In addition, all nonvolatile memory elements and nonvolatile memory devices that can be implemented by those skilled in the art based on the nonvolatile memory elements and nonvolatile memory devices described above as embodiments of the present invention are also included As long as the gist of the invention is included, it belongs to the scope of the present invention.

In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

According to the present invention, a non-volatile memory element and a non-volatile memory device having good processability, high accuracy, and high repetitive operation stability are provided.

Claims

A first layer having electrical conductivity;
A second layer having electrical conductivity;
A recording layer provided between the first layer and the second layer and capable of recording information by reversibly transitioning between a high resistance state and a low resistance state;
At least one of the first layer and the second layer is made of at least one of a metal oxide, a metal nitride, and a metal carbide, and contains a first noble metal. .
2. The nonvolatile memory element according to claim 1, wherein the first noble metal is dispersed in at least one of the layers.
2. The non-volatile memory element according to claim 1, wherein the first noble metal is contained on the recording layer side of the at least one of the layers.
The concentration of the first noble metal on the side close to the recording layer of the at least one layer is higher than the concentration of the first noble metal on the side farther from the recording layer than the near side of the at least one layer. The nonvolatile memory element according to claim 1.
2. The nonvolatile memory element according to claim 1, wherein the concentration of the first noble metal in the at least one layer is 2 atomic percent or more and 40 atomic percent or less.
The non-volatile memory element according to claim 1, wherein the first noble metal is precipitated in at least one of the inside and the surface of the at least one layer.
2. The nonvolatile memory element according to claim 1, wherein the first noble metal is precipitated as a plurality of first grains in at least one of the inside and the surface of the at least one layer.
The nonvolatile memory element according to claim 7, wherein an average interval between the first grains is larger than a diameter of the first grains.
The non-volatile memory element according to claim 1, wherein the first noble metal is at least one selected from the group consisting of Ag, Pt, and Pd.
The recording layer has a spinel structure represented by A x B y X 4 (0.1 ≦ x ≦ 2.2, 1.5 ≦ y ≦ 2), and A x B y X 2 (0.1 ≦ x ≦ 1.1, 0.9 ≦ y ≦ 1.1) Delafossite structure, A x B y X 4 (0.5 ≦ x ≦ 1.1, 0.7 ≦ y ≦ 1.1) And a ilmenite structure represented by A x B y X 3 (0.5 ≦ x ≦ 1.1, 0.9 ≦ y ≦ 1). Item 10. The nonvolatile memory element according to Item 1.
Provided between at least one of the layers and the recording layer, comprising at least one of metal, metal oxide, metal nitride, and metal carbide, and including a second noble metal of a type different from the first noble metal. The nonvolatile memory element according to claim 1, further comprising a third layer.
The nonvolatile memory element according to claim 11, wherein the concentration of the second noble metal in the third layer is not less than 2 atomic percent and not more than 50 atomic percent.
12. The nonvolatile memory element according to claim 11, wherein the thickness of the third layer is not less than 0.5 nm and not more than 10 nm.
14. The non-volatile memory element according to claim 13, wherein the concentration of the second noble metal in the third layer is not less than 2 atomic percent and not more than 50 atomic percent.
12. The nonvolatile memory element according to claim 11, wherein the second noble metal is precipitated in at least one of the inside and the surface of the third layer.
12. The nonvolatile memory element according to claim 11, wherein the second noble metal is precipitated as a plurality of second grains in at least one of the inside and the surface of the third layer.
The nonvolatile memory element according to claim 16, wherein an average interval between the second grains is larger than a diameter of the second grains.
The non-volatile memory element according to claim 1, wherein the second noble metal is at least one selected from the group consisting of Ag, Pt, and Pd.
The recording layer has a spinel structure represented by A x B y X 4 (0.1 ≦ x ≦ 2.2, 1.5 ≦ y ≦ 2), and A x B y X 2 (0.1 ≦ x ≦ 1.1, 0.9 ≦ y ≦ 1.1) Delafossite structure, A x B y X 4 (0.5 ≦ x ≦ 1.1, 0.7 ≦ y ≦ 1.1) And a ilmenite structure represented by A x B y X 3 (0.5 ≦ x ≦ 1.1, 0.9 ≦ y ≦ 1). Item 12. The nonvolatile memory element according to Item 11.
The nonvolatile memory element according to claim 1,
Transition between the high resistance state and the low resistance state in the recording layer by at least one of application of a voltage to the recording layer of the nonvolatile memory element and energization of current to the recording layer A drive unit for recording information,
A non-volatile storage device comprising:
A word line and a bit line provided so as to sandwich the nonvolatile memory element;
The driving unit performs at least one of application of a voltage to the recording layer of the nonvolatile memory element and energization of a current to the recording layer via the word line and the bit line. 21. The nonvolatile memory device according to claim 20, wherein:
A probe provided alongside the nonvolatile memory element;
21. The drive unit performs at least one of application of the voltage and energization of the current to a recording unit of the recording layer of the nonvolatile memory element via the probe. Nonvolatile storage device.
A MIS transistor including a gate electrode sandwiching the nonvolatile memory element and a gate insulating layer;
The drive unit performs at least one of application of a voltage to the recording layer of the nonvolatile memory element and energization of a current to the recording layer through the gate electrode. Item 20. The nonvolatile memory device according to Item 20.
First and second second conductivity type semiconductor regions provided in the first conductivity type semiconductor substrate;
A first conductivity type semiconductor region between the first and second second conductivity type semiconductor regions;
A gate electrode for controlling conduction / non-conduction between the first and second second conductivity type semiconductor regions;
Further comprising
The nonvolatile memory element is disposed between the gate electrode and the first conductivity type semiconductor region,
The drive unit performs at least one of application of a voltage to the recording layer of the nonvolatile memory element and energization of a current to the recording layer through the gate electrode. Item 20. The nonvolatile memory device according to Item 20.