WO2010025568A1

WO2010025568A1 - A method and system for dynamic signal to noise ratio adjustment in a transceiver

Info

Publication number: WO2010025568A1
Application number: PCT/CA2009/001246
Authority: WO
Inventors: Steven Arnold Devison; Tajinder Manku
Original assignee: Icera Canada ULC
Priority date: 2008-09-05
Filing date: 2009-09-08
Publication date: 2010-03-11
Also published as: WO2010025568A8

Abstract

A method and system for dynamically adjusting the signal to noise ratio (SNR) of the downconverted signal in the receive path of a transceiver. The system extracts the SNR from an unchanging repeated data pattern that accompanies data in the received signal, and compares it to the desired SNR in order to determine whether an SNR adjustment is required or not. Because the repeated data pattern is known, this repeated data pattern can be extracted from the input signal, and the measured SNR of the repeated data pattern corresponds to the SNR of the data. If the measured SNR is lower than the desired SNR, the system controls circuitry in the receiver for adjusting the SNR. In an embodiment, the system adjusts the SNR in the received signal by reducing the effects of the second order intermodulation products (IP2), and the third order intermodulation products (IM3) in the mixer and the low noise amplifier of the receiver.

Description

A METHOD AND SYSTEM FOR DYNAMIC SIGNAL TO NOISE RATIO ADJUSTMENT

IN A TRANSCEIVER

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application claims the benefit of priority of U.S. Provisional Patent

Application No. 61/094,682 filed on September 5, 2008, which is incorporated herein by reference in its entirety.

FIELD OF THE INVENTION [0002] The present invention relates generally to wireless transceivers. More particularly, the present invention relates to adjusting the signal to noise ratio (SNR) in the receive path of the transceiver.

BACKGROUND OF THE INVENTION [0003] Wireless devices have been in use for many years for enabling mobile communication of voice and data. Such devices can include mobile phones and wireless enabled personal digital assistants (PDA's) for example. Figure 1 is a generic block diagram of the core components of such wireless devices. The wireless core 10 includes a base band processor 12 for controlling application specific functions of the wireless device and for providing and receiving voice or data signals to a radio frequency (RF) transceiver chip 14. The RF transceiver chip 14 is responsible for frequency up- conversion of transmission signals, and frequency down-conversion of received signals. RF transceiver chip 14 includes a receiver core 16 connected to an antenna 18 for receiving transmitted signals from a base station or another mobile device, and a transmitter core 20 for transmitting signals through the antenna 18. Those of skill in the art should understand that Figure 1 is a simplified block diagram, and can include other functional blocks that may be necessary to enable proper operation or functionality.

[0004] Generally, the transmitter core 20 is responsible for up-converting electromagnetic signals from base band to higher frequencies for transmission, while receiver core 16 is responsible for down-converting those high frequencies back to their original frequency band when they reach the receiver, processes known as up-conversion and down-conversion (or modulation and demodulation) respectively. The original (or base band) signal, may be, for example, data, voice or video. These base band signals may be produced by transducers such as microphones or video cameras, be computer generated, or transferred from an electronic storage device. In general, the high frequencies provide longer range and higher capacity channels than base band signals, and because high frequency radio frequency (RF) signals can propagate through the air, they are preferably used for wireless transmissions.

[0005] All of these signals are generally referred to as radio frequency (RF) signals, which are electromagnetic signals; that is, waveforms with electrical and magnetic properties within the electromagnetic spectrum normally associated with radio wave propagation.

[0006] Figure 2 is a block diagram showing some circuits in the receive path of the receiver 16 that is used in a conventional transceiver such as the transceiver 10 shown in Figure 1. The circuitry in the receiver 16 is well known, and in the present example includes a low noise amplifier 24 (LNA), a mixer 26 to downconvert the signal to a local frequency, a filter 28 to remove noise, a variable gain amplifier (VGA) 30 to increase signal gain, and an analog to digital converter (ADC) 32 to convert the signal into digital words. In operation, an input signal RFin is received at the receiver circuit 16 to be demodulated in order to extract the information sent on this signal. The resulting digital word BBin is provided to the base band processor for further processing as voice or data information. Those skilled in the art understand that receiver circuit 16 is a generalized example, and different specific circuit configurations are possible, depending on the particular communication standard being adhered to. [0007] In the receiver 16, it is desirable to keep the SNR above a certain threshold so that the signal can be properly extracted. The problem with receiver 16 shown in Figure 2, is that the components of receiver 16 are subject to noise or other adverse effects that degrade the SNR of the received signal as it is processed through receiver 16. One such adverse effect is that the antenna 18 may receive copies of the signal due to reflections. The signal copies are faded versions of the signal, and thus, add noise to the signal and reduce the SNR in the receiver 16. Another adverse effect is that signals from the transmitter 20 can leak back into components of the receiver 16, thereby adding noise and reducing SNR. [0008] Another factor that reduces the SNR is the non-linearity of specific circuit elements e.g. mixers, amplifiers etc, due to environmental changes. In conventional systems, the LNA 24 and mixer 26 can be calibrated during manufacturing or at power up to compensate for process variations that affect the linearity. However, those skilled in the art understand that the linearity can change as the temperature of the LNA and/or mixer change during operation. For instance during a long call, the power amplifier which powers the antenna during transmit operations can heat up the wireless device, motherboard and chip packages to such an extent that the linearity of elements 24 to 32 of the receiver 16 is lost, thereby contributing to a decrease in the SNR of the signal to be provided to the baseband processor 12.

[0009] While there are techniques for correcting linearity of receiver components at power up, those settings are typically valid only for the power up conditions. Since most wireless devices remain turned on for long durations of time and are rarely powered off, this technique does not resolve the issue where SNR may decrease due to any of the previously mentioned adverse effects which may occur while the wireless device is active, or turned on. Techniques are known for sampling the received data signal to evaluate the SNR for dynamic adjustment of the receive path components, however such systems may be complex, consume large areas of the chip, and consume more power. [0010] It is, therefore, desirable to provide an inexpensive system for determining an SNR of the receive path circuits to enable feedback adjustment to maintain the SNR of the signal at some minimum acceptable level.

SUMMARY OF THE INVENTION

[0011] It is an object of the present invention to obviate or mitigate at least one disadvantage of previous receive path circuits.

[0012] In a first aspect, the present invention provides a receive path for a transceiver. The receive path includes down conversion circuitry and a signal to noise (SNR) corrector. The down conversion circuitry receives a signal, including data and a repeated code, and downconverts the signal to provide a downconverted signal. The SNR corrector is configured for determining an SNR of the repeated code and for adjusting linearity of at least one circuit element in the down conversion circuitry in response to the SNR of the repeated code being lower than a predetermined SNR.

According to a present embodiment, the SNR corrector includes an SNR extractor and an SNR adjuster. The SNR extractor determines the SNR of the repeated code and provides a control signal indicating that the SNR of the repeated code is lower than the predetermined SNR. The SNR adjuster provides at least one preset adjustment code effective for adjusting linearity of the at least one circuit element in response to the control signal. The at least one circuit element is configured to be responsive to the preset adjustment code. The SNR extractor includes a code extractor and an SNR determinator. The code extractor is configured to extract only the repeated code from the downconverted signal for providing extracted code. The SNR determinator determines the SNR of the extracted code and compares the SNR of the extracted code to the predetermined SNR. The code extractor provides the control signal when the SNR of the extracted code is less than the predetermined SNR, where the control signal corresponds to a magnitude of a difference between the SNR of the extracted code and the predetermined SNR. [0013] In an aspect of the present embodiment, the SNR adjuster includes an optimizer and at least one digital to analog converter (DAC). The optimizer provides the at least one preset adjustment code in response to the control signal. The at least one DAC converts the at least one preset adjustment code to an analog signal that adjusts the linearity of the at least one circuit element. The at least one circuit element can include a mixer having adjustable IP2, and the at least one DAC can include an IP2 DAC for receiving the at least one preset adjustment code. Alternately, the at least one circuit element can include a low noise amplifier (LNA) having adjustable IM3, and the at least one DAC can include an IM3 DAC for receiving the at least one preset adjustment code. Alternately, the at least one circuit element can include a mixer having adjustable IP2 and an LNA having adjustable IM3, and the at least one DAC can include an IP2 DAC for receiving a first preset adjustment code and an IM3 DAC for receiving a second preset adjustment code.

[0014] In another aspect of the present embodiment, the code extractor includes at least one finite impulse response (FIR) filter having taps configured to have coefficients corresponding to the repeated code. The signal can be a wideband code division multiple access (W-CDMA) compliant signal, and the repeated code can be a primary synchronization channel (PSCH) code.

[0015] In a second aspect, the present invention provides a method for adjusting the signal to noise ratio (SNR) in a receive path. The method includes downconverting a signal containing data and a predetermined code for providing a downconverted signal; determining an SNR of the predetermined code; comparing the SNR of the predetermined code to a minimum SNR value to determine if an SNR adjustment is needed; and adjusting a linearity characteristic of at least one circuit element in the receive path if the SNR of the predetermined code is lower than the minimum SNR value. According to a present embodiment, the step of determining includes extracting a primary synchronization channel (PSCH) code from the signal, the signal being wideband code division multiple access (W-CDMA) compliant. The step of extracting the PSCH then includes filtering the signal using at least one finite impulse response (FIR) filter having taps configured with coefficients corresponding to the PSCH code.

- A - [0016] In another embodiment, the step of comparing includes providing a magnitude of a difference between the SNR of the predetermined code and the minimum SNR value when the SNR of the predetermined code is lower than the minimum SNR value. In further embodiments of the present aspect, the at least one circuit element includes a mixer having adjustable IP2, and the step of adjusting includes sending a preset adjustment code to the mixer to adjust a linearity characteristic of the mixer. In yet another embodiment, the at least one circuit element includes a low noise amplifier (LNA) having adjustable IM3, and the step of adjusting includes sending a preset adjustment code to the LNA to adjust a linearity characteristic of the mixer. [0017] Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.

BRIEF DESCRIPTION OF THE DRAWINGS [0018] Embodiments of the present invention will now be described, by way of example only, with reference to the attached Figures, wherein:

Figure 1 is a block diagram of a known wireless core for a wireless device; Figure 2 is a block diagram of the receiver in the transceiver circuit of Figure 1 ; Figure 3 is a schematic of a receiver having an SNR correction circuit, in accordance with a present embodiment;

Figure 4 is a graphical representation of one time slot of a conventional W- CDMA signal;

Figure 5 is a block diagram of the SNR extractor shown in Figure 3, according to a present embodiment;

Figure 6 is a graphical representation of the signal at the output of the SNR extractor of Figure 5 in the frequency domain;

Figure 7 is block diagram of an SNR adjuster, in accordance with a present embodiment; and Figure 8 is a flowchart illustrating a method of adjusting SNR in a receiver, according to a present embodiment.

DETAILED DESCRIPTION [0019] Generally, the present invention provides a method and system for dynamically adjusting the signal to noise ratio (SNR) of the downconverted signal in the receive path of a transceiver. The system extracts the SNR from an unchanging repeated data pattern that accompanies data in the received signal, and compares it to the desired SNR in order to determine whether an SNR adjustment is required or not. Because the repeated data pattern is known, this repeated data pattern can be extracted from the input signal, and the measured SNR of the repeated data pattern corresponds to the SNR of the data. If the measured SNR is lower than the desired SNR, the system controls circuitry in the receiver for adjusting the SNR. In an embodiment, the system adjusts the SNR in the received signal by reducing the effects of the second order intermodulation products (IP2), and the third order intermodulation products (IM3) in the mixer and the low noise amplifier of the receiver.

[0020] Figure 3 shows a receiver 34 having an SNR corrector in accordance with an embodiment of the invention. Similar to the conventional receiver 16 shown in Figure 2, the receiver 34 includes down conversion circuitry for downconverting input signal RFin into signal BBin. The down conversion circuitry includes an LNA 36, a mixer 38 to downconvert the signal to a local frequency, a filter 40 to remove noise, a VGA 42 to increase signal gain, and an ADC 44 to convert the signal into digital words. The receiver 34 also includes a feedback loop consisting of an SNR corrector for dynamically adjusting components of the receiver 34 to improve the SNR in the downconverted signal. The

SNR corrector includes an SNR extractor 46 for extracting the SNR from a repeated data pattern in the received signal, and an SNR adjuster 48 for generating signals effective for adjusting the LNA 36 and/or mixer 38. In the present embodiment, the SNR adjuster 48 adjusts the SNR in the receiver 34 by controlling the linearity of either the low noise amplifier 36, or the mixer 38, or both. It is assumed that the repeated data pattern is established by a communications standard or protocol, and is used for some other purpose where its repeating nature is required. Therefore, because the repeated pattern is known, the SNR extractor can be specifically configured to extract the repeated data pattern from the signal, which may include other data and voice channels. It should be noted that the functionality described for SNR extractor 46 can be shifted into SNR adjuster 48, and vice versa.

[0021] For the purpose of explanation, the application will continue hereinafter to describe a system and method for determining the SNR from a W-CDMA signal. However, it should be noted that the invention is not limited to a CDMA protocol, and may be used with other standards and protocols in which a predetermined constant signal is provided with the data signal.

[0022] In a W-CDMA system, the same frequency is used to transmit different data channels, with each data channel being coded differently. Figure 4 shows one data slot in which data is transmitted from a base station to a wireless device. In this example, four channels CH 1 to CH4 are provided with each channel being encoded with a different code PN1 to PN4. According to the standard, each W-CDMA data slot includes a primary synchronization channel (PSCH). Those skilled in the art should understand that a secondary synchronization channel (SSCH) is provided and used in W-CDMA communications. The PSCH signal is a 256-chip spreading code that is repeated in every data slot. More specifically, the PSCH is repeated every 2560 chips (666.66 micro seconds) in every cell, and repeats 15 times in each WCDMA frame having a duration of about 10ms. The PSCH is transmitted by the base station (also known as base transceiver station) and is used for initial cell synchronization by user equipment that operates in accordance with the W-CDMA standard. The PSCH sequence has been optimized for matched filter FIR implementations so the user equipment correlators can easily find the P-SCH signals during their cell search procedure. The PSCH is repeated every 2560 chips (666.66 us) in every cell and repeats 15 times in each W-CDMA frame (10 ms). [0023] The primary synchronization code (PSC)₁ C_psc is constructed as a so-called generalized hierarchical Golay sequence. The PSCH has the following fixed coding sequence : <1 , 1 , 1 , 1 , 1 , 1 , -1 , -1 , 1 , -1 , 1 , -1 , 1 , -1 , -1 , 1 >. The primary purpose of the PSCH is to establish slot synchronization to a cell, typically done by matching a filter configured to the known PSCH code sequence. This fixed coding sequence of the PSCH, which is repeated in every slot is used to determine the SNR, in accordance with an embodiment of the invention as will be described as follows.

[0024] Figure 5 is block diagram illustrating the components of SNR extractor 46 of the SNR corrector of Figure 3, in accordance with an embodiment of the present invention. As illustrated in Figure 5, a PSCH extractor 50 extracts the PSCH from the digital BBin signal taken as a feedback signal at the output of the ADC 44, and outputs the PSCH code and any accompanying noise which may have been introduced by components of the down conversion circuitry. An SNR determinator 52 calculates the approximate SNR of the extracted PSCH code. Those skilled in the art should understand that there are known techniques for achieving this result. For example, one technique is to convert the extracted PSCH signal with its accompanying noise into the frequency domain and measuring the signal peak relative to the noise floor. An example plot of the extracted signal converted to the frequency domain appears in Figure 6. As will be discussed later, the determined SNR of the extracted signal corresponds to the SNR of the downconverted signal data. Since the PSCH appears in the same slot as the signal data, any noise affecting the PSCH affects the signal data as well.

[0025] Following is an example calculation for determining the SNR of the extracted PSCH code. In this example, a first step is to determine an appropriate SNR condition for the PSCH at the receiver output, which in the present embodiments is taken at output signal BBin. The most critical point for a high IIP2 is near sensitivity. At sensitivity the typical receiver NF is 7dB. The PSCH channel and a secondary synchronization channel SSCH channels are multiplexed together on a SCH_Ec physical channel. The expected REFIor level at sensitivity is -109dBm (2 dB better than 3GPP). With the DPCH-Ec at 10.3dB below REFIor in 3GPP₁ the DPCH_Ec level will be - 119.3dBm. From 3GPP, the SCH_Ec / DPCH_Ec ratio is +5 dB with the SCH_Ec power equally distributed between PSCH and SSCH. So PSCH and SSCH are 1.99 dB each above DPCH_Ec.

[0026] The representative 'P-SCH to noise' ratio is thus:

[0027] SNRp.sc_H = (DPCH_Ec + 1.99) - (DPCH_Ec +25 - 7)

= (-119.3 + 1.99) - (-101.3) SNR_P-scH = -16 dB.

[0028] The worst case SNR for REFIor is:

SNR_REFIor = -109 - (-174+7+65.84) = -7.84 dB.

[0029] Extraction of the PSCH may be effected using a finite impulse response

(FIR) filter configured with the PSCH code. As shown in Figure 5, a number of FIR filters 54 are used in order to eliminate the effect of the reflected versions of the signal received at the receiver 34. Although Figure 6 shows only three FIR 54, any number of FIR 54 can be used for the purposes of noise cancellation. The outputs of the FIR's 54 are then summed using an adder 56 in order to eliminate out of phase components. The adder 56 outputs the PSCH with the noise of the downconverted signal. As persons of skill in the art should understand, an FIR filter has taps where each tap has a corresponding coefficient that is multiplied by the data, as the data passes through a delay line of the FIR filter. In the present embodiment, FIR filters 54 have taps with coefficients that correspond to the previously shown PSCH code sequence. [0030] Figure 6 is a graphical representation of the extracted PSCH signal when converted to the frequency domain. In the present embodiment, this conversion can take place within SNR determinator 52 after the PSCH signal is provided by PSCH extractor 50. Alternately, some calculated result corresponding to the output of Figure 6 can be executed in SNR determinator 52. The central peak 58 represents the desired signal, and should have the greatest amplitude, which is based on the fixed logical sequence of the PSCH code. The side peaks 60 represent the noise in the downconverted PSCH code signal. Depending on the setting, the highest amplitude of the side peaks 60 is taken to represent a noise floor, or alternately, an average amplitude of all the peaks 60 is taken to represent the noise floor. Accordingly, the SNR is directly related to the difference in voltage between the central peak 58, and the established noise floor, based on the amplitude of side peaks 60. Because the voltage difference 62 between the central peak 58 and the side peaks 60 is proportional to the SNR, this difference can be compared to a predetermined minimum difference which has been calibrated to correspond to a minimum acceptable SNR. Such a minimum acceptable SNR can be determined based on the design of the circuit and any constraints imposed by a particular communication standard.

[0031] In summary, the SNR determinator 52 receives as its input, an extracted known repeating data pattern, such as the extracted PSCH signal for example, from the output of the PSCH extractor 50. SNR determinator 52 then executes operations to convert the extracted known data pattern into a form that is comparable to a value calibrated to be a minimum desired SNR value. The minimum desired SNR value may be pre-set by the manufacturer or stored in a register or memory. The output of this comparison can be a word representing a magnitude of the difference between the determined SNR and the minimum desired SNR, if the determined SNR is too small. In such an embodiment, SNR determinator 52 would include an analog to digital converter having a suitable resolution for providing the digital word. If the comparison indicates that the determined SNR is sufficiently high, then the digital word can be set to a null value. In either embodiment, the output signal of SNR determinator 52 is referred to as signal SNR_ADJ. The SNR determinator 52 can continuously compare the determined SNR received from the SNR extractor 46, or it can periodically compare the determined SNR against the minimum desired SNR. Each comparison iteration results in the generation of SNR_ADJ. [0032] Signal SNR_ADJ is provided to the SNR adjuster 48, as illustrated in Figure 3, in order to control circuitry in the receiver 34 for adjusting a linearity characteristic of one or more circuit elements to improve the SNR in the downconverted signal. In the embodiment shown in Figure 3, the SNR adjuster 48 adjusts the SNR in the receiver 34 by controlling either the low noise amplifier 36, or the mixer 38, or both. However, the invention is not limited to adjusting these two elements only. Persons skilled in the art understand that the linearity of other circuitry may also be adjusted in order to improve the SNR in the downconverted signal.

[0033] In one example of the present embodiment, linearity of the LNA 36 is adjusted by reducing the effect of the third order intermodulation products (IM3) in the received signal in order to improve the SNR in the downconverted signal. Third-order intermodulation products (IM3) is a common interference problem in RF circuits where two or more signals mix in a non-linear phase or "device" to form one or more new signals, and thereby creating intermodulation products. In the receiver section of a transceiver chip, these intermodulation signals may fall on top of a desirable signal (in frequency domain) thereby reducing the signal to noise ratio. The linearity of the LNA 36 can be adjusted using the techniques and circuits disclosed in commonly owned United States Patent Publication No. 20080007334, which is incorporated herein by reference. [0034] According to the present embodiments, another circuit where its linearity can be adjusted is mixer 38. More specifically, the linearity of mixer 38 is adjustable to reduce the effect of second order intermodulation products (IP2). The second order intermodulation products IP2 are usually caused by a mismatch in the electrical components such as transistors, for example, in the differential signal path of the mixer. In the present embodiment, the linearity a mixer can be adjusted using the techniques and circuits disclosed in commonly owned U.S. Patent No. 7,554,380, which is incorporated herein by reference. [0035] Figure 7 is block diagram of an example SNR adjuster 48, in accordance with an embodiment of the invention which is adapted to use the linearity adjustment techniques disclosed in United States Patent Publication No. 20080007334 and U.S. Patent No. 7,554,380. The SNR adjuster 48 includes an optimizer 64, IP2 DAC 68 and IM3 DAC 66. It is noted that IP2 DAC 68 represents any number of individual DACs that may be required for the mixer design. The optimizer 64 determines which of the mixer 38 and/or the LNA 36 are to have their linearity adjusted in response to SNR_ADJ. Since SNR_ADJ represents a magnitude of the difference between the determined SNR and the desired minimum SNR, optimizer 64 is configured for providing at least one adjustment code usable by either IP2 DAC 68 or IM3 DAC 66. The at least one adjustment code can be read out from a memory which stores a plurality of different preset adjustment codes, where the preset adjustment codes are calibrated for adjusting linearity of either the mixer 38 or the LNA 36 by predetermined amounts. Logic within optimizer 64 then selects the closest preset adjustment code based on the magnitude of SNR_ADJ. [0036] Ideally, the magnitude of SNR_ADJ progressively decreases with each iteration of SNR determination. This indicates that the SNR of the downsampled signals is being increased, or improved. In the example where linearity of the mixer is adjusted using the techniques described in U.S. Patent No. 7,554,380, sequential DAC codes can be provided adjust the measured IIP2 until a maximum value represented by the peak of a plotted curve is attained, as shown in Figure 6 of U.S. Patent No. 7,554,380. Therefore, depending on which side of the peak the selected DAC code is on and the direction of adjustment, it is possible that the selected preset adjustment code does not improve the SNR, and may in fact further degrade the SNR relative to its previous level. In the present embodiment, this condition can be detected when the magnitude of SNR_ADJ increases relative to the previous level. In such a situation, a new preset adjustment code progressing in an opposite direction is used. This principle of operation also applies to the adjustment codes for changing the linearity of LNA 36.

[0037] In the embodiment of Figure 7, SNR adjuster 48 includes both IP2 DAC 68 and IM3 DAC 66. This provides maximum flexibility since different combinations of linearity adjustments to both mixer 38 and LNA 36 are possible for improving SNR. In such an embodiment, those skilled in the art understand that mixer 38 and LNA 36 are of the type where their linearity can be adjusted. Optimizer 64 is then preconfigured to provide different combinations of adjustment codes to both IP2 DAC 68 and IM3 DAC 66 at the same time. Such combinations may overcome situations where the range of linearity adjustment to one circuit element alone is insufficient to improve SNR to the desired level. For example, if the linearity adjustments performed on the selected circuit element (either LNA 36 or mixer 38) are not sufficient to adjust the SNR to the desired SNR, the optimizer 64 can then start adjusting the linearity the other circuit element while fixing the adjustment code for the previous circuit element. Alternatively, the optimizer 64 can control both circuit elements simultaneously. In both embodiments, the optimizer keeps track of the previous code that was used, and the resulting SNR in order to determine the direction of adjustment that is required. In a further alternate embodiment, SNR adjuster 48 includes only one of IP2 DAC 68 or IM3 DAC 66. This simplifies the design of optimizer 64, and minimizes the number of preset adjustment codes that are needed, since only one component is to be adjusted. [0038] It is within the scope of the invention, to use other methods to reduce the effects of IP2 and IM3 in the received signal. All of these methods are incorporated herein by reference, and may be used in the present invention in order to improve the SNR in the received signal by adjusting a linearity parameter of a circuit element. It is also within the scope of the invention to control other circuitry in the receiver by adjusting the effect of other parameters such as IP3 and the like without departing form the scope of the invention as recited in the claims.

[0039] Figure 8 is a flowchart illustrating a method for adjusting the SNR in the received signal, according to an embodiment of the present invention. At step 100 an RF signal is received at the input of the receiver 34, which includes data and a repeating code, such as the PSCH code. The signal is then downconverted to extract the information sent on this signal. At step 102, the repeating code is extracted from the downconverted signal. As shown in the embodiment of Figure 5, the repeating code is extracted using FIR filters. Once the repeating code is extracted, the SNR of the repeating code is then determined at step 104. In the present embodiments, the SNR is calculated in SNR determinator 52.

[0040] When the SNR of the extracted PSCH code is determined, a comparison to the desired SNR is done at step 106. If, at step 108, it is determined that the SNR of the repeating code is less than the desired SNR, the method proceeds to step 110 to adjust the linearity of circuit elements the receiver circuit. After the linearity adjustment is made, the method returns to initial step 100. On the other hand, if the SNR of the repeating code is equal to or greater than the desired SNR, then no linearity adjustments are made, and the method loops back to step 100 where the next repeating code is received in the RF signal. In summary, the method continuously extracts the repeating code from the received signal, determines the SNR of the extracted repeating code, and compares it to the desired SNR to make any linearity adjustments. [0041] In an alternate embodiment, the method does not resume at step 100 until a predetermined delay has passed or until some triggering event has occurred. For example, the receiver can have a temperature sensor for monitoring the internal temperature of the wireless device. If the temperature changes by a preset amount, then a signal can be sent to initiate the method of Figure 8. In the circuit embodiment of Figure 3, the SNR extractor 46 can be configured to receive a control signal to enable extraction of the repeating code in response to the temperature change. [0042] Embodiments of the invention may be represented as circuits, or by code running on the baseband processor. [0043] From experimental simulations, a length of 4 PSCH filter provides acceptable noise and fading performance, but at the expense of capture time, which is about 2ms. Longer length PSCH filters can be used to further improve discrimination of individual fading paths. It has been discovered that a length of 2 PSCH filter is sufficient for achieving adequate SNR adjustment.

[0044] In the preceding description, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the embodiments of the invention. However, it will be apparent to one skilled in the art that these specific details are not required in order to practice the invention. In other instances, well-known electrical structures and circuits are shown in block diagram form in order not to obscure the invention. For example, specific details are not provided as to whether the embodiments of the invention described herein are implemented as a software routine, hardware circuit, firmware, or a combination thereof. [0045] Embodiments of the invention can be represented as a software product stored in a machine-readable medium (also referred to as a computer-readable medium, a processor-readable medium, or a computer usable medium having a computer- readable program code embodied therein). The machine-readable medium can be any suitable tangible medium, including magnetic, optical, or electrical storage medium including a diskette, compact disk read only memory (CD-ROM), memory device (volatile or non-volatile), or similar storage mechanism. The machine-readable medium can contain various sets of instructions, code sequences, configuration information, or other data, which, when executed, cause a processor to perform steps in a method according to an embodiment of the invention. Those of ordinary skill in the art will appreciate that other instructions and operations necessary to implement the described invention can also be stored on the machine-readable medium. Software running from the machine- readable medium can interface with circuitry to perform the described tasks. [0046] The above-described embodiments of the invention are intended to be examples only. Alterations, modifications and variations can be effected to the particular embodiments by those of skill in the art without departing from the scope of the invention, which is defined solely by the claims appended hereto.

Claims

WHAT IS CLAIMED IS:

1. A receive path for a transceiver comprising: down conversion circuitry for receiving a signal, including data and a repeated code, and for downconverting the signal to provide a downconverted signal; and, a signal to noise (SNR) corrector configured for determining an SNR of the repeated code and for adjusting linearity of at least one circuit element in the down conversion circuitry in response to the SNR of the repeated code being lower than a predetermined SNR.

2. The receive path of claim 1 , wherein the SNR corrector includes an SNR extractor for determining the SNR of the repeated code and providing a control signal indicating that the SNR of the repeated code is lower than the predetermined SNR, and an SNR adjuster for providing at least one preset adjustment code effective for adjusting linearity of the at least one circuit element in response to the control signal, the at least one circuit element configured to be responsive to the preset adjustment code.

3. The receive path of claim 2, wherein the SNR extractor includes, a code extractor configured to extract only the repeated code from the downconverted signal for providing extracted code, and an SNR determinator for determining the SNR of the extracted code and comparing the SNR of the extracted code to the predetermined SNR, the code extractor providing the control signal when the SNR of the extracted code is less than the predetermined SNR.

4. The receive path of claim 3, wherein the control signal corresponds to a magnitude of a difference between the SNR of the extracted code and the predetermined SNR.

5. The receive path of claim 2, wherein the SNR adjuster includes an optimizer for providing the at least one preset adjustment code in response to the control signal, and at least one digital to analog converter (DAC) for converting the at least one preset adjustment code to an analog signal that adjusts the linearity of the at least one circuit element.

6. The receive path of claim 5, wherein the at least one circuit element includes a mixer having adjustable IP2, and the at least one DAC includes an IP2 DAC for receiving the at least one preset adjustment code.

7. The receive path of claim 5, wherein the at least one circuit element includes a low noise amplifier (LNA) having adjustable IM3, and the at least one DAC includes an

IM3 DAC for receiving the at least one preset adjustment code.

8. The receive path of claim 5, wherein the at least one circuit element includes a mixer having adjustable IP2 and an LNA having adjustable IM3, and the at least one DAC includes an IP2 DAC for receiving a first preset adjustment code and an IM3 DC for receiving a second preset adjustment code.

9. The receive path of claim 3, wherein the code extractor includes at least one finite impulse response (FIR) filter having taps configured to have coefficients corresponding to the repeated code.

10. The receive path of claim 8, wherein the signal is a wideband code division multiple access (W-CDMA) compliant signal, and the repeated code is a primary synchronization channel (PSCH) code.

11. A method for adjusting the signal to noise ratio (SNR) in a receive path, comprising downconverting a signal containing data and a predetermined code for providing a downconverted signal; determining an SNR of the predetermined code; comparing the SNR of the predetermined code to a minimum SNR value to determine if an SNR adjustment is needed; and adjusting a linearity characteristic of at least one circuit element in the receive path if the SNR of the predetermined code is lower than the minimum SNR value.

12. The method of claim 11 , wherein the step of determining includes extracting a primary synchronization channel (PSCH) code from the signal, the signal being wideband code division multiple access (W-CDMA) compliant.

13. The method of claim 12, wherein the step of extracting the PSCH includes filtering the signal using at least one finite impulse response (FIR) filter having taps configured with coefficients corresponding to the PSCH code.

14. The method of claim 11 , wherein the step of comparing includes providing a magnitude of a difference between the SNR of the predetermined code and the minimum SNR value when the SNR of the predetermined code is lower than the minimum SNR value.

15. The method of claim 11 , wherein the at least one circuit element includes a mixer having adjustable IP2, and the step of adjusting includes sending a preset adjustment code to the mixer to adjust a linearity characteristic of the mixer.

16. The method of claim 11 , wherein the at least one circuit element includes a low noise amplifier (LNA) having adjustable IM3, and the step of adjusting includes sending a preset adjustment code to the LNA to adjust a linearity characteristic of the mixer.