WO2010024237A1 - Junction semiconductor device and method for manufacturing same - Google Patents

Junction semiconductor device and method for manufacturing same Download PDF

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Publication number
WO2010024237A1
WO2010024237A1 PCT/JP2009/064766 JP2009064766W WO2010024237A1 WO 2010024237 A1 WO2010024237 A1 WO 2010024237A1 JP 2009064766 W JP2009064766 W JP 2009064766W WO 2010024237 A1 WO2010024237 A1 WO 2010024237A1
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region
resistance layer
semiconductor device
conductivity type
high resistance
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PCT/JP2009/064766
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French (fr)
Japanese (ja)
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賢一 野中
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本田技研工業株式会社
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Priority to JP2010526710A priority Critical patent/JP5514726B2/en
Publication of WO2010024237A1 publication Critical patent/WO2010024237A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H01L29/8083—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H01L21/0465—Making n or p doped regions or layers, e.g. using diffusion using ion implantation using masks
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
    • H01L29/66901—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with a PN homojunction gate
    • H01L29/66909—Vertical transistors, e.g. tecnetrons
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/7722—Field effect transistors using static field induced regions, e.g. SIT, PBT

Definitions

  • the present invention relates to a junction type semiconductor device and a manufacturing method thereof, and in particular, a junction suitable for suppressing recombination between a main current flowing between main electrodes and a control current flowing through a control electrode and increasing a current amplification factor.
  • the present invention relates to a type semiconductor device and a method for manufacturing the same.
  • SiC Silicon carbide
  • the junction type SiC power device includes an electrostatic induction transistor (Static Induction Transistor, hereinafter referred to as “SIT”), a junction field effect transistor (Junction Field Effect Transistor, hereinafter referred to as “JFET”), or bipolar.
  • SIT Static Induction Transistor
  • JFET Junction Field Effect Transistor
  • BJT Bipolar Junction Transistor
  • SIT, JFET, and BJT are collectively referred to as “junction transistors”.
  • the SIT disclosed in Patent Document 1 includes, on the n + -type 4H—SiC (0001) plane substrate serving as a drain region, from the lower side, an n-type first high-resistance layer, a p-type channel doped layer, n A ⁇ type second high resistance layer and an n + type source region are stacked in this order.
  • the source region is separated and formed by etching in a predetermined planar pattern shape from the top surface to the source region and the middle of the second high resistance layer in the stacked structure.
  • the SIT has a plurality of source regions separated on the upper surface based on a predetermined pattern shape.
  • the SIT disclosed in Patent Document 1 has a structure in which the SiC surface in the SIT is covered with a surface recombination suppressing semiconductor layer between the source region and the gate region.
  • This surface recombination suppressing semiconductor layer has a function of suppressing recombination of electrons flowing out of the source region (n + type source region and n ⁇ type second high resistance layer) and holes flowing out of the gate region. is doing. As a result, recombination of electrons from the source region and holes from the gate region is suppressed, and an improvement in the current amplification factor of the junction type semiconductor layer device is achieved.
  • Non-Patent Document 1 there is one having a structure described in Non-Patent Document 1, for example.
  • BJT is stacked on the low resistance n + -type 4H-SiC (0001) plane 8 degree off substrate in the order of n ⁇ -type high resistance region, p-type base region, and n + -type emitter region from the bottom. It is formed.
  • the emitter region is composed of a number of elongated regions. In the emitter region, the base region (base contact region), and the collector region, electrodes for external electrical connection are formed.
  • FIG. 13 shows a cross-sectional structure diagram of the BJT disclosed in Non-Patent Document 1.
  • the BJT 500 surrounds the collector region 501, which is an n-type low resistance layer, the n-type high resistance region 502, the base region 503 of the p-type region, the emitter region 504 of n-type low resistance, and the emitter region.
  • the base contact region 505 of the p-type low resistance region is formed.
  • a collector electrode 506, a base electrode 507, and an emitter electrode 508 for electrical connection are joined to the outside of the collector region 501, the base region 503 (base contact region 505), and the emitter region. Further, the entire exposed surface other than the electrodes of the BJT 500 is covered with a surface protective film 509.
  • a control electrode called a gate or a base is formed by a pn junction.
  • main current Id the current flowing between the main electrodes
  • control current Ig the ratio of both currents (Id / Ig) is called “current amplification factor”.
  • recombination of holes flowing from the control electrode carrier of control current Ig
  • electrons flowing between the main electrodes carrier of main current Id
  • the value of the recombination current depends on the electron density, hole density, and recombination level density, and the higher the density, the larger the recombination current.
  • the SiC surface is known as a site where recombination is likely to occur.
  • various proposals have been made in the process of forming a protective film by oxidizing the SiC surface. This point is also described in Patent Document 1.
  • Patent Document 1 in order to reduce the recombination probability, a surface recombination suppressing semiconductor layer composed of a p-type region having a low concentration is provided on the SiC surface.
  • a potential barrier against electrons is formed on the SiC surface, so that the electron density on the SiC surface can be lowered.
  • the hole density can be kept low by forming a high resistance layer on the SiC surface in a p-type region having a low concentration.
  • a surface recombination suppressing semiconductor layer By forming such a surface recombination suppressing semiconductor layer, even if a recombination level exists on the SiC surface of the junction transistor, the recombination probability can be reduced and the current amplification factor of the junction transistor is increased. be able to.
  • junction transistor many attempts have been made to increase the current amplification factor by suppressing recombination on the SiC surface.
  • the recombination probability of electrons and holes is high also in the p-type gate region of SIT and the p-type base contact region of BJT.
  • the above problem will be described in terms of phenomena based on the structure example of SIT.
  • the p-type gate region is formed by a high energy and high concentration Al ion implantation step and a subsequent activation heat treatment step. Since many defects are generated in the crystal by high energy and high concentration Al ion implantation, the crystallinity is restored by activation heat treatment. However, crystallinity cannot be completely recovered, and defects remain in the vicinity of the p-type gate region. The defect acts as a recombination center of electrons and holes, and causes a decrease in current amplification factor.
  • the object of the present invention is to reduce the recombination probability of electrons and holes in the surrounding region such as the gate region of SIT or the base region of BJT, and between the main current flowing between the main electrodes and the control current flowing to the control electrode. It is an object of the present invention to provide a junction type semiconductor device and a method for manufacturing the same that can suppress recombination of the semiconductor layer, improve the current amplification factor, and improve the current density by miniaturization.
  • a junction type semiconductor device includes a first main electrode region (a first region corresponding to one main electrode) which is a substrate made of a silicon carbide (SiC) semiconductor crystal, and one of the substrates.
  • a second main electrode region formed on the side of the surface (a second region corresponding to the other main electrode), a high resistance layer formed between the first and second main electrode regions,
  • a control electrode region (a region corresponding to the control electrode) formed around the two main electrode regions, and a recombination suppression region formed so as to cover at least the side surface of the control electrode region. Characterized.
  • the first main electrode region is a drain region or a collector region
  • the second main electrode region is a source region or an emitter region.
  • the region is a gate region or a base region. Since the recombination suppression region is provided so as to cover at least a predetermined range of the side surface of the control electrode region such as the gate region, for example, an electron is present in a region where many recombination levels exist in the manufacturing process of the junction type semiconductor device. Is provided, and electrons flowing from the source region or the like can be kept away from the recombination suppression region.
  • the high resistance layer has a channel dope layer in contact with the control electrode region, and the recombination suppression region is formed to a depth position where the channel dope layer is formed.
  • the recombination suppressing region can be formed so as to cover the side surface and the bottom surface of the control electrode region.
  • the first main electrode region is a drain region made of a first conductive type low resistance layer
  • the second main electrode region is a first conductive type low resistance layer.
  • a source region composed of a resistive layer the control electrode region is a gate region of a second conductivity type
  • the recombination suppression region has the same second conductivity type as the gate region
  • the resistivity of the recombination suppression region Is higher than the resistivity of the gate region
  • the recombination suppression region has the same first conductivity type as the high resistance layer
  • the resistivity of the recombination suppression region is higher than that of the high resistance layer.
  • the first main electrode region is a drain region composed of a low resistance layer of the second conductivity type
  • the second main electrode region is a second conductivity type of low resistance.
  • the control electrode region is a gate region of the first conductivity type
  • the recombination suppression region has the same first conductivity type as the gate region
  • the resistivity of the recombination suppression region Is higher than the resistivity of the gate region, or the recombination suppression region has the same second conductivity type as the high resistance layer, and the resistivity of the recombination suppression region is higher than that of the high resistance layer.
  • the first main electrode region is a collector region made of a first conductivity type low-resistance layer
  • the second main electrode region is a first conductivity type low resistance layer.
  • the control electrode region is a second contact type base contact region
  • the recombination suppression region has the same second conductivity type as the base contact region
  • the recombination suppression region The resistivity is higher than the resistivity of the base contact region, or the recombination suppression region has the same first conductivity type as the high resistance layer, and the recombination suppression region has a higher resistivity than the high resistance layer.
  • the first main electrode region is a collector region made of a low resistance layer of the second conductivity type
  • the second main electrode region is a low conductivity type of the second conductivity type.
  • the control electrode region is a base contact region of the first conductivity type
  • the recombination suppression region has the same first conductivity type as the base contact region
  • the resistivity is higher than the resistivity of the base contact region, or the recombination suppression region has the same second conductivity type as the high resistance layer, and the recombination suppression region has a higher resistivity than the high resistance layer.
  • a method for manufacturing a junction type semiconductor device includes a first step of forming a high resistance layer on a substrate made of a silicon carbide semiconductor crystal and serving as a first main electrode region, and a high resistance layer.
  • a method for manufacturing a junction type semiconductor device includes a first step of forming a high resistance layer on a substrate made of a silicon carbide semiconductor crystal and serving as a first main electrode region, and a high resistance.
  • the recombination suppression region includes a fourth step of forming a control electrode region by ion implantation from the surface side of the recombination suppression region.
  • the impurity concentration implanted to form the recombination suppression region is lower than the impurity concentration implanted to form the control electrode region. It is characterized by.
  • a step for forming a channel dope layer in the high resistance layer is provided.
  • the substrate, the high resistance layer, and the low resistance layer are of a first conductivity type, and the control electrode region is of a second conductivity type.
  • the substrate, the high resistance layer, and the low resistance layer are of the second conductivity type, and the control electrode region is of the first conductivity type.
  • the first main electrode, the second main electrode, and the control are respectively provided in the first main electrode region, the second main electrode region, and the control electrode region.
  • the recombination suppression region is provided in contact with the gate region or the base region of the SiC semiconductor device so as to cover at least a side surface of the SiC semiconductor device within a predetermined range. Can be suppressed, and the current amplification factor can be improved. Further, in the junction type semiconductor device, even if miniaturization is performed, the current density of the main current can be improved.
  • the recombination suppression region that is in contact with the gate region or the base region of the SiC semiconductor device and can cover at least a side surface thereof in a predetermined range is formed in the depth direction. Therefore, the junction type semiconductor device having a high current amplification factor can be manufactured easily and reliably by suppressing the recombination between the gate and the source as described above.
  • 1 is a partial longitudinal sectional view of a junction type semiconductor device (SIT) according to a first embodiment of the present invention.
  • 1 is a plan view of a part of a junction type semiconductor device (SIT) according to a first embodiment. It is a fragmentary longitudinal cross-section explaining the problem of operation
  • junction type semiconductor device BJT
  • 4th Example of this invention It is a fragmentary longitudinal cross-sectional view of the junction type semiconductor device (BJT) by 4th Example of this invention. It is a fragmentary longitudinal cross-sectional view of the junction type semiconductor device (BJT) by 5th Example of this invention. It is a fragmentary longitudinal cross-section explaining the structure of the conventional junction type semiconductor device (BJT).
  • FIG. 1 is a partial longitudinal sectional view showing a unit structure of a junction type semiconductor device according to the first embodiment
  • FIG. 2 is a plan view of the junction type semiconductor device.
  • FIG. 1 shows a longitudinal sectional view of a portion including at least one source electrode in the cross section taken along the line AA in FIG.
  • This junction type semiconductor device shows an example of SIT (electrostatic induction transistor).
  • the SIT 10 includes, for example, five source electrodes 19 arranged in parallel in a specific unit region on the upper surface of the device.
  • the SIT 10 has a drain region 11 formed of an n-type low resistance layer (n + layer) formed on a lower surface portion having a SiC (silicon carbide) crystal, and the SiC crystal.
  • a source region 12 made of an n-type low resistance layer (n + layer) formed on the upper side surface portion is provided.
  • the layer forming the drain region 11 is a substrate.
  • a gate electrode 20 is formed around each of the plurality of source electrodes 19 so as to surround the source electrode 19 in the positional relationship of the plan view. This means that the source region 12 located below the source electrode 19 is surrounded by the p-type gate region 13 located below the gate electrode 20.
  • the gate region 13 is formed up to a predetermined deep position.
  • an n-type high resistance layer (n ⁇ layer) 14 is formed between the upper source region 12 and the lower drain region 11.
  • a p-type channel dope layer 15 is formed so as to be connected to the gate region 13.
  • n-type is “first conductivity type” and the “p-type” is “second conductivity type”.
  • a p-type recombination suppression region is preferably formed at a boundary region between the gate region 13 and the n-type high resistance layer 14, preferably up to a depth position exceeding the channel dope layer 15. 16 is provided.
  • the formation position of the recombination suppression region 16 in the depth direction can be appropriately set according to the purpose as described later.
  • the recombination suppression region 16 is provided all around the side surface of the gate region 13.
  • the recombination suppression region 16 is formed of a p ⁇ semiconductor having a higher resistivity than that of the gate region 13 or an n ⁇ semiconductor having a higher resistivity than that of the high resistance layer 14.
  • the drain electrode 18 is joined to the lower surface of the drain region 11
  • the source electrode 19 is joined to the upper surface of the source region 12, and the upper side of the gate region 13.
  • a gate electrode 20 is bonded to the surface.
  • the exposed surface between the source electrode 19 and the gate electrode 20 is covered and protected by the surface protective film 17.
  • an upper layer electrode 21 is provided on the upper side of each of the source electrode 19 and the gate electrode 20. In FIG. 1, the upper layer electrode 21 is not shown.
  • the main current is an electron flow that flows from the source region 12 (or the source electrode 19) to the drain region 11 (or the drain electrode 18).
  • Energization (ON) and non-energization (OFF) of the main current are controlled based on a gate voltage applied to the gate electrode 20, that is, a control signal applied between the gate region 13 and the source region 12.
  • the applied voltage between the gate and the source is 0 V or less
  • the main current does not flow through the SIT 10 and it is turned off.
  • a voltage of a certain level or higher is applied between the gate and the source, the main current flows through the SIT 10 and shifts to the on state. In the on state, the pn junction formed between the gate region 13 and the source region 12 is forward-biased, and a hole current that is a control current flows through the source region 12 in the gate region 13.
  • SIT 10 the characteristic structure of SIT 10 will be described while comparing the conventional SIT structure and the SIT structure according to the present embodiment.
  • FIG. 3 the same elements as those described in FIG. 1 are given the same reference numerals.
  • a region 31 having a large number of recombination levels 31a is formed around the gate region 13.
  • the holes 32 flowing from the gate region 13 and the electrons 33 flowing from the source region 12 coexist. Therefore, in the region 31, recombination of electrons 33 and holes 32 occurs actively, an invalid gate current that does not contribute to the operation of the SIT 10A flows, and the current amplification factor of the SIT 10A decreases.
  • I1 is a main current.
  • the recombination suppression region 16 is formed at the boundary with the n-type high resistance layer 14 around the side surface of the gate region 13. Yes.
  • the recombination suppression region 16 is formed, for example, by performing ion implantation on the main portion of the region 31 where many recombination levels 31a exist.
  • the recombination suppression region 16 is the same conductivity type as the gate region 13 and is a p - semiconductor having a higher resistivity than the gate region 13 or the same conductivity type as the high resistance layer 14 and a higher resistivity than the high resistance layer 14. N ⁇ semiconductor. Since the recombination suppression region 16 is designed to have a high resistance, the density of holes is low when “p ⁇ ”, and the density of electrons is low when “n ⁇ ”.
  • the implantation concentration is extremely low compared to the ion implantation for forming the gate region 13, and the energy required for the ion implantation is also low. Therefore, in the ion implantation for forming the recombination suppression region 16, the density of recombination levels can be suppressed low.
  • the SIT 10 is designed with a target of a blocking voltage of 600V, for example.
  • a low resistance n-type 4H—SiC substrate turned off by 8 degrees from the (0001) plane is used as the substrate portion.
  • the substrate portion becomes the drain region 11.
  • the high resistance layer 14 on the substrate is a layer for preventing a high voltage applied between the source and the drain.
  • the high resistance layer 14 is set to have a thickness of 10 ⁇ m and an impurity concentration of 1 ⁇ 10 16 cm ⁇ 3 , for example, so as to block a voltage of 600 V or higher.
  • the p-type channel dope layer 15 has a thickness of 0.1 to 0.5 ⁇ m and an impurity concentration of 4 ⁇ 10 17 to 2 ⁇ 10 18 cm ⁇ 3 .
  • a high resistance layer 14 having a thickness of 0.1 to 0.4 ⁇ m and an impurity concentration of 5 ⁇ 10 15 cm ⁇ 3 to 5 ⁇ 10 17 cm ⁇ 3 is sandwiched, and a thickness of 0.5 to A low-resistance n-type source region 12 having 2.0 ⁇ m and an impurity concentration of 1 to 5 ⁇ 10 19 cm ⁇ 3 is provided.
  • a low resistance gate region 13 having a thickness of 1 to 2 ⁇ m and an impurity concentration of about 1 ⁇ 10 18 to 1 ⁇ 10 19 cm ⁇ 3 is provided around the source region 12.
  • the planar shape of the source region 12 is an elongated island shape.
  • One SIT 10 includes a plurality of source regions 12. The size of one source region 12 is about 3 to 10 ⁇ m in width and about 100 to 1000 ⁇ m in length. The period of the unit structure including the gate region 13 and the source region 12 is about 10 to 30 ⁇ m.
  • FIG. 5 shows a flowchart of the manufacturing method.
  • 6A and 6B show a semiconductor device manufactured in each step.
  • the manufacturing method of SIT10 consists of the following processes (1) to (11) (steps S11 to S21). As shown in FIG. 5, the process is executed in the order from step S11 to step S21.
  • step S11 High resistance layer forming process
  • step S12 Channel dope layer forming process
  • step S13 High resistance layer formation process
  • step S14 Low resistance layer formation process
  • Source etching process step S15
  • gate region formation process step 16
  • Recombination suppression region formation process step S17
  • Ion implantation layer activation process step S18
  • step S19 Surface protective film formation process
  • Electrode formation process step S20) (11) Upper layer electrode formation process (step S21)
  • FIG. 6A (a) is formed by performing the above steps S11 to S14.
  • step S11 a high resistance in which nitrogen having a thickness of 10 ⁇ m and a concentration of 1 ⁇ 10 16 cm ⁇ 3 is doped as an impurity on an n-type substrate 40 formed of SiC by an epitaxial growth method. Layer 41 is grown. “4H—SiC (0001) 8 ° off” is used for the substrate 40. The substrate 40 becomes the drain region 11 of the n-type low resistance layer described above.
  • step S12 aluminum (Al) as an impurity is formed on the n-type high resistance layer 41 by an epitaxial growth method at a concentration of 4 ⁇ 10 17 to 2 ⁇ 10 18 cm ⁇ 3.
  • a p-type channel dope layer 42 of about 0.5 ⁇ m is grown.
  • step S13 nitrogen having a thickness of 0.1 to 0.4 ⁇ m and a concentration of 5 ⁇ 10 15 to 5 ⁇ 10 17 cm ⁇ 3 is then formed on the channel dope layer 42 by an epitaxial growth method. An n-type high-resistance layer 43 doped with impurities is grown.
  • step S14 nitrogen is doped on the n-type high resistance layer 43 by an epitaxial growth method with a thickness of 0.5 to 2.0 ⁇ m and a concentration of 1 to 5 ⁇ 10 19 cm ⁇ 3.
  • An n-type low resistance layer 44 doped as follows is grown.
  • the low resistance layer 44 forms the source region 12 described above.
  • step S15 in the structure shown in FIG. 6A (a), a silicon oxide film 51 is deposited on the upper surface by CVD, photolithography is performed, and then silicon oxide is oxidized by RIE. The film 51 is etched. Thus, a mask is formed. Thereafter, using this silicon oxide film 51, SiC etching of the low resistance layer 44 is performed by RIE, thereby forming the source region 12. SF 6 gas or the like is used for RIE of SiC etching. The resulting structure is shown in FIG. 6A (b). The etching depth is, for example, about 0.5 to 2.3 ⁇ m.
  • the mask 52 is formed so that the surface portion for forming the gate region 13 is further exposed.
  • the mask 52 is formed by depositing a silicon oxide film by a CVD method, performing photolithography, and then etching the silicon oxide film by RIE. Thereafter, the gate region 13 is formed by ion implantation.
  • the ions to be implanted are aluminum (Al), and the depth of implantation is, for example, 1 to 2 ⁇ m.
  • the ion implantation amount is 1 ⁇ 10 18 to 1 ⁇ 10 19 cm ⁇ 3 , and the energy required for ion implantation is 700 KeV to 2 MeV or more.
  • a mask for forming the recombination suppression region 16 is formed as shown in FIG. 6D (d).
  • a mask 53 silicon oxide film
  • isotropic etching such as wet etching is used to remove only the portion for forming the recombination suppression region.
  • ion implantation of aluminum (Al) as an impurity (ion species) is performed.
  • the region to be implanted is wider than the gate region 13 and narrower than the gate-source distance.
  • the recombination suppression region 16 may be formed from the gate surface to the deepest depth of the gate region.
  • the ion implantation amount is about 5 ⁇ 10 15 to 5 ⁇ 10 17 cm ⁇ 3 , and is preferably about the same as that of the n ⁇ -type high resistance layers 41 and 43.
  • the energy required for ion implantation is, for example, about 400 KeV, but is determined according to the implantation depth. In this way, the recombination suppression region 16 is formed at a required depth all around the side surface of the gate region 13. In consideration of the planar shape shown in FIG. 2, the recombination suppression region 16 is formed so as to cover the entire periphery of the side surface of the gate region 13.
  • the recombination suppression region 16 which is a p-type region does not have a function as a gate and is intended to reduce the density of holes and electrons in a region where a large number of recombination levels exist. Therefore, both the implantation amount and the implantation energy are set to be smaller than the ion implantation at the time of forming the gate region. As a result, damage to the crystal due to ion implantation can be kept low, and adverse effects on the device characteristics of the SIT due to the manufacturing process can be suppressed.
  • step S16 and S17 the main parts are conceptually shown in more detail as shown in (a) to (c) of FIG. In FIG. 7, only the gate region 13 and the recombination suppression region 16 are shown, and the source region and the channel dope region are omitted.
  • FIG. 7A shows a process of implanting ions (Al + ) 61 to form the gate region 13
  • FIG. 7B shows a mask 62 for forming a recombination suppression region around the side surface of the gate region 13.
  • a process for forming the oxide film by wet etching is shown
  • (c) shows a process for implanting ions (Al + ) 61 in order to form the recombination suppression region 16.
  • Al ions 61 are selectively implanted into the SiC 63 to form the gate region 13 using the mask 62 formed of a silicon oxide film or the like, and then the mask 62 is just the SiC surface of the recombination suppression region 16. Etching is performed so that is exposed. The width of the SiC surface newly exposed by etching is, for example, 0.5 ⁇ m. Al ions are again implanted into the SiC 63 in order to form the recombination suppression region 16 using the mask 62 after the etching. In FIG. 7C, the depth of the recombination suppression region 16 is represented by d.
  • FIG. 8 In addition to the process of forming the gate region 13 and the recombination suppression region 16, there is a formation method as shown in FIG. In FIG. 8, only the gate region 13 and the recombination suppression region 16 are shown, and the source region and the channel dope region are omitted.
  • a mask 62 is formed so that ion implantation 61 for forming a recombination suppression region can be performed, and ion implantation 61 for forming the recombination suppression region 16 is performed (FIG. 8A). ).
  • an oxide film 64 is deposited on the entire surface by CVD (FIG. 8B).
  • the oxide film 64 formed on the surface is etched by anisotropic etching to expose the surface 65 that forms the gate region (FIG. 8C).
  • the surface 65 is the upper surface of the recombination suppression region 16 described above.
  • ion implantation 61 for forming the gate region 13 is performed on the exposed surface 65 (FIG. 8D).
  • the gate region 13 is formed.
  • the recombination suppression region 16 is formed around the side surface of the gate region 13 with a depth d from the surface of the gate region 13. This method is also a self-alignment process, and no positional deviation occurs between the gate region 13 and the recombination suppression region 16.
  • a mask may be formed for each using a photo process. This method is particularly effective when the width of the recombination suppression region is widened to about 1 ⁇ m or more.
  • the depth d is desired to be approximately the same as the depth of the gate region.
  • SiC an ion implantation method is used as a method for forming the recombination suppression region 16, but high energy is required to implant ions into a deep portion, and ion implantation with high energy is a new method. A defect will be generated. Therefore, it is desirable that the depth d is shallow from the viewpoint of not generating new defects. In determining the depth d in this way, it is necessary to consider the conflicting phenomenon of forming the recombination suppression region 16 over as wide a range as possible and minimizing the formation of new defects. There is.
  • the region near the channel dope layer 15 from the SiC surface is a region where both the electron density and the hole density are high.
  • the depth d of the recombination suppression region 16 reaches the channel dope layer at least.
  • the depth d is about 0.1 to 0.3 ⁇ m, and even if it is formed by ion implantation, it is possible to minimize the generation of new defects with low energy.
  • the upper limit of the depth d is about the same as the depth of the gate region 13, but this value is determined when forming the depth of the gate region 13 of an individual device and the recombination suppression region 16 of that depth. This is determined in consideration of a new defect density generated by ion implantation energy.
  • the p ⁇ recombination suppression region 16 is required to have a low hole concentration while suppressing entry of electrons into the recombination suppression region 16 by forming a pn junction with the high resistance layer. For this reason, the impurity concentration in the recombination suppression region 16 is appropriately the same as or slightly higher than that of the high resistance layer.
  • the impurity concentration of the high resistance layer 14 is about 5 ⁇ 10 15 to 5 ⁇ 10 17 cm ⁇ 3
  • the appropriate value of the impurity concentration of the recombination suppression region 16 is 5 ⁇ 10 15 to 5 ⁇ 10 17 cm ⁇ 3 or slightly higher than this.
  • the recombination suppression region 16 may be formed of an n ⁇ region having a higher resistivity than the high resistance layer 14. In that case, the electron concentration in the recombination suppression region 16 becomes low, and the junction potential of the pn junction formed between the gate region 13 and the recombination suppression region 16 becomes a potential barrier against holes, and The flow into the region 31 is suppressed. As a result, recombination in the region 31 is suppressed.
  • the implanted impurity concentration is appropriately the same as or slightly lower than that of the high resistance layer 14, and ions are implanted from the n type impurity concentration in the high resistance layer 14.
  • the value obtained by subtracting the p-type impurity concentration is the substantial impurity concentration in the recombination suppression region.
  • a value slightly lower than 5 ⁇ 10 15 to 5 ⁇ 10 17 cm ⁇ 3 is an appropriate value of the impurity concentration.
  • step S18 In the process of activating the ion-implanted layer (step S18), after the ion implantation, the implanted ions are electrically activated in the semiconductor and a heat treatment is performed to eliminate crystal defects generated by the ion implantation (FIG. 6B ( e)).
  • a heat treatment is performed to eliminate crystal defects generated by the ion implantation (FIG. 6B ( e)).
  • both the implanted ions in the gate region 13 and the implanted ions in the recombination suppression region 16 are activated at the same time.
  • heat treatment is performed at a high temperature of about 1700 to 1800 ° C. for about 10 minutes.
  • argon gas (Ar) is used as the atmospheric gas.
  • step S19 In the process of forming the surface protective film (step S19), as shown in FIG. 6B (f), first, in order to remove the surface layer generated in the ion implantation step and the activation step, the oxide film is removed after the thermal oxidation. Perform sacrificial oxidation.
  • the oxidation condition is, for example, 1100 ° C. for 20 hours in dry oxygen. Hydrogen fluoride is used to remove the oxide film.
  • thermal oxidation is performed again to form an oxide film 54.
  • the thermal oxide film formation conditions are, for example, a temperature of 1100 ° C., a time of 5 hours, and an atmosphere of wet.
  • POA Post Oxidation Anneal
  • heat treatment is performed to reduce the impurity level at the interface of the SiC oxide film.
  • POA is performed in a hydrogen, nitrogen oxide (NO, N 2 O) or argon atmosphere at a high temperature of about 800 to 1300 ° C. for about 10 to 30 minutes.
  • a CVD oxide film or a CVD nitride film is formed.
  • the source electrode 19, the gate electrode 20, and the drain electrode 18 are formed on the surfaces of the source region 12 (low resistance layer 44), the gate region 13, and the drain region 11 (substrate 40). (FIG. 6B (g)).
  • the source electrode 19 and the drain electrode 18 are made of nickel or titanium, and the gate electrode 20 is made of a titanium / aluminum laminated film.
  • Each electrode 18, 19, 20 is formed by vapor deposition or sputtering.
  • dry etching, wet etching, lift-off method or the like is used.
  • heat treatment is performed to reduce the contact resistance between the metal portion and the semiconductor portion.
  • the heat treatment conditions are a temperature condition of 800 to 1000 ° C. and a time condition of about 10 to 30 minutes.
  • the upper layer electrode formation process (step S21) is executed.
  • an upper layer wiring 56 for taking out the plurality of separated source electrodes 19 to one electrode is formed (FIG. 6B (h)).
  • the silicon oxide film or the like in the portion of the source electrode 19 is removed by photolithography and etching.
  • the upper layer electrode 56 is deposited.
  • aluminum (Al) is used as the material of the upper layer electrode 56.
  • the SIT 10 shown in FIGS. 1 and 2 is manufactured.
  • the SIT 10 is a high-performance junction type semiconductor device having normally-off characteristics.
  • the combinations of the first and second conductivity types such as the drain region, the source region, the high resistance layer, the gate region, and the recombination suppression region may be reversed. This also applies to the embodiments described below.
  • junction type semiconductor device is also SIT. 9, elements that are substantially the same as those described in FIG. 1 are denoted by the same reference numerals.
  • the SIT 100 according to the second embodiment is characterized in that the recombination suppression region 71 formed on the side surface of the gate region 13 is formed at a position shallower than the portion where the channel dope layer 15 is formed. Other configurations are the same as those described in the first embodiment.
  • the configuration of SIT100 has the following advantages. Since the recombination suppression region 71 is formed by ion implantation, although it is a small amount, damage occurs during ion implantation. This damage is not completely eliminated by the subsequent activation heat treatment. In order to improve this, it is effective to reduce the energy for ion implantation and to form a recombination suppression region 71 with less damage and higher quality during ion implantation. The recombination of holes and electrons occurs violently in a region shallower than the channel dope layer 15 where current tends to concentrate. Therefore, even if the recombination suppression region 71 is formed only in the region, the effect of the present invention is sufficiently obtained. Can be achieved.
  • the configuration of the second embodiment is particularly effective when the thickness of the second high resistance layer 14 located on the upper side of the device structure of the SIT 100 is large.
  • junction type semiconductor device is SIT. 10, elements that are substantially the same as those described in FIG. 1 are denoted by the same reference numerals.
  • the recombination suppressing region 72 is formed so as to cover the entire region that forms the boundary portion between the side surface and the bottom surface portion of the gate region 13, that is, the other portion of the gate region 13.
  • Other configurations are the same as those described in the first embodiment.
  • the manufacturing method of the SIT 200 can be realized by applying the manufacturing method shown in FIG. That is, the SIT 200 having the structure shown in FIG. 10 can be manufactured by forming the recombination suppression region 16 deeper than the depth of the gate region 13 in the manufacturing method shown in FIG. Although the implantation energy for ion implantation for forming the recombination suppression region 16 is high, the ion implantation amount in the recombination suppression region 16 is much less than the ion implantation amount in the gate region 13, thereby reducing damage to the crystal. be able to.
  • the configuration of the third embodiment is more effective when the gate region 13 is shallow.
  • the junction type semiconductor device according to the fourth embodiment shows an example of BJT (bipolar junction transistor).
  • the BJT 300 includes a collector region 311, an emitter region 312, a base contact region 313, upper and lower high resistance layers 314, and a base region 315.
  • the base region 315 of the BJT 300 corresponds to the aforementioned channel dope layer of SIT. Further, a collector electrode 321, an emitter electrode 322, and a base electrode 323 are joined to the collector region 311, the emitter region 312, and the base contact region 313, respectively.
  • the base contact region 313 corresponds to the gate region 13 of the SIT 10 described above and is supplied with a control signal.
  • a surface protective film 316 is provided on the exposed surface between the emitter electrode 322 and the base electrode 323 on the device surface of the BJT 300. Also in the BJT 300 according to the present embodiment, the entire peripheral surface of the side surface and the bottom surface of the base contact region 313 is covered with the recombination suppression region 317.
  • a fifth embodiment of the junction type semiconductor device according to the present invention will be described with reference to FIG.
  • the junction type semiconductor device according to the fifth embodiment also shows an example of BJT as in the fourth embodiment. 12, the same elements as those described in FIG. 11 are denoted by the same reference numerals, and the description thereof is omitted.
  • the BJT 400 according to the fifth embodiment is characterized in that the recombination suppression region 411 is formed in the range around the side surface of the base contact region 313 and above the base region 315.
  • the present invention is provided with the recombination suppression region on the side surface of the gate region or the base contact region. For this reason, for example, recombination of minority carriers injected from the gate region and majority carriers injected from the source region is suppressed, the current amplification factor of the junction semiconductor device can be improved, and the on-voltage (resistance) can be reduced.
  • a reverse polarity type in which the polarities of p and n in the description of the process of the manufacturing method are reversed may be used.
  • SiC an example of SiC has been described, but the present invention can also be applied to other semiconductors in which recombination is a problem.
  • the present invention can be used for manufacturing a high performance junction type semiconductor device.

Abstract

Disclosed is a junction semiconductor device which achieves an increase in current amplification factor.  The junction semiconductor device comprises a recombination suppressing region (16) formed so as to cover at least the side surfaces of a gate region (13). The recombination suppressing region (16) is formed by a p- semiconductor having a resistivity higher than that of the gate region (13) or an n- semiconductor having a resistivity higher than that of a high resistive layer (14). Thus, the probability of recombination of electrons and holes in the region around the gate region or the like is reduced, and the recombination of the principal current flowing between the main electrodes and the control current flowing in the control electrode is suppressed, thereby enabling both an increase in the current amplification factor and an increase in the current density due to miniaturization.

Description

接合型半導体装置およびその製造方法Junction type semiconductor device and manufacturing method thereof
　本発明は、接合型半導体装置およびその製造方法に関し、特に、主電極間に流れる主電流と制御電極に流れる制御電流との間の再結合を抑制し、電流増幅率を高めるのに適した接合型半導体装置およびその製造方法に関する。 The present invention relates to a junction type semiconductor device and a manufacturing method thereof, and in particular, a junction suitable for suppressing recombination between a main current flowing between main electrodes and a control current flowing through a control electrode and increasing a current amplification factor. The present invention relates to a type semiconductor device and a method for manufacturing the same.
　炭化珪素（シリコン・カーバイド（Silicon Carbide）、以下では「ＳｉＣ」と記す。）は、広く半導体装置に応用されているシリコンと比べて、バンドギャップエネルギーが大きいという特性を有する。そのためＳｉＣを利用した半導体装置は、高電圧、大電力、高温動作の条件に適しており、パワーデバイスなどへの適用が期待されている。現在、研究開発されているＳｉＣパワーデバイスの構造は、主に、「ＭＯＳ型」と「接合型」の２つの型に分類されている。 Silicon carbide (Silicon Carbide, hereinafter referred to as “SiC”) has a characteristic that its band gap energy is larger than silicon that is widely applied to semiconductor devices. Therefore, a semiconductor device using SiC is suitable for high voltage, high power, and high temperature operation conditions, and is expected to be applied to power devices and the like. The structures of SiC power devices currently being researched and developed are mainly classified into two types, “MOS type” and “junction type”.
　ここでは接合型ＳｉＣパワーデバイスの性能向上という観点で説明する。接合型ＳｉＣパワーデバイスには、静電誘導トランジスタ（Static Induction Transistor、以下では「ＳＩＴ」と記す。）や接合型電界効果トランジスタ（Junction Field Effect Transistor、以下では「ＪＦＥＴ」と記す。)、あるいはバイポーラ接合トランジスタ（Bipolar Junction Transistor、以下では「ＢＪＴ」と記す。）などがある。なお以下において、ＳＩＴ、ＪＦＥＴ、ＢＪＴは、総称して、「接合型トランジスタ」と呼ぶこととする。 Here, it demonstrates from a viewpoint of the performance improvement of a junction type SiC power device. The junction type SiC power device includes an electrostatic induction transistor (Static Induction Transistor, hereinafter referred to as “SIT”), a junction field effect transistor (Junction Field Effect Transistor, hereinafter referred to as “JFET”), or bipolar. A junction transistor (Bipolar Junction Transistor, hereinafter referred to as “BJT”). In the following, SIT, JFET, and BJT are collectively referred to as “junction transistors”.
　従来のＳＩＴの例としては、例えば特許文献１に開示された構造を有するものが知られている。特許文献１に開示されたＳＩＴは、ドレイン領域となるｎ＋型４Ｈ－ＳｉＣ（０００１）面基板上に、下側から、ｎ型の第１の高抵抗層、ｐ型のチャネルドープ層、ｎ－型の第２の高抵抗層、ｎ＋型のソース領域の順序で積層された構造をしている。当該ＳＩＴで、そのソース領域は、当該積層構造において上面からソース領域、および第２の高抵抗層の途中まで所定の平面パターン形状でエッチングされることにより、分離されて形成される。当該ＳＩＴは、その上面に、所定のパターン形状に基づいて分離された複数のソース領域を有している。分離された複数のソース領域の間の領域には、その後にＡｌイオン注入の工程が実行され、ｐ型のゲート領域が形成される。従って、分離された複数のソース領域の各々は、ＳＩＴの平面形状で見てみると、その周囲をゲート領域で囲まれている。特許文献１に開示されるＳＩＴは、ソース領域とゲート領域との間において、当該ＳＩＴにおけるＳｉＣ表面を表面再結合抑制半導体層で覆うようにした構造を有している。この表面再結合抑制半導体層は、ソース領域（ｎ＋型のソース領域とｎ－型の第２の高抵抗層）から流れ出る電子とゲート領域から流れ出る正孔との再結合を抑制する機能を有している。これにより、ソース領域からの電子とゲート領域からの正孔の再結合を抑え、接合型半導体層装置の電流増幅率の向上を達成している。 As an example of a conventional SIT, for example, one having a structure disclosed in Patent Document 1 is known. The SIT disclosed in Patent Document 1 includes, on the n + -type 4H—SiC (0001) plane substrate serving as a drain region, from the lower side, an n-type first high-resistance layer, a p-type channel doped layer, n A − type second high resistance layer and an n + type source region are stacked in this order. In the SIT, the source region is separated and formed by etching in a predetermined planar pattern shape from the top surface to the source region and the middle of the second high resistance layer in the stacked structure. The SIT has a plurality of source regions separated on the upper surface based on a predetermined pattern shape. In the region between the plurality of separated source regions, an Al ion implantation process is subsequently performed to form a p-type gate region. Accordingly, each of the plurality of separated source regions is surrounded by the gate region when viewed in the planar shape of the SIT. The SIT disclosed in Patent Document 1 has a structure in which the SiC surface in the SIT is covered with a surface recombination suppressing semiconductor layer between the source region and the gate region. This surface recombination suppressing semiconductor layer has a function of suppressing recombination of electrons flowing out of the source region (n + type source region and n − type second high resistance layer) and holes flowing out of the gate region. is doing. As a result, recombination of electrons from the source region and holes from the gate region is suppressed, and an improvement in the current amplification factor of the junction type semiconductor layer device is achieved.
　また、従来のＢＪＴの例として例えば非特許文献１に記載された構造を有するものがある。ＢＪＴは、低抵抗のｎ＋型４Ｈ－ＳｉＣ（０００１）面８度オフ基板上に、下側から、ｎ－型高抵抗領域、ｐ型ベース領域、ｎ＋型エミッタ領域の順序に積層されて形成される。エミッタ領域は、多数の細長い形状の領域からなっている。エミッタ領域、ベース領域（ベースコンタクト領域）、コレクタ領域には外部に電気的接続を取るための電極が形成されている。 Further, as an example of a conventional BJT, there is one having a structure described in Non-Patent Document 1, for example. BJT is stacked on the low resistance n + -type 4H-SiC (0001) plane 8 degree off substrate in the order of n − -type high resistance region, p-type base region, and n + -type emitter region from the bottom. It is formed. The emitter region is composed of a number of elongated regions. In the emitter region, the base region (base contact region), and the collector region, electrodes for external electrical connection are formed.
　図１３に非特許文献１に開示されたＢＪＴの断面構造図を示す。図１３に示すように、ＢＪＴ５００は、ｎ型低抵抗層であるコレクタ領域５０１、ｎ型高抵抗領域５０２、ｐ型領域のベース領域５０３、ｎ型低抵抗のエミッタ領域５０４、エミッタ領域を囲むように形成されたｐ型低抵抗領域のベースコンタクト領域５０５を備えている。コレクタ領域５０１とベース領域５０３（ベースコンタクト領域５０５）とエミッタ領域のそれぞれの外部には、電気的接続をとるためのコレクタ電極５０６、ベース電極５０７、エミッタ電極５０８が接合されている。さらにＢＪＴ５００の電極以外の露出表面の全体は表面保護膜５０９で覆われている。 FIG. 13 shows a cross-sectional structure diagram of the BJT disclosed in Non-Patent Document 1. As shown in FIG. 13, the BJT 500 surrounds the collector region 501, which is an n-type low resistance layer, the n-type high resistance region 502, the base region 503 of the p-type region, the emitter region 504 of n-type low resistance, and the emitter region. The base contact region 505 of the p-type low resistance region is formed. A collector electrode 506, a base electrode 507, and an emitter electrode 508 for electrical connection are joined to the outside of the collector region 501, the base region 503 (base contact region 505), and the emitter region. Further, the entire exposed surface other than the electrodes of the BJT 500 is covered with a surface protective film 509.
特開２００６－２６９６８１号公報JP 2006-269682 A
　ＳＩＴやＢＪＴ等の接合型トランジスタでは、ゲートあるいはベースと呼ばれる制御電極がｐｎ接合で形成されている。ソースとドレインの間、あるいはエミッタとコレクタの間のような主電極の間に電流を流すためには、当該制御電極に電流を流す必要がある。主電極の間に流れる電流を「主電流Ｉｄ」、制御電極に流れる電流を「制御電流Ｉｇ」とするとき、両電流の比（Ｉｄ／Ｉｇ）は「電流増幅率」と呼ばれる。接合型トランジスタの開発では、電流増幅率の値を大きくすることが重要な課題となっている。 In a junction type transistor such as SIT or BJT, a control electrode called a gate or a base is formed by a pn junction. In order to pass a current between main electrodes such as between a source and a drain or between an emitter and a collector, it is necessary to pass a current through the control electrode. When the current flowing between the main electrodes is “main current Id” and the current flowing through the control electrode is “control current Ig”, the ratio of both currents (Id / Ig) is called “current amplification factor”. In the development of junction transistors, increasing the value of the current amplification factor is an important issue.
　上記電流増幅率を低下させる要因としては、制御電極から流れ込む正孔（制御電流Ｉｇのキャリア）と主電極間を流れる電子（主電流Ｉｄのキャリア）との再結合を挙げることができる。再結合電流の値は、電子密度、正孔密度、再結合準位密度に依存し、それぞれの密度が高いほど再結合電流も大きくなる。 As a factor for reducing the current amplification factor, recombination of holes flowing from the control electrode (carrier of control current Ig) and electrons flowing between the main electrodes (carrier of main current Id) can be mentioned. The value of the recombination current depends on the electron density, hole density, and recombination level density, and the higher the density, the larger the recombination current.
　再結合が発生しやすい部位としてはＳｉＣ表面が知られている。ＳｉＣ表面の再結合準位の密度を低減するために、ＳｉＣ表面を酸化して保護膜を形成するプロセスで各種の工夫をなすことが提案されている。この点は特許文献１にも記載されている。さらに特許文献１では、再結合確率を下げるために、ＳｉＣ表面に、濃度の低いｐ型領域からなる表面再結合抑制半導体層を設けるようにしている。このような表面再結合抑制半導体層を形成すると、ＳｉＣ表面に電子に対する電位障壁が形成されるので、ＳｉＣ表面での電子密度を下げることができる。さらに、濃度の低いｐ型領域でＳｉＣ表面に高抵抗層を形成することにより、正孔の密度も低く抑えることができる。かかる表面再結合抑制半導体層を形成することにより、接合型トランジスタのＳｉＣ表面に再結合準位が存在したとしても、再結合確率を低減することができ、接合型トランジスタの電流増幅率を大きくすることができる。 The SiC surface is known as a site where recombination is likely to occur. In order to reduce the density of recombination levels on the SiC surface, various proposals have been made in the process of forming a protective film by oxidizing the SiC surface. This point is also described in Patent Document 1. Further, in Patent Document 1, in order to reduce the recombination probability, a surface recombination suppressing semiconductor layer composed of a p-type region having a low concentration is provided on the SiC surface. When such a surface recombination-inhibiting semiconductor layer is formed, a potential barrier against electrons is formed on the SiC surface, so that the electron density on the SiC surface can be lowered. Furthermore, the hole density can be kept low by forming a high resistance layer on the SiC surface in a p-type region having a low concentration. By forming such a surface recombination suppressing semiconductor layer, even if a recombination level exists on the SiC surface of the junction transistor, the recombination probability can be reduced and the current amplification factor of the junction transistor is increased. be able to.
　以上のように接合型トランジスタにおいて、ＳｉＣ表面での再結合を抑制して電流増幅率を大きくする試みが多くなされている。しかしながら、ＳＩＴのｐ型ゲート領域やＢＪＴのｐ型ベースコンタクト領域でも電子と正孔の再結合確率が高いことが知られている。ところが、従来の接合型トランジスタの開発では、当該領域での再結合を抑制する試みは見当たらない。 As described above, in the junction transistor, many attempts have been made to increase the current amplification factor by suppressing recombination on the SiC surface. However, it is known that the recombination probability of electrons and holes is high also in the p-type gate region of SIT and the p-type base contact region of BJT. However, in the development of a conventional junction transistor, there is no attempt to suppress recombination in this region.
　ここで上記の問題を、ＳＩＴの構造例に基づいて現象的な面で説明する。典型的なＳＩＴの断面構造において、ｐ型ゲート領域は、高エネルギかつ高濃度のＡｌイオン注入工程と、その後の活性化熱処理工程とによって形成される。高エネルギかつ高濃度のＡｌイオン注入によって結晶中に多くの欠陥が発生するため、活性化熱処理により結晶性の回復を図る。しかしながら、結晶性は完全に回復することはできず、ｐ型ゲート領域近辺に欠陥が残ることになる。当該欠陥が、電子と正孔の再結合中心として働き、電流増幅率を低下させる原因となる。当該再結合を抑制するため、ゲート領域とソース領域の間の距離を大きくし、電子を遠ざける手法が考えられる。しかし、当該手法は、接合型トランジスタを微細化するという設計思想に反するため、電流増幅率の向上と微細化による電流密度の向上とが両立することができない。 Here, the above problem will be described in terms of phenomena based on the structure example of SIT. In a typical SIT cross-sectional structure, the p-type gate region is formed by a high energy and high concentration Al ion implantation step and a subsequent activation heat treatment step. Since many defects are generated in the crystal by high energy and high concentration Al ion implantation, the crystallinity is restored by activation heat treatment. However, crystallinity cannot be completely recovered, and defects remain in the vicinity of the p-type gate region. The defect acts as a recombination center of electrons and holes, and causes a decrease in current amplification factor. In order to suppress the recombination, a method of increasing the distance between the gate region and the source region and keeping the electrons away can be considered. However, since this method is contrary to the design concept of miniaturizing the junction transistor, it is impossible to achieve both improvement of the current amplification factor and improvement of the current density by miniaturization.
　ＳＩＴに関する上記の問題は、ＢＪＴでも同様に生じる問題である。 The above problem related to SIT is a problem that occurs in BJT as well.
　本発明の目的は、ＳＩＴのゲート領域あるいはＢＪＴのベース領域等の周囲領域での電子と正孔の再結合確率を低減し、主電極間に流れる主電流と制御電極に流れる制御電流との間の再結合を抑制し、電流増幅率を向上することができ、併せて微細化による電流密度の向上も実現することができる接合型半導体装置およびその製造方法を提供することにある。 The object of the present invention is to reduce the recombination probability of electrons and holes in the surrounding region such as the gate region of SIT or the base region of BJT, and between the main current flowing between the main electrodes and the control current flowing to the control electrode. It is an object of the present invention to provide a junction type semiconductor device and a method for manufacturing the same that can suppress recombination of the semiconductor layer, improve the current amplification factor, and improve the current density by miniaturization.
　本発明に係る接合型半導体装置は、炭化珪素（ＳｉＣ）の半導体結晶で作られた基板である第１の主電極用領域（一方の主電極に対応する第１領域）と、基板の１つの面の側に形成された第２の主電極用領域（他方の主電極に対応する第２領域）と、第１および第２の主電極用領域の間に形成された高抵抗層と、第２の主電極用領域の周囲に形成された制御電極用領域（制御電極に対応する領域）と、制御電極用領域の少なくとも側面を覆うように形成された再結合抑制領域と、を有することで特徴づけられる。 A junction type semiconductor device according to the present invention includes a first main electrode region (a first region corresponding to one main electrode) which is a substrate made of a silicon carbide (SiC) semiconductor crystal, and one of the substrates. A second main electrode region formed on the side of the surface (a second region corresponding to the other main electrode), a high resistance layer formed between the first and second main electrode regions, A control electrode region (a region corresponding to the control electrode) formed around the two main electrode regions, and a recombination suppression region formed so as to cover at least the side surface of the control electrode region. Characterized.
　上記の接合型半導体装置において、ＳＩＴまたはＢＪＴに応じて、第１の主電極用領域はドレイン領域またはコレクタ領域であり、第２の主電極用領域はソース領域またはエミッタ領域であり、制御電極用領域はゲート領域またはベース領域である。ゲート領域等の制御電極用領域の少なくとも所定範囲の側面を覆うように再結合抑制領域を設けるようにしたため、当該接合型半導体装置の製造工程で生じる再結合準位が多数存在する領域に例えば電子等に対する電位障壁が設けられ、ソース領域等から流れ込む電子等を再結合抑制領域で遠ざけることができる。 In the above junction type semiconductor device, according to SIT or BJT, the first main electrode region is a drain region or a collector region, and the second main electrode region is a source region or an emitter region. The region is a gate region or a base region. Since the recombination suppression region is provided so as to cover at least a predetermined range of the side surface of the control electrode region such as the gate region, for example, an electron is present in a region where many recombination levels exist in the manufacturing process of the junction type semiconductor device. Is provided, and electrons flowing from the source region or the like can be kept away from the recombination suppression region.
　上記の接合型半導体装置において、好ましくは、高抵抗層内に制御電極用領域に接触するチャネルドープ層を有し、再結合抑制領域はチャネルドープ層が形成された深さ位置まで形成される。 In the above junction type semiconductor device, preferably, the high resistance layer has a channel dope layer in contact with the control electrode region, and the recombination suppression region is formed to a depth position where the channel dope layer is formed.
　さらに、再結合抑制領域を制御電極用領域の側面と底面を覆うように形成することもできる。 Furthermore, the recombination suppressing region can be formed so as to cover the side surface and the bottom surface of the control electrode region.
　上記の接合型半導体装置において、好ましくは、第１の主電極用領域は第１の導電型の低抵抗層からなるドレイン領域であり、第２の主電極用領域は第１の導電型の低抵抗層からなるソース領域であり、制御電極用領域は第２の導電型のゲート領域であり、再結合抑制領域はゲート領域と同じ第２の導電型を有し、再結合抑制領域の抵抗率はゲート領域の抵抗率よりも高いか、あるいは再結合抑制領域は高抵抗層と同じ第１の導電型を有し、再結合抑制領域の抵抗率は高抵抗層よりも高い。 In the above junction type semiconductor device, preferably, the first main electrode region is a drain region made of a first conductive type low resistance layer, and the second main electrode region is a first conductive type low resistance layer. A source region composed of a resistive layer, the control electrode region is a gate region of a second conductivity type, the recombination suppression region has the same second conductivity type as the gate region, and the resistivity of the recombination suppression region Is higher than the resistivity of the gate region, or the recombination suppression region has the same first conductivity type as the high resistance layer, and the resistivity of the recombination suppression region is higher than that of the high resistance layer.
　上記の接合型半導体装置において、好ましくは、第１の主電極用領域は第２の導電型の低抵抗層からなるドレイン領域であり、第２の主電極用領域は第２の導電型の低抵抗層からなるソース領域であり、制御電極用領域は第１の導電型のゲート領域であり、再結合抑制領域はゲート領域と同じ第１の導電型を有し、再結合抑制領域の抵抗率はゲート領域の抵抗率よりも高いか、あるいは再結合抑制領域は高抵抗層と同じ第２の導電型を有し、再結合抑制領域の抵抗率は高抵抗層よりも高い。 In the above junction type semiconductor device, preferably, the first main electrode region is a drain region composed of a low resistance layer of the second conductivity type, and the second main electrode region is a second conductivity type of low resistance. A source region composed of a resistance layer, the control electrode region is a gate region of the first conductivity type, the recombination suppression region has the same first conductivity type as the gate region, and the resistivity of the recombination suppression region Is higher than the resistivity of the gate region, or the recombination suppression region has the same second conductivity type as the high resistance layer, and the resistivity of the recombination suppression region is higher than that of the high resistance layer.
　上記の接合型半導体装置において、好ましくは、第１の主電極用領域は第１の導電型の低抵抗層からなるコレクタ領域であり、第２の主電極用領域は第１の導電型の低抵抗層からなるエミッタ領域であり、制御電極用領域は第２の導電型のベースコンタクト領域であり、再結合抑制領域はベースコンタクト領域と同じ第２の導電型を有し、再結合抑制領域の抵抗率はベースコンタクト領域の抵抗率よりも高いか、あるいは再結合抑制領域は高抵抗層と同じ第１の導電型を有し、再結合抑制領域の抵抗率は高抵抗層よりも高い。 In the above junction type semiconductor device, preferably, the first main electrode region is a collector region made of a first conductivity type low-resistance layer, and the second main electrode region is a first conductivity type low resistance layer. An emitter region composed of a resistance layer, the control electrode region is a second contact type base contact region, the recombination suppression region has the same second conductivity type as the base contact region, and the recombination suppression region The resistivity is higher than the resistivity of the base contact region, or the recombination suppression region has the same first conductivity type as the high resistance layer, and the recombination suppression region has a higher resistivity than the high resistance layer.
　上記の接合型半導体装置において、好ましくは、第１の主電極用領域は第２の導電型の低抵抗層からなるコレクタ領域であり、第２の主電極用領域は第２の導電型の低抵抗層からなるエミッタ領域であり、制御電極用領域は第１の導電型のベースコンタクト領域であり、再結合抑制領域はベースコンタクト領域と同じ第１の導電型を有し、再結合抑制領域の抵抗率はベースコンタクト領域の抵抗率よりも高いか、あるいは再結合抑制領域は高抵抗層と同じ第２の導電型を有し、再結合抑制領域の抵抗率は高抵抗層よりも高い。 In the above junction type semiconductor device, preferably, the first main electrode region is a collector region made of a low resistance layer of the second conductivity type, and the second main electrode region is a low conductivity type of the second conductivity type. An emitter region composed of a resistive layer, the control electrode region is a base contact region of the first conductivity type, the recombination suppression region has the same first conductivity type as the base contact region, The resistivity is higher than the resistivity of the base contact region, or the recombination suppression region has the same second conductivity type as the high resistance layer, and the recombination suppression region has a higher resistivity than the high resistance layer.
　本発明に係る接合型半導体装置の製造方法は、炭化珪素の半導体結晶で作られかつ第１の主電極用領域となる基板の上に高抵抗層を形成する第１の工程と、高抵抗層の上に第２の主電極用領域となる低抵抗層を形成する第２の工程と、高抵抗層の表面側の所定領域にイオン注入により制御電極用領域を形成する第３の工程と、制御電極用領域の少なくとも側面を覆うようにイオン注入により再結合抑制領域を形成する第４の工程と、を含むことを特徴とする。 A method for manufacturing a junction type semiconductor device according to the present invention includes a first step of forming a high resistance layer on a substrate made of a silicon carbide semiconductor crystal and serving as a first main electrode region, and a high resistance layer. A second step of forming a low-resistance layer serving as a second main electrode region on the first layer; a third step of forming a control electrode region by ion implantation in a predetermined region on the surface side of the high-resistance layer; And a fourth step of forming a recombination suppression region by ion implantation so as to cover at least the side surface of the control electrode region.
　また本発明に係る接合型半導体装置の製造方法は、炭化珪素の半導体結晶で作られかつ第１の主電極用領域となる基板の上に高抵抗層を形成する第１の工程と、高抵抗層の上に第２の主電極用領域となる低抵抗層を形成する第２の工程と、高抵抗層の表面側の所定領域にイオン注入により再結合抑制領域を形成する第３の工程と、再結合抑制領域に、再結合抑制領域の表面側からイオン注入により制御電極用領域を形成する第４の工程と、を含むことを特徴とする。 A method for manufacturing a junction type semiconductor device according to the present invention includes a first step of forming a high resistance layer on a substrate made of a silicon carbide semiconductor crystal and serving as a first main electrode region, and a high resistance. A second step of forming a low resistance layer serving as a second main electrode region on the layer; and a third step of forming a recombination suppression region by ion implantation in a predetermined region on the surface side of the high resistance layer; The recombination suppression region includes a fourth step of forming a control electrode region by ion implantation from the surface side of the recombination suppression region.
　上記の接合型半導体装置の製造方法において、好ましくは、再結合抑制領域を形成するためにイオン注入される不純物濃度は、制御電極用領域を形成するためにイオン注入される不純物濃度よりも低いことを特徴とする。 In the above method for manufacturing a junction type semiconductor device, preferably, the impurity concentration implanted to form the recombination suppression region is lower than the impurity concentration implanted to form the control electrode region. It is characterized by.
　上記の接合型半導体装置の製造方法において、好ましくは、高抵抗層の中にチャネルドープ層を形成するための工程を設けたことを特徴とする。 In the manufacturing method of the junction type semiconductor device, preferably, a step for forming a channel dope layer in the high resistance layer is provided.
　上記の接合型半導体装置の製造方法において、好ましくは、基板、高抵抗層、および低抵抗層は第１の導電型であり、制御電極用領域は第２の導電型であることを特徴とする。 In the method for manufacturing a junction semiconductor device, preferably, the substrate, the high resistance layer, and the low resistance layer are of a first conductivity type, and the control electrode region is of a second conductivity type. .
　上記の接合型半導体装置の製造方法において、好ましくは、基板、高抵抗層、および低抵抗層は第２の導電型であり、制御電極用領域は第１の導電型であることを特徴とする。 In the method for manufacturing a junction semiconductor device, preferably, the substrate, the high resistance layer, and the low resistance layer are of the second conductivity type, and the control electrode region is of the first conductivity type. .
　上記の接合型半導体装置の製造方法において、好ましくは、第１の主電極用領域、第２の主電極用領域、および制御電極用領域のそれぞれに、第１主電極、第２主電極、制御電極を形成する工程と、第２主電極と制御電極の上側に上層電極を形成する工程と、を有することを特徴とする。 In the manufacturing method of the junction type semiconductor device, preferably, the first main electrode, the second main electrode, and the control are respectively provided in the first main electrode region, the second main electrode region, and the control electrode region. A step of forming an electrode; and a step of forming an upper layer electrode on the upper side of the second main electrode and the control electrode.
　本発明に係る接合型半導体装置によれば、ＳｉＣ半導体デバイスのゲート領域またはベース領域に接して少なくともその側面を所定の範囲で覆う再結合抑制領域を設けるようにしたため、ゲート領域等とソース領域等との間の再結合を抑制することができ、電流増幅率を向上することができる。また接合型半導体装置において、微細化を行っても、主電流の電流密度の向上を実現することができる According to the junction type semiconductor device according to the present invention, the recombination suppression region is provided in contact with the gate region or the base region of the SiC semiconductor device so as to cover at least a side surface of the SiC semiconductor device within a predetermined range. Can be suppressed, and the current amplification factor can be improved. Further, in the junction type semiconductor device, even if miniaturization is performed, the current density of the main current can be improved.
　本発明に係る接合型半導体装置の製造方法によれば、ＳｉＣ半導体デバイスのゲート領域またはベース領域に接して少なくともその側面を所定の範囲で覆うことができる再結合抑制領域を深さ方向に形成することができる工程を備えるようにしたため、上記のごときゲート・ソース間等の再結合を抑制することによって高い電流増幅率を有する接合型半導体装置を容易にかつ確実に製作することができる。 According to the method for manufacturing a junction type semiconductor device according to the present invention, the recombination suppression region that is in contact with the gate region or the base region of the SiC semiconductor device and can cover at least a side surface thereof in a predetermined range is formed in the depth direction. Therefore, the junction type semiconductor device having a high current amplification factor can be manufactured easily and reliably by suppressing the recombination between the gate and the source as described above.
本発明の第１実施例による接合型半導体装置（ＳＩＴ）の部分縦断面図である。1 is a partial longitudinal sectional view of a junction type semiconductor device (SIT) according to a first embodiment of the present invention. 第１実施例による接合型半導体装置（ＳＩＴ）の一部の平面図である。1 is a plan view of a part of a junction type semiconductor device (SIT) according to a first embodiment. 従来の接合型半導体装置（ＳＩＴ）の動作の問題を説明する部分縦断面図である。It is a fragmentary longitudinal cross-section explaining the problem of operation | movement of the conventional junction type semiconductor device (SIT). 第１実施例による接合型半導体装置（ＳＩＴ）の動作を説明する部分縦断面図である。It is a fragmentary longitudinal cross-section explaining operation | movement of the junction type semiconductor device (SIT) by 1st Example. 第１実施例による接合型半導体装置（ＳＩＴ）の製造方法を説明するフローチャートである。It is a flowchart explaining the manufacturing method of the junction type semiconductor device (SIT) by 1st Example. 第１実施例による接合型半導体装置（ＳＩＴ）の製造方法の各工程に対応するデバイス構造を示す部分縦断面図である。It is a fragmentary longitudinal cross-section which shows the device structure corresponding to each process of the manufacturing method of the junction type semiconductor device (SIT) by 1st Example. 第１実施例による接合型半導体装置（ＳＩＴ）の製造方法の各工程に対応するデバイス構造を示す部分縦断面図である。It is a fragmentary longitudinal cross-section which shows the device structure corresponding to each process of the manufacturing method of the junction type semiconductor device (SIT) by 1st Example. 第１実施例による接合型半導体装置（ＳＩＴ）の製造方法における特徴的工程に対応するデバイス構造を説明するための部分縦断面図である。It is a fragmentary longitudinal cross-sectional view for demonstrating the device structure corresponding to the characteristic process in the manufacturing method of the junction type semiconductor device (SIT) by 1st Example. 第１実施例による接合型半導体装置（ＳＩＴ）の製造方法における他の特徴的工程に対応するデバイス構造を説明するための部分縦断面図である。It is a fragmentary longitudinal cross-sectional view for demonstrating the device structure corresponding to the other characteristic process in the manufacturing method of the junction type semiconductor device (SIT) by 1st Example. 本発明の第２実施例による接合型半導体装置（ＳＩＴ）の部分縦断面図である。It is a partial longitudinal cross-sectional view of the junction type semiconductor device (SIT) by 2nd Example of this invention. 本発明の第３実施例による接合型半導体装置（ＳＩＴ）の部分縦断面図である。It is a partial longitudinal cross-sectional view of the junction type semiconductor device (SIT) by 3rd Example of this invention. 本発明の第４実施例による接合型半導体装置（ＢＪＴ）の部分縦断面図である。It is a fragmentary longitudinal cross-sectional view of the junction type semiconductor device (BJT) by 4th Example of this invention. 本発明の第５実施例による接合型半導体装置（ＢＪＴ）の部分縦断面図である。It is a fragmentary longitudinal cross-sectional view of the junction type semiconductor device (BJT) by 5th Example of this invention. 従来の接合型半導体装置（ＢＪＴ）の構造を説明する部分縦断面図である。It is a fragmentary longitudinal cross-section explaining the structure of the conventional junction type semiconductor device (BJT).
　以下に、本発明の好適な幾つかの実施例について添付図面に基づいて説明する。 Hereinafter, some preferred embodiments of the present invention will be described with reference to the accompanying drawings.
　＜第１の実施例＞
　図１～図８を参照して本発明の第１実施例による接合型半導体装置を説明する。図１は第１実施例による接合型半導体装置の単位構造を示す部分縦断面図であり、図２は当該接合型半導体装置の平面図である。図１は、図２におけるＡ－Ａ線断面における少なくとも１つのソース電極を含む部分の縦断面図を示している。この接合型半導体装置はＳＩＴ（静電誘導トランジスタ）の例を示している。 <First embodiment>
A junction type semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a partial longitudinal sectional view showing a unit structure of a junction type semiconductor device according to the first embodiment, and FIG. 2 is a plan view of the junction type semiconductor device. FIG. 1 shows a longitudinal sectional view of a portion including at least one source electrode in the cross section taken along the line AA in FIG. This junction type semiconductor device shows an example of SIT (electrostatic induction transistor).
　図２に示すように、ＳＩＴ１０は、そのデバイス上面の特定な単位領域に、並列に配列された例えば５本のソース電極１９を備えている。 As shown in FIG. 2, the SIT 10 includes, for example, five source electrodes 19 arranged in parallel in a specific unit region on the upper surface of the device.
　図１に示す縦断面構造において、ＳＩＴ１０は、ＳｉＣ（炭化珪素）結晶を有する下側面部分に形成されたｎ型の低抵抗層（ｎ＋層）からなるドレイン領域１１と、当該ＳｉＣ結晶を有する上側面部分に形成されたｎ型の低抵抗層（ｎ＋層）からなるソース領域１２を備えている。ドレイン領域１１を形成する層が基板となっている。 In the longitudinal cross-sectional structure shown in FIG. 1, the SIT 10 has a drain region 11 formed of an n-type low resistance layer (n + layer) formed on a lower surface portion having a SiC (silicon carbide) crystal, and the SiC crystal. A source region 12 made of an n-type low resistance layer (n + layer) formed on the upper side surface portion is provided. The layer forming the drain region 11 is a substrate.
　図２に示すように、平面図の位置関係において、複数のソース電極１９の各々の周囲には、当該ソース電極１９を囲むようにゲート電極２０が形成されている。この意味は、ソース電極１９の下側に位置するソース領域１２の周囲は、ゲート電極２０の下側に位置するｐ型のゲート領域１３によって囲まれているということである。ゲート領域１３は所定の深い位置まで形成されている。さらに、ＳＩＴ１０において、上側のソース領域１２と下側のドレイン領域１１の間にはｎ型の高抵抗層（ｎ－層）１４が形成される。また当該高抵抗層１４の中には、上記のゲート領域１３と接続されるように配置されたｐ型のチャネルドープ層１５が形成されている。 As shown in FIG. 2, a gate electrode 20 is formed around each of the plurality of source electrodes 19 so as to surround the source electrode 19 in the positional relationship of the plan view. This means that the source region 12 located below the source electrode 19 is surrounded by the p-type gate region 13 located below the gate electrode 20. The gate region 13 is formed up to a predetermined deep position. Further, in the SIT 10, an n-type high resistance layer (n − layer) 14 is formed between the upper source region 12 and the lower drain region 11. Further, in the high resistance layer 14, a p-type channel dope layer 15 is formed so as to be connected to the gate region 13.
　本実施例において、上記の「ｎ型」は「第１の導電型」であり、上記の「ｐ型」は「第２の導電型」であるとする。 In this embodiment, it is assumed that the “n-type” is “first conductivity type” and the “p-type” is “second conductivity type”.
　本実施例に係るＳＩＴ１０では、さらに、ゲート領域１３とｎ型の高抵抗層１４との間の境界領域において、好ましくは、チャネルドープ層１５を超える深さ位置までにｐ型の再結合抑制領域１６を設けている。再結合抑制領域１６の深さ方向の形成位置は、後述するように目的に応じて適宜に設定することができる。当該再結合抑制領域１６は、ゲート領域１３の側面の全周囲に設けられる。上記の再結合抑制領域１６は、ゲート領域１３よりも抵抗率の高いｐ－半導体あるいは高抵抗層１４よりも抵抗率の高いｎ－半導体で形成されている。 In the SIT 10 according to the present embodiment, a p-type recombination suppression region is preferably formed at a boundary region between the gate region 13 and the n-type high resistance layer 14, preferably up to a depth position exceeding the channel dope layer 15. 16 is provided. The formation position of the recombination suppression region 16 in the depth direction can be appropriately set according to the purpose as described later. The recombination suppression region 16 is provided all around the side surface of the gate region 13. The recombination suppression region 16 is formed of a p − semiconductor having a higher resistivity than that of the gate region 13 or an n − semiconductor having a higher resistivity than that of the high resistance layer 14.
　上記のＳＩＴ１０の構造において、図１に示すように、ドレイン領域１１の下側表面にはドレイン電極１８が接合され、ソース領域１２の上側表面にはソース電極１９が接合され、ゲート領域１３の上側表面にはゲート電極２０が接合されている。ＳＩＴ１０の上面において、ソース電極１９とゲート電極２０の間における露出表面は、表面保護膜１７によって覆われ保護されている。 In the structure of the SIT 10, as shown in FIG. 1, the drain electrode 18 is joined to the lower surface of the drain region 11, the source electrode 19 is joined to the upper surface of the source region 12, and the upper side of the gate region 13. A gate electrode 20 is bonded to the surface. On the upper surface of the SIT 10, the exposed surface between the source electrode 19 and the gate electrode 20 is covered and protected by the surface protective film 17.
　図２に示すように、ソース電極１９およびゲート電極２０の各々の上側には上層電極２１が設けられている。図１において、上層電極２１の図示は省略されている。 As shown in FIG. 2, an upper layer electrode 21 is provided on the upper side of each of the source electrode 19 and the gate electrode 20. In FIG. 1, the upper layer electrode 21 is not shown.
　上記ＳＩＴ１０において、主電流は、ソース領域１２（またはソース電極１９）からドレイン領域１１（またはドレイン電極１８）に流れる電子流である。主電流の通電（オン）と非通電（オフ）は、ゲート電極２０に印加されるゲート電圧、すなわち、ゲート領域１３とソース領域１２の間に加えられる制御信号に基づいて制御される。ゲート・ソース間の印加電圧が０Ｖ以下であるときにはＳＩＴ１０は主電流が流れず、オフ状態になる。ゲート・ソース間に一定以上の電圧が印加されると、ＳＩＴ１０は主電流が流れてオン状態に移行する。オン状態では、ゲート領域１３とソース領域１２の間に形成されているｐｎ接合が順バイアスされて、ゲート領域１３ソース領域１２に制御電流である正孔電流が流れる。 In the SIT 10, the main current is an electron flow that flows from the source region 12 (or the source electrode 19) to the drain region 11 (or the drain electrode 18). Energization (ON) and non-energization (OFF) of the main current are controlled based on a gate voltage applied to the gate electrode 20, that is, a control signal applied between the gate region 13 and the source region 12. When the applied voltage between the gate and the source is 0 V or less, the main current does not flow through the SIT 10 and it is turned off. When a voltage of a certain level or higher is applied between the gate and the source, the main current flows through the SIT 10 and shifts to the on state. In the on state, the pn junction formed between the gate region 13 and the source region 12 is forward-biased, and a hole current that is a control current flows through the source region 12 in the gate region 13.
　図３と図４を参照し、従来のＳＩＴ構造と本実施形態に係るＳＩＴ構造を対比しながら、ＳＩＴ１０の特徴的構造を説明する。 Referring to FIGS. 3 and 4, the characteristic structure of SIT 10 will be described while comparing the conventional SIT structure and the SIT structure according to the present embodiment.
　図３において、上記の図１で説明した要素と同一の要素には同一の符号を付している。従来の構造を有するＳＩＴ１０Ａでは、ゲート領域１３の周辺に多数の再結合準位３１ａが存在する領域３１が形成されている。ＳＩＴ１０Ａのオン状態では、領域３１において、ゲート領域１３から流れ込む正孔３２とソース領域１２から流れ込む電子３３とが共存する。そのため領域３１では、電子３３と正孔３２との再結合が盛んに生じ、ＳＩＴ１０Ａの動作に寄与しない無効なゲート電流が流れ、ＳＩＴ１０Ａの電流増幅率を低下させる。図３において、Ｉ１が主電流である。 In FIG. 3, the same elements as those described in FIG. 1 are given the same reference numerals. In the SIT 10A having the conventional structure, a region 31 having a large number of recombination levels 31a is formed around the gate region 13. In the on state of the SIT 10A, in the region 31, the holes 32 flowing from the gate region 13 and the electrons 33 flowing from the source region 12 coexist. Therefore, in the region 31, recombination of electrons 33 and holes 32 occurs actively, an invalid gate current that does not contribute to the operation of the SIT 10A flows, and the current amplification factor of the SIT 10A decreases. In FIG. 3, I1 is a main current.
　従来構造を有するＳＩＴ１０Ａに対して、本実施例によるＳＩＴ１０では、図４に示すように、ゲート領域１３の側面周囲におけるｎ型高抵抗層１４との境界部分に再結合抑制領域１６が形成されている。当該再結合抑制領域１６は、再結合準位３１ａが多数存在する領域３１において、特にその主要部分に対してイオン注入を行うことなどにより形成される。 In contrast to the SIT 10A having the conventional structure, in the SIT 10 according to the present embodiment, as shown in FIG. 4, the recombination suppression region 16 is formed at the boundary with the n-type high resistance layer 14 around the side surface of the gate region 13. Yes. The recombination suppression region 16 is formed, for example, by performing ion implantation on the main portion of the region 31 where many recombination levels 31a exist.
　再結合抑制領域１６は、ゲート領域１３と同じ導電型であり、ゲート領域１３よりも高抵抗率のｐ－半導体か、あるいは高抵抗層１４と同じ導電型で高抵抗層１４よりも高抵抗率のｎ－半導体で形成されている。再結合抑制領域１６が高抵抗になるように設計されているために、「ｐ－」であれば正孔、「ｎ－」であれば電子の密度が低くなっている。 The recombination suppression region 16 is the same conductivity type as the gate region 13 and is a p - semiconductor having a higher resistivity than the gate region 13 or the same conductivity type as the high resistance layer 14 and a higher resistivity than the high resistance layer 14. N − semiconductor. Since the recombination suppression region 16 is designed to have a high resistance, the density of holes is low when “p − ”, and the density of electrons is low when “n − ”.
　さらに再結合抑制領域１６と高抵抗層１４の間あるいはゲート領域１３と再結合抑制領域１６の間にｐｎ接合による電子あるいは正孔に対する電位障壁が形成されるために、電子あるいは正孔の再結合抑制領域１６への侵入が抑制される。その結果、ソース領域１２から流れ込む電子３３は多数の再結合準位が存在する領域３１で再結合電流として消費されることなく主電流Ｉ２としてドレイン領域１１に流れ込む。このようにしてＳＩＴ１０の電流増幅率が向上する。 Further, since a potential barrier against electrons or holes is formed between the recombination suppression region 16 and the high resistance layer 14 or between the gate region 13 and the recombination suppression region 16, electrons or holes are recombined. Intrusion into the suppression region 16 is suppressed. As a result, electrons 33 flowing from the source region 12 flow into the drain region 11 as the main current I2 without being consumed as a recombination current in the region 31 where a large number of recombination levels exist. In this way, the current amplification factor of the SIT 10 is improved.
　再結合抑制領域１６を形成する際にも、ゲート領域１３を作る場合と同様に、Ａｌ等のイオン注入法を用いる。しかし、ゲート領域１３を作るときのイオン注入に比較して注入濃度が極めて低く、イオン注入に要するエネルギも低い。そのため再結合抑制領域１６を形成するためのイオン注入では再結合準位の密度を低く抑えることができる。 When forming the recombination suppression region 16, an ion implantation method of Al or the like is used as in the case of forming the gate region 13. However, the implantation concentration is extremely low compared to the ion implantation for forming the gate region 13, and the energy required for the ion implantation is also low. Therefore, in the ion implantation for forming the recombination suppression region 16, the density of recombination levels can be suppressed low.
　次に、第１実施例によるＳＩＴ１０の各高抵抗層等の不純物濃度および寸法について具体的な一例を説明する。 Next, a specific example of the impurity concentration and dimensions of each high resistance layer of the SIT 10 according to the first embodiment will be described.
　ＳＩＴ１０は、例えば阻止電圧６００Ｖを目標に設計されている。基板の部分には、（０００１）面から８度オフさせた低抵抗のｎ型４Ｈ－ＳｉＣ基板を使用している。ＳＩＴ１０において、当該基板部分がドレイン領域１１となる。基板上の高抵抗層１４は、ソース・ドレイン間に加わる高電圧を阻止するための層である。本実施例では、高抵抗層１４は、６００Ｖ以上の電圧を阻止するように、例えば、厚み１０μｍ、不純物濃度１×１０１６ｃｍ－３に設定されている。 The SIT 10 is designed with a target of a blocking voltage of 600V, for example. As the substrate portion, a low resistance n-type 4H—SiC substrate turned off by 8 degrees from the (0001) plane is used. In SIT 10, the substrate portion becomes the drain region 11. The high resistance layer 14 on the substrate is a layer for preventing a high voltage applied between the source and the drain. In the present embodiment, the high resistance layer 14 is set to have a thickness of 10 μm and an impurity concentration of 1 × 10 16 cm −3 , for example, so as to block a voltage of 600 V or higher.
　高抵抗層１４上のｐ型チャネルドープ層１５は、ソース・ドレイン間に高電圧が印加されたときに、ゲート・ソース間電圧ＶＧＳ＝０Ｖにおいても、ＳＩＴ１０がオン動作しないように、その厚みと不純物濃度が設定されている。本実施例では、ｐ型チャネルドープ層１５は、厚み０．１～０．５μｍ、不純物濃度４×１０１７～２×１０１８ｃｍ－３とした。チャネルドープ層１５上には、厚さ０．１～０．４μｍ、不純物濃度５×１０１５ｃｍ－３～５×１０１７ｃｍ－３の高抵抗層１４を挟んで、厚さ０．５～２．０μｍ、不純物濃度１～５×１０１９ｃｍ－３の低抵抗のｎ型ソース領域１２が設けられている。 The p-type channel doped layer 15 on the high resistance layer 14 has a thickness so that the SIT 10 does not turn on even when a gate-source voltage V GS = 0 V when a high voltage is applied between the source and the drain. And impurity concentration is set. In this embodiment, the p-type channel dope layer 15 has a thickness of 0.1 to 0.5 μm and an impurity concentration of 4 × 10 17 to 2 × 10 18 cm −3 . On the channel dope layer 15, a high resistance layer 14 having a thickness of 0.1 to 0.4 μm and an impurity concentration of 5 × 10 15 cm −3 to 5 × 10 17 cm −3 is sandwiched, and a thickness of 0.5 to A low-resistance n-type source region 12 having 2.0 μm and an impurity concentration of 1 to 5 × 10 19 cm −3 is provided.
　さらに、ソース領域１２の周囲には、厚み１～２μｍ、不純物濃度１×１０１８～１×１０１９ｃｍ－３程度の低抵抗ゲート領域１３が設けられている。図２に示すように、ソース領域１２の平面形状は、細長い島状の形状である。１つのＳＩＴ１０に複数のソース領域１２を備えている。１つのソース領域１２の寸法は、幅３～１０μｍ、長さ１００～１０００μｍ程度である。ゲート領域１３とソース領域１２を含めた単位構造の周期は約１０～３０μｍである。 Further, a low resistance gate region 13 having a thickness of 1 to 2 μm and an impurity concentration of about 1 × 10 18 to 1 × 10 19 cm −3 is provided around the source region 12. As shown in FIG. 2, the planar shape of the source region 12 is an elongated island shape. One SIT 10 includes a plurality of source regions 12. The size of one source region 12 is about 3 to 10 μm in width and about 100 to 1000 μm in length. The period of the unit structure including the gate region 13 and the source region 12 is about 10 to 30 μm.
　次に、図５～図８を参照してＳＩＴ１０の製造方法を説明する。図５は、製造方法のフローチャートを示している。図６Ａ及び図６Ｂは、各ステップで製作される半導体装置を示している。 Next, a method for manufacturing the SIT 10 will be described with reference to FIGS. FIG. 5 shows a flowchart of the manufacturing method. 6A and 6B show a semiconductor device manufactured in each step.
　ＳＩＴ１０の製造方法は、次のプロセス（１）～（１１）（ステップＳ１１～Ｓ２１）から成っている。図５に示されるようにステップＳ１１からステップＳ２１に到る順序で実行される。 The manufacturing method of SIT10 consists of the following processes (1) to (11) (steps S11 to S21). As shown in FIG. 5, the process is executed in the order from step S11 to step S21.
　（１）高抵抗層形成プロセス（ステップＳ１１）
　（２）チャネルドープ層形成プロセス（ステップＳ１２）
　（３）高抵抗層形成プロセス（ステップＳ１３）
　（４）低抵抗層形成プロセス（ステップＳ１４）
　（５）ソースエッチングプロセス（ステップＳ１５）
　（６）ゲート領域形成プロセス（ステップ１６）
　（７）再結合抑制領域形成プロセス（ステップＳ１７）
　（８）イオン注入層活性化プロセス（ステップＳ１８）
　（９）表面保護膜形成プロセス（ステップＳ１９）
　（１０）電極形成プロセス（ステップＳ２０）
　（１１）上層電極形成プロセス（ステップＳ２１） (1) High resistance layer forming process (step S11)
(2) Channel dope layer forming process (step S12)
(3) High resistance layer formation process (step S13)
(4) Low resistance layer formation process (step S14)
(5) Source etching process (step S15)
(6) Gate region formation process (step 16)
(7) Recombination suppression region formation process (step S17)
(8) Ion implantation layer activation process (step S18)
(9) Surface protective film formation process (step S19)
(10) Electrode formation process (step S20)
(11) Upper layer electrode formation process (step S21)
　上記のステップＳ１１～Ｓ１４を実施することによって図６Ａの（ａ）に示される構造が形成される。 The structure shown in FIG. 6A (a) is formed by performing the above steps S11 to S14.
　高抵抗層形成プロセス（ステップＳ１１）では、ＳｉＣで形成されたｎ型基板４０の上に、エピタキシャル成長法により、厚さ１０μｍで、濃度１×１０１６ｃｍ－３の窒素を不純物としてドープした高抵抗層４１を成長させる。基板４０には「４Ｈ－ＳｉＣ（0001）８°off」が用いられている。また基板４０は、前述したｎ型低抵抗層のドレイン領域１１となる。 In the high resistance layer formation process (step S11), a high resistance in which nitrogen having a thickness of 10 μm and a concentration of 1 × 10 16 cm −3 is doped as an impurity on an n-type substrate 40 formed of SiC by an epitaxial growth method. Layer 41 is grown. “4H—SiC (0001) 8 ° off” is used for the substrate 40. The substrate 40 becomes the drain region 11 of the n-type low resistance layer described above.
　チャネルドープ層形成プロセス（ステップＳ１２）では、ｎ型高抵抗層４１の上に、エピタキシャル成長法により、アルミニウム（Ａｌ）を不純物として４×１０１７～２×１０１８ｃｍ－３の濃度で０．１～０．５μｍのｐ型のチャネルドープ層４２を成長させる。 In the channel dope layer forming process (step S12), aluminum (Al) as an impurity is formed on the n-type high resistance layer 41 by an epitaxial growth method at a concentration of 4 × 10 17 to 2 × 10 18 cm −3. A p-type channel dope layer 42 of about 0.5 μm is grown.
　高抵抗層形成プロセス（ステップＳ１３）では、その後、チャネルドープ層４２の上に、エピタキシャル成長法により、厚さ０．１～０．４μｍで濃度５×１０１５～５×１０１７ｃｍ－３の窒素を不純物としてドープしたｎ型の高抵抗層４３を成長させる。 In the high resistance layer forming process (step S13), nitrogen having a thickness of 0.1 to 0.4 μm and a concentration of 5 × 10 15 to 5 × 10 17 cm −3 is then formed on the channel dope layer 42 by an epitaxial growth method. An n-type high-resistance layer 43 doped with impurities is grown.
　低抵抗層形成プロセス（ステップＳ１４）では、ｎ型の高抵抗層４３の上に、エピタキシャル成長法により、厚さ０．５～２．０μｍで濃度１～５×１０１９ｃｍ－３の窒素を不純物としてドープしたｎ型の低抵抗層４４を成長させる。この低抵抗層４４は、前述したソース領域１２を形成する。 In the low resistance layer formation process (step S14), nitrogen is doped on the n-type high resistance layer 43 by an epitaxial growth method with a thickness of 0.5 to 2.0 μm and a concentration of 1 to 5 × 10 19 cm −3. An n-type low resistance layer 44 doped as follows is grown. The low resistance layer 44 forms the source region 12 described above.
　次のソースエッチングプロセス（ステップＳ１５）では、図６Ａの（ａ）に示された構造において、その上面に、ＣＶＤ法によりシリコン酸化膜５１を堆積させ、フォトリソグラフィーを行い、その後にＲＩＥによりシリコン酸化膜５１をエッチングする。こうしてマスクが形成される。その後、このシリコン酸化膜５１を用いて、ＲＩＥにより低抵抗層４４のＳｉＣエッチングを行い、ソース領域１２を形成する。ＳｉＣエッチングのＲＩＥにはＳＦ６ガスなどが用いられる。その結果得られた構造を図６Ａの（ｂ）に示す。なおエッチング深さは例えば約０．５～２．３μｍである。 In the next source etching process (step S15), in the structure shown in FIG. 6A (a), a silicon oxide film 51 is deposited on the upper surface by CVD, photolithography is performed, and then silicon oxide is oxidized by RIE. The film 51 is etched. Thus, a mask is formed. Thereafter, using this silicon oxide film 51, SiC etching of the low resistance layer 44 is performed by RIE, thereby forming the source region 12. SF 6 gas or the like is used for RIE of SiC etching. The resulting structure is shown in FIG. 6A (b). The etching depth is, for example, about 0.5 to 2.3 μm.
　ゲート領域形成プロセス（ステップＳ１６）では、図６Ａの（ｃ）に示すように、さらにゲート領域１３を形成するための表面部分が露出するように、マスク５２が形成される。マスク５２は、ＣＶＤ法によりシリコン酸化膜を堆積し、フォトリソグラフィーを行い、その後にＲＩＥによりシリコン酸化膜をエッチングすることにより形成される。その後、イオン注入してゲート領域１３を形成する。注入されるイオンはアルミニウム（Ａｌ）であり、注入の深さは例えば１～２μｍである。イオン注入量は１×１０１８～１×１０１９ｃｍ－３であり、イオン注入に必要なエネルギは７００ＫｅＶ～２ＭｅＶ以上である。 In the gate region formation process (step S16), as shown in FIG. 6A (c), the mask 52 is formed so that the surface portion for forming the gate region 13 is further exposed. The mask 52 is formed by depositing a silicon oxide film by a CVD method, performing photolithography, and then etching the silicon oxide film by RIE. Thereafter, the gate region 13 is formed by ion implantation. The ions to be implanted are aluminum (Al), and the depth of implantation is, for example, 1 to 2 μm. The ion implantation amount is 1 × 10 18 to 1 × 10 19 cm −3 , and the energy required for ion implantation is 700 KeV to 2 MeV or more.
　再結合抑制領域を形成するプロセス（Ｓ１７）では、図６Ａの（ｄ）に示されるように、再結合抑制領域１６を形成するためのマスクが形成される。このマスク形成では、ゲート領域形成用のマスク５３（シリコン酸化膜）を利用する。図６Ａの（ｃ）で示したマスク５２において、例えば、ウェットエッチング等の等方性エッチングを利用し、再結合抑制領域を形成するための部分のみを除去する。その後に、不純物（イオン種）としてアルミニウム（Ａｌ）のイオン注入を行う。注入する領域は、ゲート領域１３よりも広く、かつゲート・ソース間距離よりも狭い範囲である。寸法的には、例えば、ゲート幅の両側の各々で０．５μｍである。注入の深さは、例えば約０．４μｍ程度である。さらにゲート表面からゲート領域の最深の深さ程度まで再結合抑制領域１６を形成する場合もある。イオン注入量は５×１０１５～５×１０１７ｃｍ－３程度であり、ｎ－型高抵抗層４１，４３と同程度前後の値が望ましい。またイオン注入に必要なエネルギは一例として４００ＫｅＶ程度であるが、注入深さに応じて決定される。こうして再結合抑制領域１６がゲート領域１３の側面の全周囲に所要の深さで形成される。図２に示す平面形状を考慮すれば、ゲート領域１３の側面の全周囲を覆うように再結合抑制領域１６が形成される。 In the process (S17) for forming the recombination suppression region, a mask for forming the recombination suppression region 16 is formed as shown in FIG. 6D (d). In this mask formation, a mask 53 (silicon oxide film) for forming a gate region is used. In the mask 52 shown in FIG. 6A (c), for example, isotropic etching such as wet etching is used to remove only the portion for forming the recombination suppression region. Thereafter, ion implantation of aluminum (Al) as an impurity (ion species) is performed. The region to be implanted is wider than the gate region 13 and narrower than the gate-source distance. In terms of dimensions, for example, it is 0.5 μm on each side of the gate width. The depth of implantation is, for example, about 0.4 μm. Furthermore, the recombination suppression region 16 may be formed from the gate surface to the deepest depth of the gate region. The ion implantation amount is about 5 × 10 15 to 5 × 10 17 cm −3 , and is preferably about the same as that of the n − -type high resistance layers 41 and 43. The energy required for ion implantation is, for example, about 400 KeV, but is determined according to the implantation depth. In this way, the recombination suppression region 16 is formed at a required depth all around the side surface of the gate region 13. In consideration of the planar shape shown in FIG. 2, the recombination suppression region 16 is formed so as to cover the entire periphery of the side surface of the gate region 13.
　ｐ型領域である再結合抑制領域１６は、ゲートとしての機能は持たず、再結合準位が多数存在する領域の正孔および電子の密度を低減することが目的である。そのために、ゲート領域形成時のイオン注入と比較して、注入量・注入エネルギともに小さく設定されている。結果として、イオン注入による結晶の損傷を低く抑えることができ、製造プロセスによるＳＩＴのデバイス特性への悪影響を抑えることができる。 The recombination suppression region 16 which is a p-type region does not have a function as a gate and is intended to reduce the density of holes and electrons in a region where a large number of recombination levels exist. Therefore, both the implantation amount and the implantation energy are set to be smaller than the ion implantation at the time of forming the gate region. As a result, damage to the crystal due to ion implantation can be kept low, and adverse effects on the device characteristics of the SIT due to the manufacturing process can be suppressed.
　ゲート領域１３と再結合抑制領域１６を形成するプロセス（ステップＳ１６，Ｓ１７）に関して、概念的により詳しく要部を示すと、図７の（ａ）～（ｃ）のようになる。図７においては、ゲート領域１３および再結合抑制領域１６のみが示されており、ソース領域とチャネルドープ領域は省略されている。 Regarding the process of forming the gate region 13 and the recombination suppression region 16 (steps S16 and S17), the main parts are conceptually shown in more detail as shown in (a) to (c) of FIG. In FIG. 7, only the gate region 13 and the recombination suppression region 16 are shown, and the source region and the channel dope region are omitted.
　図７（ａ）はゲート領域１３を形成するためにイオン（Ａｌ＋）６１を注入するプロセスを示し、（ｂ）はゲート領域１３の側面周囲に再結合抑制領域を形成するためのマスク６２を酸化膜ウェットエッチングにより形成するプロセスを示し、（ｃ）は再結合抑制領域１６を形成するためにイオン（Ａｌ＋）６１を注入するプロセスを示している。 FIG. 7A shows a process of implanting ions (Al + ) 61 to form the gate region 13, and FIG. 7B shows a mask 62 for forming a recombination suppression region around the side surface of the gate region 13. A process for forming the oxide film by wet etching is shown, and (c) shows a process for implanting ions (Al + ) 61 in order to form the recombination suppression region 16.
　本プロセスでは、シリコン酸化膜などで形成されるマスク６２を用いてゲート領域１３を形成するためＡｌイオン６１を選択的にＳｉＣ６３中に注入したのち、マスク６２は丁度再結合抑制領域１６のＳｉＣ表面が露出するようにエッチングされる。エッチングにより新たに露出するＳｉＣ表面の幅は、例えば０．５μｍである。そのエッチングされたあとのマスク６２を利用して再結合抑制領域１６を形成するために再びＳｉＣ６３にＡｌイオンが注入される。図７（ｃ）では再結合抑制領域１６の深さをｄで表している。このように再結合抑制領域１６を形成するためのイオン注入マスク６２の形成にはマスク合わせ工程を用いていないため、ゲート領域１３と再結合抑制領域１６の位置関係にズレが生じないセルフアライン工程となっている。 In this process, Al ions 61 are selectively implanted into the SiC 63 to form the gate region 13 using the mask 62 formed of a silicon oxide film or the like, and then the mask 62 is just the SiC surface of the recombination suppression region 16. Etching is performed so that is exposed. The width of the SiC surface newly exposed by etching is, for example, 0.5 μm. Al ions are again implanted into the SiC 63 in order to form the recombination suppression region 16 using the mask 62 after the etching. In FIG. 7C, the depth of the recombination suppression region 16 is represented by d. Since the mask alignment process is not used for forming the ion implantation mask 62 for forming the recombination suppression region 16 in this way, a self-alignment process in which the positional relationship between the gate region 13 and the recombination suppression region 16 does not occur. It has become.
　ゲート領域１３と再結合抑制領域１６を形成する工程については、その他に、図８に示すような形成方法もある。なお図８においても、ゲート領域１３および再結合抑制領域１６のみが示されており、ソース領域とチャネルドープ領域は省略されている。 In addition to the process of forming the gate region 13 and the recombination suppression region 16, there is a formation method as shown in FIG. In FIG. 8, only the gate region 13 and the recombination suppression region 16 are shown, and the source region and the channel dope region are omitted.
　図８に従って当該形成方法を説明する。この形成方法では、最初に再結合抑制領域を形成するためのイオン注入６１を行えるようにマスク６２を形成し、再結合抑制領域１６を形成するためのイオン注入６１を行う（図８（ａ））。その後、表面の全体にＣＶＤ法により酸化膜６４を堆積する（図８（ｂ））。表面に形成した酸化膜６４を異方性エッチングによりエッチングし、ゲート領域を作る表面６５を露出させる（図８（ｃ））。当該表面６５は、上記の再結合抑制領域１６の上表面になっている。その後、露出した表面６５に対してゲート領域１３を形成するためのイオン注入６１を行う（図８（ｄ））。 The formation method will be described with reference to FIG. In this forming method, first, a mask 62 is formed so that ion implantation 61 for forming a recombination suppression region can be performed, and ion implantation 61 for forming the recombination suppression region 16 is performed (FIG. 8A). ). Thereafter, an oxide film 64 is deposited on the entire surface by CVD (FIG. 8B). The oxide film 64 formed on the surface is etched by anisotropic etching to expose the surface 65 that forms the gate region (FIG. 8C). The surface 65 is the upper surface of the recombination suppression region 16 described above. Thereafter, ion implantation 61 for forming the gate region 13 is performed on the exposed surface 65 (FIG. 8D).
　以上によって、ゲート領域１３が作られることになる。この場合にも、再結合抑制領域１６は、ゲート領域１３の側面周囲において、ゲート領域１３の表面からの深さｄで形成される。この方法もセルフアラインプロセスであり、ゲート領域１３と再結合抑制領域１６の間に位置のズレは生じない。なお、ゲート領域１３と再結合抑制領域１６の形成に関しては各々に対してフォト工程を用いてマスクを形成しても良い。特に、再結合抑制領域の幅を１μｍ以上程度に広くする場合にはこの方法が有効である。 Thus, the gate region 13 is formed. Also in this case, the recombination suppression region 16 is formed around the side surface of the gate region 13 with a depth d from the surface of the gate region 13. This method is also a self-alignment process, and no positional deviation occurs between the gate region 13 and the recombination suppression region 16. In addition, regarding the formation of the gate region 13 and the recombination suppression region 16, a mask may be formed for each using a photo process. This method is particularly effective when the width of the recombination suppression region is widened to about 1 μm or more.
　次に、再結合抑制領域１６の深さｄと不純物濃度についてさらに詳しく説明する。 Next, the depth d of the recombination suppression region 16 and the impurity concentration will be described in more detail.
　再結合抑制領域１６は、可能な限り広い範囲に渡ってゲートを覆うことが望ましいため、この点からすると深さｄはゲート領域の深さと同程度が望まれる。一方で、ＳｉＣでは再結合抑制領域１６の形成手法としてはイオン注入法が用いられるが、深い部分にまでイオンを注入するためには高いエネルギが必要であり、高いエネルギでのイオン注入は新たな欠陥を生成することになる。そのため、新たな欠陥を生成しないという観点からは深さｄは浅い方が望ましい。このように深さｄを決定するに際しては、可能なかぎり広い範囲に渡って再結合抑制領域１６を形成すること、および新たな欠陥の形成を最小限に留めることという相反する事象を考慮する必要がある。 Since it is desirable that the recombination suppression region 16 covers the gate as much as possible, the depth d is desired to be approximately the same as the depth of the gate region. On the other hand, in SiC, an ion implantation method is used as a method for forming the recombination suppression region 16, but high energy is required to implant ions into a deep portion, and ion implantation with high energy is a new method. A defect will be generated. Therefore, it is desirable that the depth d is shallow from the viewpoint of not generating new defects. In determining the depth d in this way, it is necessary to consider the conflicting phenomenon of forming the recombination suppression region 16 over as wide a range as possible and minimizing the formation of new defects. There is.
　前述したように再結合の発生には、再結合準位密度、電子密度、正孔密度が影響を与える。デバイス中でこれらの密度がより高い部分に再結合抑制領域１６を形成することが重要となる。図１のＳＩＴ構造のゲート周辺領域に限ると、ＳｉＣ表面からチャネルドープ層１５付近が電子密度と正孔密度の両方が高い領域である。 As described above, recombination level density, electron density, and hole density affect the occurrence of recombination. It is important to form the recombination suppression region 16 in the higher density portion of the device. When limited to the gate peripheral region of the SIT structure of FIG. 1, the region near the channel dope layer 15 from the SiC surface is a region where both the electron density and the hole density are high.
　これらの点を踏まえると再結合抑制領域１６の深さｄは、最低でもチャネルドープ層に届いていることが望ましい。その場合の深さｄは０．１～０．３μｍ程度であり、イオン注入で形成しても低いエネルギで新たな欠陥の発生を最小限に留めることが可能である。また、深さｄの上限は、最大でゲート領域１３の深さと同程度であるが、この値は個別のデバイスのゲート領域１３の深さとその深さの再結合抑制領域１６を形成する際にイオン注入エネルギで生成される新たな欠陥密度との兼ね合いで決められる。 Considering these points, it is desirable that the depth d of the recombination suppression region 16 reaches the channel dope layer at least. In this case, the depth d is about 0.1 to 0.3 μm, and even if it is formed by ion implantation, it is possible to minimize the generation of new defects with low energy. The upper limit of the depth d is about the same as the depth of the gate region 13, but this value is determined when forming the depth of the gate region 13 of an individual device and the recombination suppression region 16 of that depth. This is determined in consideration of a new defect density generated by ion implantation energy.
　ｐ－再結合抑制領域１６には、高抵抗層との間でｐｎ接合を形成することにより再結合抑制領域１６への電子の進入を抑制し、かつ正孔濃度が低いことが求められる。そのため、再結合抑制領域１６の不純物濃度に関しては、高抵抗層と同程度かやや高い値が適切である。 The p − recombination suppression region 16 is required to have a low hole concentration while suppressing entry of electrons into the recombination suppression region 16 by forming a pn junction with the high resistance layer. For this reason, the impurity concentration in the recombination suppression region 16 is appropriately the same as or slightly higher than that of the high resistance layer.
　図１の第１実施例の場合には、高抵抗層１４の不純物濃度が５×１０１５～５×１０１７ｃｍ－３程度であるので、再結合抑制領域１６の不純物濃度の適正値は５×１０１５～５×１０１７ｃｍ－３あるいはこれよりもやや高い値となる。 In the case of the first embodiment of FIG. 1, since the impurity concentration of the high resistance layer 14 is about 5 × 10 15 to 5 × 10 17 cm −3 , the appropriate value of the impurity concentration of the recombination suppression region 16 is 5 × 10 15 to 5 × 10 17 cm −3 or slightly higher than this.
　再結合抑制領域１６は高抵抗層１４よりも抵抗率がさらに高いｎ－領域で形成しても良い。その場合には再結合抑制領域１６中の電子濃度が低くなり、さらにゲート領域１３と再結合抑制領域１６との間に形成されるｐｎ接合の接合電位が正孔に対する電位障壁となり、正孔が領域３１内に流れ込むことが抑制される。その結果、領域３１での再結合が抑制される。ｎ－型の再結合抑制領域１６を形成する場合には、注入不純物濃度は高抵抗層１４と同程度かやや低い値が適切であり、高抵抗層１４中のｎ型不純物濃度からイオン注入したｐ型不純物濃度を差し引いた値が再結合抑制領域の実質的な不純物濃度となる。図１の第１実施例の場合には、５×１０１５～５×１０１７ｃｍ－３よりもやや低い値が不純物濃度の適正値となる。 The recombination suppression region 16 may be formed of an n − region having a higher resistivity than the high resistance layer 14. In that case, the electron concentration in the recombination suppression region 16 becomes low, and the junction potential of the pn junction formed between the gate region 13 and the recombination suppression region 16 becomes a potential barrier against holes, and The flow into the region 31 is suppressed. As a result, recombination in the region 31 is suppressed. When forming the n − -type recombination suppression region 16, the implanted impurity concentration is appropriately the same as or slightly lower than that of the high resistance layer 14, and ions are implanted from the n type impurity concentration in the high resistance layer 14. The value obtained by subtracting the p-type impurity concentration is the substantial impurity concentration in the recombination suppression region. In the case of the first embodiment of FIG. 1, a value slightly lower than 5 × 10 15 to 5 × 10 17 cm −3 is an appropriate value of the impurity concentration.
　よって、再結合抑制領域１６へのイオン注入量としては、高抵抗層１４の不純物濃度と同程度前後の値が適切であると言える。 Therefore, it can be said that a value around the same level as the impurity concentration of the high resistance layer 14 is appropriate as the ion implantation amount into the recombination suppression region 16.
　イオン注入層を活性化するプロセス（ステップＳ１８）では、イオン注入後に、注入イオンを半導体中で電気的に活性化すると共に、イオン注入で発生した結晶欠陥を消すための熱処理を行う（図６Ｂ（ｅ））。この活性化の熱処理では、ゲート領域１３の注入イオンと再結合抑制領域１６の注入イオンの両方の活性化を同時に行っている。高周波熱処理炉などを用い、１７００～１８００℃程度の高温下で約１０分程度の熱処理を行う。雰囲気ガスには例えばアルゴンガス（Ａｒ）を用いる。 In the process of activating the ion-implanted layer (step S18), after the ion implantation, the implanted ions are electrically activated in the semiconductor and a heat treatment is performed to eliminate crystal defects generated by the ion implantation (FIG. 6B ( e)). In this activation heat treatment, both the implanted ions in the gate region 13 and the implanted ions in the recombination suppression region 16 are activated at the same time. Using a high-frequency heat treatment furnace or the like, heat treatment is performed at a high temperature of about 1700 to 1800 ° C. for about 10 minutes. For example, argon gas (Ar) is used as the atmospheric gas.
　表面保護膜を形成するプロセス（ステップＳ１９）では、図６Ｂ（ｆ）で示すように、初めに、イオン注入工程と活性化工程で生じた表面層を取り除くために、熱酸化後に酸化膜を取り除く犠牲酸化を行う。酸化条件は、例えばドライ酸素中で１１００℃、２０時間などである。酸化膜の除去にはフッ化水素を用いる。犠牲酸化後に再び熱酸化を行い酸化膜５４を形成する。熱酸化膜形成条件は、例えば、温度が１１００℃、時間が５時間、雰囲気はウェットである。その後、ＳｉＣ酸化膜界面の不純物準位を低減するための熱処理（ＰＯＡ：Post Oxidation Anneal)を行う。ＰＯＡは、水素や酸化窒素（ＮＯ、Ｎ２Ｏ）またはアルゴン雰囲気中で、８００～１３００℃程度の高温下で、１０～３０分程度、行う。ＰＯＡ後、ＣＶＤ酸化膜やＣＶＤ窒化膜を形成する。 In the process of forming the surface protective film (step S19), as shown in FIG. 6B (f), first, in order to remove the surface layer generated in the ion implantation step and the activation step, the oxide film is removed after the thermal oxidation. Perform sacrificial oxidation. The oxidation condition is, for example, 1100 ° C. for 20 hours in dry oxygen. Hydrogen fluoride is used to remove the oxide film. After the sacrificial oxidation, thermal oxidation is performed again to form an oxide film 54. The thermal oxide film formation conditions are, for example, a temperature of 1100 ° C., a time of 5 hours, and an atmosphere of wet. Thereafter, heat treatment (POA: Post Oxidation Anneal) is performed to reduce the impurity level at the interface of the SiC oxide film. POA is performed in a hydrogen, nitrogen oxide (NO, N 2 O) or argon atmosphere at a high temperature of about 800 to 1300 ° C. for about 10 to 30 minutes. After POA, a CVD oxide film or a CVD nitride film is formed.
　電極を形成するプロセス（ステップＳ２０）では、ソース領域１２（低抵抗層４４）、ゲート領域１３、ドレイン領域１１（基板４０）の各々の表面にソース電極１９、ゲート電極２０、ドレイン電極１８を形成する（図６Ｂ（ｇ））。ソース電極１９、ドレイン電極１８にはニッケルやチタンを用い、ゲート電極２０にはチタン／アルミニウム積層膜などを用いる。各電極１８，１９，２０は、蒸着やスパッタリングなどで形成する。電極パターンの形成には、ドライエッチング、ウェットエッチング、リフトオフ法などが利用される。また電極１８～２０を形成した後には、金属部分と半導体部分との間の接触抵抗を低減するために熱処理を行う。当該熱処理の条件は、温度条件が８００～１０００℃、時間条件が１０～３０分程度である。 In the process of forming electrodes (step S20), the source electrode 19, the gate electrode 20, and the drain electrode 18 are formed on the surfaces of the source region 12 (low resistance layer 44), the gate region 13, and the drain region 11 (substrate 40). (FIG. 6B (g)). The source electrode 19 and the drain electrode 18 are made of nickel or titanium, and the gate electrode 20 is made of a titanium / aluminum laminated film. Each electrode 18, 19, 20 is formed by vapor deposition or sputtering. For the formation of the electrode pattern, dry etching, wet etching, lift-off method or the like is used. Further, after the electrodes 18 to 20 are formed, heat treatment is performed to reduce the contact resistance between the metal portion and the semiconductor portion. The heat treatment conditions are a temperature condition of 800 to 1000 ° C. and a time condition of about 10 to 30 minutes.
　最後に上層電極形成プロセス（ステップＳ２１）が実行される。この上層電極形成プロセス（ステップＳ２１）では、分離されている複数のソース電極１９を１つの電極に取り出すための上層配線５６を形成する（図６Ｂ（ｈ））。ＣＶＤ法によりシリコン酸化膜などを層間膜５５として形成した後、フォトリソグラフィーとエッチングによりソース電極１９の部分のシリコン酸化膜などを取り除く。こうしてソース電極１９を露出させた後に、上層電極５６を堆積させる。上層電極５６の材料には例えばアルミニウム（Ａｌ）を用いる。 Finally, the upper layer electrode formation process (step S21) is executed. In this upper layer electrode formation process (step S21), an upper layer wiring 56 for taking out the plurality of separated source electrodes 19 to one electrode is formed (FIG. 6B (h)). After a silicon oxide film or the like is formed as the interlayer film 55 by the CVD method, the silicon oxide film or the like in the portion of the source electrode 19 is removed by photolithography and etching. After the source electrode 19 is exposed in this way, the upper layer electrode 56 is deposited. For example, aluminum (Al) is used as the material of the upper layer electrode 56.
　このようにして、図１と図２で示したＳＩＴ１０が作製される。当該ＳＩＴ１０は、ノーマリオフ特性を有する高性能の接合型半導体装置である。 In this way, the SIT 10 shown in FIGS. 1 and 2 is manufactured. The SIT 10 is a high-performance junction type semiconductor device having normally-off characteristics.
　上記第１実施例において、ドレイン領域、ソース領域、高抵抗層、ゲート領域、再結合抑制領域等の第１および第２の導電型の組合せをすべて逆にして構成することもできる。この点については、以下に説明する実施例においても同様である。 In the first embodiment, the combinations of the first and second conductivity types such as the drain region, the source region, the high resistance layer, the gate region, and the recombination suppression region may be reversed. This also applies to the embodiments described below.
　＜第２実施例＞
　図９を参照して本発明による接合型半導体装置の第２実施例を説明する。第２実施例による接合型半導体装置も同様にまたＳＩＴである。図９において、図１で説明した要素と実質的に同一の要素には同一の符号を付している。第２実施例によるＳＩＴ１００では、ゲート領域１３の側面に形成される再結合抑制領域７１をチャネルドープ層１５が形成された箇所よりも浅い位置に形成している点に特徴がある。その他の構成については第１実施例で説明した構成と同じである。 <Second embodiment>
A second embodiment of the junction type semiconductor device according to the present invention will be described with reference to FIG. The junction type semiconductor device according to the second embodiment is also SIT. 9, elements that are substantially the same as those described in FIG. 1 are denoted by the same reference numerals. The SIT 100 according to the second embodiment is characterized in that the recombination suppression region 71 formed on the side surface of the gate region 13 is formed at a position shallower than the portion where the channel dope layer 15 is formed. Other configurations are the same as those described in the first embodiment.
　ＳＩＴ１００の構成によれば、次の利点を有する。再結合抑制領域７１はイオン注入によって形成しているため、少量ではあるが、イオン注入時に損傷が生じる。この損傷は、その後の活性化熱処理によっても完全に消滅しない。これを改善するためには、イオン注入のためのエネルギを低く抑え、イオン注入時の損傷がより少なくかつより高品質の再結合抑制領域７１を形成することが有効である。正孔と電子の再結合は、電流が集中しやすいチャネルドープ層１５よりも浅い領域部分で激しく起きるため、当該領域部分のみに再結合抑制領域７１を形成しただけでも十分に本発明の効果を達成することができる。第２実施例の構成は、特に、ＳＩＴ１００のデバイス構造上で上側に位置する第２の高抵抗層１４の厚みが大きい場合などに有効である。 The configuration of SIT100 has the following advantages. Since the recombination suppression region 71 is formed by ion implantation, although it is a small amount, damage occurs during ion implantation. This damage is not completely eliminated by the subsequent activation heat treatment. In order to improve this, it is effective to reduce the energy for ion implantation and to form a recombination suppression region 71 with less damage and higher quality during ion implantation. The recombination of holes and electrons occurs violently in a region shallower than the channel dope layer 15 where current tends to concentrate. Therefore, even if the recombination suppression region 71 is formed only in the region, the effect of the present invention is sufficiently obtained. Can be achieved. The configuration of the second embodiment is particularly effective when the thickness of the second high resistance layer 14 located on the upper side of the device structure of the SIT 100 is large.
　＜第３実施例＞
　図１０を参照して本発明による接合型半導体装置の第３実施例を説明する。第３実施例による接合型半導体装置はＳＩＴである。図１０において、図１で説明した要素と実質的に同一の要素には同一の符号を付している。第３実施例によるＳＩＴ２００では、再結合抑制領域７２は、ゲート領域１３の側面と底面の部分、すなわちゲート領域１３の他の部分との境界部を作る全領域を覆うように形成されている。その他の構成については第１実施例で説明した構成と同じである。 <Third embodiment>
A third embodiment of the junction type semiconductor device according to the present invention will be described with reference to FIG. The junction type semiconductor device according to the third embodiment is SIT. 10, elements that are substantially the same as those described in FIG. 1 are denoted by the same reference numerals. In the SIT 200 according to the third embodiment, the recombination suppressing region 72 is formed so as to cover the entire region that forms the boundary portion between the side surface and the bottom surface portion of the gate region 13, that is, the other portion of the gate region 13. Other configurations are the same as those described in the first embodiment.
　ＳＩＴ２００の構成によれば、ゲート領域形成時にイオン注入で発生した再結合準位のほとんどすべてを再結合抑制領域７２によって覆うことができる。ＳＩＴ２００の製造方法は、図８に示した製造方法を応用することにより実現することができる。すなわち、図８に示された製造方法において、ゲート領域１３の深さよりも再結合抑制領域１６をより深かく形成することにより、図１０に示した構造を有するＳＩＴ２００を製造することできる。再結合抑制領域１６を形成するイオン注入のための注入エネルギは高くなるが、再結合抑制領域１６のイオン注入量はゲート領域１３のイオン注入量よりも極めてすくないので、結晶での損傷を少なくすることができる。この第３の実施例の構成は、ゲート領域１３の深さが浅い場合などにおいてより有効である。 According to the configuration of the SIT 200, almost all of the recombination levels generated by ion implantation at the time of forming the gate region can be covered by the recombination suppression region 72. The manufacturing method of the SIT 200 can be realized by applying the manufacturing method shown in FIG. That is, the SIT 200 having the structure shown in FIG. 10 can be manufactured by forming the recombination suppression region 16 deeper than the depth of the gate region 13 in the manufacturing method shown in FIG. Although the implantation energy for ion implantation for forming the recombination suppression region 16 is high, the ion implantation amount in the recombination suppression region 16 is much less than the ion implantation amount in the gate region 13, thereby reducing damage to the crystal. be able to. The configuration of the third embodiment is more effective when the gate region 13 is shallow.
　＜第４実施例＞
　図１１を参照して、本発明による接合型半導体装置の第４実施例を説明する。第４実施例による接合型半導体装置はＢＪＴ（バイポーラ接合トランジスタ）の例を示している。図１１において、ＢＪＴ３００は、コレクタ領域３１１、エミッタ領域３１２、ベースコンタクト領域３１３、上下の高抵抗層３１４、ベース領域３１５を備える。 <Fourth embodiment>
With reference to FIG. 11, a description will be given of a fourth embodiment of the junction type semiconductor device according to the present invention. The junction type semiconductor device according to the fourth embodiment shows an example of BJT (bipolar junction transistor). In FIG. 11, the BJT 300 includes a collector region 311, an emitter region 312, a base contact region 313, upper and lower high resistance layers 314, and a base region 315.
　ＢＪＴ３００のベース領域３１５は、ＳＩＴの前述のチャネルドープ層に対応している。さらにコレクタ領域３１１、エミッタ領域３１２、ベースコンタクト領域３１３のそれぞれには、コレクタ電極３２１、エミッタ電極３２２、ベース電極３２３が接合されている。 The base region 315 of the BJT 300 corresponds to the aforementioned channel dope layer of SIT. Further, a collector electrode 321, an emitter electrode 322, and a base electrode 323 are joined to the collector region 311, the emitter region 312, and the base contact region 313, respectively.
　ＢＪＴ３００において、主電流である電子は、エミッタ領域３１２からコレクタ領域３１１へ流れる。ベースコンタクト領域３１３は、前述したＳＩＴ１０のゲート領域１３に対応し、制御信号が供給される。ＢＪＴ３００のデバイス表面において、エミッタ電極３２２とベース電極３２３との間の露出表面には表面保護膜３１６が設けられている。本実施例によるＢＪＴ３００においても、ベースコンタクト領域３１３の側面および底面の全周囲面は、再結合抑制領域３１７で覆われている。 In the BJT 300, electrons that are the main current flow from the emitter region 312 to the collector region 311. The base contact region 313 corresponds to the gate region 13 of the SIT 10 described above and is supplied with a control signal. A surface protective film 316 is provided on the exposed surface between the emitter electrode 322 and the base electrode 323 on the device surface of the BJT 300. Also in the BJT 300 according to the present embodiment, the entire peripheral surface of the side surface and the bottom surface of the base contact region 313 is covered with the recombination suppression region 317.
　＜第５実施例＞
　図１２を参照して、本発明による接合型半導体装置の第５実施例を説明する。第５実施例による接合型半導体装置も第４実施例と同様にＢＪＴの例を示している。図１２において、図１１で説明した要素と同一の要素には同一の符号を付し、説明を省略する。第５実施例によるＢＪＴ４００は、ベースコンタクト領域３１３の側面の周囲であって、ベース領域３１５の上側の範囲で再結合抑制領域４１１が形成されている点に特徴がある。 <Fifth embodiment>
A fifth embodiment of the junction type semiconductor device according to the present invention will be described with reference to FIG. The junction type semiconductor device according to the fifth embodiment also shows an example of BJT as in the fourth embodiment. 12, the same elements as those described in FIG. 11 are denoted by the same reference numerals, and the description thereof is omitted. The BJT 400 according to the fifth embodiment is characterized in that the recombination suppression region 411 is formed in the range around the side surface of the base contact region 313 and above the base region 315.
　以上説明したように、本発明は従来の接合型半導体装置と異なり、ゲート領域あるいはベースコンタクト領域の側面等に再結合抑制領域が設けられる。このため、例えば、ゲート領域から注入される少数キャリアとソース領域から注入される多数キャリアの再結合が抑制され、接合型半導体装置の電流増幅率を向上でき、オン電圧（抵抗）を小さくできる。 As described above, unlike the conventional junction type semiconductor device, the present invention is provided with the recombination suppression region on the side surface of the gate region or the base contact region. For this reason, for example, recombination of minority carriers injected from the gate region and majority carriers injected from the source region is suppressed, the current amplification factor of the junction semiconductor device can be improved, and the on-voltage (resistance) can be reduced.
　各層の厚みやイオン注入エネルギー量等の本実施例で示した具体的な数値はあくまでも一例であり、本発明を実現する範囲で適宜に変更可能である。 The specific numerical values shown in this embodiment such as the thickness of each layer and the amount of ion implantation energy are merely examples, and can be appropriately changed within the scope of realizing the present invention.
　本実施例においては、製造方法の工程の説明中のｐとｎの極性を逆にした逆極性タイプのものでも良い。さらに本実施例では、ＳｉＣの例について説明したが、本発明は再結合が問題となる他の半導体にも適用できる。 In this embodiment, a reverse polarity type in which the polarities of p and n in the description of the process of the manufacturing method are reversed may be used. Furthermore, in the present embodiment, an example of SiC has been described, but the present invention can also be applied to other semiconductors in which recombination is a problem.
　以上、各実施例で説明された構成、形状、大きさおよび配置関係については本発明が理解・実施できる程度に概略的に示したものにすぎず、さらに数値および各構成の組成（材質）等については例示にすぎない。従って本発明は、説明された実施例に限定されるものではなく、請求の範囲に示された技術的思想の範囲を逸脱しない限り様々な形態に変更することができる。 The configurations, shapes, sizes, and arrangement relationships described in the above embodiments are merely schematically shown to the extent that the present invention can be understood and implemented. Further, numerical values and compositions (materials) of the respective components, etc. Is merely an example. Therefore, the present invention is not limited to the described embodiments, and can be modified in various forms without departing from the scope of the technical idea shown in the claims.
　本発明は、高性能の接合型半導体装置とそれを製造するために利用することができる。 The present invention can be used for manufacturing a high performance junction type semiconductor device.
　１０　接合型半導体装置（ＳＩＴ）
　１１　ドレイン領域
　１２　ソース領域
　１３　ゲート領域
　１４　高抵抗層
　１５　チャネルドープ層
　１６　再結合抑制領域
　１７　表面保護膜
　１８　ドレイン電極
　１９　ソース電極
　２０　ゲート電極
　２１　上層電極
　４０　基板
　４１，４３　高抵抗層
　４２　チャネルドープ層
　４４　低抵抗層
　１００　接合型半導体装置（ＳＩＴ）
　２００　接合型半導体装置（ＳＩＴ）
　３００　接合型半導体装置（ＢＪＴ）
　４００　接合型半導体装置（ＢＪＴ） 10 Junction semiconductor devices (SIT)
DESCRIPTION OF SYMBOLS 11 Drain region 12 Source region 13 Gate region 14 High resistance layer 15 Channel dope layer 16 Recombination suppression region 17 Surface protective film 18 Drain electrode 19 Source electrode 20 Gate electrode 21 Upper layer electrode 40 Substrate 41, 43 High resistance layer 42 Channel dope layer 44 Low resistance layer 100 Junction type semiconductor device (SIT)
200 Junction semiconductor devices (SIT)
300 Junction semiconductor device (BJT)
400 Junction type semiconductor device (BJT)

Claims (19)

  1. 　炭化珪素の半導体結晶で作られた基板である第１の主電極用領域と、
    　前記基板の１つの面の側に形成された第２の主電極用領域と、
    　前記の第１および第２の主電極用領域の間に形成された高抵抗層と、
    　前記第２の主電極用領域の周囲に形成された制御電極用領域と、
    　前記制御電極用領域の少なくとも側面を覆うように形成された再結合抑制領域と、
    　を有することを特徴とする接合型半導体装置。     A first main electrode region which is a substrate made of a silicon carbide semiconductor crystal;
    A second main electrode region formed on one side of the substrate;
    A high resistance layer formed between the first and second main electrode regions;
    A control electrode region formed around the second main electrode region;
    A recombination suppression region formed so as to cover at least a side surface of the control electrode region;
    A junction type semiconductor device comprising:
  2. 　前記高抵抗層内に前記制御電極用領域に接触するチャネルドープ層を有し、前記再結合抑制領域は前記チャネルドープ層が形成された深さ位置まで形成されることを特徴とする請求項１に記載の接合型半導体装置。 2. The channel doped layer in contact with the control electrode region in the high resistance layer, and the recombination suppression region is formed to a depth position where the channel doped layer is formed. 2. A junction type semiconductor device according to 1.
  3. 　前記再結合抑制領域は、前記制御電極用領域の側面と底面を覆うように形成されていることを特徴とする請求項１に記載の接合型半導体装置。 2. The junction type semiconductor device according to claim 1, wherein the recombination suppression region is formed so as to cover a side surface and a bottom surface of the control electrode region.
  4. 　前記第１の主電極用領域は第１の導電型の低抵抗層からなるドレイン領域であり、
    　前記第２の主電極用領域は第１の導電型の低抵抗層からなるソース領域であり、
    　前記制御電極用領域は、第２の導電型のゲート領域であり、
    　前記再結合抑制領域は、前記ゲート領域と同じ導電型でありかつ前記ゲート領域よりも高い抵抗率を有するか、または前記高抵抗層と同じ導電型でありかつ前記高抵抗層よりも高い抵抗率を有することを特徴とする請求項１に記載の接合型半導体装置。     The first main electrode region is a drain region composed of a low resistance layer of the first conductivity type,
    The second main electrode region is a source region made of a low resistance layer of the first conductivity type,
    The control electrode region is a gate region of a second conductivity type,
    The recombination suppression region has the same conductivity type as the gate region and a higher resistivity than the gate region, or the same conductivity type as the high resistance layer and a higher resistivity than the high resistance layer. The junction type semiconductor device according to claim 1, comprising:
  5. 　前記第１の主電極用領域は、第２の導電型の低抵抗層からなるドレイン領域であり、
    　前記第２の主電極用領域は、第２の導電型の低抵抗層からなるソース領域であり、
    　前記制御電極用領域は、第１の導電型のゲート領域であり、
    　前記再結合抑制領域は、前記ゲート領域と同じ導電型でありかつ前記ゲート領域よりも高い抵抗率を有するか、または前記高抵抗層と同じ導電型でありかつ前記高抵抗層よりも高い抵抗率を有することを特徴とする請求項１に記載の接合型半導体装置。     The first main electrode region is a drain region composed of a low-resistance layer of the second conductivity type,
    The second main electrode region is a source region composed of a low-resistance layer of the second conductivity type,
    The control electrode region is a gate region of a first conductivity type,
    The recombination suppression region has the same conductivity type as the gate region and a higher resistivity than the gate region, or the same conductivity type as the high resistance layer and a higher resistivity than the high resistance layer. The junction type semiconductor device according to claim 1, comprising:
  6. 　前記第１の主電極用領域は、第１の導電型の低抵抗層からなるコレクタ領域であり、
    　前記第２の主電極用領域は、第１の導電型の低抵抗層からなるエミッタ領域であり、
    　前記制御電極用領域は、第２の導電型のベースコンタクト領域であり、
    　前記再結合抑制領域は、前記ベースコンタクト領域と同じ導電型でありかつ前記ベースコンタクト領域よりも高い抵抗率を有するか、または前記高抵抗層と同じ導電型でありかつ前記高抵抗層よりも高い抵抗率を有することを特徴とする請求項１に記載の接合型半導体装置。     The first main electrode region is a collector region made of a low-resistance layer of the first conductivity type,
    The second main electrode region is an emitter region composed of a low resistance layer of the first conductivity type,
    The control electrode region is a base contact region of a second conductivity type,
    The recombination suppression region has the same conductivity type as the base contact region and a higher resistivity than the base contact region, or the same conductivity type as the high resistance layer and higher than the high resistance layer The junction type semiconductor device according to claim 1, wherein the junction type semiconductor device has a resistivity.
  7. 　前記第１の主電極用領域は、第２の導電型の低抵抗層からなるコレクタ領域であり、
    　前記第２の主電極用領域は、第２の導電型の低抵抗層からなるエミッタ領域であり、
    　前記制御電極用領域は、第１の導電型のベースコンタクト領域であり、
    　前記再結合抑制領域は、前記ベースコンタクト領域と同じ導電型でありかつ前記ベースコンタクト領域よりも高い抵抗率を有するか、または前記高抵抗層と同じ導電型でありかつ前記高抵抗層よりも高い抵抗率を有することを特徴とする請求項１に記載の接合型半導体装置。     The first main electrode region is a collector region composed of a low-resistance layer of the second conductivity type,
    The second main electrode region is an emitter region made of a low-resistance layer of the second conductivity type,
    The control electrode region is a base contact region of a first conductivity type,
    The recombination suppression region has the same conductivity type as the base contact region and a higher resistivity than the base contact region, or the same conductivity type as the high resistance layer and higher than the high resistance layer The junction type semiconductor device according to claim 1, wherein the junction type semiconductor device has a resistivity.
  8. 　炭化珪素の半導体結晶で作られかつ第１の主電極用領域となる基板の上に高抵抗層を形成する第１の工程と、
    　前記高抵抗層の上に第２の主電極用領域となる低抵抗層を形成する第２の工程と、
    　前記高抵抗層の表面側の所定領域にイオン注入により制御電極用領域を形成する第３の工程と、
    　前記制御電極用領域の少なくとも側面を覆うようにイオン注入により再結合抑制領域を形成する第４の工程と、
    　を含むことを特徴とする接合型半導体装置の製造方法。     A first step of forming a high resistance layer on a substrate made of a semiconductor crystal of silicon carbide and serving as a first main electrode region;
    A second step of forming a low resistance layer to be a second main electrode region on the high resistance layer;
    A third step of forming a control electrode region by ion implantation in a predetermined region on the surface side of the high resistance layer;
    A fourth step of forming a recombination suppression region by ion implantation so as to cover at least a side surface of the control electrode region;
    The manufacturing method of the junction type semiconductor device characterized by the above-mentioned.
  9. 　前記再結合抑制領域を形成するためにイオン注入される不純物濃度は、前記制御電極用領域を形成するためにイオン注入される不純物濃度よりも低いことを特徴とする請求項８に記載の接合型半導体装置の製造方法。 9. The junction type according to claim 8, wherein an impurity concentration ion-implanted to form the recombination suppression region is lower than an impurity concentration ion-implanted to form the control electrode region. A method for manufacturing a semiconductor device.
  10. 　前記高抵抗層の中にチャネルドープ層を形成するための工程を設けたことを特徴とする請求項８に記載の接合型半導体装置の製造方法。 9. The method of manufacturing a junction type semiconductor device according to claim 8, further comprising a step of forming a channel dope layer in the high resistance layer.
  11. 　前記基板、前記高抵抗層、および前記低抵抗層は第１の導電型であり、前記制御電極用領域は第２の導電型であることを特徴とする請求項８に記載の接合型半導体装置の製造方法。 9. The junction type semiconductor device according to claim 8, wherein the substrate, the high resistance layer, and the low resistance layer are of a first conductivity type, and the control electrode region is of a second conductivity type. Manufacturing method.
  12. 　前記基板、前記高抵抗層、および前記低抵抗層は第２の導電型であり、前記制御電極用領域は第１の導電型であることを特徴とする請求項８に記載の接合型半導体装置の製造方法。 9. The junction type semiconductor device according to claim 8, wherein the substrate, the high resistance layer, and the low resistance layer are of a second conductivity type, and the control electrode region is of a first conductivity type. Manufacturing method.
  13. 　前記第１の主電極用領域、前記第２の主電極用領域、および前記制御電極用領域のそれぞれに、第１主電極、第２主電極、制御電極を形成する工程と、
    　前記２主電極と前記制御電極の上側に上層電極を形成する工程と、
    　を有することを特徴とする請求項８に記載の接合型半導体装置の製造方法。     Forming a first main electrode, a second main electrode, and a control electrode in each of the first main electrode region, the second main electrode region, and the control electrode region;
    Forming an upper layer electrode above the two main electrodes and the control electrode;
    The method for manufacturing a junction type semiconductor device according to claim 8, wherein:
  14. 　炭化珪素の半導体結晶で作られかつ第１の主電極用領域となる基板の上に高抵抗層を形成する第１の工程と、
    　前記高抵抗層の上に第２の主電極用領域となる低抵抗層を形成する第２の工程と、
    　前記高抵抗層の表面側の所定領域にイオン注入により再結合抑制領域を形成する第３の工程と、
    　前記再結合抑制領域に、前記再結合抑制領域の表面側からイオン注入により制御電極用領域を形成する第４の工程と、
    　を含むことを特徴とする接合型半導体装置の製造方法。     A first step of forming a high resistance layer on a substrate made of a semiconductor crystal of silicon carbide and serving as a first main electrode region;
    A second step of forming a low resistance layer to be a second main electrode region on the high resistance layer;
    A third step of forming a recombination suppression region by ion implantation in a predetermined region on the surface side of the high resistance layer;
    A fourth step of forming a control electrode region in the recombination suppression region by ion implantation from the surface side of the recombination suppression region;
    The manufacturing method of the junction type semiconductor device characterized by the above-mentioned.
  15. 　前記再結合抑制領域を形成するためにイオン注入される不純物濃度は、前記制御電極用領域を形成するためにイオン注入される不純物濃度よりも低いことを特徴とする請求項１４に記載の接合型半導体装置の製造方法。 15. The junction type according to claim 14, wherein an impurity concentration ion-implanted to form the recombination suppression region is lower than an impurity concentration ion-implanted to form the control electrode region. A method for manufacturing a semiconductor device.
  16. 　前記高抵抗層の中にチャネルドープ層を形成するための工程を設けたことを特徴とする請求項１４に記載の接合型半導体装置の製造方法。 15. The method of manufacturing a junction type semiconductor device according to claim 14, further comprising a step of forming a channel dope layer in the high resistance layer.
  17. 　前記基板、前記高抵抗層、および前記低抵抗層は第１の導電型であり、前記制御電極用領域は第２の導電型であることを特徴とする請求項１４に記載の接合型半導体装置の製造方法。 15. The junction type semiconductor device according to claim 14, wherein the substrate, the high resistance layer, and the low resistance layer are of a first conductivity type, and the control electrode region is of a second conductivity type. Manufacturing method.
  18. 　前記基板、前記高抵抗層、および前記低抵抗層は第２の導電型であり、前記制御電極用領域は第１の導電型であることを特徴とする請求項１４に記載の接合型半導体装置の製造方法。 15. The junction type semiconductor device according to claim 14, wherein the substrate, the high resistance layer, and the low resistance layer are of a second conductivity type, and the control electrode region is of a first conductivity type. Manufacturing method.
  19. 　前記第１の主電極用領域、前記第２の主電極用領域、および前記制御電極用領域のそれぞれに、第１主電極、第２主電極、制御電極を形成する工程と、
    　前記２主電極と前記制御電極の上側に上層電極を形成する工程と、
    　を有することを特徴とする請求項１４に記載の接合型半導体装置の製造方法。     Forming a first main electrode, a second main electrode, and a control electrode in each of the first main electrode region, the second main electrode region, and the control electrode region;
    Forming an upper layer electrode above the two main electrodes and the control electrode;
    The method of manufacturing a junction type semiconductor device according to claim 14, wherein:
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