WO2009153728A1 - Procédé de remplissage à travers les traversées d'une tranche - Google Patents

Procédé de remplissage à travers les traversées d'une tranche Download PDF

Info

Publication number
WO2009153728A1
WO2009153728A1 PCT/IB2009/052541 IB2009052541W WO2009153728A1 WO 2009153728 A1 WO2009153728 A1 WO 2009153728A1 IB 2009052541 W IB2009052541 W IB 2009052541W WO 2009153728 A1 WO2009153728 A1 WO 2009153728A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductive material
wafer
filling
laser
conductive
Prior art date
Application number
PCT/IB2009/052541
Other languages
English (en)
Inventor
Jinesh Balakrishna Pillai Kochupurackal
Yann Pierre Roger Lamy
Original Assignee
Nxp B.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp B.V. filed Critical Nxp B.V.
Publication of WO2009153728A1 publication Critical patent/WO2009153728A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/032—Materials
    • H05K2201/0329—Intrinsically conductive polymer [ICP]; Semiconductive polymer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
    • H05K2203/107—Using laser light
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/12—Using specific substances
    • H05K2203/128—Molten metals, e.g. casting thereof, or melting by heating and excluding molten solder

Definitions

  • the present invention relates to a method of filling a via extending through a wafer such as a silicon wafer.
  • aggregate devices that comprise more than one integrated circuit die in the packaged device.
  • aggregate devices include die-on-die devices, die-on-wafers devices and stacked wafer devices, which may also be referred to as systems in package.
  • a problem associated with such aggregated devices is that the provision of contacts between different dies and/or wafers poses a serious design challenge for the designers of such devices.
  • the concept of through- silicon- vias has been developed, in which a via is extended through a silicon wafer such that a direct connection between dies on opposite sides of the silicon wafer can be provided.
  • the formation of the via itself can be readily achieved by readily available techniques such as etching or drilling, the subsequent filling of the vias is far from trivial.
  • EP application No 0 256 494 A2 discloses an activatable conductive link structure in a semiconductor device, wherein a void opening in an insulating layer is surrounded by an aluminum alloy conductive track, which is heated by a laser such that a part of the conductive track flows into the void, thereby forming a conductive connection between conductive tracks of the semiconductor device.
  • this technique is of limited use for through- wafer applications, because the conductive contacts that need connecting are usually not already present on the wafer, but may be provided on separate dies that will be mounted on opposite sides of the wafer.
  • the use of the aluminum alloy of the conductive track to fill the void causes a reduction of thickness in the conductive track, thereby increasing the risk of performance degradation of the conductive track. This risk can only be avoided by increasing the thickness of the conductive track, which adds to the cost of the semiconductor device.
  • the present invention seeks to provide a method of providing a method of filling a via extending through a silicon wafer that can provide a reliable conductive contact without requiring long wafer processing times.
  • a method of filling a via extending through a wafer comprising covering the via by depositing a portion of a conductive material over the via; and filling the via with the conductive material by irradiating the portion with a laser during a predefined time period, thereby bringing the conductive material in a fluid state.
  • the inventive filling techniques reduces the via filling time by several orders compared to recommended electroplating techniques, and facilitates the use of a wide variety of conductive materials other than copper, thus avoiding the aforementioned problems associated with the use of copper in silicon- based processes.
  • the present invention relies on the use of conductive materials that have a lower viscosity than water in the laser- induced fluid state. This is because in contrast to the prior art vias in e.g.
  • the through-silicon-vias of the present invention typically have a large aspect ratio, i.e. a much larger length than width, which makes filling these vias a far from trivial exercise. It has been realized by the present inventors that for such high aspect ratio vias, capillary forces play a key role in filling such vias.
  • the choice of a conductive material that in its laser-induced fluid state has a lower viscosity than water ensures that these materials are suitable for filling these vias through capillary force.
  • the depositing step comprises injection printing or sputtering the portion over the via. This is advantageous because it is possible to accurately control the portion size using such techniques, thereby providing an accurate way of controlling the amount of conductive material to be transferred into the via.
  • alternative depositing steps such as vapor depositing the portion over the via or paste-printing the portion over the via are also feasible.
  • said depositing step may comprise providing a film of the conductive material over the wafer such that the via is covered by said film, after which the film may be patterned to yield the portions of the via.
  • the method further comprises coating the via with a thermal insulator layer prior to said covering step.
  • a thermal insulator layer is a silicon oxide layer, which may be deposited in any suitable way, such as a chemical vapor deposition step or by oxidation of the surface of a silicon wafer.
  • the method further comprises at least partially coating the via with a thin film of the conductive material prior to said covering step.
  • the reduction of the width of the via e.g. by the introduction of a plug or neck of the conductive material in the opening of the via, has the advantage that the capillary effect for filling the via is promoted, which facilitates efficient filling of the via during the laser exposure step.
  • the partial coating of the via and the deposition of the conductive material portion over the via may be performed simultaneously by means of a fast electroplating step to reduce the number of process steps.
  • the method may further comprise providing a mask exposing the vias in the wafer prior to said partially coating step.
  • said irradiation step comprises intermittently irradiating said conductive material during said predefined time period.
  • This may for instance be realized with a pulsed laser such as an excimer laser, and has the advantage that premature solidification of the conductive material is avoided.
  • the conductive material may be a metal such as Al, Ag or Sn.
  • the conductive material may be a conductive polymer, such as a thermoplastic. A non- limiting example of such a material is PANI.
  • a wafer having a via filled with a conductive material by the method of the present invention is provided.
  • Such a via is substantially void- free, in contrast to vias through wafers filled by prior art techniques.
  • Fig. 2 depicts an aspect of an embodiment of the method of the present invention in more detail
  • Fig. 3 depicts an aspect of an embodiment of the method of the present invention
  • Fig. 4 depicts an aspect of another embodiment of the method of the present invention
  • Fig. 5 depicts a result of a simulation of the heat transfer between a via filled with a conductive material and a silicon wafer in the absence and presence of a thermal insulator layer inside the via;
  • Fig. 6 depicts a result of a simulation of the heat transfer between a via filled with a conductive material and a silicon wafer as a function of via aspect ratio and thermal insulator layer thickness respectively.
  • Fig. Ia a silicon wafer 10 comprising a via 12 is provided.
  • the via 12 may be formed in any suitable way, for instance by means of laser drilling, by means of an anisotropic or isotropic reactive ion etch and so on.
  • the via 12 may be a blind via, which is exposed, i.e.
  • the via 12 has an aspect ratio defined by its depth 1, i.e. the thickness of the silicon wafer 10, and the radius r, although it should be understood that the shape of the via 12 is not limited to a cylindrical shape.
  • Fig. Ib depicts an optional step of the method of the present invention.
  • a thermal insulator layer 14 is grown on the inner walls of the via 12, for instance by oxidizing the surface of the Si- wafer 10.
  • a suitable insulator material may be grown on the surface of the Si- wafer 10 using e.g. PE-CVD or LP- CVD techniques. The purpose of the thermal insulator layer 14 will be explained in more detail later.
  • a portion 16 of a conductive material is deposited over the via 12.
  • the portion 16 has a volume that substantially corresponds with the volume of the via 12, such that upon melting or otherwise fluidizing the portion 16 by exposing the portion 16 to a laser for a predefined period of time, the conductive material is transferred into the via 12, as shown in Fig. Id. Assuming that the portion 16 can be described as a semi-spherical droplet of radius R, the volume of the portion 16 has to satisfy the following condition to fill up the via 12:
  • a droplet of 79 ⁇ m radius would be sufficient. That means that in general, a droplet- shaped portion 16 of approximately 1.5 times the radius of the via 12 can effectively fill the via 12.
  • the size of the droplet can be fixed by the amount of conductive material deposited on the wafer 10. For instance, inject printing or sputtering on pre-patterned wafer can be used to deposit droplets having well-controlled volumes. Such droplets typically remain solid until exposed to a heat source such as a laser, thus avoiding the risk of droplet agglomeration prior to filling the vias 12 of the wafer 10.
  • the portions 16 may be formed using any other suitable deposition technique such as a vapor deposition technique.
  • the portion 16 may be deposited in solid form, e.g. by means of vapor deposition or in a highly viscous form such as a gel, e.g. by means of inject printing or sputtering.
  • paste printing may be used.
  • conducting polymers such as poly- aniline (PANI) may also be used.
  • the deposited portions 16 will typically quickly assume a solid form due to the relatively high thermal conductivity of silicon (150AVmK). Because of this relatively high thermal conductivity of the silicon wafer, the conductive material may also cool down quickly when being transferred into the via 12 upon irradiating the portion 16 with a laser, which may prevent the full transfer of the portion 16 into the via 12. This will also depend on the aspect ratio of the via 12. In order to reduce the risk that such premature solidification of the conductive material prevents the complete filling of the via 12, the via 12 may be lined with a thermal insulator layer 14 as previously discussed.
  • the wafer 10 may be covered by a photoresist, which is subsequently patterned to expose the openings of the vias 12, after which the portions 16 of the conductive material may be deposited over the vias 12, after which the photoresist may be removed.
  • a photoresist which is subsequently patterned to expose the openings of the vias 12, after which the portions 16 of the conductive material may be deposited over the vias 12, after which the photoresist may be removed.
  • any suitable patterned layer may be applied, and the patterned layer may be removed prior to or after filling the vias 12 with the conductive material.
  • a foil of the conductive material e.g. an Al-foil, may be directly deposited over the vias 12. The specific application of the portion 16 is not essential to the present invention.
  • One or more portions 16 are irradiated, i.e. heated, with a laser 20 for a predefined period of time in order to bring the conductive material in a fluid state, e.g. by melting a solid portion 16.
  • the laser 20 is a pulsed laser such as an excimer laser. This has the advantage that the conductive material is periodically reheated such that premature solidification leading to the via 12 remaining partially unfilled can be avoided. For instance, for a IkHz excimer laser, this means that the irradiated portions 16 are reheated every 1 ms.
  • the presence of a thermal insulating layer 14 further aids the prevention of partial via filling as previously discussed.
  • the duration of the exposure of the portion 16 to the laser 20 should be sufficiently long to bring the portion 16 in its fluid state.
  • the pulse width of the laser 20 should be set accordingly. However, it should be understood that any suitable type of laser may be used, e.g. a CO 2 laser.
  • the number of laser pulses, the laser pulse frequency and/or the laser irradiation period should be optimized such that the vias 12 are fully filled with the conductive material.
  • the optimized irradiation parameters will depend on the used conductive material and the dimensions of the via 12.
  • the use of such optimized irradiation parameters such as the optimization of the number of applies pulses avoids formation of voids in the via 12.
  • the several pulses guaranty a good homogeneity of the filling, because this technique allows for re-melting of the conductive material inside the vias 12 to increase the homogeneity of the fill, thus decreasing the probability of voids in the fill.
  • the pulse frequency is chosen such that re-solidification of the conductive material is avoided during the filling of the via 12.
  • a reduced pressure e.g. a vacuum is applied to the bottom of the wafer to accelerate the filling process of the vias 12.
  • the use of the laser 20 facilitates the filling of the vias 12 in milliseconds.
  • the focus of the laser 20, e.g. an excimer or CO 2 laser spot may be routinely limited to an area as little as l ⁇ m 2 , which allows for the filling of vias having a similar area.
  • the present invention allows for the fast processing of a wafer.
  • a 50 cm laser beam facilitates the simultaneous processing of two 8" wafers, with the total processing time being limited by the translation speed of the wafer mount. At high translation speeds, a minimum of two 8" wafers can be fully exposed in 1 second, including the mounting time, aligning time and removal time from the wafer holder.
  • the present invention is particularly suitable for filling vias 12 that have a large aspect ratio, where capillary force forms the driving force behind filling the via 12.
  • capillary pressure acting on the fluid meniscus of the droplet over the via 12 may be estimated.
  • the capillary pressure is given by:
  • a hydrostatic pressure P H acting on the meniscus is defined as: With ⁇ is the surface tension of the fluid, ⁇ is the angle between the fluid meniscus and the wetting surface, p is the density of the liquid, g is the gravitational acceleration and r is the radius of the via 12.
  • the hydrostatic pressure/? ⁇ is typically much smaller than the capillary pressure p c .
  • ⁇ 0.87IxIO "3 J/m 2
  • the main contribution to the filling driving force is the capillarity pressure, which is even more prominent for vias 12 having smaller radii.
  • p c 110 Pa.
  • Aluminum is a suitable conductive material because it has a viscosity (5.2xlO ⁇ 4 Pa.s) in a molten state that is less than water (8.9 ⁇ 10 ⁇ 4 Pa.s). This means that the molten aluminum flows through the via 12 faster than water under the capillary force. In general, any conductive material that can flow quickly through the via 12 under the capillary force may be used.
  • the present invention may be applied to fill any through- wafer via 12, regardless of its size and thickness.
  • the only limitation could come from the counterbalancing lateral shear force of the conductive material due to its own viscosity. This is especially relevant when the conductive fluid is cooling down.
  • This counterbalancing force may be estimated as follows. The loss of pressure load in a tube is given by the Poiseuille law:
  • ⁇ p the loss of pressure load
  • r the radius of the tube, i.e. the via 12
  • p the density of the fluid conductive material
  • V the speed
  • 1 the length of the via 12
  • the Reynolds number Re is given by: Re (6)
  • the capillary fill time is much smaller than the agglomeration time of the droplets, which means that the droplets fill the vias 12 rather than agglomerate with each other on the surface of the wafer 10.
  • the wafer 10 may be subjected to further processing steps such as cleaning steps and steps to remove excess conductive material from the wafer surface.
  • Such excess conductive material may for instance be removed by means of chemical mechanical polishing or ultra- fine grinding techniques.
  • the capillary force exerted on the fluid portion 16 may be increased by reducing the radius r of the via 12.
  • the radius r of the via 12 is reduced, at least at the opening of the via 12 receiving the portion 16 prior to the deposition of the portion 16 of the conductive material.
  • Such a reduction increases the capillary force on the fluid portion 16 and therefore reduces the filling time of the via 12, which also reduces the risk of the introduction of voids into the conductive filler material by partial solidification.
  • a thin film 22 of the conductive material is grown, e.g.
  • Non- limiting examples of suitable deposition techniques include physical vapor deposition (PVD), sputtering, evaporation and so on. It is not necessary that the thin film 22 covers the full surface of the via 12; as long as the top of the via 12 is narrowed, the capillary force of the fluid portion 16 is increased, thereby reducing the filling time of the via 12. In other words, the thin film 22 at the top of the via 12 acts as an excellent promoter of the capillary filling process.
  • a thermal insulator layer 14 may be formed prior to the deposition of the thin film 22 of the conductive material in an alternative embodiment.
  • Fig. 4 depicts a non- limiting example of how the portion 16 of the conductive material.
  • a photoresist layer 24 is deposited over the wafer 10 and subsequently patterned to expose the via holes.
  • An electroplating technique is used to grow the portions 16 over the vias 12. This electroplating step may be performed quickly because the quality of the electroplated structure is not important since the conductive material 16 will be fluidized, e.g. melted by subsequent irradiation with the laser 20, as long as is ensured that the portion 16 has the appropriate volume. Hence, relatively high currents may be used to electroplate the conductive material.
  • FIG. 5 shows a simulation of the heat transfer through a silicon wafer 10 without a silicon oxide thermal insulator layer 14 (left pane) and with a silicon oxide thermal insulator layer 14 (right pane) separating an Al filler of a blind via 12 (i.e. the via 12 is sealed at the bottom) from the wafer silicon.
  • the simulation has been performed using the COMSOL MultiphysicsTM program.
  • the temperature at the top of the wafer 10 was set at 1000 C, and the temperature at the top of the wafer 10 was set at 300 C
  • the heat transfer through the aluminum filler and the silicon is comparable, which indicates an efficient heat transfer between the aluminum and the silicon.
  • the aluminum retains a much higher temperature throughout the via 12, thus indicating that the thermally insulating oxide layer 14 effectively insulates the aluminum from the wafer silicon.
  • the thermal conduction between the conductive material in the via 12 and the wafer 10, e.g. a silicon wafer may be tuned by varying the aspect ration of the via 12 and/or the thickness of the oxide insulating layer 14. This is demonstrated in Fig. 6. As shown in the left pane of Fig. 6, a higher aspect ratio of the via 12 filled with a conductive material lowers the temperature of that material at the bottom of the via 12. As shown in the right pane of Fig.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne un procédé de remplissage de traversées (12) d'une tranche (10), de préférence une tranche de silicium. Le procédé consiste à recouvrir la traversée (12) en déposant une partie (16) d'un matériau conducteur sur la traversée ; et à remplir la traversée (12) avec le matériau conducteur en exposant la partie (16) à un laser (20) pendant un laps de temps prédéfini, en portant ainsi le matériau à l’état liquide, par exemple en le faisant fondre.
PCT/IB2009/052541 2008-06-16 2009-06-15 Procédé de remplissage à travers les traversées d'une tranche WO2009153728A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP08158337.9 2008-06-16
EP08158337 2008-06-16

Publications (1)

Publication Number Publication Date
WO2009153728A1 true WO2009153728A1 (fr) 2009-12-23

Family

ID=41010465

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2009/052541 WO2009153728A1 (fr) 2008-06-16 2009-06-15 Procédé de remplissage à travers les traversées d'une tranche

Country Status (1)

Country Link
WO (1) WO2009153728A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102915949A (zh) * 2011-08-01 2013-02-06 中国科学院微电子研究所 在基板中嵌入金属材料的方法
WO2019191621A1 (fr) * 2018-03-30 2019-10-03 Samtec, Inc. Trous d'interconnexion électroconducteur et leurs procédés de production
US10593562B2 (en) 2015-04-02 2020-03-17 Samtec, Inc. Method for creating through-connected vias and conductors on a substrate
CN111250715A (zh) * 2020-03-06 2020-06-09 北京航空航天大学 一种基于粉末烧结工艺的三维mems结构金属填充方法
WO2022217146A1 (fr) * 2021-04-09 2022-10-13 Samtec, Inc. Trous d'interconnexion à rapport de forme élevé remplis d'un remplissage de métal liquide
US11646246B2 (en) 2016-11-18 2023-05-09 Samtec, Inc. Method of fabricating a glass substrate with a plurality of vias

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3770529A (en) * 1970-08-25 1973-11-06 Ibm Method of fabricating multilayer circuits
US20030060000A1 (en) * 2001-03-07 2003-03-27 Seiko Epson Corporation Wiring board and fabricating method thereof, semiconductor device and fabricating method thereof, circuit board and electronic instrument
EP1575084A2 (fr) * 2004-03-01 2005-09-14 Interuniversitair Microelektronica Centrum ( Imec) Méthode de déposer un matériau de soudure sur un substrat en form de motif prédéterminé
WO2007089206A1 (fr) * 2006-02-01 2007-08-09 Silex Microsystems Ab Trous d'interconnexion et leur procédé de réalisation
US20080303163A1 (en) * 2007-06-07 2008-12-11 United Test And Assembly Center Ltd. Through silicon via dies and packages

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3770529A (en) * 1970-08-25 1973-11-06 Ibm Method of fabricating multilayer circuits
US20030060000A1 (en) * 2001-03-07 2003-03-27 Seiko Epson Corporation Wiring board and fabricating method thereof, semiconductor device and fabricating method thereof, circuit board and electronic instrument
EP1575084A2 (fr) * 2004-03-01 2005-09-14 Interuniversitair Microelektronica Centrum ( Imec) Méthode de déposer un matériau de soudure sur un substrat en form de motif prédéterminé
WO2007089206A1 (fr) * 2006-02-01 2007-08-09 Silex Microsystems Ab Trous d'interconnexion et leur procédé de réalisation
US20080303163A1 (en) * 2007-06-07 2008-12-11 United Test And Assembly Center Ltd. Through silicon via dies and packages

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SPIESS W ET AL: "VIA HOLE FILLING WITH GOLD MELTING BY KRF EXCIMER LASER IRRADIATION", JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY: PART B, AVS / AIP, MELVILLE, NEW YORK, NY, US, vol. 7, no. 1, 1 January 1989 (1989-01-01), pages 127/128, XP000054840, ISSN: 1071-1023 *

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102915949A (zh) * 2011-08-01 2013-02-06 中国科学院微电子研究所 在基板中嵌入金属材料的方法
US10593562B2 (en) 2015-04-02 2020-03-17 Samtec, Inc. Method for creating through-connected vias and conductors on a substrate
US10727084B2 (en) 2015-04-02 2020-07-28 Samtec, Inc. Method for creating through-connected vias and conductors on a substrate
US11107702B2 (en) 2015-04-02 2021-08-31 Samtec, Inc. Method for creating through-connected vias and conductors on a substrate
US11646246B2 (en) 2016-11-18 2023-05-09 Samtec, Inc. Method of fabricating a glass substrate with a plurality of vias
WO2019191621A1 (fr) * 2018-03-30 2019-10-03 Samtec, Inc. Trous d'interconnexion électroconducteur et leurs procédés de production
CN112154538A (zh) * 2018-03-30 2020-12-29 申泰公司 导电过孔及其制造方法
US12009225B2 (en) 2018-03-30 2024-06-11 Samtec, Inc. Electrically conductive vias and methods for producing same
CN111250715A (zh) * 2020-03-06 2020-06-09 北京航空航天大学 一种基于粉末烧结工艺的三维mems结构金属填充方法
CN111250715B (zh) * 2020-03-06 2021-01-26 北京航空航天大学 一种基于粉末烧结工艺的三维mems结构金属填充方法
WO2022217146A1 (fr) * 2021-04-09 2022-10-13 Samtec, Inc. Trous d'interconnexion à rapport de forme élevé remplis d'un remplissage de métal liquide

Similar Documents

Publication Publication Date Title
US11508694B2 (en) Chip assembly
US8324103B2 (en) Vias and method of making
WO2009153728A1 (fr) Procédé de remplissage à travers les traversées d'une tranche
US8124521B2 (en) Electrical through contact
EP2381469A1 (fr) Matériau de remplissage et procédé de remplissage l'utilisant
TWI354529B (en) Metal thermal interface material and thermal modul
WO2010041165A1 (fr) Procédé de placage à travers les trous d’interconnexion d’une plaquette dans une plaquette pour l’emballage 3d
JP2010147308A (ja) 配線基板の製造方法、およびインクジェット記録ヘッド用基板の製造方法
US10727192B2 (en) Multiple sized bump bonds
US9003654B2 (en) Method for metalizing blind vias
CN101770963A (zh) 形成导电层的方法及半导体器件
US7361593B2 (en) Methods of forming vias in multilayer substrates
WO2019071012A1 (fr) Boîtier à échelle de puce industriel pour dispositif microélectronique
EP1675445A1 (fr) Procédé de fabrication d'un substrat semi-conducteur
JP5522377B2 (ja) 貫通電極の形成方法、及び半導体基板
EP1575084B1 (fr) Procédé pour déposer un matériau de soudure sur un substrat
JP6996823B2 (ja) 自己整列はんだバンプを備えた基板貫通ビアを含む半導体デバイスを製造する方法および半導体構造
CN104900547B (zh) 多元合金成分的微凸点制备工艺
WO2016207719A1 (fr) Appareil et procédé comprenant des microcanaux de métal à auto-assemblage
JP2007329156A (ja) 半導体装置およびその製造方法、並びに電子部品
JP7083648B2 (ja) 半導体装置の製造方法
JP2007305715A (ja) 配線基板の製造方法
CN113471090B (zh) 一种金属凸点的键合方法及键合机构
US20180182669A1 (en) Method of filling a via hole and apparatus for performing the same
JP2006520543A (ja) 傾斜した面上に設けるはんだ

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09766265

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 09766265

Country of ref document: EP

Kind code of ref document: A1