WO2009148264A2

WO2009148264A2 - Plasma display apparatus

Info

Publication number: WO2009148264A2
Application number: PCT/KR2009/002960
Authority: WO
Inventors: Jinhyuk Jang
Original assignee: Lg Electronics Inc.
Priority date: 2008-06-04
Filing date: 2009-06-03
Publication date: 2009-12-10
Also published as: KR20090126535A; WO2009148264A3

Abstract

A plasma display apparatus is provided. The plasma display appratus includes an electrode and a driver supplying a sustain signal to the electrode. The driver includes a first capacitor, a first inductor arranged between the electrode and the first capacitor, a first switch and a second switch arranged in parallel between the first inductor and the first capacitor, a second inductor arranged between the first inductor and the electrode, a third switch arranged between a node between the first inductor and the second inductor and a sustain voltage source supplying a sustain voltage, a fourth switch arranged between the node between the first inductor and the second inductor and the ground, a third inductor arranged between a node between the sustain voltage source and the third switch and a node between the electrode and the second inductor, and a first diode arranged between the node between the electrode and the second inductor and the third inductor.

Description

PLASMA DISPLAY APPARATUS

Embodiments relate to a plasma display apparatus.

A plasma display apparatus includes a plasma display panel. The plasma display panel includes a phosphor layer inside discharge cells partitioned by barrier ribs and a plurality of electrodes.

When driving signals are applied to the electrodes of the plasma display panel, a discharge occurs inside the discharge cells. More specifically, when the discharge occurs in the discharge cells by applying the driving signals to the electrodes, a discharge gas filled in the discharge cells generates vacuum ultraviolet rays, which thereby cause phosphors between the barrier ribs to emit visible light. An image is displayed on the screen of the plasma display panel using the visible light.

FIG. 1 illustrates an exemplary configuration of a plasma display apparatus according to an embodiment;

FIG. 2 illustrates an exemplary structure of a plasma display panel according to an embodiment;

FIGs. 3 and 4 illustrate an exemplary method of driving a plasma display panel;

FIGs. 5 and 6 illustrate an exemplary configuration of a driver according to an embodiment of the present invention;

FIGs. 7, 8, 9 and 10 illustrate an exemplary operating method of the driver;

FIGs. 11 and 12 illustrate an exemplary configuration of a cable

FIGs. 13 and 14 illustrate a distance between a pad area and a united driver board;

FIG. 15 illustrates an exemplary configuration of a driver for providing a sustain signal to a scan electrode;

FIGs. 16, 17 and 18 illustrate a comparison of a sustain signal supplied to a scan electrode with a sustain signal provided to a sustain electrode; and

FIGs. 19, 20 and 21 illustrate an exemplary configuration of the driver according to another embodiment of the present invention.

FIG. 1 illustrates an exemplary configuration of a plasma display apparatus according to an embodiment.

As shown in FIG. 1, the plasma display apparatus according to the exemplary embodiment includes a plasma display panel 100 and a

driver

110, 120.

The plasma display panel 100 may include scan electrodes Y1 to Yn and sustain electrodes Z1 to Zn positioned substantially parallel to each other and address electrodes X1 to Xm crossing the scan electrodes Y1 to Yn and the sustain electrodes Z1 to Zn.

The driver may supply driving signals to at least one of the scan electrodes Y1 to Yn, the sustain electrodes Z1 to Zn, or the address electrodes X1 to Xm and allow an image to be displayed on the screen of the plasma display panel 100.

The driver may include a data driver board 120 and a united driver board 110.

The data driver board 120 may supply a driving signal to the address electrode X, the united driver board 110 may supply a driving signal to the scan electrode Y and sustain electrode Z.

As described above, an unit supplying the driving signal to the scan electrode Y and an unit supplying the driving signal to the sustain electrode Z may form an integral body (i.e., the united driver board 110). Hence, the manufacturing cost of plasma display apparatus may be reduced and the size of the plasma display apparatus may be reduced.

A cable 130 may be disposed between the united driver board 110 and the sustain electrode Z to transfer the driving signal generated by the united driver board 110 to the sustain electrode Z.

Although FIG. 1 shows that the cable 130 is disposed between the united driver board 110 and the sustain electrode Z, the cable 130 may be disposed between the united driver board 110 and the scan electrode Y when the united driver board 110 is adjacent to a pad area of the sustain electrode.

FIG. 2 illustrates an exemplary structure of a plasma display panel according to an embodiment.

As shown in FIG. 2, the plasma display panel may include a front substrate 101, on which a scan electrode 102 and a sustain electrode 103 are formed substantially parallel to each other and a rear substrate 111 on which an address electrode 113 is formed to cross the scan electrode 102 and the sustain electrode 103.

An upper dielectric layer 104 may be formed on the scan electrode 102 and the sustain electrode 103 to limit a discharge current of the scan electrode 102 and the sustain electrode 103 and to provide insulation between the scan electrode 102 and the sustain electrode 103.

A protective layer 105 may be formed on the upper dielectric layer 104 to facilitate discharge conditions. The protective layer 105 may be formed of a material having a high secondary electron emission coefficient, for example, magnesium oxide (MgO).

A lower dielectric layer 115 may be formed on the address electrode 113 to provide insulation between the address electrodes 113.

Barrier ribs 112 of a stripe type, a well type, a delta type, a honeycomb type, etc. may be formed on the lower dielectric layer 115 to partition discharge spaces (i.e., discharge cells). Hence, a first discharge cell emitting red light, a second discharge cell emitting blue light, and a third discharge cell emitting green light, etc. may be formed between the front substrate 101 and the rear substrate 111.

Each discharge cell portioned by the barrier ribs 112 may be filled with a discharge gas. It may be preferable that the discharge gas contains nitrogen gas (N₂).

A phosphor layer 114 may be formed inside the discharge cells to emit visible light for an image display during an address discharge. For example, first, second, and third phosphor layers that respectively generate red, blue, and green light may be formed inside the discharge cells.

When a predetermined signal is supplied to at least one of the scan electrode 102, the sustain electrode 103, and the address electrode 113, a discharge may occur inside the discharge cell. The discharge may allow the discharge gas filled in the discharge cell to generate ultraviolet rays. The ultraviolet rays may be incident on phosphor particles of the phosphor layer 114, and then the phosphor particles may emit visible light. Hence, an image may be displayed on the screen of the plasma display panel.

FIGs. 3 and 4 illustrate an exemplary method of driving a plasma display panel.

As shown in FIG. 3, reset signal may be supplied to the scan electrode Y during a reset period RP for initialization of at least one subfield of a plurality of subfields of a frame.

More specifically, the Set-Up signal SU may be supplied to the scan electrode Y during a setup period SUP of the reset period RP, and the Set-Down signal SD may be supplied to the scan electrode Y during a set-down period SDP following the setup period SUP. The Set-Up signal SU may generate a weak dark discharge (i.e., a setup discharge) inside the discharge cells. Hence, the remaining wall charges may be uniformly distributed inside the discharge cells. The Set-Down signal SD may generate a weak erase discharge (i.e., a set-down discharge) inside the discharge cells. Hence, the remaining wall charges may be uniformly distributed inside the discharge cells to the extent that an address discharge occurs stably.

During an address period AP following the reset period RP, a scan signal Sc may be supplied to the scan electrode Y and a data signal Dt corresponding to the scan signal Sc may be supplied to the address electrode X. As the voltage difference between the scan signal Sc and the data signal Dt is added to a wall voltage resulting from the wall charges produced during the reset period RP, an address discharge may occur inside the discharge cells to which the data signal Dt is supplied.

And, a Sustain Bias signal Zbias may be supplied to the sustain electrode during address period for stability of address discharge.

A voltage of the Sustain Bias signal Zbias may be lower than the sustain voltage Vs or as shown in FIG 4 the voltage of the Sustain Bias signal Zbias may be equal to the sustain voltage Vs.

A pulse width of a scan signal supplied to the scan electrode during an address period of at least one subfield of a frame may be different from pulse widths of scan signals supplied during address periods of other subfields of the frame. A pulse width of a scan signal in a subfield may be greater than a pulse width of a scan signal in a next subfield. For example, a pulse width of the scan signal may be gradually reduced in the order of 2.6 ㎲, 2.3 ㎲, 2.1 ㎲, 1.9 ㎲, etc. or may be reduced in the order of 2.6 ㎲, 2.3 ㎲, 2.3 ㎲, 2.1 ㎲, …, 1.9 ㎲, 1.9 ㎲, etc. in the successively arranged subfields.

During a sustain period SP following the address period AP, a sustain signal SUS may be supplied to at least one of the scan electrode Y or the sustain electrode Z. FIG. 3 shows that the sustain signals SUS are alternately supplied to the scan electrode Y and the sustain electrode Z. As the wall voltage inside the discharge cells selected by the generation of the address discharge is added to a sustain voltage of the sustain signal SUS, every time the sustain signal SUS is supplied, a sustain discharge (i.e., a display discharge) may occur between the scan electrode Y and the sustain electrode Z.

FIGs. 5 and 6 illustrate an exemplary configuration of the driver according to an embodiment of the present invention in more detail. Illustration and explanation of the data driver board and power supply unit are omitted in FIGs. 5 and 6.

Referring to FIG. 5, a metal frame 500 may be arranged on the backside of the plasma display panel 100 and the united driver board 110 of the driver may be located on the rear side of the frame 500.

A first connector 530 may be arranged on the united driver board 110. In addition, a first flexible board 520 such as a flexible printed circuit (FPC) may be connected between the first connector 530 and the scan electrode Y of the plasma display panel 100, and thus the united driver board 110 and the scan electrode Y can be electrically connected to each other.

The driver may further include an auxiliary board 510. The cable 130 may be arranged between the auxiliary board 510 and the united driver board 110 to electrically connect the auxiliary board 510 to the united driver board 110.

Here, the cable 130 may transmit a driving signal generated in the united driver board 110 to the sustain electrode.

The auxiliary board 510 may include a second connector 550 arranged thereon. A second flexible board 540 may be connected between the second connector 550 and the sustain electrode Z of the plasma display panel 100 to electrically connect the auxiliary board 510 to the sustain electrode Z.

Here, the auxiliary board 510 does not generate a driving signal to be supplied to the sustain electrode and may transmit the driving signal generated in the united driver board 110 to the sustain electrode. Accordingly, the auxiliary board 510 may not include a switching element and may have an area smaller than that of the united driver board 110.

The auxiliary board 510 may be omitted since the auxiliary board 510 does not include the switching element.

Referring to FIG. 6, the united driver board 110 may include an energy recovery circuit 600 which supplies a sustain signal to the scan electrode Y and the sustain electrode Z and recovers voltages of the scan electrode Y and the sustain electrode Z.

Although FIG. 6 illustrates the energy recovery circuit of Weber type, an energy recovery circuit of Sakai type may be applied to the present invention.

FIG. 6 illustrates only a case that the sustain signal is supplied to the sustain electrode. A case that the sustain signal is supplied to the scan electrode will be explained later with reference to FIG. 15.

The energy recovery circuit 600 may include a first capacitor C1, a first switch S1, a second switch S2, a first inductor L1, a third switch S3 and a fourth switch S4.

The voltage of the sustain electrode Z may be recovered and stored in the first capacitor C1 and the voltage stored in the first capacitor C1 may be supplied to the sustain electrode Z.

The first inductor L1 may be arranged between the first capacitor C1 and the sustain electrode. The first inductor L1 may generate LC resonance when the voltage stored in the first capacitor C1 is supplied to the sustain electrode and when the voltage of the sustain electrode is recovered to the first capacitor C1.

The first switch S1 and the second switch S2 may be arranged in parallel between the first inductor L1 and the first capacitor C1. That is, the first switch S1 and the second switch S2 may be arranged in parallel between a first node n1 and a second node n2.

The first switch S1 may supply the voltage stored in the first capacitor C1 to the sustain electrode during a rising period of the sustain signal SUS through a predetermined switching operation.

The second switch S2 may recover the voltage of the sustain electrode to the first capacitor C1 during a falling period of the sustain signal SUS through a predetermined switching operation.

The third switch S3 may be arranged between the sustain electrode and a sustain voltage source supplying the sustain voltage Vs. That is, the third switch S3 may be placed between a third node n3 and the sustain voltage source. Here, the third node n3 is located between the first inductor L1 and a second inductor L2.

The third switch S3 can supply the sustain voltage Vs to the sustain electrode through a predetermined switching operation.

The fourth switch S4 may be arranged between the sustain electrode and the ground. That is, the fourth switch S4 may be located between the third node n3 and the ground.

The fourth switch S4 can supply a voltage having ground level GND to the sustain electrode through a predetermined switching operation.

Furthermore, the auxiliary board 510 may include a first diode D1 and a second capacitor C2 and the cable 130 may include the second inductor L2 and a third inductor L3.

Here, the second inductor L2 may be a first cable arranged between the united driver board 110 and the auxiliary board 510 and the third inductor L3 may be a second cable arranged between the united driver board 110 and the auxiliary board 510. The first cable and the second cable have sufficient lengths in order to transmit the sustain signal from the united driver board 110 to the auxiliary board 510, and thus the first cable and the second cable have sufficiently large inductance. Accordingly, the first cable and the second cable can be represented as the second inductor L2 and the third inductor L3, as illustrated in FIG. 6.

The second inductor L2 can transmit the sustain signal generated in the united driver board 110 to the sustain electrode. To achieve this, the second inductor L2 may be arranged between the first inductor L1 and the sustain electrode. Preferably, the second inductor L2 may be located between the third node n3 and a fifth node n5.

The third inductor L3 may be arranged between a node between the sustain voltage source supplying the sustain voltage Vs and the third switch S3, that is, a fourth node n4, and a node between the sustain electrode and the second inductor L2, that is, the fifth node n5.

The first diode D2 arranged on the auxiliary board 510 can prevent the voltage of the fifth node n5 from excessively increasing higher than the sustain voltage Vs. To achieve this, the first diode D1 may be arranged between a node between the third inductor L3 and the sustain electrode, that is, a sixth node, and the fifth node n5.

The cathode of the first diode D1 may be arranged in the direction of the third inductor L3 and the anode of the first diode D1 may be arranged in the direction of a node between the sustain electrode and the second inductor L2, that is, the fifth node n5.

The second capacitor C2 arranged on the auxiliary board 510 can restrain excessively large current from flowing to the sustain electrode through the second inductor L2. To achieve this, the second capacitor C2 may be arranged between a node between the first diode D1 and the third inductor L3, that is, the sixth node n6, and the ground.

FIGs. 7, 8, 9 and 10 illustrate an exemplary operating method of the driver.

Referring to FIG. 7, the sustain signal SUS may include a rising period d1 in which the voltage gradually increases, a sustain period d2 in which the peak voltage, that is, the sustain voltage Vs, is substantially sustained, and a falling period d3 in which the voltage gradually decreases.

During the rising period d1 of the sustain signal, the first switch S1 can be turned on while the second, third and fourth switches S2, S3 and S4 are turned off.

Then, the voltage stored in the first capacitor C1 can be supplied to the sustain electrode through LC resonance according to the first inductor L1 and the second inductor L2 during the rising period d1, as represented by ① in FIG. 8. Accordingly, the voltage of the sustain electrode may gradually increase from the ground level GND to a first voltage V1.

During the sustain period d2, the third switch S3 can be turned on while the first switch S1 is turned on.

Then, the sustain voltage Vs generated from the sustain voltage source can be supplied to the sustain electrode, as represented by ② in FIG. 8. Accordingly, the voltage of the sustain electrode is clamped from the first voltage V1 to the sustain voltage Vs, and thus the sustain voltage Vs may be substantially maintained.

During the falling period d3, the second switch S2 can be turned on while the first switch S1 and the third switch S3 are turned off.

Then, the voltage of the sustain electrode can be recovered to the first capacitor C1 through LC resonance according to the first inductor L1 and the second inductor L2, as represented by ③ in FIG. 8. Accordingly, the voltage of the sustain electrode may gradually decrease from the sustain voltage Vs to a second voltage V2.

The fourth switch S4 may be turned on after the falling period d3.

Then, a current path starting from the sustain electrode to the ground via the fourth switch S4 may be formed, as represented by ④ in FIG. 8, and thus the voltage of the sustain electrode may gradually decrease from the second voltage V2 to the ground level GND.

The sustain signal SUS can be supplied to the sustain electrode by using the aforementioned method.

In a case that the voltage of the fifth node n5 abruptly increases higher than the sustain voltage Vs due to noise, a current path starting from the fifth node n5 to the sustain voltage source via the first diode D1 and the third inductor L3 may be formed, as represented by ⑤ in FIG. 9, and thus the voltage of the fifth node n5 can be restrained from increasing higher than the sustain voltage Vs.

Furthermore, the second capacitor C2 may form a current path from the fifth node n5 to the ground via the first diode D1 and the second capacitor C2. Accordingly, when an unnecessary current is induced by the second inductor L2, that is, an induced current is generated by the second inductor L2, as represented by ⑥ in FIG. 9, the induced current can be filtered.

When the auxiliary board 510 does not include the second capacitor C2, for instance, the induced current generated by the second inductor L2 may flow through the fifth node n5, the first diode D1, the sixth node n6, the third inductor L3, the fourth node n4, the third switch S3, the third node n3 and the second inductor L2, and thus load applied to the third switch S3 and the first diode D1 may increase.

FIG. 10(a) illustrates the induced current generated by the second inductor L2. Referring to FIG. 10(a), current A induced by the second inductor L2 may flow through the third node n3 after a discharge current flows through the third node n3 when sustain discharge occurs.

When the auxiliary board 510 includes the second capacitor C2, the induced current generated by the second inductor L2 is considerably reduced, as represented by B in FIG. 10(b), because the induced current is charged in the second capacitor C2 and consumed.

Accordingly, the load applied to the third switch S3 and the first diode D1 can be reduced, and thus the driving operation can be stabilized.

When the load applied to the third switch S3 and the first diode D1 is reduced, rated voltages of the third switch S3 and the first diode D1 can be decreased, and thus the manufacturing cost of the plasma display apparatus can be reduced.

FIGs. 11 and 12 illustrate an exemplary configuration of the cable.

Referring to FIG. 11, the cable 130 may include the first cable 1100 (L2) and the second cable 1110 (L3) and the first and

second cables

1100 and 1110 may be arranged between the united driver board 110 and the auxiliary board 510.

The first cable 1100 may be arranged between the third node n3 of the united driver board 110 and the fifth node n5 of the auxiliary board 510 and supply the sustain signal generated by the united driver board 110 to the sustain electrode through the auxiliary board 510. The second cable 1110 may be arranged between the fourth node n4 of the united driver board 110 and the sixth node n6 of the auxiliary board 510.

The first cable 1100 and the second cable 1110 may be located apart from each other by a predetermined distance.

Otherwise, the first cable 1100 and the second cable 1110 can be arranged in a bundle, as illustrated in FIG. 12.

FIGs. 13 and 14 illustrate a distance between the pad area and the united driver board.

Referring to FIG. 13, the united driver board 110 may be located in proximity to the scan electrode Y and a pad electrode 102P. That is, the distance d1 between the united driver board 110 and the pad electrode 102P of the scan electrode is smaller than the distance d2 between the united driver board 110 and a pad electrode 103P of the sustain electrode.

In this case, it is possible to supply the sustain signal to the sustain electrode by using the cables, as illustrated in FIGs. 11 and 12.

Here, the pad area Y-PA of the scan electrode may correspond to a region where the pad electrode 102P of the scan electrode is located.

The pad electrode 102P of the scan electrode may be exposed to the outside and a flexible board may be attached to the pad electrode 102P in order to electrically connect the pad electrode 102P to the united driver board 110.

The pad area Z-PA of the sustain electrode may correspond to a region where the pad electrode 103P of the sustain electrode is located and be exposed to the outside. A flexible board may be attached to the pad electrode 103P of the sustain electrode in order to electrically connect the pad electrode 103P to the united driver board 110.

That is, the united driver board 110 supplies the sustain signal to the pad electrode 102P of the scan electrode, which is located relatively close to the united driver board 110, by using a flexible board such as FPC without passing through the cable and provides the sustain signal to the pad electrode 103P of the sustain electrode, which is located in a distance from the united driver board, by using the cable.

If the united driver board 110 is located in proximity to the pad electrode 103P of the sustain electrode, as illustrated in FIG. 4, the united driver board 110 can supply the sustain signal to the pad electrode 103P of the sustain electrode, which is located relatively close to the united driver board 110, by using a flexible board such as FPC without passing through the cable and provide the sustain signal to the pad electrode 102P of the sustain electrode, which is located in a distance from the united driver board, by using the cable.

FIG. 15 illustrates an exemplary configuration of a driver for providing the sustain signal to the scan electrode. Explanations of the parts described above will be omitted.

Referring to FIG. 15, the driver for supplying the sustain signal to the scan electrode may include the first capacitor C1, the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4.

In comparison of the driver illustrated in FIG. 15 to the driver illustrated in FIG. 6, the driver illustrated in FIG. 15 does not include the second inductor L2, the third inductor L3, the first diode D1 and the second capacitor C2.

The united driver board may not use the cable to supply the sustain signal because the united driver board is located in proximity to the pad electrode of the scan electrode. Accordingly, the driver does not require the second and third inductors L2 and L3, and thus the first diode D1 and the second capacitor C2 can be omitted.

To respectively supply sustain signals to the scan electrode and the sustain electrode, the plasma display apparatus may respectively include the driver illustrated in FIG. 15 and the driver illustrated in FIG. 6.

Otherwise, the driver illustrated in FIG. 15 and the driver illustrated in FIG. 6 may be integrated.

FIGs. 16, 17 and 18 illustrate a comparison of the sustain signal supplied to the scan electrode with the sustain signal provided to the sustain electrode.

Referring to FIG. 16, a rising period d1y of the sustain signal Y-SUS supplied to the scan electrode Y may be shorter than a rising period d1z of the sustain signal Z-SUS supplied to the sustain electrode Z, and a falling period d3y of the sustain signal Y-SUS supplied to the scan electrode Y may be shorter than a falling period d3z of the sustain signal Z-SUS supplied to the sustain electrode Z.

The sustain signal is supplied to the sustain electrode via the first inductor L1 and the second inductor L2, as described above with reference to FIG. 8, and the sustain signal is supplied to the scan electrode via the first inductor L1 without passing through the second inductor L2, as described above with reference to FIG. 15, and thus the rising period d1z and the falling period d3z of the sustain signal Z-SUS supplied to the sustain electrode Z become longer than the rising period d1y and the falling period d3y of the sustain signal Y-SUS provided to the scan electrode Y.

Furthermore, a sustain period d2z of the sustain signal Z-SUS supplied to the sustain electrode Z may be shorter than a sustain period d2y of the sustain signal Y-SUS supplied to the scan electrode Y, and thus a pulse width W1 of the sustain signal Z-SUS supplied to the sustain electrode Z may be substantially equal to a pulse width W1 of the sustain signal Y-SUS provided to the scan electrode Y.

As the rising period d1z and the falling period d3z of the sustain signal Z-SUS supplied to the sustain electrode Z become longer than the rising period d1y and the falling period d3y of the sustain signal Y-SUS provided to the scan electrode Y, a pulse width W3 of the sustain signal Z-SUS supplied to the sustain electrode Z may be greater than a pulse width W2 of the sustain signal Y-SUS provided to the scan electrode Y, as illustrated in FIG. 17. In this case, the sustain period d2z of the sustain signal Z-SUS supplied to the sustain electrode Z may be substantially equal to the sustain period d2y of the sustain signal Y-SUS provided to the scan electrode Y.

As illustrated in FIG. 18, the sustain signal Z-SUS supplied to the sustain electrode Z and the sustain signal Y-SUS supplied to the scan electrode Y may be overlapped with each other.

For instance, the rising period d1z of the sustain signal Z-SUS provided to the sustain electrode Z may be overlapped with the falling period d3y of the sustain signal Y-SUS supplied to the scan electrode Y and the falling period d3z of the sustain signal Z-SUS provided to the sustain electrode Z may be overlapped with the rising period d1y of the sustain signal Y-SUS supplied to the scan electrode Y.

When the sustain signal Z-SUS provided to the sustain electrode Z is overlapped with the sustain signal Y-SUS supplied to the scan electrode Y, as described above, a larger number of sustain signals can be supplied for a sustain period, and thus the luminance of an image can be improved.

This case may be applied to a plasma display apparatus using a Sakai type energy recovery circuit.

FIGs. 19, 20 and 21 illustrate an exemplary configuration of a driver according to another embodiment of the present invention.

Referring to FIG. 19, the second capacitor C2 may be a variable capacitor.

The variable capacitor has a variable capacitance, and thus it can cope with various noise frequency bands. Accordingly, noise of various frequency bands can be eliminated.

Referring to FIG. 20, a first resistor R1 may be arranged between the second capacitor C1 and the ground. The first resistor R1 facilitates removal of induced current.

Referring to FIG. 21, the driver may include the second diode D2, a third capacitor C3 and a fourth inductor L4.

The fourth inductor L4 may be a third cable. The third cable (not shown) has a length enough to be extended from the united driver board to the auxiliary board, and thus the third cable has a sufficiently large inductance. Accordingly, the third cable is represented as the fourth inductor L4 in FIG. 21.

The fourth inductor L4 may be arranged between a node between the ground and the fourth switch S4, that is, a seventh node n7, and a node between the sustain electrode and the second inductor L2, that is, the fifth node n5.

The second diode D2 may prevent the voltage of the fifth node n5 from excessively decreasing lower than the ground level GND. To achieve this, the second diode D2 may be arranged between the fourth inductor L4 and the sustain electrode, that is, between an eighth node n8 and the fifth node n5.

The cathode of the second diode D2 may be arranged in the direction of the fifth node n5 and the anode thereof may be arranged in the direction of the fourth inductor L4.

The third capacitor C3 may restrain an excessively large negative current from flowing from the ground to the sustain electrode via the fourth inductor L4. To achieve this, the third capacitor C3 may be arranged between a node between the second diode D2 and the fourth inductor L4, that is, the eighth node n8, and the ground.

Furthermore, the third capacitor C3 may be a variable capacitor as the second capacitor C2 described above with reference to FIG. 19. A second resistor R2 may be arranged between the third capacitor C3 and the ground, as described above with reference to FIG. 20. This configuration may be derived from the configurations illustrated in FIGs. 19 and 20 so that it is not illustrated in a figure.

Any reference in this specification to one embodiment, an embodiment, example embodiment, etc., means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with any embodiment, it is submitted that it is within the purview of one skilled in the art to effect such feature, structure, or characteristic in connection with other ones of the embodiments.

Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.

Claims

A plasma display apparatus comprising:

a plasma display panel including an electrode; and

a driver supplying a sustain signal to the electrode,

wherein the driver comprises

a first capacitor;

a first inductor arranged between the electrode and the first capacitor;

a first switch and a second switch arranged in parallel between the first inductor and the first capacitor;

a second inductor arranged between the first inductor and the electrode;

a third switch arranged between a node between the first inductor and the second inductor and a sustain voltage source supplying a sustain voltage;

a fourth switch arranged between the node between the first inductor and the second inductor and the ground;

a third inductor arranged between a node between the sustain voltage source and the third switch and a node between the electrode and the second inductor; and

a first diode arranged between the node between the electrode and the second inductor and the third inductor.
The plasma display apparatus of claim 1, wherein the cathode of the first diode is arranged in the direction of the third inductor and the anode of the first diode is arranged in the direction of the node between the electrode and the second inductor.
The plasma apparatus of claim 1, further comprising a second capacitor arranged between a node between the first diode and the third inductor and the ground.
The plasma display apparatus of claim 3, wherein the second capacitor is a variable capacitor.
The plasma display apparatus of claim 3, further comprising a first resistor arranged between the second capacitor and the ground.
The plasma display apparatus of claim 1, further comprising:

a fourth inductor arranged between a node between the ground and the fourth switch and the node between the electrode and the second inductor; and

a second diode arranged between the node between the electrode and the second inductor and the fourth inductor.
The plasma display apparatus of claim 6, further comprising a third capacitor arranged between a node between the second diode and the fourth inductor and the ground.
The plasma display apparatus of claim 6, wherein the anode of the second diode is arranged in the direction of the fourth inductor and the cathode of the second diode is arranged in the direction of the node between the electrode and the second inductor.
The plasma display apparatus of claim 7, wherein the third capacitor is a variable capacitor.
The plasma display apparatus of claim 7, further comprising a second resistor arranged between the third capacitor and the ground.
A plasma display apparatus comprising:

a plasma display panel including a scan electrode and a sustain electrode; and

a driver supplying sustain signals to the scan electrode and the sustain electrode,

wherein each of the sustain signals includes a rising period in which a voltage gradually increases, a sustain period in which a peak voltage is sustained, and a falling period in which the voltage gradually decreases, and the rising period and the falling period of the sustain signal supplied to the sustain electrode are respectively longer than the rising period and the falling period of the sustain signal supplied to the scan electrode.
The plasma display apparatus of claim 11, wherein the rising period of the sustain signal supplied to the sustain electrode is overlapped with the falling period of the sustain signal supplied to the scan electrode and the falling period of the sustain signal supplied to the sustain electrode is overlapped with the rising period of the sustain signal supplied to the scan electrode.
The plasma display apparatus of claim 11, wherein a pulse width of the sustain signal supplied to the sustain electrode is wider than a pulse width of the sustain signal supplied to the scan electrode.
A plasma display apparatus comprising:

a plasma display panel including a scan electrode and a sustain electrode;

a united driver board located on the backside of the plasma display panel and including an energy recovery circuit supplying sustain signals to the scan electrode and the sustain electrode;

a first cable arranged between the united driver board and the sustain electrode and transmitting the corresponding sustain signal to the sustain electrode;

a second cable arranged between a sustain voltage source generating the sustain voltage and the sustain electrode;

a diode arranged between the cable and the sustain electrode; and

a capacitor arranged between a node between the second cable and the diode and the ground.
The plasma display apparatus of claim 14, wherein the cathode of the diode is connected to a node between the second cable and the capacitor and the anode of the diode is connected to a node between the sustain electrode and the first cable.
The plasma display apparatus of claim 14, wherein the capacitor is a variable capacitor.
The plasma display apparatus of claim 14, further comprising a resistor arranged between the capacitor and the ground.
The plasma display apparatus of claim 14, further comprising an auxiliary board arranged between the first and second cables and the sustain electrode and having the diode and the capacitor arranged thereon.
The plasma display apparatus of claim 18, wherein the auxiliary board does not include a switching element.
The plasma display apparatus of claim 18, wherein the area of the auxiliary board is smaller than the area of the united driver board.