WO2009148054A1

WO2009148054A1 - Solid state imaging device

Info

Publication number: WO2009148054A1
Application number: PCT/JP2009/060066
Authority: WO
Inventors: 行信杉山
Original assignee: 浜松ホトニクス株式会社
Priority date: 2008-06-06
Filing date: 2009-06-02
Publication date: 2009-12-10
Also published as: JP2009295876A

Abstract

A solid state imaging device (1) includes: a light reception unit (10), a first signal output circuit (21), a second signal output circuit (22), a first control circuit (31), and a second control circuit (32). The light reception unit (10) has M × N first pixel units P_1,1 to P_M,N containing photodiodes arranged two-dimensionally in M rows and N columns and I × J second pixel units Q_1,1 to Q_I,J each containing photodiodes. The photodiodes of each of the second pixel units Q_I,J are continuously arranged over a plurality of rows or columns in the two-dimensional arrangement in a region different from the region where the photodiodes of the M × N first pixel units P_1,1 to P_M,N are arranged two-dimensionally. This can realize a solid state imaging device which can perform a high-resolution imaging and a low-resolution imaging at a high speed.

Description

Solid-state imaging device

The present invention relates to a solid-state imaging device.

A solid-state imaging device includes a light receiving unit in which a plurality of pixel units each including a photodiode are two-dimensionally arranged, a signal output unit that outputs an electric signal having a value corresponding to the amount of electric charge generated in the photodiode of each pixel unit, And a control unit for controlling the output of an electrical signal by the signal output unit for each pixel unit. The solid-state imaging device can obtain an image of the intensity distribution of the light input to the light receiving unit based on the electrical signal output from the signal output unit.

Patent Document 1 discloses a solid-state imaging device capable of performing high-resolution imaging and low-resolution imaging. The solid-state imaging device disclosed in Patent Document 1 performs high-resolution imaging by individually outputting an electrical signal for each of a plurality of pixel units included in a light receiving unit. In addition, this solid-state imaging device performs low-resolution imaging by adding electrical signals for a certain number of pixel units among a plurality of pixel units included in the light receiving unit. Such a low-resolution imaging operation is called a binning operation.

JP 2005-277709 A

The solid-state imaging device disclosed in Patent Document 1 cannot perform high-speed imaging when switching between high-resolution imaging and low-resolution imaging, for example.

The present invention has been made to solve the above-described problems, and an object thereof is to provide a solid-state imaging device capable of performing high-resolution imaging and low-resolution imaging at high speed.

The solid-state imaging device according to the present invention includes (1) M × N first pixel portions P _1,1 to P _{M, N} that are two-dimensionally arranged in M rows and N columns and each include a photodiode. In accordance with the amount of charge generated in the photodiode of each of the first pixel portions P _{m, n} and (2) the light receiving portion having I × J second pixel portions Q _1,1 to Q _{I, J} A signal output unit that outputs a first electric signal having a value corresponding to the amount of electric charge generated in the photodiode of each second pixel unit Q _{i, j} , and (3) A control unit for controlling the output of the first electric signal by the signal output unit for each first pixel unit P _{m, n and} for controlling the output of the second electric signal by the signal output unit for each second pixel unit Q _{i, j} And. Further, a region in which the photodiodes of the M × N first pixel portions P _1,1 to P _{M, N} in which the photodiodes of the second pixel portions Q _{i, j} are two-dimensionally arranged are provided, and Are provided in different regions continuously over the length of a plurality of rows or a plurality of columns in the two-dimensional array.

However, M and N are integers of 2 or more, I is an integer of 2 or more and less than M, J is an integer of 2 or more and less than N, m is an integer of 1 or more and M or less, and n is 1 These are integers of N or less, i is an integer of 1 or more and I or less, and j is an integer of 1 or more and J or less. Note that the rows and columns for the M × N first pixel portions P _1,1 to P _{M, N} and the rows and columns for the I × J second pixel portions Q _1,1 to Q _{I, J} are shown. Is different.

In the solid-state imaging device according to the present invention, in the light receiving unit, each of the I × J second pixel units Q _1,1 to Q _{I, J} has two-dimensionally arranged M × N first pixels. _Are provided continuously in a region different from the region where the photodiodes of the parts P _1,1 to P _{M, N} are provided over a length corresponding to a plurality of rows or a plurality of columns in the two-dimensional array. Yes.

From the signal output unit, a first electric signal having a value corresponding to the amount of electric charge generated in the photodiode of each first pixel unit P _{m, n} is output, and the photodiode of each second pixel unit Q _{i, j} The second electric signal having a value corresponding to the amount of electric charge generated in the step is output. The control unit controls the output of the first electric signal by the signal output unit for each first pixel unit P _{m, n and} outputs the second electric signal by the signal output unit for each second pixel unit Q _{i, j} Is controlled. High-speed high-resolution imaging can be performed using the first pixel portion P _{m, n} , and high-speed low-resolution imaging can be performed using the second pixel portion Q _{i, j} .

The solid-state imaging device according to the present invention can perform high-resolution imaging and low-resolution imaging at high speed.

FIG. 1 is a diagram illustrating a schematic configuration of a solid-state imaging device 1 according to the present embodiment. FIG. 2 is a diagram illustrating a configuration of the solid-state imaging device 1 according to the present embodiment. FIG. 3 is a diagram illustrating a circuit configuration of each of the first pixel unit P _{m, n} and the holding circuit 23 _n included in the solid-state imaging device 1 according to the present embodiment. FIG. 4 is a diagram illustrating a circuit configuration of the difference calculation circuit 25 included in the solid-state imaging device 1 according to the present embodiment. FIG. 5 is a diagram illustrating a circuit configuration of each of the second pixel unit Q _{i, j} and the holding circuit 24 _j included in the solid-state imaging device 1 according to the present embodiment. FIG. 6 is a diagram illustrating a circuit configuration of the difference calculation circuit 26 included in the solid-state imaging device 1 according to the present embodiment. FIG. 7 is a diagram illustrating a first arrangement example of the first pixel unit P _{m, n} and the second pixel unit Q _{i, j} in the light receiving unit 10 included in the solid-state imaging device 1 according to the present embodiment. FIG. 8 is a diagram illustrating a second arrangement example of the first pixel unit P _{m, n} and the second pixel unit Q _{i, j} in the light receiving unit 10 included in the solid-state imaging device 1 according to the present embodiment. FIG. 9 is a diagram illustrating a third arrangement example of the first pixel unit P _{m, n} and the second pixel unit Q _{i, j} in the light receiving unit 10 included in the solid-state imaging device 1 according to the present embodiment. FIG. 10 is a diagram illustrating a first layout example of the light receiving unit 10 included in the solid-state imaging device 1 according to the present embodiment. FIG. 11 is a cross-sectional view taken along the line A-A ′ in the first layout example shown in FIG. 10. FIG. 12 is a diagram illustrating a second layout example of the light receiving unit 10 included in the solid-state imaging device 1 according to the present embodiment. FIG. 13 is a configuration diagram of a solid-state imaging device 2 according to another embodiment.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

FIG. 1 is a diagram showing a schematic configuration of a solid-state imaging device 1 according to the present embodiment. The solid-state imaging device 1 shown in this figure includes a light receiving unit 10, a first signal output circuit 21, a second signal output circuit 22, a first control circuit 31, and a second control circuit 32.

The light receiving unit 10 includes M × N first pixel units P _1,1 to P _{M, N} and I × J second pixel units Q _1,1 to Q _{I, J.} The M × N first pixel portions P _1,1 to P _{M, N} have a common configuration and are two-dimensionally arranged in M rows and N columns. Each first pixel portion P _{m, n} includes a photodiode that generates an amount of charge corresponding to the amount of incident light, and is located in the mth row and the nth column. The I × J second pixel portions Q _1,1 to Q _{I, J} have a common configuration and are two-dimensionally arranged in I rows and J columns. Each second pixel portion Q _{i, j} includes a photodiode that generates an amount of charge corresponding to the amount of incident light, and is located in the i-th row and j-th column. Details of the light receiving unit 10 will be described later.

Here, M and N are integers of 2 or more. I is an integer of 2 or more and less than M, and J is an integer of 2 or more and less than N. m is an integer from 1 to M, and n is an integer from 1 to N. Further, i is an integer from 1 to I, and j is an integer from 1 to J. I is preferably a divisor of M, and J is preferably a divisor of N. For example, M and N are 1024, and I and J are 128. In the case of this example, one second pixel portion Q is provided for 8 × 8 first pixel portions P. Note that the rows and columns for the M × N first pixel portions P _1,1 to P _{M, N} and the rows and columns for the I × J second pixel portions Q _1,1 to Q _{I, J} are shown. Is different.

The photodiodes of the second pixel portions Q _{i, j} are different from the regions where the photodiodes of the M × N first pixel portions P _1,1 to P _{M, N} arranged two-dimensionally are provided. The region is continuously provided over a length corresponding to a plurality of rows or a plurality of columns in the two-dimensional array.

Each first pixel portion P _{m, n} and each second pixel portion Q _{i, j} may be of the PPS (Passive Pixel Sensor) type, but of the APS (Active Pixel Sensor) type. preferable. That is, each first pixel portion P _{m, n} and each second pixel portion Q _{i, j} include an amplification MOS transistor for inputting the charge generated by the photodiode, and the amplification MOS transistor according to the input charge amount. It is preferable to output an electrical signal.

Each first pixel unit P _{m, n} included in the light receiving unit 10 is connected to the first signal output circuit 21. The first signal output circuit 21 outputs a first electric signal having a value corresponding to the amount of charge generated in the photodiode of each first pixel unit P _{m, n} . More specifically, the output terminals of the _M first pixel portions P _{1, n} to P _{M, n} in the n-th column are connected to the first signal output circuit 21 by a common readout wiring. The first signal output circuit 21 sequentially inputs data from each of _{the N} first pixel portions P _{m, 1} to P _{m, N} in the m-th row in order for the first to M-th rows, These N pieces of data are serially output as the first electric signal.

The first control circuit 31 controls the output of the first electric signal by the first signal output circuit 21 for each first pixel unit P _{m, n} , and includes a first timing control circuit 41, a first row selection circuit, and so on. 51 and a first column selection circuit 61. The first timing control circuit 41 controls the operation timings of the first signal output circuit 21, the first row selection circuit 51, and the first column selection circuit 61.

Under the timing control by the first timing control circuit 41, the first row selection circuit 51 selects each row in the two-dimensional array of M × N first pixel portions P _1,1 to P _{M, N} of the light receiving unit 10. Sequentially specified, a predetermined control signal is given to each of _{the N} first pixel portions P _{m, 1} to P _{m, N} in the designated m-th row, and the N first pixel portions P in the m-th row Data is output from each of _{m, 1} to P _{m, N} to the first signal output circuit 21. The first row selection circuit 51 includes an M-stage shift register circuit, and each row can be sequentially designated by an output bit of each stage of the shift register circuit.

Under the timing control by the first timing control circuit 41, the first column selection circuit 61 is configured so that each column in the two-dimensional array of M × N first pixel units P _1,1 to P _{M, N} of the light receiving unit 10. Are sequentially designated, and a control signal indicating the designated n-th column is supplied to the first signal output circuit 21, and each of the N first pixel portions P _{m, 1} to P _{m, N in the m-} th row is designated. Are sequentially output from the first signal output circuit 21 as the first electric signal. The first column selection circuit 61 includes an N-stage shift register circuit, and each column can be sequentially designated by an output bit of each stage of the shift register circuit.

Each second pixel unit Q _{i, j} included in the light receiving unit 10 is connected to the second signal output circuit 22. The second signal output circuit 22 outputs a second electric signal having a value corresponding to the amount of charge generated in the photodiode of each second pixel portion Q _{i, j} . More specifically, the output terminals of the _I second pixel portions Q _{1, j 1} to Q _{I, j} in the j-th column are connected to the second signal output circuit 22 by a common readout wiring. The second signal output circuit 22 inputs data from each of _{the J} second pixel portions Q _{i, 1} to Q _{i, J} in the i-th row in parallel for the first row to the I-th row in parallel, These J pieces of data are serially output as the second electric signal.

The second control circuit 32 controls the output of the second electric signal by the second signal output circuit 22 for each second pixel portion Q _{i, j} , and includes a second timing control circuit 42, a second row selection circuit, and the like. 52 and a second column selection circuit 62. The second timing control circuit 42 controls operation timings of the second signal output circuit 22, the second row selection circuit 52, and the second column selection circuit 62.

The second row selection circuit 52 selects each row in the two-dimensional array of I × J second pixel portions Q _1,1 to Q _{I, J} of the light receiving unit 10 under the timing control by the second timing control circuit 42. A predetermined control signal is given to each of _{the J} second pixel portions Q _{i, 1} to Q _{i, J} in the designated i-th row in order, and the J second pixel portions Q in the _i- th row are designated. Data is output from each of _{i, 1} to Q _{i, J} to the second signal output circuit 22. The second row selection circuit 52 includes an I-stage shift register circuit, and each row can be sequentially designated by an output bit of each stage of the shift register circuit.

Under the timing control by the second timing control circuit 42, the second column selection circuit 62 is configured so that each column in the two-dimensional array of I × J second pixel portions Q _1,1 to Q _{I, J} of the light receiving unit 10. Are sequentially designated, and a control signal indicating the designated j-th column is given to the second signal output circuit 22, and from each of the J second pixel portions Q _{i, 1} to Q _{i, J} in the i-th row. Are sequentially output from the second signal output circuit 22 as a second electric signal. The second column selection circuit 62 includes a J-stage shift register circuit, and each column can be sequentially designated by the output bit of each stage of the shift register circuit.

The first signal output circuit 21 and the second signal output circuit 22 output a first electric signal having a value corresponding to the amount of charge generated in the photodiode PD of each first pixel unit P _{m, n} , and A signal output unit configured to output a second electric signal having a value corresponding to the amount of charge generated in the photodiode PD of the two-pixel unit Q _{i, j} is configured. The first control circuit 31 and the second control circuit 32 control the output of the first electric signal by the signal output unit for each first pixel unit P _{m, n} and output the signal for each second pixel unit Q _{i, j.} The control part which controls the output of the 2nd electric signal by a part is comprised.

The first signal output circuit 21 and the second signal output circuit 22 may have the same configuration except for the difference in the number of data that are input in parallel for each row and output serially. . The first row selection circuit 51 and the second row selection circuit 52 may have the same configuration except for the point related to the difference in the number of designated rows. Further, the first column selection circuit 61 and the second column selection circuit 62 may have the same configuration except for the point relating to the difference in the number of designated columns.

FIG. 2 is a diagram illustrating a configuration of the solid-state imaging device 1 according to the present embodiment. In this figure, the light receiving unit 10 is represented by the first pixel unit P _{m, n} located in the m-th row and the n-th column among the M × N first pixel units P _1,1 to P _{M, N.} The second pixel portion Q _{i, j} located in the i-th row and j-th column of the I × J second pixel portions Q _1,1 to Q _{I, J} is representative. Is shown. The connection relationship between the light receiving unit 10 and the first signal output circuit 21 and the connection relationship between the light receiving unit 10 and the first row selection circuit 51 are related to the first pixel unit P _{m, n.} It is shown. The connection relationship between the light receiving unit 10 and the second signal output circuit 22 and the connection relationship between the light receiving unit 10 and the second row selection circuit 52 are related to the second pixel unit Q _{i, j.} It is shown. For the first signal output circuit 21, components related to the first pixel portion P _{m, n} are shown. In addition, regarding the second signal output circuit 22, components related to the second pixel portion Q _{i, j} are shown.

The first signal output circuit 21 includes N holding circuits 23 ₁ to 23 _N , a difference calculation circuit 25 and an AD conversion circuit 27. The N holding circuits 23 ₁ to 23 _N have a common configuration. Each holding circuit 23 _n is connected to an output terminal of each of the _M first pixel portions P _{1, n} to P _{M, n} in the n-th column by a common readout wiring Vline1 (n). The data output from any one of the first pixel portions P _{m, n} and input via the readout wiring Vline1 (n) is held, and the held data is output to the wirings Hline_s1 and Hline_n1. The difference calculation circuit 25 inputs two data that arrive via the wirings Hline_s1 and Hline_n1, and outputs data corresponding to the difference between the two data to the AD conversion circuit 27. The AD conversion circuit 27 receives the analog data output from the difference calculation circuit 25 and outputs digital data corresponding to the analog data as a first electric signal.

The second signal output circuit 22 includes J holding circuits 24 ₁ to 24 _J , a difference calculation circuit 26, and an AD conversion circuit 28. The J holding circuits 24 ₁ to 24 _J have a common configuration. Each holding circuit 24 _j is connected to an output terminal of each of the _I second pixel portions Q _{1, j} to Q _{I, j} in the j-th column by a common readout wiring Vline2 (j). The data output from any one of the second pixel portions Q _{i, j} and input via the readout wiring Vline2 (j) is stored, and the stored data is output to the wirings Hline_s2 and Hline_n2. The difference calculation circuit 26 inputs two data arrived via the wirings Hline_s2 and Hline_n2, and outputs data corresponding to the difference between the two data to the AD conversion circuit 28. The AD conversion circuit 28 receives the analog data output from the difference calculation circuit 26, and outputs digital data corresponding to the analog data as a second electric signal.

FIG. 3 is a diagram illustrating a circuit configuration of each of the first pixel unit P _{m, n} and the holding circuit 23 _n included in the solid-state imaging device 1 according to the present embodiment. In this figure, the first pixel portion P _{m, n} is shown as a representative of the M × N first pixel portions P _1,1 to P _{M, N} and the N holding circuits 23 ₁ to 23 _N are represented. Of these, the holding circuit 23 _n is shown as a representative.

Each first pixel portion P _{m, n} is of the APS type, and includes a photodiode PD and five MOS transistors T1 to T5. As shown in this figure, the transistor T1, the transistor T2, and the photodiode PD are connected in series in order, the reference voltage Vb1 is input to the drain terminal of the transistor T1, and the anode terminal of the photodiode PD is grounded. Has been.

The transistor T3 and the transistor T4 are connected in series, the reference voltage Vb2 is input to the drain terminal of the transistor T3, and the source terminal of the transistor T4 is connected to the wiring Vline1 (n). A connection point between the transistor T1 and the transistor T2 is connected to the gate terminal of the transistor T3 through the transistor T5. A constant current source is connected to the wiring Vline1 (n). The amplifying transistor T3 outputs an electric signal having a value corresponding to the amount of charge input to the gate terminal.

The Reset1 (m) signal is input to the gate terminal of the reset transistor T1, the Trans1 (m) signal is input to the gate terminal of the transfer transistor T2, and the Address1 (m) signal is input to the gate of the output selection transistor T4. The Hold1 (m) signal is input to the terminal of the transistor T5. The Reset1 (m) signal, Trans1 (m) signal, Address1 (m) signal, and Hold1 (m) signal are output from the first row selection circuit 51 under the control of the first timing control circuit 41, and the mth row. Are commonly input to the _N first pixel portions P _{m, 1} to P _{m, N.}

When the Reset1 (m) signal and the Trans1 (m) signal are at a high level, the junction capacitance portion (charge storage portion) of the photodiode PD is discharged, and when the Hold1 (m) signal is also at a high level, the transistor T3 The potential of the gate terminal is reset. After that, when the Reset1 (m) signal, Trans1 (m) signal, and Hold1 (m) signal become low level, the charge generated in the photodiode is accumulated in the junction capacitor. When the Hold1 (m) signal is at a low level and the Address1 (m) signal is at a high level, a noise component is output from the first pixel unit Pm _{, n} to the wiring Vline1 (n). When the Trans1 (m) signal, the Hold1 (m) signal, and the Address1 (m) signal become high level, the voltage value corresponding to the amount of charge accumulated in the junction capacitance portion of the photodiode PD is changed to the wiring Vline1 (n ) As a signal component.

Each holding circuit 23 _n includes two capacitive elements C ₁ , C ₂ and four switches SW ₁₁ , SW ₁₂ , SW ₂₁ , SW ₂₂ . In the holding circuit 23 _n, the switch _{SW 11} and the switch _{SW 12} is provided between the serially connected to the wiring Vline1 (n) and the wiring Hline_s1, one terminal of the capacitance _{C 1,} the switch _{SW 11} and the switch is connected to the connection point between the SW _12, the other end of the capacitive element C ₁ is grounded. The switch _{SW 21} and the switch _{SW 22} is provided between the serially connected to the wiring Vline1 (n) and the wiring Hline_n1, one terminal of the capacitance _{C 2} is between the switch _{SW 21} and the switch _{SW 22} is connected to the connection point, the other end of the capacitive element C ₂ is grounded.

In the holding circuit 23 _n , the switch SW ₁₁ opens and closes according to the level of the set_s1 signal supplied from the first column selection circuit 61. The switch SW ₂₁ opens and closes according to the level of the set_n1 signal supplied from the first column selection circuit 61. The set_s1 signal and the set_n1 signal are input in common to the _N holding circuits 23 ₁ to 23 _N. The switches SW ₁₂ and SW ₂₂ open and close according to the level of the hshift1 (n) signal supplied from the first column selection circuit 61.

In the holding circuit 23 _n , the noise component output from the first pixel unit P _{m, n} to the wiring Vline1 (n) when the set_n1 signal changes from the high level to the low level and the switch SW ₂₁ is opened is thereafter It is held as a voltage value out_n1 (n) by the capacitance element C _2. set_s1 signal is first pixel unit P _m, the signal component being output from the _n wiring Vline1 to (n) when the switch SW ₁₁ is opened in turn from a high level to a low level, thereafter, the voltage by the capacitive element C ₁ Stored as value out_s1 (n). When hshift1 (n) signal becomes a high level, the switch SW ₁₂ is closed, is output to the voltage value out_s1 (n) is the wiring Hline_s1 that has been held by the capacitor element C _1, The switch SW ₂₂ is closed , voltage value out_n1 that has been held by the capacitor element C ₂ (n) is output to the wiring Hline_n1. The difference between the voltage value out_s1 (n) and the voltage value out_n1 (n) represents a voltage value corresponding to the amount of charge generated in the photodiode PD of the first pixel unit Pm _{, n} .

FIG. 4 is a diagram illustrating a circuit configuration of the difference calculation circuit 25 included in the solid-state imaging device 1 according to the present embodiment. As shown in this figure, the difference calculation circuit 25 includes amplifiers A ₁ to A ₃ , switches SW ₁ and SW ₂ , and resistors R ₁ to R ₄ . Inverting input terminal of the amplifier A ₃ is connected to the output terminal of the buffer amplifier A ₁ via a resistor R _1, and is connected to its own output terminal via the resistor R _3. The non-inverting input terminal of the amplifier A ₃ is connected to the output terminal of the buffer amplifier A ₂ via the resistor R _2, and is connected to the ground potential via the resistor R _4. The output terminal of the amplifier A ₃ is connected to the input terminal of the AD conversion circuit 27. Input terminal of the buffer amplifier A ₁ is connected to the N holding circuits 23 1 _~ 23 _N via the wiring Hline_s1, it is connected to the ground potential via the switch SW _1. The input terminal of the buffer amplifier A ₂ is connected to the _N holding circuits 23 ₁ to 23 _N through the wiring Hline_n ₁ and is connected to the ground potential through the switch SW ₂ .

The switches SW ₁ and SW ₂ of the difference calculation circuit 25 are controlled by the hreset1 signal supplied from the first column selection circuit 61 to open and close. When the switch SW ₁ is closed, the voltage value input to the input terminal of the buffer amplifier A ₁ is reset. When the switch SW ₂ is closed, the voltage value input to the input terminal of the buffer amplifier A ₂ is reset. When the switch _SW 1, SW ₂ is open, the wiring from one of the holding circuit 23 _n of the N holding circuits ₂₃ 1 ~ ₂₃ _N Hline_s1, the voltage value outputted to the Hline_n1 out_s1 (n), out_n1 (n) is input to the input terminals of the buffer amplifiers A ₁ and A ₂ . Assuming that the amplification factors of the buffer amplifiers A ₁ and A ₂ are 1, and the resistance values of the _four resistors R ₁ to R ₄ are equal to each other, the voltage value output from the output terminal of the difference calculation circuit 25 is The difference between the voltage values input through the wiring Hline_s1 and the wiring Hline_n1 is represented, and the noise component is removed.

FIG. 5 is a diagram illustrating a circuit configuration of each of the second pixel unit Q _{i, j} and the holding circuit 24 _j included in the solid-state imaging device 1 according to the present embodiment. In this figure, the second pixel portion Q _{i, j} is representatively shown among the I × J second pixel portions Q _1,1 to Q _{I, J} , and the J holding circuits 24 ₁ to 24 _J Of these, the holding circuit 24 _j is shown as a representative.

Each second pixel portion Q _{i, j} has the same configuration as the first pixel portion P _{m, n} and is of the APS system, and includes a photodiode PD and five MOS transistors T1 to T5. The connection relationship between these elements in the second pixel portion Q _{i, j} is the same as the connection relationship in the first pixel portion P _{m, n} . The source terminal of the transistor T4 is connected to the wiring Vline2 (j). A constant current source is connected to the wiring Vline2 (j). The amplifying transistor T3 outputs an electric signal having a value corresponding to the amount of charge input to the gate terminal.

The Reset2 (i) signal is input to the gate terminal of the reset transistor T1, the Trans2 (i) signal is input to the gate terminal of the transfer transistor T2, and the Address2 (i) signal is input to the gate of the output selection transistor T4. The Hold2 (i) signal is input to the terminal of the transistor T5. The Reset2 (i) signal, Trans2 (i) signal, Address2 (i) signal, and Hold2 (i) signal are output from the second row selection circuit 52 under the control of the second timing control circuit 42, and the i-th row. Are commonly input to the _J second pixel portions Q _{i, 1} to Q _{i, J.} The operation of the second pixel unit Q _{i, j is the same as} the operation of the first pixel unit P _{m, n} .

Each holding circuit 24 _j has the same configuration as the holding circuit 23 _n and includes two capacitive elements C ₁ and C ₂ and four switches SW ₁₁ , SW ₁₂ , SW ₂₁ , and SW ₂₂ . The connection relationship between these elements in the holding circuit 24 _j is the same as the connection relationship in the holding circuit 23 _n . The switches SW ₁₁ and SW ₂₁ are connected to the wiring Vline2 (j). Switch _{SW 12} is connected to the wiring Hline_s2. The switch SW ₂₂ is connected to the wiring Hline_n2.

In the holding circuit 24 _j , the switch SW ₁₁ opens and closes according to the level of the set_s2 signal supplied from the second column selection circuit 62. The switch SW ₂₁ opens and closes according to the level of the set_n2 signal supplied from the second column selection circuit 62. The set_s2 signal and the set_n2 signal are input in common to the _J holding circuits 24 ₁ to 24 _J. The switches SW ₁₂ and SW ₂₂ open and close according to the level of the hshift2 (j) signal supplied from the second column selection circuit 62.

The operation of the holding circuit 24 _{j is the same as} the operation of the holding circuit 23 _n . When hshift2 (j) signal becomes a high level, the switch SW ₁₂ is closed, the voltage value out_s2 that has been held by the capacitor element C ₁ (j) is output to the wiring Hline_s2, The switch SW ₂₂ is closed, capacitor voltage out_n2 which has been held by the element C ₂ (j) is output to the wiring Hline_n2. The difference between the voltage value out_s2 (j) and the voltage value out_n2 (j) represents a voltage value corresponding to the amount of charge generated in the photodiode PD of the second pixel unit Q _{i, j} .

FIG. 6 is a diagram illustrating a circuit configuration of the difference calculation circuit 26 included in the solid-state imaging device 1 according to the present embodiment. The difference calculation circuit 26 has the same configuration as the difference calculation circuit 25, and includes amplifiers A ₁ to A ₃ , switches SW ₁ and SW ₂ , and resistors R ₁ to R ₄ . The connection relationship between these elements in the difference calculation circuit 26 is the same as the connection relationship in the difference calculation circuit 25. Input terminal of the buffer amplifier A ₁ is connected to the J hold circuits 24 1 _~ 24 _J through the wire Hline_s2, is connected to the ground potential via the switch SW _1. Input terminal of the buffer amplifier A ₂ is connected to the J hold circuits 24 1 _~ 24 _J through the wire Hline_n2, is connected to the ground potential via the switch SW _2.

The switches SW ₁ and SW ₂ of the difference calculation circuit 26 are controlled by the hreset2 signal supplied from the second column selection circuit 62 to open and close. When the switch SW ₁ is closed, the voltage value input to the input terminal of the buffer amplifier A ₁ is reset. When the switch SW ₂ is closed, the voltage value input to the input terminal of the buffer amplifier A ₂ is reset. When the switch _SW 1, SW ₂ is open, the wiring from any holding circuit 24 _j of the J holding circuits ₂₄ 1 ~ ₂₄ _J Hline_s2, the voltage value outputted to the Hline_n2 out_s2 (j), out_n2 (j) is input to the input terminals of the buffer amplifiers A ₁ and A ₂ . Assuming that the amplification factors of the buffer amplifiers A ₁ and A ₂ are 1, and the resistance values of the _four resistors R ₁ to R ₄ are equal to each other, the voltage value output from the output terminal of the difference calculation circuit 26 is The difference between the voltage values input through the wiring Hline_s2 and the wiring Hline_n2 is represented, and the noise component is removed.

FIG. 7 to FIG. 9 are diagrams showing examples of arrangement of the first pixel unit P _{m, n} and the second pixel unit Q _{i, j} in the light receiving unit 10. In each of FIGS. 7 and 8, the range of 8 × 8 first pixel portions P _{m, n} is defined as a unit region, and the range of 2 × 2 unit regions is shown. The arrangement of the photodiodes PD of _{m, n} and the second pixel portion Q _{i, j} is shown. In FIG. 9, the range of 8 × 24 first pixel portions P _{m, n} is a unit region, and the range of 2 × 2 unit regions is shown, and the first pixel portion P _{m, n} in the range is shown _. The arrangement of the photodiodes PD of _n and the second pixel part Q _{i, j} is shown. In the light receiving unit 10, such unit regions are two-dimensionally arranged. In each figure, in the two-dimensional array of the first pixel portion P _{m, n} , the first row, the second row, the third row,... 2 columns, 3rd column,...

FIG. 7 is a diagram illustrating a first arrangement example of the first pixel unit P _{m, n} and the second pixel unit Q _{i, j} in the light receiving unit 10 included in the solid-state imaging device 1 according to the present embodiment. In the first arrangement example shown in this figure, the photodiode PD of each second pixel portion Q _{i, j} includes 8 × 8 first pixel portions P _8i-7,8j-7 to P _{8i, 8j,} respectively. It is arranged in the surrounding continuous area (between rows, between columns and around).

FIG. 8 is a diagram illustrating a second arrangement example of the first pixel unit P _{m, n} and the second pixel unit Q _{i, j} in the light receiving unit 10 included in the solid-state imaging device 1 according to the present embodiment. In the second arrangement example shown in this figure, the photodiode PD of each second pixel portion Q _{i, j} is _arranged in each row of 8 × 8 first pixel portions P _8i-7,8j-7 to P _{8i, 8j} . 8 have photosensitive regions (PN junction regions) arranged continuously over the length of eight rows, and these eight photosensitive regions are formed by wirings L _{i, j.} They are connected to each other, and eight photodiodes are connected in parallel. Note that, instead of the arrangement example shown in this figure, the photodiode PD of each second pixel portion Q _{i, j} includes 8 × 8 first pixel portions P _{8i-7, 8j-7} to P _{8i, 8j} has eight photosensitive regions (PN junction regions) arranged continuously over the length of eight rows on one side of each column of _8j , and these eight photosensitive regions are connected by wiring. They may be connected to each other so that eight photodiodes are connected in parallel.

FIG. 9 is a diagram illustrating a third arrangement example of the first pixel unit P _{m, n} and the second pixel unit Q _{i, j} in the light receiving unit 10 included in the solid-state imaging device 1 according to the present embodiment. In the third arrangement example shown in this drawing, a color filter is attached to the photodiode PD of each first pixel portion _{Pm, n} . The photodiodes PD of the first pixel unit P _{m, 3k-2} , the first pixel unit P _{m, 3k-1} and the first pixel unit P _{m, 3k} are provided with color filters having different center wavelengths in the transmission band. It has been. More specifically, the photodiode PD of the first pixel unit _{Pm, 3k-2} is provided with a red filter whose transmission band center wavelength is in the red wavelength band. The photodiode PD of the first pixel unit P _{m, 3k−1} is provided with a green filter whose center wavelength in the transmission band is in the green wavelength band. The photodiode PD of the first pixel unit P _{m, 3k} is provided with a blue filter whose transmission band has a center wavelength in the blue wavelength band. Here, k is a natural number. The photodiode PD of each second pixel portion Q _{i, j} is 24 columns on one side of each row of the 8 × 24 first pixel portions P _8i-7,24j-23 to P _8i, _24j . It has eight photosensitive regions (PN junction regions) arranged continuously over the length, and these eight photosensitive regions are connected to each other by wirings L _{i, j.} The photodiodes are connected in parallel. In this way, high-resolution color imaging can be performed using M × N first pixel portions P _1,1 to P _{M, N.}

The arrangement of the first pixel unit P _{m, n} and the second pixel unit Q _{i, j} in the light receiving unit 10 is not limited to these design examples. The photodiodes of the second pixel portions Q _{i, j} are different from the regions where the photodiodes of the M × N first pixel portions P _1,1 to P _{M, N} arranged two-dimensionally are provided. It suffices if the region is provided continuously over the length of a plurality of rows or a plurality of columns in the two-dimensional array. Thereby, the solid-state imaging device 1 according to the present embodiment can perform high-resolution imaging at high speed using the M × N first pixel portions P _1,1 to P _{M, N} , and I × J Low resolution imaging can be performed at high speed using the second pixel portions Q _1,1 to Q _{I, J.}

In addition, when each first pixel portion P _{m, n} and each second pixel portion Q _{i, j} is of the APS system, high-speed imaging can be performed with high sensitivity and low noise.

In addition, a first signal output circuit 21 that outputs a first electric signal for each first pixel portion P _{m, n} and a second signal output circuit 22 that outputs a second electric signal for each second pixel portion Q _{i, j} . Since the high-resolution imaging using the first pixel portion P _{m, n} and the low-resolution imaging using the second pixel portion Q _{i, j} can be performed in parallel, High-speed imaging is possible.

The first control circuit 31 controls the output of the first electric signal by the first signal output circuit 21 for each first pixel portion P _{m, n} , and the second signal output circuit for each second pixel portion Q _{i, j} . And a second control circuit 32 for controlling the output of the second electric signal by 22 separately, so that high-resolution imaging using the first pixel portion P _{m, n} and the second pixel portion Q _{i, j} are used. It becomes easy to perform the low-resolution imaging that has been performed independently of each other.

10 to 12 are diagrams showing layout examples of the light receiving unit 10 included in the solid-state imaging device 1 according to the present embodiment. The solid-state imaging device 1 according to this embodiment is preferably integrated on a semiconductor substrate, and in that case, for example, has a structure as shown in FIGS. FIG. 10 is a diagram illustrating a first layout example of the light receiving unit 10 included in the solid-state imaging device 1 according to the present embodiment. FIG. 11 is a cross-sectional view taken along the line A-A ′ in the first layout example shown in FIG. 10. FIG. 12 is a diagram illustrating a second layout example of the light receiving unit 10 included in the solid-state imaging device 1 according to the present embodiment.

In the layout examples shown in FIGS. 10 and 12, respectively, the diffusion layer 1 is formed in the region of the photodiode PD of each first pixel portion _{Pm, n} and the region of the photodiode PD of each second pixel portion Q _{i, j.} is there. The diffusion layer 2 is a source and drain region of the transistors T1 to T5 of each first pixel portion _{Pm, n} and a source and drain region of the transistors T1 to T5 of each second pixel portion Q _{i, j} . The polysilicon is the gate of each of the transistors T1 to T5 of each first pixel portion _{Pm, n} and each second pixel portion Qi _{, j} . The metal wiring is a wiring for connecting the reading wiring Vline1 (n) and the reading wiring Vline2 (j), and the transistor T3 and the transistor T5. The upper layer metal in FIG. 12 is a wiring L _{i, j} that connects a plurality of photosensitive regions to each other in each second pixel portion Q _{i, j} .

In FIG. 10 and FIG. 12, the other metal wirings are not shown. Further, in FIG. 11 showing an AA ′ cross section in the first layout example shown in FIG. 10, illustration of an insulating layer and the like is omitted.

Layout example shown in Figure 12 each of the second pixel section Q _i, wiring a plurality of photosensitive regions in _j L _i, but is intended to be connected to each other by _j, the second pixel unit Q _{i, j} is Even in the case of having one photodiode, the photosensitive region of the photodiode (the region of the diffusion layer 1) is wide. Therefore, in order to reduce the resistance, contact holes are provided at various locations in the photosensitive region and metal wiring is provided. It is preferable to connect with.

In the above embodiment, the first signal output circuit 21 and the second signal output circuit 22 are provided separately, and the first column selection circuit 61 and the second column selection circuit 62 are provided separately. However, as in the configuration shown in FIG. 13, the signal output unit 20 may be provided instead of the first signal output circuit 21 and the second signal output circuit 22, or the first column selection circuit 61 and the second column A column selection circuit 60 may be provided instead of the selection circuit 62.

FIG. 13 is a configuration diagram of a solid-state imaging device 2 according to another embodiment. The solid-state imaging device 2 shown in this figure includes a light receiving unit 10, a signal output unit 20, and a control unit 30. The light receiving unit 10 is the same as described above. The signal output unit 20 has the same configuration as that of the first signal output circuit 21, but the operation differs depending on whether high-resolution imaging is performed or low-resolution imaging. The control unit 30 includes a timing control circuit 40, a first row selection circuit 51, a second row selection circuit 52, and a column selection circuit 60. The timing control circuit 40 controls operation timings of the signal output unit 20, the first row selection circuit 51, the second row selection circuit 52, and the column selection circuit 60.

When high-resolution imaging is performed using M × N first pixel portions P _1,1 to P _{M, N} , the column selection circuit 60 performs the same operation as the first column selection circuit 61 and outputs a signal. The unit 20 operates in the same manner as the first signal output circuit 21. On the other hand, when low-resolution imaging is performed using the I × J second pixel portions Q _1,1 to Q _{I, J} , the signal output unit 20 holds J of the N holding circuits. The second electrical signal is output using the circuit, and the column selection circuit 60 controls the signal output unit 20 to perform such an operation.

The solid-state imaging device according to the present invention is not limited to the above-described embodiments and configuration examples, and various modifications are possible.

Here, the solid-state imaging device according to the above embodiment has (1) M × N first pixel portions P _1,1 to P _{M, N} each two-dimensionally arranged in M rows and N columns and including photodiodes. A light receiving portion having I × J second pixel portions Q _1,1 to Q _{I, J} each including a photodiode, and (2) charge generated in the photodiode of each first pixel portion P _{m, n} A signal output unit that outputs a first electric signal having a value corresponding to the amount and outputting a second electric signal having a value corresponding to the amount of electric charge generated in the photodiode of each second pixel unit Q _{i, j} ; (3) Controlling the output of the first electric signal by the signal output unit for each first pixel unit P _{m, n} and controlling the output of the second electric signal by the signal output unit for each second pixel unit Q _{i, j} The control part which comprises is used. Further, a region in which the photodiodes of the M × N first pixel portions P _1,1 to P _{M, N} in which the photodiodes of the second pixel portions Q _{i, j} are two-dimensionally arranged are provided, and Uses a configuration in which different regions are continuously provided over a length corresponding to a plurality of rows or a plurality of columns in the two-dimensional array.

In the solid-state imaging device having the above-described configuration, it is preferable that contact holes are provided at various locations in the photosensitive regions of the photodiodes of the second pixel portions Q _{i, j} and these are connected by metal wiring. In this case, even if the photosensitive region of the photodiode of each second pixel portion Q _{i, j} is wide, the resistance can be reduced.

In the solid-state imaging device, each first pixel portion P _{m, n} and each second pixel portion Q _{i, j} include an amplification MOS transistor that inputs charges generated by the photodiode to the gate terminal. It is preferable to output an electric signal corresponding to the input charge amount from the MOS transistor to the signal output unit. In this way, when each first pixel portion P _{m, n} and each second pixel portion Q _{i, j} are of the APS system, high-speed imaging can be performed with high sensitivity and low noise.

In the solid-state imaging device, the signal output unit includes a first signal output circuit that outputs a first electric signal for each first pixel unit P _{m, n} and a second electric signal for each second pixel unit Q _{i, j} . It is preferable to separately have a second signal output circuit that outputs. In this case, since high-resolution imaging using the first pixel unit P _{m, n} and low-resolution imaging using the second pixel unit Q _{i, j} can be performed in parallel, higher-speed imaging is possible. It is.

In the solid-state imaging device, the control unit controls the first control circuit that controls the output of the first electric signal by the signal output unit for each first pixel unit P _{m, n} , and each second pixel unit Q _{i, j} . It is preferable to separately have a second control circuit that controls the output of the second electric signal by the signal output unit. In this case, it becomes easy to perform high-resolution imaging using the first pixel portion P _{m, n} and low-resolution imaging using the second pixel portion Q _{i, j} independently of each other.

In the solid-state imaging device, it is preferable that a color filter is provided in the photodiode of each first pixel unit _{Pm, n} . In this case, high-resolution color imaging can be performed.

The present invention can be used as a solid-state imaging device capable of performing high-resolution imaging and low-resolution imaging at high speed.

1,2 ... solid-state imaging device, 10 ... receiving unit, 20 ... signal output section, 21 ... first signal output circuit, 22 ... second signal output circuit, 23 n _... holding circuit, 24 j _... holding circuit, 25 and 26 ... difference calculation circuit, 27, 28 ... AD conversion circuit, 30 ... control unit, 31 ... first control circuit, 32 ... second control circuit, 40 ... timing control circuit, 41 ... first timing control circuit, 42 ... second Timing control circuit 51 ... first row selection circuit 52 ... second row selection circuit 60 ... column selection circuit 61 ... first column selection circuit 62 ... second column selection circuit _{Pm, n} ... first pixel Part, Q _{i, j} ... second pixel part.

Claims

I × J second pixel portions each having M × N first pixel portions P 1,1 to P M, N that are two-dimensionally arranged in M rows and N columns and each include a photodiode. A light receiving portion having Q 1,1 to Q I, J ;
The first electric signal having a value corresponding to the amount of charge generated in the photodiodes of the first pixel portions P m, n is output, and the amount of charge generated in the photodiodes of the second pixel portions Q i, j A signal output unit for outputting a second electric signal having a value corresponding to
For each first pixel portion P m, n , the output of the first electric signal by the signal output portion is controlled, and for each second pixel portion Q i, j , the second electric signal is output by the signal output portion. A control unit to control;
With
The photodiodes of the second pixel portions Q i, j are different from the regions where the M × N first pixel portions P 1,1 to P M, N of the two-dimensionally arranged photodiodes are provided. The region is continuously provided over a length corresponding to a plurality of rows or a plurality of columns in the two-dimensional array.
Solid-state imaging device (where M and N are integers of 2 or more, I is an integer of 2 or more and less than M, J is an integer of 2 or more and less than N, m is an integer of 1 or more and M or less, and n is Each integer of 1 to N, i is an integer of 1 to I, and j is an integer of 1 to J).
2. The solid-state imaging device according to claim 1, wherein contact holes are provided at various locations in the photosensitive region of the photodiode of each second pixel portion Q i, j , and these are connected by metal wiring. .
Each first pixel portion P m, n and each second pixel portion Q i, j include an amplifying MOS transistor that inputs the charge generated by the photodiode to the gate terminal, and the amount of input charge from this amplifying MOS transistor The solid-state imaging device according to claim 1, wherein a corresponding electrical signal is output to the signal output unit.
The signal output unit outputs a first signal output circuit for outputting the first electric signal for each first pixel unit P m, n and a second signal for outputting the second electric signal for each second pixel unit Q i, j . The solid-state imaging device according to any one of claims 1 to 3, further comprising a two-signal output circuit.
The control unit controls the output of the first electric signal by the signal output unit for each first pixel unit P m, n , and the signal output unit for each second pixel unit Q i, j 5. The solid-state imaging device according to claim 1, further comprising a second control circuit that controls output of the second electric signal according to 1.
6. The solid-state imaging device according to claim 1, wherein a color filter is provided in the photodiode of each first pixel portion P m, n .