WO2009145441A2

WO2009145441A2 - Inverter circuit

Info

Publication number: WO2009145441A2
Application number: PCT/KR2009/001624
Authority: WO
Inventors: 권오경
Original assignee: 한양대학교 산학협력단
Priority date: 2008-03-31
Filing date: 2009-03-31
Publication date: 2009-12-03
Also published as: TW200945782A; KR20090104362A; WO2009145441A3

Abstract

The present invention relates to an inverter circuit of the same type that comprises N-type or P-type transistors of the same type. The inverter circuit of the present invention includes a first transistor and a second transistor connected in series between a first power source (high level power) and a second power source (low level power), and a third transistor connected between a gate electrode and a drain electrode of the second transistor. An input terminal is connected to gate electrodes of the first transistor and the third transistor, and an output terminal is connected to a common node between the first transistor and the second transistor. The first to third transistors are comprised of transistors of the same type.

Description

Inverter circuit

The present invention relates to an inverter circuit, and more particularly, to a single inverter circuit composed of an N-type or P-type single transistor.

The inverter circuit is a circuit for inverting and outputting an input signal and is widely used in various electronic devices such as flat panel display devices.

Such an inverter circuit is generally composed of opposite types of transistors (ie, N-type transistors and P-type transistors) commonly connected to the same input terminal and connected in series.

1 is a circuit diagram showing a conventional inverter circuit.

Referring to FIG. 1, a conventional inverter circuit is connected in series between a first power supply VDD and a second power supply VSS, and a transistor P1 having an opposite shape in which a gate electrode is commonly connected to an input terminal IN. N1).

Here, the first power source VDD is a high level voltage source, and the second power source VSS is a low level voltage source having a lower voltage level than the first power source VDD. For example, the second power source VSS may be set to the ground power source GND.

The inverter circuit inverts the input signal Vin input to the input terminal IN and outputs the output signal to the output terminal OUT.

To this end, the P-type transistor P1 turned on in response to the low level input signal Vin is connected between the high power source VDD and the output terminal OUT, and the high level input signal. The N-type transistor N1, which is turned on in response to Vin, is connected between the low level second power supply VSS and the output terminal OUT.

In the conventional inverter circuit described above, since only one of the two transistors P1 and N1 having opposite shapes is turned on in correspondence to the voltage level of the input signal Vin, leakage current hardly occurs, so power consumption is small and operation speed is low. It is fast and has the advantage of allowing full swing from the voltage level of the first power supply VDD to the voltage level of the second power supply VSS. However, since the transistors P1 and N1 having opposite shapes must be formed, the manufacturing cost increases and the efficiency of the process decreases, such as an increase in a mask and an additional process step.

Therefore, there is a need to develop a single inverter circuit configured to be composed of an N-type or P-type single transistor to achieve high-speed operation and low power and to stably output the output signal Vout.

It is therefore an object of the present invention to provide a single inverter circuit which stably outputs an output signal while achieving high speed operation and low power.

In order to achieve the above object, the present invention provides first and second transistors connected in series between a first power supply (high level power supply) and a second power supply (low level power supply), and between a gate electrode and a drain electrode of the second transistor. A third transistor connected to the input terminal, an input terminal of the first and third transistors, and an output terminal of the first and second transistors connected to a common node of the first and third transistors. Provides an inverter circuit implemented with transistors of the same type.

Here, the first to the third transistor is implemented as a P-type transistor, the first transistor is connected between the first power supply and the output terminal, the second transistor is between the second power supply and the output terminal. Can be connected.

In addition, the first to third transistors are implemented as an N-type transistor, wherein the first transistor is connected between the second power supply and the output terminal, and the second transistor is connected between the first power supply and the output terminal. Can be connected.

In addition, a first capacitor may be further included between the gate electrode and the source electrode of the second transistor.

In addition, the width W1 / L1 of the channel layer provided in the first transistor may be greater than the width W2 / L2 of the channel layer provided in the second transistor.

According to the inverter circuit of the present invention, by configuring a single inverter circuit using the transistors of the same type, it is possible to reduce the manufacturing cost and improve the efficiency of the process.

In addition, the voltage level of the output signal is fully swinged from the voltage level of the first power supply to the voltage level of the second power supply to output a stable output signal to the output terminal. Can reduce the current. As a result, it is possible to implement an inverter circuit that provides high-speed operation and stable operation characteristics and very low power consumption.

1 is a circuit diagram showing a conventional inverter circuit.

2 is a circuit diagram showing an inverter circuit according to a first embodiment of the present invention.

3 is a circuit diagram showing an inverter circuit according to a second embodiment of the present invention.

4 is a circuit diagram showing an inverter circuit according to a third embodiment of the present invention.

5 is a circuit diagram showing an inverter circuit according to a fourth embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

Referring to FIG. 2, an inverter circuit according to a first embodiment of the present invention includes a first transistor and a second transistor connected in series between a first power supply VDD as a high level voltage source and a second power supply VSS as a low level voltage source. P1 and P2 and a third transistor P3 connected between the gate electrode and the drain electrode of the second transistor P2, and the first to third transistors P1 to P3 are all implemented as P-type transistors. do.

Here, the input terminal IN of the inverter circuit is commonly connected to the gate electrodes of the first and third transistors P1 and P3, and the output terminal OUT is common to the first and second transistors P1 and P2. Connected to the node.

More specifically, the first transistor P1 is connected between the first power supply VDD and the output terminal OUT, and is turned on when a low level input signal Vin is applied to its gate electrode. The terminal OUT is connected to the first power supply VDD. That is, when the low level input signal Vin is applied to the input terminal IN, the high level output signal Vout is output by the first transistor P1.

The second transistor P2 is connected between the second power supply VSS and the output terminal OUT, and is turned on in response to a voltage supplied to its gate electrode to turn the output terminal OUT to the second power supply VSS. ). In particular, the second transistor P2 has a high level input signal in response to a parasitic capacitor (hereinafter referred to as Cgs2, not shown) formed between its gate electrode and the source electrode and the gate voltage controlled by the third transistor P3. When Vin is applied, the output terminal OUT is discharged to the voltage level of the second power supply VSS. That is, when the high level input signal Vin is applied to the input terminal IN, the low level output signal Vout is output by the second transistor P2.

The third transistor P3 is connected between the gate electrode and the drain electrode of the second transistor P2, and accurately controls the voltage of the gate electrode of the second transistor P2 to increase the switching accuracy of the second transistor P2. . The third transistor P3 is turned on when a low level input signal Vin is applied to its gate electrode to diode-connect the second transistor P2. As a result, the second transistor P2 is weakly turned on, and at this time, Cgs2 stores a voltage at which the second transistor P2 can be turned on. The third transistor P3 is turned off when a high level input signal Vin is applied to its gate electrode to float a node to which the gate electrode of the second transistor P2 is connected.

Hereinafter, the operation of the inverter circuit according to the first embodiment of the present invention as described above will be described. For convenience, the high level and low level voltages of the input signal Vin are assumed to be voltages of the first power source VDD and the second power source VSS, respectively.

First, the inverter circuit is set to an initial state by transitioning the input signal Vin to a low level voltage (for example, a ground voltage of 0 V). Then, the first and third transistors P1 and P3 are turned on in response to the input signal Vin.

When the third transistor P3 is turned on, the second transistor P2 diode-connected by the third transistor P3 is weakly turned on, and Cgs2 has a voltage at which the second transistor P2 can be turned on. Stored. However, since the node to which the gate electrode of the second transistor P2 is connected is connected to the second power supply VSS through the third transistor P3, the gate voltage of the second transistor P2 is the second power supply VSS. It is slightly higher than the voltage of. Therefore, the second transistor P2 is weakly turned on compared to the first transistor P1. The gate voltage of the second transistor P2 at this time is defined as an initial voltage.

In the state where the gate voltage of the second transistor P2 is set to the initial voltage in this manner, the first transistor P1 is completely turned on by the low level input signal Vin. Accordingly, since the voltage of the output terminal OUT is charged to the voltage level of the first power supply VDD by the first transistor P1, the high level output signal Vout is output to the output terminal OUT. That is, when the low level input signal Vin is input to the input terminal IN, the high level output signal Vout is output to the output terminal OUT. At this time, in order to output a more stable output signal Vout, the width W1 / L1 of the channel layer provided in the first transistor P1 is equal to the length of the channel layer provided in the second transistor P2. It may be formed larger than (W2 / L2).

Thereafter, when the voltage level of the input signal Vin transitions to the high level, the first and third transistors P1 and P3 are turned off. At this time, the node to which the gate electrode of the second transistor P2 is connected by turning off the third transistor P3 is in a floating state.

However, since the voltage at which the second transistor P2 is turned on is stored in Cgs2 in the previous section (the bootstrapping effect of Cgs2), the second transistor P2 remains turned on. Therefore, the output terminal OUT is connected to the second power supply VSS via the second transistor P2. As a result, the output terminal OUT, which has been charged to the voltage level of the first power supply VDD in the previous section, starts to be discharged. The gate voltage of the second transistor P2 is set to a voltage lower than VSS due to the coupling action of Cgs2 corresponding to the discharge of the output terminal OUT. While falling, the second transistor P2 is completely turned on. At this time, since the first transistor P1 is turned off, the voltage of the output terminal OUT drops to the voltage level of the second power supply VSS. do. That is, when the high level input signal Vin is input to the input terminal IN, the low level output signal Vout is output to the output terminal OUT.

According to the inverter circuit of the present invention as described above, by configuring the inverter circuit using the transistors (P1 to P3) of the same type implemented in a relatively small area it is possible to reduce the manufacturing cost and improve the efficiency of the process.

In addition, by using the third transistor P3 and Cgs2 to maintain the gate voltage of the second transistor P2 in the correct voltage range, the voltage level of the output signal Vout is reduced from the voltage level of the first power source VDD. 2 Full swing is possible up to the voltage level of the power supply (VSS). Therefore, the stable output signal Vout can be output to the output terminal OUT. In addition, since the on / off transition time of the first and second transistors P1 and P2 corresponding to the input signal Vin is short, leakage current due to a short circuit in the transition process can be reduced. That is, the inverter circuit of the present invention has the characteristics of high speed and stable operation characteristics and very small power consumption.

Meanwhile, in FIG. 2, although the bootstrapping effect is generated only by using a parasitic capacitor (that is, Cgs2) formed between the gate electrode and the source electrode of the second transistor, the gate voltage of the second transistor is precisely controlled. It can also form a capacitor of. This will be described later with reference to FIG. 3.

3 is a circuit diagram showing an inverter circuit according to a second embodiment of the present invention. When describing FIG. 3, the same parts as in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

Referring to FIG. 3, a separate capacitor, that is, a first capacitor C1, is further formed between the gate electrode and the source electrode of the second transistor P2. The first capacitor C1 performs the bootstrapping action of the Cgs2 described above with reference to FIG. 2 in addition to the Cgs2 to allow the inverter circuit to operate at a higher speed. That is, by further forming the first capacitor C1, an inverter circuit that operates at a higher speed can be implemented.

Meanwhile, although a single inverter circuit using only the P-type transistor P is illustrated in FIGS. 2 to 3, the P-type transistors P may be replaced by N-type transistors. This will be described later with reference to FIGS. 4 to 5.

4 is a circuit diagram showing an inverter circuit according to a third embodiment of the present invention, and FIG. 5 is a circuit diagram showing an inverter circuit according to a fourth embodiment of the present invention. 4 to 5, detailed descriptions of parts overlapping with those of FIGS. 2 to 3 will be omitted.

4 and 5 are implemented by replacing P-type transistors P of the inverter circuit shown in FIGS. 2 and 3 with N-type transistors N, respectively. However, since the N-type transistors N operate at opposite polarities to the P-type transistors P, the first transistor N1 turned on in response to the high-level input signal Vin has a second power supply. It is connected between the VSS and the output terminal OUT, and the second transistor N2 is connected between the first power supply VDD and the output terminal OUT. In addition, when the high level input signal Vin is supplied, the third transistor N3 which diode-connects the second transistor N2 and turns it on weakly turns on the first power source VDD and the second transistor N2. It is connected between the gate electrodes (that is, between the drain electrode and the gate electrode of the second transistor N2).

As described above, the inverter circuit shown in FIGS. 4 and 5 outputs the low level output signal Vout by the first transistor N1 when the high level input signal Vin is applied, When the input signal Vin is applied, the high level output signal Vout is output by the second transistor N2. Since the rest of the operation principle is the same as that of the inverter circuit shown in FIGS. 2 and 3, a detailed description thereof will be omitted.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various modifications are possible within the scope of the technical idea of the present invention.

Claims

First and second transistors connected in series between a first power supply (high level power supply) and a second power supply (low level power supply);

A third transistor connected between the gate electrode and the drain electrode of the second transistor,

An input terminal is connected to gate electrodes of the first and third transistors, an output terminal is connected to a common node of the first and second transistors, and the first to third transistors are implemented with transistors of the same type. .
The method of claim 1,

The first to third transistors are implemented as p-type transistors,

The first transistor is connected between the first power supply and the output terminal, and the second transistor is connected between the second power supply and the output terminal.
The method of claim 1,

The first to third transistors are implemented as an N-type transistor,

The first transistor is connected between the second power supply and the output terminal, and the second transistor is connected between the first power supply and the output terminal.
The method of claim 1,

And a first capacitor connected between the gate electrode and the source electrode of the second transistor.
The method of claim 1,

And a width W1 / L1 of the channel layer provided in the first transistor is greater than the width W2 / L2 of the channel layer provided in the second transistor.