WO2009144616A1 - Transistor ldmos - Google Patents

Transistor ldmos Download PDF

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Publication number
WO2009144616A1
WO2009144616A1 PCT/IB2009/052080 IB2009052080W WO2009144616A1 WO 2009144616 A1 WO2009144616 A1 WO 2009144616A1 IB 2009052080 W IB2009052080 W IB 2009052080W WO 2009144616 A1 WO2009144616 A1 WO 2009144616A1
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Prior art keywords
region
drain
contact
ldmos transistor
drain contact
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PCT/IB2009/052080
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English (en)
Inventor
Stephan J. C. H. Theeuwen
Freerk Van Rijs
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Nxp B.V.
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Publication of WO2009144616A1 publication Critical patent/WO2009144616A1/fr

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates to an LDMOS transistor. Also, the invention relates to a semiconductor device comprising such an LDMOS transistor.
  • LDMOS RF Laterally Diffused Metal Oxide Semiconductor
  • transistors are now the preferred choice of technology, because of their excellent high power capabilities, gain and linearity.
  • W-CDMA Wideband CDMA
  • W-CDMA Wideband CDMA
  • the performance boost has been primarily accomplished by a rigorous reduction of output losses of the LDMOS transistor.
  • the dominant loss mechanisms for the LDMOS transistor are series and parallel losses. Series losses are due to the ON-resistance, which is determined by the drain-extension and is frequency independent. Parallel losses are due to loss in the output capacitance where the resistive part is a combination of resistance of the drain-extension and substrate resistance.
  • an LDMOS transistor which comprises a source and a drain region in a semiconductor substrate of first conductivity type (e.g., p type), both source and drain region being of a second conductivity type (e.g., n type) and being mutually connected through a channel region over which a gate electrode extends.
  • the drain region comprises a drain contact region and a drain extension region extending from the channel region towards the drain contact region.
  • the drain contact region is highly doped, while the drain extension region is relatively low doped.
  • the drain contact region is electrically connected to a top metal layer via a drain contact.
  • connection between the drain contact and the top metal layer may extend over at least one intermediate metallisation level comprising at least one intermediate metal layer and at least one inter-metal contact.
  • the drain contact is connected to the drain contact region by a suicided area acting as drain suicide region.
  • a reduction in drain width of the drain contact region to reduce the output capacitance of the LDMOS transistor has been the main driver for efficiency improvement during recent development of state-of-art RF-LDMOS transistor technology for base- stations.
  • an LDMOS transistor on a substrate of a first conductivity type, comprising a first source region, a second source region and a common drain region; the first and second source and common drain regions being of a second conductivity type opposite to the first conductivity type; the first source region and the common drain region being mutually connected through a first channel region in the substrate over which a first gate electrode extends; the second source region and the common drain region being mutually connected through a second channel region in the substrate over which a second gate electrode extends; the common drain region being a compound drain region comprising a first drain region, a second drain region and an isolation region; the isolation region separating the first drain region from the second drain region by a separating distance.
  • the LDMOS transistor according to the present invention provides a spread of the heat generating areas and the associated heat transport over a larger area of the substrate, which result in a lower junction temperature of the transistor and a higher current capability.
  • the LDMOS transistor according to the present invention provides a larger distance between the drain metal layer and the shield and gate electrodes, which advantageously reduces the (parasitic) capacitances between the drain metal layer and the shield electrodes (output capacitance) and gate electrodes (feedback capacitance), respectively.
  • the first drain region of the LDMOS transistor comprises a first drain contact region and a first drain extension region which extends from the first channel region towards the first drain contact region
  • the second drain region comprises a second drain contact region and a second drain extension region which extends from the second channel region towards the second drain contact region, and wherein the first and second drain contact regions are electrically contacted by a conductor.
  • the conductor comprises a conductive layer arranged over the isolation region and at least a portion of the first drain contact region and at least a portion of the second drain contact region, the conductive layer being in contact with the first and second drain contact regions.
  • this embodiment allows that a single central drain contact connected to the conductor can be used for contacting the first and second drain regions.
  • the conductor comprises a field plate body, the field plate body comprising a conductor layer, a first contact and a second contact, the conductor layer being arranged on a first dielectric layer that covers at least the first and second drain regions; the first contact being arranged in a contact opening in the first dielectric layer to connect the conductor layer with the first drain contact region; the second contact is arranged in a contact opening in the first dielectric layer to connect the conductor layer with the second drain contact region.
  • this embodiment provides a well defined contact between the conductor and each of the first and second drain regions.
  • the conductor of the LDMOS transistor comprises a first drain contact plate and a second drain contact plate, the first drain contact plate being connected to the first drain contact region through a first contact which is arranged in a contact opening in a first dielectric layer that covers at least the first and second drain regions, the second drain contact plate being connected to the second drain contact region through a second contact which is arranged in a contact opening in the first dielectric layer.
  • the LDMOS transistor comprises a top metal layer arranged for contacting the first and second drain regions, a compound connection between the first drain contact plate and the second drain contact plate, respectively, and the top metal layer; the first drain contact plate being connected to the first drain contact plate by a first connection over at least one intermediate metallisation level comprising at least one intermediate metal layer and at least one inter-metal contact; the second drain contact plate being connected by a second connection over at least one intermediate metallisation level comprising at least one intermediate metal layer and at least one inter-metal contact.
  • An advantage of this embodiment is that by using a compound connection over separate connection paths between the top metal layer and the first and second drain contact regions, respectively, the resistance between top metal and drain regions is reduced which may have the effect of a lower dissipation or may allow to use a higher current in each connection path.
  • the first and second contacts are arranged to partially overlap the isolation region.
  • this allows to reduce the size of the drain contact regions which results in a reduction of the output capacitance between drain and substrate.
  • the LDMOS transistor comprises one or more deep trench isolation regions, which are arranged in the substrate below the isolation region.
  • the one or more deep trench isolation regions reduce the capacitance of the LDMOS transistor relative to the substrate.
  • a width of the first and second drain regions is in the range of about 3 to about 8 ⁇ m
  • the separating distance S is in the range up to about 60 ⁇ m
  • the first and second source regions have a width of about 30 ⁇ m.
  • the isolation region is one selected from a group comprising a shallow trench isolation region, a LOCOS region or an undoped poly-Si region.
  • the undoped poly-Si region is arranged on a high resistance "HRS" Si substrate or a HRS Si substrate region.
  • the conductor is one selected from a metal and doped poly-Si.
  • the conductor acts as a dopant source for the first and second drain contact regions.
  • This embodiment allows to fabricate the first and second drain contact regions by means of a selective doping process in which dopant element diffuses from the conductor layer (which acts as a dopant source) to the drain.
  • a selective doping process in which dopant element diffuses from the conductor layer (which acts as a dopant source) to the drain.
  • such selective doping allows to create drain contact regions with relatively small feature sizes in comparison with drain contact regions created by ion implantation and lithography.
  • the LDMOS transistor according to the invention has a first conductivity type which is p-type and the second conductivity type which is n-type, or vice- versa.
  • the present invention relates to a semiconductor device comprising at least one LDMOS transistor in accordance with the present invention.
  • Fig. 1 shows a cross-sectional view of an LDMOS transistor design from the prior art
  • Fig.2 shows a cross-sectional view of an LDMOS transistor design according to a first embodiment of the present invention
  • Fig. 3 shows a cross-sectional view of an LDMOS transistor design according to a second embodiment of the present invention
  • Fig. 4 shows a cross-sectional view of an LDMOS transistor design according to a third embodiment of the present invention
  • Fig. 5 shows a cross-sectional view of an LDMOS transistor design according to a fourth embodiment of the present invention
  • Fig. 6 shows a cross-sectional view of an LDMOS transistor design according to a fifth embodiment of the present invention.
  • the figures are schematic and not drawn to scale. In general, identical entities are represented by the same reference numeral throughout the Figures.
  • Fig. 1 shows a cross-sectional view of a design of an LDMOS transistor 1 from the prior art.
  • the LDMOS transistor 1 of the prior art is arranged on a substrate 70a, 70b and comprises first and second source regions 10a, 10b, and a common drain region 12.
  • the substrate 70a, 70b comprises a highly doped semiconductor substrate layer 70a of a first conductivity type (e.g., p-type).
  • a first conductivity type e.g., p-type
  • an epitaxial Si layer 70b is arranged on top of the highly doped semiconductor substrate 70a.
  • the source and drain regions 10a, 10b, 12 are of a second conductivity type opposite to the first conductivity type (e.g., n-type).
  • the first source region 10a and the common drain region are mutually connected through a first channel region 28a over which a gate electrode 14a extends.
  • the gate electrode 14a is separated from the first channel region 28a by a gate oxide 26a.
  • the second source region 10b and the common drain region are mutually connected through a second channel region 28b over which a second gate electrode 14b extends.
  • the gate electrode 14b is separated from the second channel region 28b by the gate oxide 26a.
  • the source region 10a, 10b is in connection with the highly doped semiconductor substrate layer 70a.
  • the substrate region is contacted with a highly doped sinker 71a, 71b of the first conductivity type, which is in contact via a suicide or metal layer 72a, 72b to a doped source portion of second conductivity type 73 a, 73b.
  • the doped source portion 73a, 73b of second conductivity type is arranged between the channel region 28a, 28b and the sinker 71a, 71b.
  • the doped source portion 73a, 73b of the second conductivity type is embedded in a well region PW of the first conductivity type.
  • the common drain region 12 comprises a drain contact region 16 and a drain extension region 15 which extends from both the first channel region 28a and the second channel 28b towards the drain contact region 16.
  • the drain contact region 16 is highly doped (n+), while the drain extension region is relatively low doped (n- or n).
  • the drain contact region 16 is electrically connected to a top metal layer 22 via a drain contact 20.
  • the drain contact 20 is connected to the drain contact region 16 by a suicided area acting as drain suicide region 18.
  • the drain contact 20 comprises a conducting body embedded in a liner 20a.
  • connection between the drain contact 20 and the top metal layer may extend over at least one intermediate metallisation level comprising at least one intermediate metal layer 30, 34, 38 and at least one inter-metal contact 32, 36, 40.
  • the at least one inter-metal contact 32; 36; 40 each comprises a conducting body optionally embedded in a respective liner 32a; 36a; 40a.
  • the connection between the drain contact 20 and the top metal layer is embedded in a dielectric layer 50. Between the dielectric layer 50 and the top metal layer a liner 24 may be arranged.
  • Each gate electrode 14a, 14b is arranged with a shield 60 arranged to shield the gate electrode 14a, 14b from the top metal layer 22 and the connection between drain contact region and top metal layer.
  • the shield is connected to the source by several connection lines equally distributed in the third dimension.
  • the drain width of the LDMOS transistor (along horizontal direction X) is typically of the order of 10 ⁇ m.
  • the LDMOS transistor extends in a direction orthogonal to the horizontal direction X and vertical direction Z over a length typically in the order of about 500 ⁇ m.
  • the width of the source region 10a; 10b is about 50 ⁇ m.
  • a parasitic capacitance CP between the drain metal layer 22 and each shield and gate electrode 14a, 14b is symbolically indicated.
  • the value of the parasitic capacitance is inversely proportional to the distance between the top metal layer 22 and the respective gate electrode 14a, 14b.
  • a heat generating zone TZ that relates to a region with relatively elevated temperature due to a localized heat generation during use, is schematically indicated at the drain region 12. Note that the position and size of the zone TZ as depicted here are only indicative.
  • the localized heat generation during use is caused by a combination of a relatively small dimension of the common drain region and a relatively high current flowing through the common drain region.
  • Fig. 2 shows a cross-sectional view of an LDMOS transistor design according to a first embodiment of the present invention.
  • the present invention provides a drain region which comprises a first drain region portion and a second drain region portion which are separated by an isolation region. In this manner a split drain design is provided which allows decoupling of the output capacitance and the thermal properties.
  • the LDMOS transistor according to the present invention has a compound drain region 112, 212 which comprises a first drain region portion 112, a second drain region portion 212 and an isolation region 130. The isolation region separates the first drain region 112 from the second drain region 212 by a separating distance S.
  • the first drain region 112 extends between the isolation region 130 and a first source region 110a in a first horizontal direction X.
  • the first drain region 112 comprises a first drain extension region 115 and a first drain contact region 116.
  • the first drain contact region 116 is arranged adjacent to the isolation region 130 and is embedded in the first drain extension region 115.
  • the second drain region 212 extends in a second horizontal direction opposite to the first horizontal direction between the isolation region 130 and a second source region 110b.
  • the second drain region 212 comprises a second drain extension region 215 and a second drain contact region 216.
  • the second drain contact region 216 is arranged adjacent to the isolation region 130 and is embedded in the second drain extension region 215.
  • the isolation region 130 is arranged to be substantially centered below the top metal layer 22.
  • the drain contact 20 is arranged substantially in the horizontal center of the isolation region 130.
  • a conductor layer 120 is arranged which contacts the drain contact 20 and the respective drain contact region 116, 216 of the first and second drain regions 112, 212.
  • the isolation region is arranged to separate the first and second drain regions by the separating distance S.
  • the distance between the first and second drain regions is relatively enlarged in comparison with the LDMOS transistor from the prior art.
  • a first heat generating zone TZl associated with the first drain region 112 is now separated from a second heat generating zone TZ2 associated with the second drain region 212.
  • the local heating in the drain region(s) during use is now distributed over a larger area and advantageously the junction temperature will therefore be reduced and the current capability will be improved. Note that the position and size of the zones TZl, TZ2 as depicted here are only indicative.
  • the lateral size of the top metal layer is substantially the same in this first embodiment. Consequently, due to the separation S of the first and second drain regions 112, 212 the distance between the top metal layer and the gate electrodes is relatively enlarged in comparison to the prior art. Therefore, the parasitic capacitance CP between the shield electrode 60, gate electrode 14 and the top metal layer 22 is beneficially reduced.
  • the width of the first and second drain regions is in the range of about 3 - about 8 ⁇ m, the separating distance S is in the range up to about 60 ⁇ m.
  • the first and second source regions 110a, 110b may have a width of about 30 ⁇ m. All other dimensions may be substantially identical to those as mentioned in connection with the LDMOS transistor of the prior art.
  • the isolation region 130 may be one selected from a group comprising a shallow trench isolation (STI) region, a LOCOS (local oxidation of silicon) region or an undoped poly-Si region.
  • the undoped poly-Si region may be applied on a high resistance (HRS) Si substrate or a HRS Si substrate region.
  • the first and second drain contact regions 116, 216 are arranged adjacent to the isolation region 130.
  • the conductor layer 120 is arranged to contact each of the drain contact regions 116, 216.
  • the conductor layer 120 may comprise a metal or a doped poly-Si layer.
  • the first and second drain contact regions may be formed either by ion implantation or by a selective doping process in which dopant element diffuses from the conductor layer (which acts as a dopant source) to the drain. Due to the fact that the rate of out-diffusion from the conductor layer to the drain region is higher than the (internal) diffusion rate of the dopant in the drain region material an area comprising a local enrichment of dopant material is created which forms the drain contact region.
  • Fig. 3 shows a cross-sectional view of an LDMOS transistor 101 according to a second embodiment of the present invention.
  • the LDMOS transistor 101 comprises as conductor layer between the first and second drain contact regions 116, 216 a field plate body 220.
  • the field plate body 220 comprises a conductor layer 221, a first contact 222 and a second contact 223.
  • the conductor layer 221 is arranged on a first dielectric layer 52 that covers the first and second drain regions 112, 212 and the isolation region 130.
  • the first contact 222 is arranged in a contact opening 52a in the first dielectric layer 52 to connect the conductor layer 221 with the first drain contact region 116.
  • the second contact 223 is arranged in a contact opening 52b in the first dielectric layer 52 to connect the conductor layer 221 with the second drain contact region 216.
  • the field plate body in this manner is capable of reducing the electric field strength at the edges of the drain contact regions 116, 216, which has the effect that the breakdown voltage is tailored.
  • Fig. 4 shows a cross-sectional view of an LDMOS transistor design according to a third embodiment of the present invention.
  • the LDMOS transistor 102 comprises the compound drain region 112, 212 which comprises the first drain region 112, the second drain region 212 and the isolation region 130.
  • the isolation region separates the first drain region 112 from the second drain region 212 by the separating distance S.
  • the first drain region 112 extends between the isolation region 130 and the first source region 110a in the first horizontal direction X.
  • the first drain region 112 comprises the first drain extension region 115 and a first drain contact region 316.
  • the first drain contact region 316 is arranged adjacent to the isolation region 130 and is embedded in the first drain extension region 115.
  • the second drain region 212 extends in the second horizontal direction opposite to the first horizontal direction between the isolation region 130 and the second source region 110b.
  • the second drain region 212 comprises the second drain extension region 215 and a second drain contact region 416.
  • the second drain contact region 216 is arranged adjacent to the isolation region 130 and is embedded in the second drain extension region 215.
  • the LDMOS transistor 102 comprises a first drain contact plate 320 and a second contact plate 420.
  • the first drain contact plate 320 is connected to the first drain contact region 316 through the first contact 222 which is arranged in a contact opening in the first dielectric layer 52 to connect the first contact plate 320 with the first drain contact region 316.
  • the second drain contact plate 420 is connected to the second drain contact region 416 through the second contact 223 which is arranged in a contact opening in the first dielectric layer 52 to connect the second contact plate 420 with the second drain contact region 416.
  • the LDMOS transistor comprises a compound connection 520, 530, 532, 534,536,538,540, 620, 630, 632, 634, 636, 638, 640 between the first drain contact plate 320 and the second drain contact plate 420, respectively, and the top metal layer 22.
  • the first drain contact plate 320 is connected over a first connection
  • the second drain contact plate 420 is connected over a second connection 620, 630, 632, 634, 636, 638, 640 over at least one intermediate metallisation level comprising at least one intermediate metal layer 630, 634, 638 and at least one inter-metal contact 632, 636, 640.
  • the first and second connection between the first and second drain contact regions respectively and the top metal layer is embedded in the dielectric layer 50.
  • the first drain contact region 316, 416 are created by selective doping of the respective drain region 112, 212 by a dopant element which is supplied from the first and second contact 221, 222, respectively.
  • the first and second contact 221, 222 may comprise either a metal or doped poly-Si.
  • the metal When using a metal, the metal may act as dopant in the drain contact region.
  • the dopant element in the poly-Si may act as dopant in the drain contact region.
  • the first and second drain contact regions may be created by ion implantation.
  • the local heating in the drain region(s) during use is now distributed over a larger area and advantageously the junction temperature will therefore be reduced. Also, the parasitic capacitance CP between the shield electrode 60, gate electrode 14 and the top metal layer 22 is beneficially reduced.
  • a further advantage of this embodiment is that by using a compound connection over separate connection paths 520, 530, 532, 534, 536, 538, 540; 620, 630, 632, 634, 636, 638, 640 between the top metal layer 22 and the first and second drain contact regions 316, 416, respectively, the resistance between top metal and drain regions is reduced which may have the effect of a lower dissipation or may allow to use a higher current in each connection path.
  • Fig.5 shows a cross-sectional view of an LDMOS transistor design according to a fourth embodiment of the present invention.
  • the fourth embodiment of the LDMOS transistor is similar to the third embodiment with the exception of the location of the first and second drain contact regions 316a, 416a.
  • the first and second contacts 222, 223 are arranged to partially overlap the isolation region 130.
  • the first and second drain contact regions 316a, 416a are created by selective doping of the respective drain region 112, 212 by out-diffusion of a dopant element which is supplied from the first and second contact 222, 223, respectively.
  • this allows to reduce the size of the drain contact regions 316a, 416a which result in a reduction of the output capacitance between drain and substrate.
  • the first and second contacts may consist of doped poly-Si or metal as described above.
  • Fig.6 shows a cross-sectional view of an LDMOS transistor design according to a fifth embodiment of the present invention.
  • the LDMOS transistor 103 comprises one or more deep trench isolation regions 730, which are arranged in the substrate below the isolation region 130.
  • the one or more deep trench isolation regions reduce the capacitance of the LDMOS transistor relative to the substrate. It is noted that although the deep trench isolation is shown here in an embodiment similar to the fourth embodiment, it will be appreciated that deep trench isolation regions 730 may be used in combination with each of the embodiments as described above.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Selon l'invention, un transistor LDMOS (100) disposé sur un substrat (70a, 70b) d'un premier type de conductivité comprend: une première région source (10a); une seconde région source (10b), toutes deux présentant une partie source (73); et une région drain commune (112, 212). Les parties source et la région drain commune sont d'un second type de conductivité opposé au premier type de conductivité. Les parties source et la région drain commune sont reliées entre elles par des régions de canal (28a, 28b) respectives ménagées dans le substrat sur lequel des électrodes grilles (14a, 14b) respectives s'étendent. La région drain commune est une région drain mixte comprenant une première région drain (112) et une seconde région drain (212). Une région isolante (130) séparant d'une distance (S) la première région drain de la seconde région drain est ménagée dans la région drain commune pour permettre le découplage de la capacité de sortie et des propriétés thermiques.
PCT/IB2009/052080 2008-05-26 2009-05-19 Transistor ldmos WO2009144616A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP08156916 2008-05-26
EP08156916.2 2008-05-26

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0069429A2 (fr) * 1981-07-06 1983-01-12 Koninklijke Philips Electronics N.V. Transistor à effet de champ à électrode de porte isolée
JPH05102181A (ja) * 1991-10-05 1993-04-23 Rohm Co Ltd 高耐圧半導体装置の製法
JPH11317519A (ja) * 1998-05-01 1999-11-16 Sony Corp 半導体装置およびその製造方法
US6222233B1 (en) * 1999-10-04 2001-04-24 Xemod, Inc. Lateral RF MOS device with improved drain structure
WO2007017803A2 (fr) * 2005-08-10 2007-02-15 Nxp B.V. Transistor ldmos

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0069429A2 (fr) * 1981-07-06 1983-01-12 Koninklijke Philips Electronics N.V. Transistor à effet de champ à électrode de porte isolée
JPH05102181A (ja) * 1991-10-05 1993-04-23 Rohm Co Ltd 高耐圧半導体装置の製法
JPH11317519A (ja) * 1998-05-01 1999-11-16 Sony Corp 半導体装置およびその製造方法
US6222233B1 (en) * 1999-10-04 2001-04-24 Xemod, Inc. Lateral RF MOS device with improved drain structure
WO2007017803A2 (fr) * 2005-08-10 2007-02-15 Nxp B.V. Transistor ldmos

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