WO2009134812A1 - Mosfet with integrated field effect rectifier - Google Patents

Mosfet with integrated field effect rectifier Download PDF

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Publication number
WO2009134812A1
WO2009134812A1 PCT/US2009/041996 US2009041996W WO2009134812A1 WO 2009134812 A1 WO2009134812 A1 WO 2009134812A1 US 2009041996 W US2009041996 W US 2009041996W WO 2009134812 A1 WO2009134812 A1 WO 2009134812A1
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WO
WIPO (PCT)
Prior art keywords
mosfet
field effect
drain
gate
fer
Prior art date
Application number
PCT/US2009/041996
Other languages
French (fr)
Inventor
Alexei Ankoudinov
Vladimir Rodov
Richard Cordell
Original Assignee
Lakota Technologies, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lakota Technologies, Inc. filed Critical Lakota Technologies, Inc.
Priority to EP09739614A priority Critical patent/EP2274770A4/en
Priority to CN200980115255.XA priority patent/CN102037548B/en
Publication of WO2009134812A1 publication Critical patent/WO2009134812A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
    • H01L29/7805—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode in antiparallel, e.g. freewheel diode

Definitions

  • the present invention relates generally to semiconductor transistors, and more specifically to an integration of a field effect rectifier into a MOSFET structure for improving the performance of the MOSFET, and methods therefor.
  • MOSFETs are commonly used for fast switching in electronic circuits. However, where the load is inductive the switching speed is limited due to the intrinsic body diode problem. When the gate voltage is used to switch MOSFET from ON to OFF state (reverse recovery), the intrinsic p-n junction diode has to conduct current, and will inject carriers into the bulk of device. Until the injected carriers are dissipated, the MOSFET will continue to stay in the ON state. This causes slow switching of MOSFET from ON to OFF state and limits the frequency of the MOSFET operation.
  • an external freewheeling diode is often added between the source and the drain of the MOSFET to prevent the injection of carriers during reverse recovery.
  • the addition of the external diode can lead to increased EMI, since the current that was flowing through the MOSFET now has to flow through the external diode and connecting wires.
  • the extra EMI emissions can also limit the switching speed of the MOSFET with freewheeling diode. While the freewheeling diode is typically put as close to MOSFET as possible, the problem of extra EMI remains.
  • MOSFET has an initial appeal, this technology has a limited potential to improve the body diode problem, since the body diode is a P-N junction diode integral to MOSFET structure. Similarly, Schottky diode technology is practically incompatible with MOSFET technologies, since it requires specific metallization not well suited for MOSFET manufacturing.
  • the present invention integrates a Field Effect Rectifier (FER) into a MOSFET to improve the switching characteristics of the MOSFET when coupled to an inductive load, thus improving switching speed without significant adverse effects on EMI.
  • FER Field Effect Rectifier
  • the FER does not replace the body diode, but provides a shunt or a bypass for the current flow around the body diode.
  • the FER technology is compatible with MOSFET technology, permitting substantially conventional processing.
  • the device of the present invention can be configured for either high voltage operation (e.g., a discrete high power device) or low voltage operation (e.g., in an integrated circuit) by adjustment of, for example, the size and resistivity of the epi, gate size, and so on.
  • the low voltage FER is a majority carrier device and prevents the body diode from injecting minority carriers that slow down the MOSFET operation.
  • the high voltage FER will inject fewer carriers due to a particular one sided carrier injection mechanism (Rodov,
  • Figures 1A-1 B show a MOSFET with integrated Field Effect
  • Rectifier in accordance with the invention where Figure 1A shows a DMOS structure and Figure 1 B shows a UMOS structure.
  • the current flow between source and drain is controlled by the gate electrode.
  • the current will flow through the FER during switching, once the Gate voltage does not allow the current flow through the MOSFET.
  • MOSFET occupied area is about the same. Dark blue curve is for MOSFETR and the light blue is for MOSFET.
  • Figure 3 shows leakage current vs. reverse voltage for a conventional MOSFET (red), and MOSFETR with (green) and without
  • the present invention comprises a new MOSFET structure that has integrated therein a field effect rectifier (hereinafter sometimes referred to as a "MOSFETR").
  • MOSFETR field effect rectifier
  • the field effect rectifier provides the alternative path for the current flow when the gate voltage switches OFF the current flow through MOSFET.
  • the injection of the carriers from P-N junction can be reduced or completely eliminated, leading to faster MOSFET switching without significant EMI.
  • the DMOS MOSFETR structure indicated generally at 100 comprises a MOSFET 10OA on the left and an FER 10OB on the right.
  • the FER device can be adjustable as described in U.S. Provisional Patent Application S.N. 60/975,467, filed September 26, 2007, although an FER without adjustable area also can be used in other embodiments.
  • the MOSFETR 100 has three electrodes: source 105, gate 110 and drain 115. The main current flows between the source and drain electrodes through the epitaxial N- layer 125.
  • the P-well 130 is provided to create a depletion layer when reverse bias is applied.
  • the adjustment area comprises the window 140 inside the FER gate and the P++ implantation 145.
  • the adjustment area permits control of the current flow, and thus can be desirable in some embodiments, depending upon the implementation.
  • the gate oxide thickness and the doping levels control the height of the potential barrier under the FER gate 165, and therefore the gate oxide under FER gate 150 can, in some embodiments, have a different thickness than the gate oxide under the MOSFET gate 155.
  • the gate voltage controls the conductivity of the narrow channel 160 under MOS gate 110 and switches the MOSFET between OFF and ON states. The transition from ON to OFF happens at the threshold voltage, which can be adjusted either by using a doping profile under the gate or by changing the thickness of the gate oxide 155.
  • the gate oxide thickness for the sides of MOSFET 155 and FER gate 150 can be varied independently of one another to ensure proper operation of both components.
  • a forward characteristic of an embodiment of MOSFETR in accordance with the invention is shown in Figure 2, where the device is capable of operating at 1 OA at 20V. It can be appreciated by those skilled in the art that the MOSFETR has RDS 1 ON equal to 3.6 milliohm. If the right portion of the device is also a MOSFET, then simulated RDS 1 On is 2.0 milliohm. Notice that, for the characteristics shown in Figure 2, the area of the MOSFET is on the order of 50% of the total area of the MOSFETR. Thus RDS 1 On of MOSFETR per unit area is about 10% smaller. This results because part of the epitaxial layer under the diode is used for conduction during MOSFET operation. It will be appreciated that this effect will, for some embodiments, increase for higher voltage devices. The increase of
  • RDS 1 ON is typically smaller for high voltage devices, since the epitaxial layer becomes thicker to withstand higher reverse voltage.
  • the area covered by MOSFET can be increased to reduce RDS 1 On, while the reduced FER area is still effective for the stored charge reduction.
  • Figure 1 B shows a UMOS MOSFETR structure which operates in a manner substantially identical with that shown in Figure 1A, and like elements are shown with like reference numbers, but with the most significant digit incremented by one.
  • VF will preferably be kept below the knee voltage (-0.7V) of the body diode, where P-N junction starts to inject carriers.
  • a conventional MOSFET will inject carriers during switching while a MOSFETR according to the present invention substantially eliminates this undesirable behavior.
  • FIG. 3 demonstrates that the leakage of a MOSFETR is about 500 ⁇ A at 20V, which is similar to the leakage of a MOSFET.
  • the adjustment area of the MOSFETR plays a role to keep leakage under control, and the leakage of a MOSFETR that does not have adjustment area is on the order of twice as much, or 1 ⁇ A. At higher voltages, the effect of the adjustment area can decrease.
  • Figure 3 illustrates the absence of injected carriers during switching with inductive load.
  • VGS is set to - 5V, which turns OFF the current through MOSFET channel.
  • the electron density distribution in MOSFETR for a 1 OA forward current is substantially the same as the electron density distribution with no current, and thus confirms that no carrier density modulation occurs.
  • the electron concentration in the middle of the epitaxial N- layer can be seen to be on the order of 2.9e16.
  • operation of a conventional MOSFET shows significant injection at 1 OA current: the electron concentration becomes 5.1 e16, or almost double.
  • FIG. 4 shows the simulated transient behavior of MOSFET with and without the integrated diode.
  • the transient time and stored charge are significantly smaller for MOSFETR.
  • the low stored charge and small dl/dt of MOSFETR demonstrate that the device of the present invention is highly suitable for fast switching applications.
  • the static characteristics of MOSFETR are very similar to those of the regular MOSFET, while exhibiting faster switching due to the absence of injected carriers during switching.
  • the integrated FER diode structure is preferred over the discrete solution since it will decrease the level of EMI and allow the faster switching with low EMI.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A modified MOSFET structure comprises an integrated field effect rectifier connected between the source and drain of the MOSFET to shunt current during switching of the MOSFET. The integrated FER provides faster switching of the MOSFET due to the absence of injected carriers during switching while also decreasing the level of EMI relative to discrete solutions. The integrated structure of the MOSFET and FER can be fabricated using N-, multi-epitaxial and supertrench technologies, including 0.25μm technology. Self-aligned processing can be used.

Description

MOSFET with Integrated Field Effect Rectifier
SPECIFICATION
RELATED APPLICATIONS
[001] This application is related to, and claims the benefit of, U.S. Patent Application U.S. Patent Application S.N. 12/238,308, filed
9/25/2008, titled "Adjustable Field Effect Rectifier" (Attached as Appendix A) and through it U.S. Provisional Patent Application S.N. 60/975,467, filed September 26, 2007, as well as U.S. Patent Application S.N. 12/359,094, filed 1/23/2009, entitled "Regenerative Building Block and Diode Bridge Rectifier," and through it U.S. Provisional Patent Application
S.N. 61/022,968, filed January 23, 2008, and also provisional U.S. Patent Application S.N. 61/048,336, filed April 28, 2008, entitled "MOSFET with Integrated Field Effect Rectifier," all of which have the same inventors as the present application and are incorporated herein by reference in full for all purposes.
Field of the Invention
[002] The present invention relates generally to semiconductor transistors, and more specifically to an integration of a field effect rectifier into a MOSFET structure for improving the performance of the MOSFET, and methods therefor.
BACKGROUND OF THE INVENTION
[003] MOSFETs are commonly used for fast switching in electronic circuits. However, where the load is inductive the switching speed is limited due to the intrinsic body diode problem. When the gate voltage is used to switch MOSFET from ON to OFF state (reverse recovery), the intrinsic p-n junction diode has to conduct current, and will inject carriers into the bulk of device. Until the injected carriers are dissipated, the MOSFET will continue to stay in the ON state. This causes slow switching of MOSFET from ON to OFF state and limits the frequency of the MOSFET operation.
[004] To overcome the slow switching of the body diode an external freewheeling diode is often added between the source and the drain of the MOSFET to prevent the injection of carriers during reverse recovery. However, the addition of the external diode can lead to increased EMI, since the current that was flowing through the MOSFET now has to flow through the external diode and connecting wires. The extra EMI emissions can also limit the switching speed of the MOSFET with freewheeling diode. While the freewheeling diode is typically put as close to MOSFET as possible, the problem of extra EMI remains.
[005] While integrating the P-N junction diode technology into the
MOSFET has an initial appeal, this technology has a limited potential to improve the body diode problem, since the body diode is a P-N junction diode integral to MOSFET structure. Similarly, Schottky diode technology is practically incompatible with MOSFET technologies, since it requires specific metallization not well suited for MOSFET manufacturing.
SUMMARY OF THE INVENTION
[006] To overcome the limitations of the prior art, the present invention integrates a Field Effect Rectifier (FER) into a MOSFET to improve the switching characteristics of the MOSFET when coupled to an inductive load, thus improving switching speed without significant adverse effects on EMI.
[007] In the new design, the FER does not replace the body diode, but provides a shunt or a bypass for the current flow around the body diode. The FER technology is compatible with MOSFET technology, permitting substantially conventional processing. Depending upon the implementation, the device of the present invention can be configured for either high voltage operation (e.g., a discrete high power device) or low voltage operation (e.g., in an integrated circuit) by adjustment of, for example, the size and resistivity of the epi, gate size, and so on. Further, unlike P-N junction diodes, the low voltage FER is a majority carrier device and prevents the body diode from injecting minority carriers that slow down the MOSFET operation. The high voltage FER will inject fewer carriers due to a particular one sided carrier injection mechanism (Rodov,
Ankoudinov, Ghosh, Sol.St. Electronics 51 (2007) 714-718).
THE FIGURES
[008] Figures 1A-1 B show a MOSFET with integrated Field Effect
Rectifier in accordance with the invention, where Figure 1A shows a DMOS structure and Figure 1 B shows a UMOS structure. The current flow between source and drain is controlled by the gate electrode. The current will flow through the FER during switching, once the Gate voltage does not allow the current flow through the MOSFET. The Adjustment area
(optional) provides a control of the leakage current.
[009] Figure 2 shows in graphical form forward voltage drop vs. current for the body diode of a regular MOSFET (red) and a MOSFETR (green) in accordance with the invention. With VG=+5V the RDS1ON per
MOSFET occupied area is about the same. Dark blue curve is for MOSFETR and the light blue is for MOSFET.
[0010] Figure 3 shows leakage current vs. reverse voltage for a conventional MOSFET (red), and MOSFETR with (green) and without
(blue) the adjustment area in accordance with the invention. Scale (1A=2.5e-7) [0011] Figure 4 illustrates transients for a 1OA 20V MOSFETR according to the invention.
DETAILED DESCRIPTION OF THE INVENTION
[0012] The present invention comprises a new MOSFET structure that has integrated therein a field effect rectifier (hereinafter sometimes referred to as a "MOSFETR"). The field effect rectifier provides the alternative path for the current flow when the gate voltage switches OFF the current flow through MOSFET. The injection of the carriers from P-N junction can be reduced or completely eliminated, leading to faster MOSFET switching without significant EMI.
[0013] Referring first to Figures 1A, the DMOS MOSFETR structure indicated generally at 100 comprises a MOSFET 10OA on the left and an FER 10OB on the right. In some embodiments, the FER device can be adjustable as described in U.S. Provisional Patent Application S.N. 60/975,467, filed September 26, 2007, although an FER without adjustable area also can be used in other embodiments. As shown in Figure 1 , the MOSFETR 100 has three electrodes: source 105, gate 110 and drain 115. The main current flows between the source and drain electrodes through the epitaxial N- layer 125. The P-well 130 is provided to create a depletion layer when reverse bias is applied. The N++ regions
135 provide ohmic contact for the current flow. The adjustment area comprises the window 140 inside the FER gate and the P++ implantation 145. The adjustment area permits control of the current flow, and thus can be desirable in some embodiments, depending upon the implementation. The gate oxide thickness and the doping levels control the height of the potential barrier under the FER gate 165, and therefore the gate oxide under FER gate 150 can, in some embodiments, have a different thickness than the gate oxide under the MOSFET gate 155. The gate voltage controls the conductivity of the narrow channel 160 under MOS gate 110 and switches the MOSFET between OFF and ON states. The transition from ON to OFF happens at the threshold voltage, which can be adjusted either by using a doping profile under the gate or by changing the thickness of the gate oxide 155. The gate oxide thickness for the sides of MOSFET 155 and FER gate 150 can be varied independently of one another to ensure proper operation of both components.
[0014] When the MOSFETR 100 is in the ON state (e.g., VGS=+5V), current flows through MOSFET channel 160. A forward characteristic of an embodiment of MOSFETR in accordance with the invention is shown in Figure 2, where the device is capable of operating at 1 OA at 20V. It can be appreciated by those skilled in the art that the MOSFETR has RDS1ON equal to 3.6 milliohm. If the right portion of the device is also a MOSFET, then simulated RDS1On is 2.0 milliohm. Notice that, for the characteristics shown in Figure 2, the area of the MOSFET is on the order of 50% of the total area of the MOSFETR. Thus RDS1On of MOSFETR per unit area is about 10% smaller. This results because part of the epitaxial layer under the diode is used for conduction during MOSFET operation. It will be appreciated that this effect will, for some embodiments, increase for higher voltage devices. The increase of
RDS1ON is typically smaller for high voltage devices, since the epitaxial layer becomes thicker to withstand higher reverse voltage. For some embodiments the area covered by MOSFET can be increased to reduce RDS1On, while the reduced FER area is still effective for the stored charge reduction.
[0015] Figure 1 B shows a UMOS MOSFETR structure which operates in a manner substantially identical with that shown in Figure 1A, and like elements are shown with like reference numbers, but with the most significant digit incremented by one.
[0016] When the MOSFET is turned OFF (VGS=-5V), the current will flow through the body diode of MOSFET with VF=0.76V or through the FER of the MOSFETR with VF=0.58. In at least some embodiments, VF will preferably be kept below the knee voltage (-0.7V) of the body diode, where P-N junction starts to inject carriers. Thus, a conventional MOSFET will inject carriers during switching while a MOSFETR according to the present invention substantially eliminates this undesirable behavior.
[0017] In the OFF state, the small leakage current will flow through the AFER channel 165. In at least some embodiments, this leakage is controlled by the potential barrier height and how fast the pinch-off effect takes place. Figure 3 demonstrates that the leakage of a MOSFETR is about 500 μA at 20V, which is similar to the leakage of a MOSFET. The adjustment area of the MOSFETR plays a role to keep leakage under control, and the leakage of a MOSFETR that does not have adjustment area is on the order of twice as much, or 1 μA. At higher voltages, the effect of the adjustment area can decrease.
[0018] Figure 3 illustrates the absence of injected carriers during switching with inductive load. For the example of Figure 3, VGS is set to - 5V, which turns OFF the current through MOSFET channel. The electron density distribution in MOSFETR for a 1 OA forward current is substantially the same as the electron density distribution with no current, and thus confirms that no carrier density modulation occurs. The electron concentration in the middle of the epitaxial N- layer can be seen to be on the order of 2.9e16. In contrast, operation of a conventional MOSFET shows significant injection at 1 OA current: the electron concentration becomes 5.1 e16, or almost double. These injected carriers significantly slow down the operation of a conventional MOSFET with inductive loads.
[0019] Figure 4 shows the simulated transient behavior of MOSFET with and without the integrated diode. The transient time and stored charge are significantly smaller for MOSFETR. The low stored charge and small dl/dt of MOSFETR demonstrate that the device of the present invention is highly suitable for fast switching applications. [0020] In summary, the static characteristics of MOSFETR are very similar to those of the regular MOSFET, while exhibiting faster switching due to the absence of injected carriers during switching. The integrated FER diode structure is preferred over the discrete solution since it will decrease the level of EMI and allow the faster switching with low EMI.
[0021] While the embodiment of the invention described is based on an N- epitaxial layer, it will be appreciated by those skilled in the art that equivalent structures can be formed using multi-epitaxial or supertrench methods, and it is specifically intended that the present invention encompass such alternatives. Likewise, it will be appreciated that the present structure is typically integrated into the larger circuits, and can be fabricated using standard methods including, for example, 0.25μm technology with a mask alignment accuracy of approximately 20nm, as well as others.
[0022] The present invention has been described in detail, including numerous alternatives and equivalents. It is therefore to be understood that the invention is not to be limited by the embodiments specifically described herein, but only by the appended claims.

Claims

We claim:
1. In a metal oxide semiconductor field effect transistor (MOSFET) structure having a gate, a source, and a drain, wherein the current flow between the source and the drain is controlled by the voltage applied to the gate, the improvement comprising a field effect rectifier connected between the source and the drain and serving to shunt current therethrough during switching of the MOSFET.
2. The MOSFET structure of claim 1 wherein the MOSFET is a DMOS structure.
3. The MOSFET structure of claim 1 where the MOSFET is a UMOS structure.
4. The MOSFET structure of claim 1 formed using a self-aligned process.
5. The MOSFET structure of claim 1 formed using not greater than 0.25μm processing.
6. The MOSFET structure of claim 1 formed using N- epitaxial processing.
7. The MOSFET structure of claim 1 formed using multi-epitaxial processing.
8. The MOSFET structure of claim 1 formed using supertrench processing.
9. An integrated semiconductor structure comprising a MOSFET having a gate, a source and a drain, and a field effect rectifier formed in the same substrate as the MOSFET and connected between the source and the drain of the MOSFET for conducting current during switching of the MOSFET.
PCT/US2009/041996 2008-04-28 2009-04-28 Mosfet with integrated field effect rectifier WO2009134812A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP09739614A EP2274770A4 (en) 2008-04-28 2009-04-28 Mosfet with integrated field effect rectifier
CN200980115255.XA CN102037548B (en) 2008-04-28 2009-04-28 MOSFET with integrated field effect rectifier

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US4833608P 2008-04-28 2008-04-28
US61/048,336 2008-04-28

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CN102037548B (en) 2014-04-23
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CN102037548A (en) 2011-04-27

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