WO2009134075A3 - Manufacturing method of inverse staggered poly-si tft with center off-set - Google Patents

Manufacturing method of inverse staggered poly-si tft with center off-set Download PDF

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Publication number
WO2009134075A3
WO2009134075A3 PCT/KR2009/002255 KR2009002255W WO2009134075A3 WO 2009134075 A3 WO2009134075 A3 WO 2009134075A3 KR 2009002255 W KR2009002255 W KR 2009002255W WO 2009134075 A3 WO2009134075 A3 WO 2009134075A3
Authority
WO
WIPO (PCT)
Prior art keywords
tft
center
layer
forming
manufacturing
Prior art date
Application number
PCT/KR2009/002255
Other languages
French (fr)
Other versions
WO2009134075A9 (en
WO2009134075A2 (en
Inventor
Jin Jang
Jae-Hwan Oh
Dong-Han Kang
Original Assignee
Kyunghee University Industrial & Academic Collaboration Foundation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyunghee University Industrial & Academic Collaboration Foundation filed Critical Kyunghee University Industrial & Academic Collaboration Foundation
Publication of WO2009134075A2 publication Critical patent/WO2009134075A2/en
Publication of WO2009134075A3 publication Critical patent/WO2009134075A3/en
Publication of WO2009134075A9 publication Critical patent/WO2009134075A9/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

Disclosed herein is a method for manufacturing a poly-Si TFT with a center offset structure, including (1) preparing a buffer layer on a substrate, (2) preparing a gate electrode with a center offset structure on the buffer layer, (3) forming a gate insulating film on the gate electrode, (4) forming an active layer on the gate insulating film, (5) depositing an n+ amorphous silicon based ohmic contact layer over the active layer, (6) placing source/drain electrodes on the n+ amorphous silicon based ohmic contact layer, and (7) forming a passivation film as a protective layer on the source/drain electrodes. According to the disclosed method, an offset pattern is formed in the center of a gate constituting the TFT to form an offset region in the middle of an active layer channel, so that complicated processes for fabrication of the TFT may be simplified and leakage current may be noticeably inhibited.
PCT/KR2009/002255 2008-04-30 2009-04-29 Manufacturing method of inverse staggered poly-si tft with center off-set WO2009134075A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020080040800A KR20090114919A (en) 2008-04-30 2008-04-30 Manufacturing method of the sameInverse staggered poly-Si TFT with centet off-set
KR10-2008-0040800 2008-04-30

Publications (3)

Publication Number Publication Date
WO2009134075A2 WO2009134075A2 (en) 2009-11-05
WO2009134075A3 true WO2009134075A3 (en) 2010-03-04
WO2009134075A9 WO2009134075A9 (en) 2011-04-28

Family

ID=41255554

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2009/002255 WO2009134075A2 (en) 2008-04-30 2009-04-29 Manufacturing method of inverse staggered poly-si tft with center off-set

Country Status (2)

Country Link
KR (1) KR20090114919A (en)
WO (1) WO2009134075A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101137391B1 (en) 2010-03-24 2012-04-20 삼성모바일디스플레이주식회사 Thin film transistor substrate, method of manufacturing the same, and organic light emitting device having the Thin film transistor substrate

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05110095A (en) * 1991-10-17 1993-04-30 Seiko Epson Corp Thin film mos type transistor
KR0161892B1 (en) * 1995-03-07 1998-12-01 문정환 Thin film transistor
US6825893B2 (en) * 2002-04-08 2004-11-30 Lg. Philips Lcd Co., Ltd. Array substrate for liquid crystal display device having a contact hole situated on active layer and manufacturing method thereof
KR20060045688A (en) * 2004-04-14 2006-05-17 엔이씨 엘씨디 테크놀로지스, 엘티디. Thin film transistor and manufacturing method of the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05110095A (en) * 1991-10-17 1993-04-30 Seiko Epson Corp Thin film mos type transistor
KR0161892B1 (en) * 1995-03-07 1998-12-01 문정환 Thin film transistor
US6825893B2 (en) * 2002-04-08 2004-11-30 Lg. Philips Lcd Co., Ltd. Array substrate for liquid crystal display device having a contact hole situated on active layer and manufacturing method thereof
KR20060045688A (en) * 2004-04-14 2006-05-17 엔이씨 엘씨디 테크놀로지스, 엘티디. Thin film transistor and manufacturing method of the same

Also Published As

Publication number Publication date
WO2009134075A9 (en) 2011-04-28
WO2009134075A2 (en) 2009-11-05
KR20090114919A (en) 2009-11-04

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