WO2009129339A4 - Circular wear leveling - Google Patents
Circular wear leveling Download PDFInfo
- Publication number
- WO2009129339A4 WO2009129339A4 PCT/US2009/040714 US2009040714W WO2009129339A4 WO 2009129339 A4 WO2009129339 A4 WO 2009129339A4 US 2009040714 W US2009040714 W US 2009040714W WO 2009129339 A4 WO2009129339 A4 WO 2009129339A4
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- data
- flash memory
- payload data
- flash
- existing
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7201—Logical to physical mapping or translation of blocks or pages
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Read Only Memory (AREA)
- Arrangements For Transmission Of Measured Signals (AREA)
Abstract
A method for flash memory management comprises providing a head pointer configured to define a first location in a flash memory, and a tail pointer configured to define a second location in a flash memory. The head pointer and tail pointer define a payload data area. Payload data is received from a host, and written to the flash memory in the order it was received. The head pointer and tail pointer are updated such that the payload data area moves in a circular manner within the flash memory.
Claims
1. A method for flash memory management, comprising: providing a head pointer configured to define a first location in a flash memory; providing a tail pointer configured to define a second location in the flash memory, wherein the head pointer and tail pointer define the beginning and lend of a payload data area, respectively; receiving payload data from a host; writing the payload data to the flash memory in the order the payload data was received from the host; and updating the head pointer and the tail pointer such that the payload data area moves in a circular manner within the flash memory.
2. The method of claim 1, wherein updating the head pointer and the tail pointer causes the flash memory to wear substantially uniformly.
3. The method of claim 1, further comprising a second head pointer and a second tail pointer such that two payload data areas move in a circular manner wifhin the flash memory.
4. The method of claim 1, further comprising relocating at least a portion of existing payload data in the flash memory, wherein the relocating causes the at least a portion of existing payload data to be stored in order with respect to time receipt from the host in the flash memory,
5. The method of claim 1, further comprising providing at least one data structure configured to locate the physical address of the payload data written to the flash memory, wherein all data structures that are used to locate the physical address of the payload data are contained entirely in random access memory.
6. The method of claim 5, wherein the at least one data structure is configured to track the payload data via a logical page size which is different than a physical page size of the flash memory.
7. A method for data management on a flash memory device, comprising: defining a circular storage space comprised of erase blocks;
27 receiving payload data from a host; writing the payload data in the order it was received from tfce host to at least one erase block in the circular storage space; and relocating at least a portion of existing payload data in the circular storage space, wherein relocating existing payload data comprises operations on erase blocks located ahead of the head pointer.
8. The method of claim 7, wherein the relocating at least a portion of existing payload data in the circular storage space causes existing payload data to pe stored substantially contiguously in the circular storage space.
9. The method of claim 7, wherein relocating existing paVload data comprises operations on erase blocks located behind the head pointer and ahead of the tail pointer.
10. The method of claim 7, further comprising providing at least one data structure configured to locate the physical address of the payload data written 13 the at least one erase block, wherein all data structures that are used to locate the physical address of the payload data are contained entirely in random access memory.
11. The method of claim 1, wherein relocating existing payload d^ta comprises merging at least two partially obsolete erase blocks into a single erase block.
12. The method of claim 7, further comprising relocating at least a portion of existing payload data such that the antipayload area is substantially contiguous within the circular storage space.
13. The method of claim 7, further comprising reporting, to a [host computer, a first reported storage capacity of the flash memory device which is smaller than the actual capacity of the flash memory device, wherein the reporting is performed responsive to a number of erase blocks in an antipayload area falling below a thresholp value.
14. The method of claim 13, further comprising reporting, to the hbst computer, a second reported storage capacity of the flash memory device which is larger than the first reported storage capacity, wherein the reporting is performed responsive to a ήumber of erase blocks in an aπtipayload area exceeding a threshold value,
15. The method of claim 10, wherein the at least one data structure is configured to track the payload data via a logical page size which is different than a physical page size of at least one of the erase blocks.
16. The method of claim lύ, further comprising storing, in the at ljϊast one data structure, a record of one or more bad pages in at least one of the erase blocks.
17. The method of claim 7, wherein writing the payload data comprises writing to two erase blocks responsive to a single write command.
18. The method of claim 7, wherein the circular storage space comprises at least two flash memory chips having different storage capacities.
19. The method of claim 7, further comprising storing, in at least one of the erase blocks, error correcting information associated with payload data written to a different erase block.
20. A solid state drive, comprising: a flash memory controller configured to receive payload data f -om a host; at least one flash chip configured as a circular storage spi ce, wherein the flash memory controller is configured to write the payload data to the at lealst one flash chip in the order it was received from the host; and a random access memory for containing at least one data structure configured to locate the physical address of the payload data written to the at least < ne flash chip, wherein all data structures that are used to locate the physical address of the payload data are contained entirely in the random access memory.
21, The solid state drive of claim 20, wherein the flash memory Controller comprises at least two head pointers such that consecutively received pages of pajjload data are stored in different erase blocks in the circular storage space.
29
22. The solid state drive of claim 20, wherein the at least one data [structure is configured to track the payload data via a logical page size which is smaller than |a physical page size of the at least one flash chip.
23. The solid state drive of claim 20, wherein the at least one datalstmcture is configured to track the payload data via a logical page size which is different than a physical page size of the at least one flash chip.
24, The solid state drive of claim 20, wherein the at least one flasra chip comprises a first erase block and a second erase block, and wherein the first erase block contains error correcting information associated with payload data written to the secφnd erase block.
25, The solid state drive of claim 20, wherein the solid state drivel comprises at least two flash memory chips having different storage capacities,
26, A data storage system, comprising: a flash memory configured as a circular storage space; a flash controller coupled to the flash memory, wherein i he flash controller is configured to write incoming data to the flash memory in the order th< data is received; and a random access memory for containing at least one data structure configured to locate the physical address of the data written to the flash memory, wherein all data structures that are used to locate the physical address of the data are contained entirely in the random access memory.
27. The data storage system of claim 26, wherein the flash contjroller is configured to relocate at least a portion of existing data in the circular storage space, wherein the relocating is performed based on a timestamp associated with the at least a portion of existing data.
28. The data storage system of claim 26, wherein the flash controller is configured to relocate at least a portion of existing data in order to preserve a temporal order of the data as received from a host computer.
30
29. The data storage system of claim 26, wherein the at least one data structure is configured to support relocating at least a portion of existing pay Io id data in the circular storage space such that existing payload data is stored substantial y contiguously in the circular storage space, and wherein relocating existing payload data c jmpriεes operations on erase blocks in the flash memory which are located behind a head pointer and ahead of a tail pointer.
30. The data storage system of claim 26, wherein the flash merriory comprises at least two flash memory chips having different storage capacities.
31 , The data storage system of claim 26, wherein the flash meπiory comprises at least two flash memory chips having different physical page sizes.
31
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US4506008P | 2008-04-15 | 2008-04-15 | |
| US61/045,060 | 2008-04-15 | ||
| US12/103,273 US8566505B2 (en) | 2008-04-15 | 2008-04-15 | Flash management using sequential techniques |
| US12/103,277 | 2008-04-15 | ||
| US12/103,277 US8028123B2 (en) | 2008-04-15 | 2008-04-15 | Circular wear leveling |
| US12/103,273 | 2008-04-15 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| WO2009129339A2 WO2009129339A2 (en) | 2009-10-22 |
| WO2009129339A3 WO2009129339A3 (en) | 2010-03-04 |
| WO2009129339A4 true WO2009129339A4 (en) | 2010-04-22 |
Family
ID=41199716
Family Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2009/040713 WO2009129338A2 (en) | 2008-04-15 | 2009-04-15 | Flash management using sequential techniques |
| PCT/US2009/040715 WO2009129340A2 (en) | 2008-04-15 | 2009-04-15 | Flash memory management |
| PCT/US2009/040714 WO2009129339A2 (en) | 2008-04-15 | 2009-04-15 | Circular wear leveling |
Family Applications Before (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2009/040713 WO2009129338A2 (en) | 2008-04-15 | 2009-04-15 | Flash management using sequential techniques |
| PCT/US2009/040715 WO2009129340A2 (en) | 2008-04-15 | 2009-04-15 | Flash memory management |
Country Status (1)
| Country | Link |
|---|---|
| WO (3) | WO2009129338A2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8959416B1 (en) | 2011-12-16 | 2015-02-17 | Western Digital Technologies, Inc. | Memory defect management using signature identification |
| US8947961B2 (en) * | 2013-03-12 | 2015-02-03 | Macronix International Co., Ltd. | Management of non-volatile memory |
| TWI653630B (en) * | 2018-05-14 | 2019-03-11 | 慧榮科技股份有限公司 | Method for accessing flash memory module and related flash memory controller and electronic device |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3197815B2 (en) * | 1996-04-15 | 2001-08-13 | インターナショナル・ビジネス・マシーンズ・コーポレ−ション | Semiconductor memory device and control method thereof |
| US5930504A (en) * | 1996-07-22 | 1999-07-27 | Intel Corporation | Dynamic nonvolatile memory update in a computer system |
| US6412080B1 (en) * | 1999-02-23 | 2002-06-25 | Microsoft Corporation | Lightweight persistent storage system for flash memory devices |
| US20030163633A1 (en) * | 2002-02-27 | 2003-08-28 | Aasheim Jered Donald | System and method for achieving uniform wear levels in a flash memory device |
| WO2004001605A1 (en) * | 2002-06-19 | 2003-12-31 | Tokyo Electron Device Limited | Memory device, memory managing method and program |
| KR100944054B1 (en) * | 2002-08-29 | 2010-02-24 | 파나소닉 주식회사 | Semiconductor memory device and method for writing data into flash memory |
| US7330927B1 (en) * | 2003-05-07 | 2008-02-12 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Apparatus and methodology for a pointer manager |
| ITMI20031126A1 (en) * | 2003-06-05 | 2004-12-06 | St Microelectronics Srl | MASS MEMORY DEVICE BASED ON A MEMORY |
| US6906961B2 (en) * | 2003-06-24 | 2005-06-14 | Micron Technology, Inc. | Erase block data splitting |
| US20050038792A1 (en) * | 2003-08-14 | 2005-02-17 | Johnson Ted C. | Apparatus and method for operating circular files |
| US7139864B2 (en) * | 2003-12-30 | 2006-11-21 | Sandisk Corporation | Non-volatile memory and method with block management system |
| US8607016B2 (en) * | 2004-07-21 | 2013-12-10 | Sandisk Technologies Inc. | FAT analysis for optimized sequential cluster management |
| US20070276973A1 (en) * | 2004-09-30 | 2007-11-29 | Intel Corporation | Managing queues |
| US7464243B2 (en) * | 2004-12-21 | 2008-12-09 | Cisco Technology, Inc. | Method and apparatus for arbitrarily initializing a portion of memory |
| US7509474B2 (en) * | 2005-06-08 | 2009-03-24 | Micron Technology, Inc. | Robust index storage for non-volatile memory |
| JP2007272635A (en) * | 2006-03-31 | 2007-10-18 | Toshiba Corp | Memory system and controller |
| US20080046630A1 (en) * | 2006-08-21 | 2008-02-21 | Sandisk Il Ltd. | NAND flash memory controller exporting a logical sector-based interface |
-
2009
- 2009-04-15 WO PCT/US2009/040713 patent/WO2009129338A2/en active Application Filing
- 2009-04-15 WO PCT/US2009/040715 patent/WO2009129340A2/en active Application Filing
- 2009-04-15 WO PCT/US2009/040714 patent/WO2009129339A2/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| WO2009129339A2 (en) | 2009-10-22 |
| WO2009129338A3 (en) | 2010-02-25 |
| WO2009129338A4 (en) | 2010-04-08 |
| WO2009129340A4 (en) | 2010-03-25 |
| WO2009129338A2 (en) | 2009-10-22 |
| WO2009129339A3 (en) | 2010-03-04 |
| WO2009129340A3 (en) | 2010-01-21 |
| WO2009129340A2 (en) | 2009-10-22 |
| WO2009129338A8 (en) | 2009-12-10 |
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