TWI653630B - Method for accessing flash memory module and related flash memory controller and electronic device - Google Patents

Abstract

The invention discloses a method for accessing a flash memory module, including the following steps: receiving a first piece of data from a main device; reading a specific data from the flash memory module, and The first data and the specific data are temporarily stored in a buffer memory and then written to a first data page in the flash memory module; receiving a second data from the host device; judging the second Whether the pen data and the first piece of data have consecutive logical addresses; and if the second piece of data and the first piece of data have consecutive logical addresses, without reading the flash memory module Writing the second data together with a portion of the first data and the specific data temporarily stored in the buffer memory to a second data page in the flash memory module.

Description

Method for accessing flash memory module and related flash memory controller And electronic devices

The present invention relates to flash memory, in particular to a method for accessing flash memory modules and related flash memory controllers and electronic devices.

In the access of the flash memory module, the characteristic is that the data is written in units of pages, and the data erasing is performed in units of blocks. Therefore, if the logical address of the written data is not at the starting logical address of the data page, the flash memory controller must supplement the written data with the head and tail data before writing to the flash memory In the module. For example, assuming that the size of a data page is 16 kilobytes (16KB), it can be divided into 4 sectors, and writing data is used to update the second sector of the data page , Then the flash memory controller must read the contents of the first, third, and fourth sections of the data page from the flash memory module, and write it to another data together with the written data Page. As described above, since the content of the flash memory needs to be read separately to supplement the head and tail data of the written data, the efficiency of accessing the flash memory is reduced. In addition, with the trend of increasing size of data pages in recent years, the probability that the data to be written is aligned with the starting logical address of the data page is getting smaller and smaller, and at the same time, the length of the top and bottom data is also increased. Increase.

On the other hand, for some electronic devices with small buffer memory, such as driving recorders or some recording devices, usually a large continuous data (for example, one million bytes) is cut into multiple Small data (for example, four thousand bytes), however, these multiple small data need to perform the above operation to fill the head and tail data each time it is written, so the performance of the flash memory will be seriously reduced .

Therefore, one of the objects of the present invention is to provide a method for accessing a flash memory module, which can greatly reduce the number of times that the flash memory module needs to be read to fill in the head and tail data and improve the flash memory Effectiveness to solve the problems in the prior art.

In one embodiment of the present invention, a method for accessing a flash memory module is disclosed, wherein the flash memory module includes a plurality of blocks, each block includes a plurality of data pages, and the The method includes the following steps: receiving a first data from a main device; reading specific data from a specific data page in the flash memory module, and temporarily storing the first data together with the specific data in a Buffer memory; write the first data together with the specific data to a first data page in the flash memory module; receive a second data from the host device; determine the second data Whether there is a continuous logical address with the first piece of data to produce a judgment result; and if the judgment result indicates that the second piece of data and the first piece of data have consecutive logical addresses, the flash is not read In the case of a memory module, the second data together with a portion of the first data and the specific data temporarily stored in the buffer memory is written to a second in the flash memory module Information page.

In another embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, the flash memory module includes multiple Each block contains multiple data pages, and the flash memory controller includes a read-only memory and a microprocessor. The read-only memory system is used to store a code, and the microprocessor is used to execute the code to control access to the flash memory module. In the operation of the flash memory controller, when the microprocessor receives a first data from a host device, the microprocessor reads a specific data from a specific data page in the flash memory module Data, and temporarily store the first data and the specific data in a buffer memory, and write the first data and the specific data to a first data page in the flash memory module; And when the microprocessor receives a second piece of data from the host device, the microprocessor determines whether the second piece of data and the first piece of data have consecutive logical addresses to generate a judgment result, and if it is the The judgment result indicates that the second piece of data and the first piece of data have consecutive logical addresses. Without reading the flash memory module, the microprocessor temporarily stores the second piece of data together with the A part of the first data and the specific data of the buffer memory is written to a second data page in the flash memory module.

In another embodiment of the present invention, an electronic device is disclosed, which includes a flash memory module and a flash memory controller. In the operation of the electronic device, when the flash memory controller receives a first piece of data from a host device, the flash memory controller reads from a specific data page in the flash memory module Fetch specific data, and temporarily store the first data and the specific data in a buffer memory, and write the first data and the specific data to a first data in the flash memory module Page; and when the flash memory controller receives a second piece of data from the host device, the flash memory controller determines whether the second piece of data and the first piece of data have consecutive logical addresses Generates a judgment result, and if the judgment result indicates that the second piece of data and the first piece of data have consecutive logical addresses, without reading the flash memory module, the flash memory controls The device writes the second data together with the first data temporarily stored in the buffer memory and a part of the specific data to a second data page in the flash memory module.

110‧‧‧Flash memory controller

112‧‧‧Microprocessor

112C‧‧‧Code

112M‧‧‧Read-only memory

114‧‧‧Control logic

116‧‧‧buffer memory

118‧‧‧Interface logic

120‧‧‧Flash memory module

130‧‧‧Main device

132‧‧‧Encoder

134‧‧‧decoder

202‧‧‧Specific information page

210, 220, 230, 240 ‧‧‧ data page

D1 ~ D4‧‧‧Information

D1’‧‧‧ First document

D2’‧‧‧ Second data

D3’‧‧‧ Third data

D4’‧‧‧ Fourth data

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the invention.

FIG. 2 is a schematic diagram of a host device writing multiple data to a memory device according to an embodiment of the invention.

FIG. 1 is a schematic diagram of a memory device 100 according to an embodiment of the invention. The memory device 100 includes a flash memory module 120 and a flash memory controller 110, and the flash memory controller 110 is used to access the flash memory module 120. According to this embodiment, the flash memory controller 110 includes a microprocessor 112, a read only memory (Read Only Memory, ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic 118. The read-only memory 112M is used to store a program code 112C, and the microprocessor 112 is used to execute the program code 112C to control access to the flash memory module 120 (Access). The control logic 114 includes an encoder 132 and a decoder 134, wherein the encoder 132 is used to encode the data written into the flash memory module 120 to generate a corresponding check code (or error correction) Error Correction Code (ECC), and the decoder 134 is used to decode the data read from the flash memory module 120.

Under typical conditions, the flash memory module 120 includes a plurality of flash memory chips, and each flash memory chip includes a plurality of blocks, and the flash memory controller 110 controls the flash memory. The operation of erasing data by the memory module 120 is performed in units of blocks. In addition, a block can record a specific number of data pages (Page), wherein the operation of the flash memory controller 110 writing data to the flash memory module 120 is performed in units of data pages. In this embodiment, flash memory The body module 120 is a 3D NAND-type flash memory (3D NAND-type flash) module.

In practice, the flash memory controller 110 that executes the program code 112C through the microprocessor 112 can use its own internal components to perform many control operations, such as: using the control logic 114 to control the flash memory module 120 Access operations (especially access operations on at least one block or at least one data page), using buffer memory 116 for required buffer processing, and using interface logic 118 to communicate with a host device (Host Device) 130 . The buffer memory 116 is implemented by random access memory (Random Access Memory, RAM). For example, the buffer memory 116 may be static random access memory (Static RAM, SRAM), but the invention is not limited thereto.

In an embodiment, the memory device 100 may be a portable memory device (for example, a memory card that conforms to SD / MMC, CF, MS, XD standards), and the host device 130 is an electronic device that can be connected to the memory device. For example, mobile phones, notebook computers, desktop computers ... and so on. In another embodiment, the memory device 100 may be a solid-state drive or an embedded storage that conforms to Universal Flash Storage (UFS) or Embedded Multi Media Card (EMMC) specifications The device may be installed in an electronic device, such as a mobile phone, a notebook computer, a desktop computer, a video recording device, or a driving recorder, and the main device 130 may be a processor of the electronic device.

FIG. 2 is a schematic diagram of the main device 130 writing multiple pieces of data to the memory device 100 according to an embodiment of the present invention, in which four pieces of data D1 ′ ~ D4 ′ corresponding to different write commands are taken as an example in this embodiment To illustrate, the size of the four data D1 '~ D4' is 4KB, and the size of each data page in the flash memory module is 16KB. During the operation of the memory device 100, the flash memory controller 110 receives the first data D1 'from the autonomous device 130 according to a first write command. Then, the flash memory controls The device 110 reads data D2 ~ D4 from a specific data page 202 of a specific block in the flash memory module 120, and temporarily stores the first data D1 'together with the retrieved data D2 ~ D4 in the buffer memory 116 , And then write the first data D1 'together with the data D2 ~ D4 to a first data page 210 of a block in the flash memory module 120. In this embodiment, the first data D1 'and the data D1 in the specific data page 202 have the same logical address (ie, the same logical data page), that is, the first data D1' is used to update the data The content of D1, but the invention is not limited to this.

Then, the flash memory controller 110 receives the second data D2 'from the autonomous device 130 according to a second write command. At this time, the microprocessor 112 determines whether the second data D2' and the first data D1 'have Continuous logical addresses. In this embodiment, it is assumed that the second data D2 'and the first data D1' have continuous logical addresses, so the microprocessor 112 directly uses the second data D2 'to update the current The data D2 temporarily stored in the buffer memory 116, that is, the data temporarily stored in the buffer memory 116 becomes the first data D1 ', the second data D2', and the data D3 previously read from the specific data page 202, D4. Then, the first data D1 'and the second data D2' are written into a second data page 220 of the block in the flash memory module 120 together with the data D3 and D4. It should be noted that during the flash memory controller 110, the autonomous device 130 receives the second data D2 'and writes the second data D2' to the flash memory module 120, the flash memory controls The device 110 directly uses the contents of the temporary buffer memory 116 to supplement the head and tail data of the second data D2 ', that is, the first data D1' temporarily stored in the buffer memory 116 is used to supplement the second data D2 '. In front of the pen data D2 ', and use the data D3 and D4 temporarily stored in the buffer memory 116 to fill in the back of the second pen data D2' to form a complete data page size (ie, 16KB); flash at this time The memory controller 110 does not read the data in the flash memory module 120 to supplement the head and tail data of the second data D2 ', so as to improve the efficiency of the flash memory controller 110.

Then, the flash memory controller 110 receives the autonomous device 130 according to a third write command The third piece of data D3 ', at this time the microprocessor 112 will determine whether the third piece of data D3' and the second piece of data D2 'have consecutive logical addresses. In this embodiment, it is assumed that the third piece of data D3' and The second data D2 'has a continuous logical address, so the microprocessor 112 directly uses the third data D3' to update the data D3 currently stored in the buffer memory 116, that is, the data temporarily stored in the buffer memory 116 Becomes the first data D1 ', the second data D2', the third data D3 'and the previously read data D4 from the specific data page 202. Then, the first data D1 ', the second data D2', the third data D3 ', and the data D4 are written to a third data page 230 of the block in the flash memory module 120. It should be noted that during the flash memory controller 110, the autonomous device 130 receives the third data D3 'and writes the third data D3' to the flash memory module 120, the flash memory controls The device 110 directly uses the content of the temporary buffer memory 116 to supplement the head and tail data of the third piece of data D3 ', that is, uses the first piece of data D1' and the second piece of data temporarily stored in the buffer memory 116 D2 'is added in front of the third data D3', and the data D4 temporarily stored in the buffer memory 116 is used to fill in the back of the third data D3 'to form a complete data page size (ie, 16KB); At this time, the flash memory controller 110 does not read the data in the flash memory module 120 to supplement the head and tail data of the third data D3 '.

Finally, the flash memory controller 110 receives the fourth data D4 'from the autonomous device 130 according to a fourth write command. At this time, the microprocessor 112 determines whether the fourth data D4' and the third data D3 'have Continuous logical addresses. In this embodiment, it is assumed that the fourth data D4 'and the third data D3' have continuous logical addresses, so the microprocessor 112 directly uses the fourth data D4 'to update the current The data D4 temporarily stored in the buffer memory 116, that is, the data temporarily stored in the buffer memory 116 becomes the first data D1 ', the second data D2', the third data D3 ', and the fourth data D4' . Then write the first data D1 ', the second data D2', the third data D3 and the fourth data D4 'to a fourth data page 240 of the block in the flash memory module 120 . It should be noted that in the flash memory controller 110, the autonomous device 130 receives the fourth data D4 'and writes the fourth data D4' to the flash memory module 120 In the process, the flash memory controller 110 directly uses the content of the temporary buffer memory 116 to supplement the head and tail data of the fourth data D4 ', that is, the first data temporarily stored in the buffer memory 116 is used. D1 ', the second data D2' and the third data D3 'are added in front of the third data D3' to form a complete data page size (ie, 16KB); at this time, the flash memory controller 110 The data in the flash memory module 120 is not read to supplement the head and tail data of the fourth data D4 '.

As described above, when the flash memory controller 110 determines that the data received by the autonomous device has continuous logical addresses, the flash memory controller 110 of this embodiment does not read the flash memory module In the case of 120, the data temporarily stored in the buffer memory 116 is directly used to supplement the head and tail data, so the efficiency of the flash memory controller 110 can be improved.

It should be noted that the main concept of the present invention is that when the flash memory controller 110 determines that the received data has continuous logical addresses, the method described in the embodiment of FIG. 2 will be used to In the case of accessing the flash memory module 120, the contents of the temporary buffer memory 116 are directly used to supplement the head-to-tail data of the data to be written. The above details about FIG. 2 are only for illustration, not for limitation of the present invention. Specifically, the data pages 210, 220, 230, and 240 shown in FIG. 2 can be located in the same block or different blocks. The written data can directly use the data stored in the buffer memory 116 without It is necessary to update the original data in the buffer memory 116, or some of the data pages in the data pages 210, 220, 230, 240 can be written to the flash memory module 120 together without necessarily writing in batches All of these design changes should belong to the scope of the present invention.

In addition, when the flash memory controller 110 determines that the write data from the master device and the previous write data have discontinuous logical addresses, the write method of the write data is similar to the write in Figure 2 Into the first data D1 ', that is, some data will be read from another specific data page first The operation of supplementing the head and tail data is performed and then written into the flash memory module 120.

To briefly summarize the present invention, in the method for accessing a flash memory module of the present invention, when the data written to the flash memory module is determined to be continuous, the data temporarily stored in the buffer memory can be used directly The operation of replenishing the head and tail data can greatly reduce the number of times the flash memory module needs to be read to fill in the head and tail data and improve the performance of the flash memory. The above are only the preferred embodiments of the present invention, and all changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims (10)

A method for accessing a flash memory module, wherein the flash memory module includes a plurality of blocks, each block includes a plurality of data pages, and the method includes: receiving a first A piece of data; read specific data from a specific data page in the flash memory module, and temporarily store the first data together with the specific data in a buffer memory; the first data together with the Write specific data to a first data page in the flash memory module; receive a second data from the host device; determine whether the second data and the first data have consecutive logical addresses To produce a judgment result; and if the judgment result indicates that the second piece of data and the first piece of data have consecutive logical addresses, the second piece of data is read without reading the flash memory module The data together with the first data temporarily stored in the buffer memory and a part of the specific data is written to a second data page in the flash memory module. The method as described in item 1 of the patent application scope, wherein the second data together with the first data temporarily stored in the buffer memory and the part of the specific data is written to the flash memory module The steps of the second data page in include: directly use the second data to update the specific data temporarily stored in the buffer memory, and store the first data temporarily stored in the buffer memory and use the The specific data after the second data update is written to the second data page in the flash memory module. The method as described in item 1 of the patent application scope also includes: if the judgment result indicates that the second piece of data and the first piece of data have a discontinuous logical address: from the flash memory module Reading another specific data from a specific data page, and temporarily storing the two data together with the other specific data in the buffer memory; and writing the second data together with the other specific data to the flash The second data page in the flash memory module. The method as described in item 1 of the patent application scope, wherein the step of determining whether the second piece of data and the first piece of data have consecutive logical addresses to generate the determination result includes: determining the second piece of data and the Whether the first piece of data has the same logical block and logical data page to generate the judgment result. The method as described in item 1 of the patent application scope, wherein the second data and the first data correspond to different write commands. A flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module includes multiple blocks, and each block contains multiple data Page, and the flash memory controller includes: a read-only memory for storing a program code; and a microprocessor for executing the code to control the storage of the flash memory module Fetch; wherein when the microprocessor receives a first data from a host device, the microprocessor reads specific data from a specific data page in the flash memory module and transfers the first data Temporarily stored in the buffer memory together with the specific data, and writing the first data together with the specific data to a first data page in the flash memory module; and when the microprocessor is from the host When the device receives a second piece of data, the microprocessor determines whether the second piece of data and the first piece of data have consecutive logical addresses to generate a judgment result, and if the judgment result indicates that the second piece of data and The first piece of data has a continuous logical address. Without reading the flash memory module, the microprocessor combines the second piece of data with the first piece of data temporarily stored in the buffer memory A part of the specific data is written to a second data page in the flash memory module. The flash memory controller as described in item 6 of the patent application scope, wherein the microprocessor directly uses the second data to update the specific data temporarily stored in the buffer memory and temporarily stores the buffer memory The first data of the body and the specific data updated using the second data are written to the second data page in the flash memory module. The flash memory controller as described in item 6 of the patent application scope, wherein if the judgment result indicates that the second data and the first data have discontinuous logical addresses, the microprocessor flashes from the flash memory Reading another specific data from another specific data page in the memory module, temporarily storing the two data together with the other specific data in the buffer memory, and combining the second data with the other specific data The data is written to the second data page in the flash memory module. The flash memory controller as described in item 6 of the patent application scope, wherein the microprocessor determines whether the second data and the first data have the same logical block and logical data page to generate the judgment result. An electronic device includes: a flash memory module; and a flash memory controller for accessing the flash memory module; wherein when the flash memory controller receives from a host device For a first data, the flash memory controller reads specific data from a specific data page in the flash memory module, and temporarily stores the first data together with the specific data in a buffer memory , And writing the first data together with the specific data to a first data page in the flash memory module; and when the flash memory controller receives a second data from the host device At this time, the flash memory controller determines whether the second data and the first data have consecutive logical addresses to generate a judgment result, and if the judgment result indicates that the second data and the first data The data has continuous logical addresses. Without reading the flash memory module, the flash memory controller combines the second data with the first data temporarily stored in the buffer memory and A part of the specific data is written to a second data page in the flash memory module.