CN112181859A - Effective data merging method, memory control circuit unit and memory device - Google Patents
Effective data merging method, memory control circuit unit and memory device Download PDFInfo
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- G—PHYSICS
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
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Abstract
The invention provides an effective data merging method, a memory control circuit unit and a memory storage device. The method comprises the following steps: obtaining a first system parameter corresponding to the first area and a second system parameter corresponding to the second area; judging whether the first system parameter is larger than the second system parameter; when the first system parameter is larger than the second system parameter, preferentially selecting a third entity erasing unit from the second area, and executing effective data merging operation by using the third entity erasing unit; and when the first system parameter is not larger than the second system parameter, preferentially selecting a fourth entity erasing unit from the first area, and executing effective data merging operation by using the fourth entity erasing unit.
Description
Technical Field
The invention relates to an effective data merging method, a memory control circuit unit and a memory storage device.
Background
Digital cameras, cell phones and MP3 have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since the rewritable non-volatile memory (rewritable non-volatile memory) has the characteristics of non-volatility, power saving, small volume, no mechanical structure, high read-write speed and the like, the rewritable non-volatile memory is most suitable for portable electronic products such as notebook computers. A solid state disk is a memory storage device using a flash memory as a storage medium. Therefore, the flash memory industry has become a very popular part of the electronics industry in recent years.
Generally, the physically erased cells of the rewritable nonvolatile memory module can be logically grouped into an SLC region and a TLC region. The number of erase units in the SLC region and the number of erase units in the TLC region are set before the rewritable nonvolatile memory module is shipped. The ratio of the erase units in the SLC region is different from that in the TLC region according to the user's usage habits or the operating logic of the application. Therefore, when the rewritable nonvolatile memory module reaches the end of the life cycle (e.g., the sum of the wear-level values of all the physically erased units is greater than a threshold), one of the SLC region and the TLC region may not reach the maximum write amount (e.g., the number of writes) that the region can endure.
However, it is one of the problems to be solved by those skilled in the art to achieve the maximum write amount that can be tolerated in both the SLC region and the TLC region when the rewritable nonvolatile memory module reaches the end of the life cycle.
Disclosure of Invention
The invention provides an effective data merging method, a memory control circuit unit and a memory storage device, which can simultaneously achieve the maximum write-in quantity which can be borne by an SLC region and a TLC region when a reproducible nonvolatile memory module reaches the end of a life cycle.
The invention provides an effective data merging method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, the entity erasing units are at least grouped into a first area and a second area, the first area comprises a plurality of first entity erasing units in the entity erasing units, and the second area comprises a plurality of second entity erasing units in the entity erasing units, the effective data merging method comprises the following steps: when a valid data merging operation is executed, obtaining a first system parameter corresponding to the first area and a second system parameter corresponding to the second area; judging whether the first system parameter is larger than the second system parameter; when the first system parameter is larger than the second system parameter, preferentially selecting a third entity erasing unit from the second entity erasing units in the second region, and using the third entity erasing unit to execute the effective data merging operation; and when the first system parameter is not greater than the second system parameter, preferentially selecting a fourth entity erasing unit from the first entity erasing units in the first area, and using the fourth entity erasing unit to execute the effective data merging operation.
In an embodiment of the present invention, each of the first plurality of physically erased cells is programmed only by using a single page programming mode, and each of the second plurality of physically erased cells is programmed only by using a multiple page programming mode.
In an embodiment of the present invention, the step of performing the valid data merge operation using the third physically erased cell includes: copying at least one valid datum from at least one fifth physically-erased cell, writing the valid datum to the third physically-erased cell using a multiple page programming mode, and performing an erase operation on the fifth physically-erased cell. The step of performing the valid data merge operation using the fourth physically erased cell includes: copying the valid data from the fifth physically erased cell, writing the valid data to the fourth physically erased cell using a single page programming mode, and performing the erase operation on the fifth physically erased cell.
In an embodiment of the present invention, the plurality of physical erase units are grouped into at least one storage area and an idle area, the third physical erase unit and the fourth physical erase unit belong to the idle area, and the fifth physical erase unit belongs to the storage area.
In an embodiment of the invention, the first system parameter and the second system parameter at least include at least one of a wear level value and a write amplification factor.
The invention provides a memory control circuit unit, which is used for controlling a rewritable nonvolatile memory module and comprises: host interface, memory interface and memory management circuit. The host interface is used for electrically connecting to a host system. The memory interface is electrically connected to the rewritable nonvolatile memory module, the rewritable nonvolatile memory module has a plurality of physical erasing units, the physical erasing units are at least grouped into a first area and a second area, the first area comprises a plurality of first physical erasing units in the physical erasing units, and the second area comprises a plurality of second physical erasing units in the physical erasing units. The memory management circuit is electrically connected to the host interface and the memory interface and is used for executing the following operations: when a valid data merging operation is executed, obtaining a first system parameter corresponding to the first area and a second system parameter corresponding to the second area; judging whether the first system parameter is larger than the second system parameter; when the first system parameter is larger than the second system parameter, preferentially selecting a third entity erasing unit from the second entity erasing units in the second region, and using the third entity erasing unit to execute the effective data merging operation; and when the first system parameter is not greater than the second system parameter, preferentially selecting a fourth entity erasing unit from the first entity erasing units in the first area, and using the fourth entity erasing unit to execute the effective data merging operation.
In an embodiment of the present invention, each of the first plurality of physically erased cells is programmed only by using a single page programming mode, and each of the second plurality of physically erased cells is programmed only by using a multiple page programming mode.
In an embodiment of the invention, in the operation of performing the valid data merge operation using the third physically erased cell, the memory management circuit is further configured to copy at least one valid data from at least one fifth physically erased cell, write the valid data to the third physically erased cell using a multiple page programming mode, and perform an erase operation on the fifth physically erased cell. In operation of performing the valid data merge operation using the fourth physically erased cell, the memory management circuit is further configured to copy the valid data from the fifth physically erased cell, write the valid data to the fourth physically erased cell using a single page programming mode, and perform the erase operation on the fifth physically erased cell.
In an embodiment of the present invention, the plurality of physical erase units are grouped into at least one storage area and an idle area, the third physical erase unit and the fourth physical erase unit belong to the idle area, and the fifth physical erase unit belongs to the storage area.
In an embodiment of the invention, the first system parameter and the second system parameter at least include at least one of a wear level value and a write amplification factor.
The invention provides a memory storage device, comprising: the interface unit, the rewritable nonvolatile memory module and the memory control circuit unit are connected. The rewritable nonvolatile memory module is provided with a plurality of entity erasing units, the entity erasing units are at least grouped into a first area and a second area, the first area comprises a plurality of first entity erasing units in the entity erasing units, and the second area comprises a plurality of second entity erasing units in the entity erasing units. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module and is used for executing the following operations: when a valid data merging operation is executed, obtaining a first system parameter corresponding to the first area and a second system parameter corresponding to the second area; judging whether the first system parameter is larger than the second system parameter; when the first system parameter is larger than the second system parameter, preferentially selecting a third entity erasing unit from the second entity erasing units in the second region, and using the third entity erasing unit to execute the effective data merging operation; and when the first system parameter is not greater than the second system parameter, preferentially selecting a fourth entity erasing unit from the first entity erasing units in the first area, and using the fourth entity erasing unit to execute the effective data merging operation.
In an embodiment of the present invention, each of the first plurality of physically erased cells is programmed only by using a single page programming mode, and each of the second plurality of physically erased cells is programmed only by using a multiple page programming mode.
In an embodiment of the invention, in the operation of performing the valid data merge operation using the third physically erased cell, the memory control circuit unit is further configured to copy at least one valid data from at least one fifth physically erased cell, write the valid data to the third physically erased cell using a multiple page programming mode, and perform an erase operation on the fifth physically erased cell. In the operation of performing the valid data merge operation using the fourth physically erased cell, the memory control circuit unit is further configured to copy the valid data from the fifth physically erased cell, write the valid data into the fourth physically erased cell using a single page programming mode, and perform the erase operation on the fifth physically erased cell.
In an embodiment of the present invention, the plurality of physical erase units are grouped into at least one storage area and an idle area, the third physical erase unit and the fourth physical erase unit belong to the idle area, and the fifth physical erase unit belongs to the storage area.
In an embodiment of the invention, the first system parameter and the second system parameter at least include at least one of a wear level value and a write amplification factor.
Based on the above, the valid data merge method, the memory control circuit unit and the memory storage device of the present invention can select the physical erase unit for writing in performing the valid data merge operation from one of the SLC region and the TLC region according to the system parameter corresponding to the SLC region and the system parameter corresponding to the TLC region, thereby enabling the ratio of the SLC region to the TLC region to be close in use. In this way, it can be avoided that when the rewritable nonvolatile memory module reaches the end of the life cycle, one of the SLC region and the TLC region may not reach the maximum write amount that the region can bear.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention.
FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.
FIG. 3 is a diagram illustrating a host system and a memory storage device according to another exemplary embodiment of the invention.
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.
FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.
FIG. 6 is a diagram illustrating a management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention.
Fig. 7 is a flowchart illustrating a valid data merging method according to an exemplary embodiment of the present invention.
Description of the reference numerals
10. 30: memory storage device
11. 31: host system
110: system bus
111: processor with a memory having a plurality of memory cells
112: random access memory
113: read-only memory
114: data transmission interface
12: input/output (I/O) device
20: main machine board
201: portable disk
202: memory card
203: solid state disk
204: wireless memory storage device
205: global positioning system module
206: network interface card
207: wireless transmission device
208: keyboard with a keyboard body
209: screen
210: horn type loudspeaker
32: SD card
33: CF card
34: embedded memory device
341: embedded multimedia card
342: embedded multi-chip packaging storage device
402: connection interface unit
404: memory control circuit unit
406: rewritable nonvolatile memory module
502: memory management circuit
504: host interface
506: memory interface
508: error checking and correcting circuit
510: buffer memory
512: power management circuit
601: SLC region
602: MLC region
610(0) to 610 (B): physical erase unit
612(0) -612 (C): logic unit
S700: step of executing effective data merging operation
S701: the step of obtaining a first system parameter corresponding to a first area and a second system parameter corresponding to a second area
S703: judging whether the first system parameter is larger than the second system parameter
S705: preferentially selecting third physically erased cells from the second physically erased cells in the second region
S707: copying effective data from the fifth physically erased cell, writing the effective data to the third physically erased cell using a multiple page programming mode, and performing an erase operation on the fifth physically erased cell
S709: preferentially selecting a fourth physically erased cell from the first physically erased cells in the first region
S711: copying effective data from the fifth physically erased cell, writing the effective data to the fourth physically erased cell using a single page programming mode, and performing an erase operation on the fifth physically erased cell
Detailed Description
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module and a controller (also referred to as a control circuit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.
Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all electrically connected to the system bus (system bus) 110.
In the present exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may write data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is electrically connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.
In the present exemplary embodiment, the processor 111, the random access memory 112, the read only memory 113 and the data transmission interface 114 are disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 can be electrically connected to the memory storage device 10 through the data transmission interface 114 in a wired or wireless manner. The data is electrically connected or wirelessly transmitted to the memory storage device 10, wherein the memory storage device 10 may be, for example, a personal disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be various types of memory storage devices based on various wireless Communication technologies, such as Near Field Communication (NFC) memory storage device, wireless facsimile (WiFi) memory storage device, Bluetooth (Bluetooth) memory storage device, or low power Bluetooth memory storage device (e.g., iBeacon). In addition, the motherboard 20 may also be electrically connected to various types of I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, and the like through the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.
In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as an SD card 32, a CF card 33, or an embedded storage device 34. The embedded memory device 34 includes embedded Multi-media cards (eMMC) 341 and/or embedded Multi-Chip Package memory devices (eMCP) 342, and various types of embedded memory devices electrically connecting the memory module to the substrate of the host system.
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.
Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.
In the exemplary embodiment, connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI Express) standard, the Universal Serial Bus (USB) standard, the Secure Digital (SD) interface standard, the Ultra High Speed (UHS-I) interface standard, the Ultra High Speed (UHS-II) interface standard, the Memory Stick (Memory Stick, MS) interface standard, the Multi-Chip Package (Multi-Package) interface standard, the Multimedia Memory Card (Multi, Embedded) interface standard, the Multimedia Card (MMC) interface standard, eMMC) interface standard, Universal Flash Storage (UFS) interface standard, embedded Multi-Chip Package (eMCP) interface standard, Compact Flash (CF) interface standard, Integrated Device Electronics (IDE) standard, or other suitable standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 may be disposed outside a chip including the memory control circuit unit 404.
The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type, and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.
The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one memory Cell), a multiple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.
The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 has physical erase units 410(0) -410 (B). For example, the physical erase units 410(0) -410 (B) may belong to the same memory die or to different memory dies. Each entity erasing unit is respectively provided with a plurality of entity programming units, wherein the entity programming units belonging to the same entity erasing unit can be independently written and simultaneously erased. However, it should be understood that the invention is not limited thereto, and each of the plurality of physically erased cells may be composed of 64 physically programmed cells, 256 physically programmed cells, or any other number of physically programmed cells.
FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.
Referring to fig. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, and a memory interface 506.
The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 502 is explained below, it is equivalent to the operation of the memory control circuit unit 404.
In the exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.
In another example embodiment, the control instructions of the memory management circuit 502 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.
In another exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used for managing the memory cells or groups thereof of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may respectively include one or more program codes or command codes and instruct the rewritable nonvolatile memory module 406 to perform corresponding operations of writing, reading, and erasing. In an example embodiment, the memory management circuit 502 may issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.
The host interface 504 is electrically connected to the memory management circuit 502 and is used for receiving and recognizing commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the exemplary embodiment, host interface 504 is compatible with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.
The memory interface 506 is electrically connected to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 wants to access the rewritable nonvolatile memory module 406, the memory interface 506 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence for indicating write data, a read instruction sequence for indicating read data, an erase instruction sequence for indicating erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection procedures, etc.). The instruction sequences are generated by the memory management circuit 502 and transmitted to the rewritable nonvolatile memory module 406 through the memory interface 506, for example. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.
In an exemplary embodiment, the memory control circuitry 404 further includes error checking and correction circuitry 508, buffer memory 510, and power management circuitry 512.
The error checking and correcting circuit 508 is electrically connected to the memory management circuit 502 and is used for performing error checking and correcting processes to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 508 performs an error checking and correcting process on the read data according to the error correction code and/or the error check code.
The buffer memory 510 is electrically connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 512 is electrically connected to the memory management circuit 502 and is used for controlling the power of the memory storage device 10.
In the exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 406 form a plurality of physical programming cells, and the physical programming cells form a plurality of physical erasing cells. For example, memory cells on the same word line constitute one or more physically programmed cells. If each memory cell can store more than 2 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a memory cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a memory cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.
In the present exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, the physical programming unit is a physical page (page) or a physical fan (sector). If the physical program cells are physical pages, the physical program cells usually include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundant bit region stores system data (e.g., error correction codes).
In the present exemplary embodiment, the data bit area includes 32 physical fans, and the size of one physical fan is 512 bytes (B). However, in other example embodiments, the data bit region may also include 8, 16, or a greater or lesser number of physical fans, and the size of each physical fan may also be greater or lesser. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains the minimum number of memory cells that are erased together. For example, the physical erase unit is a physical block (block).
FIG. 6 is a diagram illustrating a management of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention. It should be understood that, when describing the operation of the physically erased cells of the rewritable non-volatile memory module 406, it is a logical concept to operate the physically erased cells by the words "select" and "group". That is, the physical locations of the physically erased cells of the rewritable nonvolatile memory module 406 are not changed, but the physically erased cells of the rewritable nonvolatile memory module 406 are logically operated.
Referring to FIG. 6, in the exemplary embodiment, the memory management circuit 502 logically groups the physically erased cells 610(0) -610 (B) of the rewritable nonvolatile memory module 406 into a storage area and an idle (spare) area. The physical erase units in the storage area store data, while the physical erase units in the idle area are not used to store data. For example, each physical erase unit belonging to the storage area may store valid data and/or invalid data, and a physical erase unit belonging to the storage area is erased and then associated with the idle area. When a physical erase unit belonging to the block is full, a physical erase unit is selected from the free block and associated with the block to store other data.
In addition, in the exemplary embodiment, the memory management circuit 502 further groups the physical erase units 610(0) -610 (B) of the rewritable nonvolatile memory module 406 into an SLC region 601 (also referred to as the first region) and a TLC region 602 (also referred to as the second region), and configures the logic units 612(0) - (612 (C) to map some of the physical erase units 610(0) -610 (a) of the SLC region 601 and some of the physical erase units 610(a +1) -610 (B) of the TLC region 602. For example, in the exemplary embodiment, the host system 11 accesses the data in the SLC area 601 and the TLC area 602 through a Logical Address (LA), and therefore, each of the logical units 612(0) -612 (C) refers to a logical address. In addition, each of the logic units 612(0) - (612 (C) may also refer to a logic program unit, a logic erase unit, or be composed of a plurality of continuous or discontinuous logic addresses. Also, each of the logic units 612(0) -612 (C) may be mapped to one or more physical erase units. It is noted that in the exemplary embodiment of the invention, the physical erase units 610(0) -610 (B) of the rewritable nonvolatile memory module 406 are logically grouped into the SLC region 601 and the TLC region 602 by the memory management circuit 502, but the invention is not limited thereto. For example, in another exemplary embodiment, the memory management circuit 502 can also logically group the physical erase units 610(0) -610 (B) of the rewritable nonvolatile memory module 406 into an SLC region and an MLC region.
The memory management circuit 502 records the mapping relationship between the logical unit and the physical erase unit (also referred to as a logical-to-physical mapping relationship) in at least one logical-to-physical mapping table. When the host system 11 is going to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 502 can perform data access to the memory storage device 10 according to the logical-to-physical mapping table.
In particular, in the exemplary embodiment, the memory management circuit 502 also configures the physical erase cells 610(0) -610 (A) (also referred to as the first physical erase cells) belonging to the SLC region 601 to be initially programmed based on a single page programming mode and configures the physical erase cells 610(A +1) -610 (B) (also referred to as the second physical erase cells) belonging to the TLC region 602 to be initially programmed based on a multi-page programming mode. Generally, the programming speed for programming the memory cell based on the single page programming mode is higher than the programming speed for programming the memory cell based on the multi-page programming mode. In addition, the reliability of data stored based on the single page program mode is also often higher than that of data stored based on the multi-page program mode. In the present embodiment, the physical erase cells 610(0) - (610A) belonging to the SLC region 601 are programmed only in the single page programming mode, and the physical erase cells 610(A +1) - (610B) belonging to the TLC region 602 are programmed only in the multi-page programming mode.
In the present exemplary embodiment, the single page program mode refers to one of a single layer memory cell (SLC) mode, a lower physical programming (lower physical programming) mode, a mixed programming (mix programming) mode, and a less layer memory cell (less layer memory cell) mode. In the single-layer memory cell mode, one memory cell stores only one bit of data. In the lower physical programming mode, only the lower physical programming unit is programmed, and the upper physical programming unit corresponding to the lower physical programming unit is not programmed. In the hybrid programming mode, valid data (or real data) is programmed in the lower physical program unit, and dummy data (dummy data) is programmed in the upper physical program unit corresponding to the lower physical program unit storing the valid data. In the few-layer memory cell mode, one memory cell stores a first number of bits of data. For example, this first number may be set to "1".
In the present exemplary embodiment, the multi-page program mode refers to a multi-level cell (MLC) program mode, a multiple level (TLC) cell program mode, or the like. In the multi-page programming mode, a memory cell stores a second number of bits of data, wherein the second number is equal to or greater than "2". For example, this second number may be set to 2 or 3. In another exemplary embodiment, the first number in the single-page programming mode and the second number in the multi-page programming mode may be other numbers as long as the second number is greater than the first number.
Generally, the number of physically erased cells in the SLC region 601 and the number of physically erased cells in the TLC region 602 are set before the rewritable nonvolatile memory module 406 is shipped from the factory. The ratio of the physical erase units in the SLC region 601 is different from that in the TLC region 602 according to the user's usage habits or the operating logic of the application. Therefore, when the rewritable nonvolatile memory module 406 reaches the end of the life cycle (e.g., the sum of the wear level values of all the physically erased cells is greater than a threshold), one of the SLC 601 and TLC 602 regions may not reach the maximum write amount (e.g., the number of writes) that the region can withstand. However, it is one of the problems to be solved by those skilled in the art how to achieve the maximum write amount that can be tolerated by both the SLC area 601 and the TLC area 602 at the same time when the rewritable nonvolatile memory module 406 reaches the end of the life cycle.
Therefore, the present invention provides an efficient data merging method, which can select the physical erase unit (also referred to as the target physical erase unit) for writing in performing the efficient data merging operation from one of the SLC region 601 and the TLC region 602 according to the system parameters corresponding to the SLC region 601 and the system parameters corresponding to the TLC region 602, thereby enabling the ratio of the SLC region 601 and the TLC region 602 to be similar in use. In this way, it can be avoided that when the rewritable nonvolatile memory module 406 reaches the end of the life cycle, one of the SLC area 601 and the TLC area 602 may not reach the maximum write amount that the area can endure.
In more detail, fig. 7 is a flowchart illustrating an effective data merging method according to an exemplary embodiment of the present invention.
Referring to fig. 7, when the number of idle physical erase units in the idle area of the rewritable nonvolatile memory module 406 is not greater than a predetermined value, in step S700, the memory management circuit 502 performs a valid data merge operation. Specifically, when the number of the idle physical erase units in the idle area is not greater than the predefined value, it represents that the physical erase units available for writing in the idle area are not enough, and the memory management circuit 502 also performs the valid data merge operation to release more space to the idle area.
When a valid data merge operation is to be performed, in step S701, the memory management circuit 502 obtains a system parameter (also referred to as a first system parameter) corresponding to the SLC region 601 and a system parameter (also referred to as a second system parameter) corresponding to the TLC region 602. In this embodiment, the first system parameter and the second system parameter are of the same type and at least include at least one of a wear level value and a write amplification factor. The wear level value is related to at least one of the erase count, program count, read count, error bit count and error bit rate of the physically erased cell. In other words, taking the first system parameter as an example, the first system parameter can be the sum of erase times, program times, read times, error bits or error bits of all the physically erased cells in the SLC region 601. The write amplification factor is well known to those skilled in the art and will not be described herein.
After obtaining the first system parameter and the second system parameter, in step S703, the memory management circuit 502 determines whether the first system parameter is greater than the second system parameter.
When the first system parameter is greater than the second system parameter, it represents that the usage of the SLC region 601 is higher than the usage of the TLC region 602. Therefore, in step S705, the memory management circuit 502 preferentially selects a physical erase unit (also referred to as a third physical erase unit) in the idle region from the second physical erase units 610(a +1) -610 (B) of the TLC region 602 as a target physical erase unit for writing in the valid data merge operation. Thereafter, in step S707, the memory management circuit 502 copies valid data from at least one physically erased cell (also referred to as a fifth physically erased cell) of the storage area, and writes the valid data to the selected third physically erased cell using the multi-page programming mode. Thereafter, the memory management circuit 502 can perform an erase operation on the fifth erased cell and re-associate the fifth erased cell with the idle region.
When the first system parameter is not greater than the second system parameter, it represents that the usage rate of the SLC region 601 is lower than that of the TLC region 602. Therefore, in step S709, the memory management circuit 502 preferentially selects a physical erase unit (also referred to as a fourth physical erase unit) belonging to the idle region from the physical erase units 610(0) -610 (a) of the SLC area 601 as a target physical erase unit for writing in the valid data merge operation. Thereafter, in step S711, the memory management circuit 502 copies valid data from at least one physically erased cell (also referred to as a fifth physically erased cell) of the storage area, and writes the valid data to the selected fourth physically erased cell by using the single page programming mode. Thereafter, the memory management circuit 502 can perform an erase operation on the fifth erased cell and re-associate the fifth erased cell with the idle region.
It should be noted that in the aforementioned step S705, in some cases, the memory management circuit 502 may not be able to select the physical erase unit belonging to the idle zone from the physical erase units 610(a +1) -610 (B) of the TLC region 602 (e.g., when there is no physical erase unit belonging to the idle zone in the physical erase units 610(a +1) -610 (B) of the TLC region 602). In this case, when the memory management circuit 502 cannot select the physical erase unit belonging to the idle region from the physical erase units 610(A +1) -610 (B) of the TLC region 602 in step S705, the memory management circuit 502 can, for example, search and select the physical erase units belonging to the idle region from the physical erase units 610(0) -610 (A) of the SLC region 601 to perform the effective data merge operation. Similarly, in step 709, the memory management circuit 502 may not select the physical erase units belonging to the idle region from the physical erase units 610(0) 610(A) of the SLC area 601 in some cases (e.g., the physical erase units 610(0) 610(A) of the SLC area 601 do not have the physical erase units belonging to the idle region). In this case, when the memory management circuit 502 cannot select the physical erase units belonging to the idle region from the physical erase units 610(A +1) -610 (B) of the SLC region 601 in step S709, the memory management circuit 502 can perform the operation of searching and selecting the physical erase units belonging to the idle region from the physical erase units 610(A +1) -610 (B) of the TLC region 602 to perform the effective data merging operation.
In summary, the valid data merge method, the memory control circuit unit and the memory storage device of the present invention can select the physical erase unit for writing in performing the valid data merge operation from one of the SLC region and the TLC region according to the system parameter corresponding to the SLC region and the system parameter corresponding to the TLC region, thereby enabling the ratio of the SLC region to the TLC region to be close in use. In this way, it can be avoided that when the rewritable nonvolatile memory module reaches the end of the life cycle, one of the SLC region and the TLC region may not reach the maximum write amount that the region can bear.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (15)
1. A valid data merging method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of physical erase units, the plurality of physical erase units are grouped into at least a first region and a second region, the first region includes a plurality of first physical erase units of the plurality of physical erase units and the second region includes a plurality of second physical erase units of the plurality of physical erase units, the valid data merging method comprises:
when the effective data merging operation is executed, obtaining a first system parameter corresponding to the first area and a second system parameter corresponding to the second area;
judging whether the first system parameter is larger than the second system parameter;
when the first system parameter is larger than the second system parameter, preferentially selecting a third entity erasing unit from the second entity erasing units in the second region, and using the third entity erasing unit to execute the effective data merging operation; and
when the first system parameter is not greater than the second system parameter, preferentially selecting a fourth entity-erased unit from the first entity-erased units in the first region, and performing the valid data merging operation by using the fourth entity-erased unit.
2. The effective data consolidation method of claim 1, wherein each of the plurality of first physically-erased cells is programmed using only a single-page programming mode, and each of the plurality of second physically-erased cells is programmed using only a multi-page programming mode.
3. The valid data merge method of claim 1, wherein the step of performing the valid data merge operation using the third physically erased cell comprises:
copying at least one valid datum from at least one fifth physically-erased cell, writing the valid datum to the third physically-erased cell using a multi-page programming mode, and performing an erase operation on the fifth physically-erased cell,
wherein performing the valid data merge operation using the fourth physically erasable unit comprises:
copying the valid data from the fifth physically erased cell, writing the valid data to the fourth physically erased cell using a single page programming mode, and performing the erase operation on the fifth physically erased cell.
4. The valid data merging method of claim 3, wherein the plurality of physically erased units are grouped into at least a storage area and an idle area, the third physically erased unit and the fourth physically erased unit belong to the idle area, and the fifth physically erased unit belongs to the storage area.
5. The valid data merging method of claim 1, wherein the first system parameter and the second system parameter include at least one of a wear level value and a write amplification factor.
6. A memory control circuit unit for controlling a rewritable nonvolatile memory module, the memory control circuit unit comprising:
a host interface for electrically connecting to a host system;
a memory interface electrically connected to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of physical erasing units, the plurality of physical erasing units are at least grouped into a first area and a second area, the first area comprises a plurality of first physical erasing units in the plurality of physical erasing units, and the second area comprises a plurality of second physical erasing units in the plurality of physical erasing units; and
a memory management circuit electrically connected to the host interface and the memory interface,
wherein the memory management circuitry is to obtain a first system parameter corresponding to the first region and a second system parameter corresponding to the second region when performing a valid data merge operation,
wherein the memory management circuitry is further to determine whether the first system parameter is greater than the second system parameter,
when the first system parameter is greater than the second system parameter, the memory management circuit is further configured to preferentially select a third physically-erased cell from the second physically-erased cells in the second region and perform the valid data merge operation using the third physically-erased cell, an
When the first system parameter is not greater than the second system parameter, the memory management circuit is further configured to preferentially select a fourth physically-erased cell from the first physically-erased cells in the first region, and perform the valid data merge operation using the fourth physically-erased cell.
7. The memory control circuit unit of claim 6, wherein each of the plurality of first physically-erased cells is programmed using only a single-page programming mode, and each of the plurality of second physically-erased cells is programmed using only a multi-page programming mode.
8. The memory control circuit unit of claim 6, wherein in operation of performing the valid data merge operation using the third physically erased cell,
the memory management circuit is further configured to copy at least one valid datum from at least one fifth physically erased cell, write the valid datum to the third physically erased cell using a multiple page programming mode, and perform an erase operation on the fifth physically erased cell,
wherein in operation of performing the valid data merge operation using the fourth physically erased cell,
the memory management circuit is further configured to copy the valid data from the fifth physically erased cell, write the valid data to the fourth physically erased cell using a single page programming mode, and perform the erase operation on the fifth physically erased cell.
9. The memory control circuit unit of claim 8, wherein the plurality of physically erased cells are grouped into at least a storage area and an idle area, the third physically erased cell and the fourth physically erased cell belong to the idle area, and the fifth physically erased cell belongs to the storage area.
10. The memory control circuitry unit of claim 6, wherein the first system parameter and the second system parameter comprise at least one of a wear level value and a write amplification factor.
11. A memory storage device, comprising:
the connection interface unit is used for electrically connecting to a host system;
the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, wherein the entity erasing units are at least grouped into a first area and a second area, the first area comprises a plurality of first entity erasing units in the entity erasing units, and the second area comprises a plurality of second entity erasing units in the entity erasing units; and
a memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module,
wherein the memory control circuit unit is to obtain a first system parameter corresponding to the first region and a second system parameter corresponding to the second region when performing a valid data merge operation,
wherein the memory control circuit unit is further configured to determine whether the first system parameter is greater than the second system parameter,
when the first system parameter is greater than the second system parameter, the memory control circuit unit is further configured to preferentially select a third physically-erased cell from the second physically-erased cells in the second region, and perform the valid data merge operation using the third physically-erased cell,
when the first system parameter is not greater than the second system parameter, the memory control circuit unit is further configured to preferentially select a fourth physically-erased cell from the first physically-erased cells in the first region, and perform the valid data merge operation using the fourth physically-erased cell.
12. The memory storage device of claim 11, wherein each of the plurality of first physically erased cells is programmed using only a single page programming mode, and each of the plurality of second physically erased cells is programmed using only a multiple page programming mode.
13. The memory storage device of claim 11, wherein in operation of performing the valid data merge operation using the third physically erased cell,
the memory control circuit unit is further configured to copy at least one valid datum from at least one fifth physically-erased cell, write the valid datum to the third physically-erased cell using a multi-page programming mode, and perform an erase operation on the fifth physically-erased cell,
wherein in operation of performing the valid data merge operation using the fourth physically erased cell,
the memory control circuit unit is further configured to copy the valid data from the fifth physically erased cell, write the valid data to the fourth physically erased cell using a single page programming mode, and perform the erase operation on the fifth physically erased cell.
14. The memory storage device of claim 13, wherein the plurality of physically erased cells are grouped into at least a storage area and an idle area, the third physically erased cell and the fourth physically erased cell belong to the idle area, and the fifth physically erased cell belongs to the storage area.
15. The memory storage device of claim 11, wherein the first system parameter and the second system parameter comprise at least one of a wear level value and a write amplification factor.
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