TWI657339B - Method for managing flash memory module and associated flash memory controller - Google Patents

Abstract

The invention discloses a method for managing a flash memory module, wherein the flash memory module comprises a plurality of flash memory chips, each of the flash memory chips comprises a plurality of first temporary storage blocks and a plurality of second temporary storage blocks, each of the first temporary storage block and the second temporary storage block includes a plurality of data pages, and the method includes: writing a data to the plurality of second temporary storage blocks a second temporary storage block in the block; when the access of the flash memory module meets a specific condition, the data stored in the second temporary storage block is moved to the plurality of A first temporary storage block in the temporary storage block, and the information of the first blank data page of the second temporary storage block is recorded in the first temporary storage block.

Description

Method for managing flash memory module and related flash memory controller

The present invention relates to flash memory, and more particularly to a method of managing a flash memory module and related flash memory controller.

In a three-dimensional NAND-type flash architecture, when the flash memory controller needs to write data to the multi-layer memory (Multiple-Level Cell) in the flash memory module, When the MLC) block or the Triple-Level Cell (TLC) block, the amount of data written at one time must be large, such as 64 kilobytes (KB) or 128 KB. However, if it is fast When the flash memory controller needs to write data with a small amount of data (for example, 4KB) of random data, the flash memory controller needs to add 60KB or 124KB of dummy data to 4KB of random data. In the data, the amount of data that is written once is 64 KB or 128 KB. In this case, if there is a large amount of random data with a small amount of data, most of the contents of each block will be invalid data, so the space of the flash memory module will be quickly insufficient. In turn, frequent garbage collection operations are required, which affects system performance.

In order to avoid the above situation, a temporary storage block may be additionally set in the flash memory module, which is used to collect random data with a small amount of data, and wait until a sufficient amount of data is collected. Then write back from the temporary storage block to the above-mentioned multi-layer storage block or three-layer storage block. However, if there is a power off recovery (POR) or a sudden power off recovery (SPOR) condition during the data write process, the temporary storage area cannot be determined. The block and the multi-layer storage block or the new and old data in the three-tier storage block, thereby causing problems in the subsequent re-establishment of the address mapping table.

Therefore, one of the objects of the present invention is to provide a method for managing a flash memory module, which can correctly determine a temporary storage block when a power failure occurs after a power failure or a power failure recovery condition occurs. And the old and new data in the multi-layer storage block or the three-tier storage block to smoothly re-establish the address mapping table to solve the problems in the prior art.

In one embodiment of the present invention, a method for managing a flash memory module is disclosed, wherein the flash memory module includes a plurality of flash memory chips, each of which includes a plurality of flash memory chips. a first temporary storage block and a plurality of second temporary storage blocks, each of the first temporary storage block and the second temporary storage block comprising a plurality of data pages, and the method comprises: placing a first data Writing to a second temporary storage block of the plurality of second temporary storage blocks; when the access of the flash memory module meets a specific condition, storing the second temporary storage block The first data in the first data is moved to a first temporary storage block of the plurality of first temporary storage blocks, and the first one of the second temporary storage blocks is currently recorded in the first temporary storage block Blank information page information.

In another embodiment of the present invention, a method of managing a flash memory module is disclosed, wherein the flash memory module includes a plurality of flash memory chips, each of which includes a flash memory chip. a plurality of first temporary storage blocks and a plurality of second temporary storage blocks, each of the first temporary storage blocks and the first The second temporary storage block includes a plurality of data pages, and the method includes: when replying to the situation after the power failure, reading the content of the spare area of a data page in the first temporary storage block, and determining a a data page number; determining that all data pages in the second temporary storage block that are located before the data page number are invalid data pages; and determining that the second temporary storage block includes the data page number and all subsequent data pages are Valid profile page.

In another embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, and the flash memory module includes a plurality of flash memory chips, each of the flash memory chips includes a plurality of first temporary storage blocks and a plurality of second temporary storage blocks, each of the first temporary storage blocks and the second temporary storage block includes a plurality of data pages, and the flash memory controller includes a read-only memory and a microprocessor, wherein the read-only memory is used to store a code, and the microprocessor is configured to execute the code Controlling access to the flash memory module; wherein the microprocessor writes a first data into a second temporary storage block of the plurality of second temporary storage blocks; and when the fast When the access of the flash memory module meets a specific condition, the microprocessor moves the first data stored in the second temporary storage block to a first one of the plurality of first temporary storage blocks Temporarily storing the block, and recording the first empty space of the second temporary storage block in the first temporary storage block Information profile page.

In another embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, and the flash memory module includes a plurality of flash memory chips, each of the flash memory chips includes a plurality of first temporary storage blocks and a plurality of second temporary storage blocks, each of the first temporary storage blocks and the second temporary storage block includes a plurality of data pages, and the flash memory controller includes a read-only memory and a microprocessor, wherein the read-only memory is used to store a code, and the microprocessor is configured to execute the code Controlling the flash memory module Accessing; wherein when a power failure occurs after a power failure, the microprocessor reads the content of the spare area of a data page in the first temporary storage block, and determines a data page serial number; and the microprocessor Determining that all the data pages in the second temporary storage block that are located before the serial number of the data page are invalid data pages, and determining that the second temporary storage block includes the data page serial number and all subsequent data pages as valid data pages.

100‧‧‧ memory device

110‧‧‧Flash Memory Controller

112‧‧‧Microprocessor

112C‧‧‧ Code

112M‧‧‧Reading memory

114‧‧‧Control logic

116‧‧‧Buffered memory

118‧‧‧Interface logic

120‧‧‧Flash Memory Module

130‧‧‧Main device

132‧‧‧Encoder

134‧‧‧Decoder

200~208, 500~506‧‧‧ steps

310, 320‧‧‧ flash memory chip

352, 534, 536‧‧‧ Super Blocks

DB_0~DB_M‧‧‧data block

TB_MLC_0~TB_MLC_K‧‧‧First temporary storage block

TB_SIC0~TB_SLC_N‧‧‧Second temporary storage block

P0~P34‧‧‧Information Page

LBA_001, LBA_XXX‧‧‧ logical address

1 is a schematic diagram of a memory device in accordance with an embodiment of the present invention.

2 is a flow chart of managing a flash memory module in accordance with an embodiment of the present invention.

Figure 3A is a schematic diagram of managing a flash memory module.

Figure 3B is a schematic illustration of a superblock in accordance with an embodiment of the present invention.

FIG. 4 is a schematic diagram of writing data to a temporary storage block and a data block according to an embodiment of the invention.

FIG. 5 is a flow chart of managing a flash memory module according to another embodiment of the present invention.

FIG. 6 is a schematic diagram of an address mapping table for re-establishing a temporary storage block and a data block according to an embodiment of the present invention.

Referring to FIG. 1, FIG. 1 is a schematic diagram of a memory device 100 in accordance with an embodiment of the present invention. The memory device 100 includes a flash memory module 120 and a flash memory controller 110, and the flash memory controller 110 is used to access the flash memory module 120. According to the embodiment, the flash memory controller 110 includes a microprocessor 112, a read only memory (ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic 118. The read-only memory 112M is used to store a code 112C, and the microprocessor 112 is used to execute the code 112C to control the flash. Access to the memory module 120. The control logic 114 includes an encoder 132 and a decoder 134, wherein the encoder 132 is configured to encode the data written into the flash memory module 120 to generate a corresponding check code (or, error correction) The code (Error Correction Code), ECC), and the decoder 134 is used to decode the data read from the flash memory module 120.

In a typical situation, the flash memory module 120 includes a plurality of flash memory chips, and each of the flash memory chips includes a plurality of blocks (eg, through a microprocessor). The flash memory controller 110 of the execution code 112C executes the erase data operation on the flash memory module 120 in units of blocks. In addition, a block can record a specific number of pages, wherein the controller (eg, the memory controller 110 executing the code 112C through the microprocessor 112) writes to the flash memory module 120. The operation of the data is written in units of data pages. In this embodiment, the flash memory module 120 is a stereo NAND-type flash (3D NAND-type flash).

In practice, the flash memory controller 110 executing the code 112C through the microprocessor 112 can perform various control operations by using its own internal components, for example, using the control logic 114 to control the flash memory module 120. Access operations (especially for at least one block or at least one data page), buffer memory 116 for buffering, and interface logic 118 for communication with a host device 130 .

In an embodiment, the memory device 100 can be a portable memory device (for example, a memory card conforming to the SD/MMC, CF, MS, and XD standards), and the main device 130 is an electronic device connectable to the memory device. For example, mobile phones, notebook computers, desktop computers, etc. In another embodiment, the memory device 100 can be disposed in an electronic device, such as a mobile phone, a notebook computer, or a desktop device. In the computer, the main device 130 can be a processor of the electronic device.

Referring to FIG. 2, a flow diagram of managing a flash memory module 120 in accordance with an embodiment of the present invention. In step 200, the process begins. In step 202, the flash memory controller 110 receives a write command from the host device 130 to write a file into a block of the flash memory module 120. In this embodiment, referring to FIG. 3A, the flash memory module 120 includes a plurality of flash memory chips 310 and 320. Each of the flash memory chips includes a plurality of data blocks DB_0~DB_M. The second temporary storage block TB_SLC_0~TB_SLC_N and the plurality of first temporary storage blocks TB_MLC_0~TB_MLC_K, and each of the blocks includes a plurality of data pages. In this embodiment, the second temporary storage block TB_SLC_0~TB_SLC_N is a single-level cell (SLC) block, and the data block DB_0~DB_M and the first temporary storage block TB_MLC_0~TB_MLC_K are multiple layers. The storage (MLC) block, but not limited thereto, in other embodiments, the data block DB0~DB_M and/or the first temporary storage block TB_MLC_0~TB_MLC_K may be a three-tier storage (TLC) block. In an embodiment, the second temporary storage block TB_SLC_0~TB_SLC_N may also be used as a single-layer storage block using a multi-layer storage block. In the actual operation of the flash memory module 120, a "super block" may be used as a mode of data writing. Specifically, referring to FIG. 3B, which is a schematic diagram of a super block according to an embodiment of the present invention. . As shown in FIG. 3B, it is assumed that the blocks in each of the flash memory chips 310, 320 are divided into two planes, and the flash memory module 120 includes only two flash memory chips 310. 320, so four blocks located in different planes of the flash memory chips 310, 320 can form a super block. In FIG. 3B, the data blocks DB_0, DB_1 in the flash memory chips 310, 320 constitute a super block 352, and the second temporary storage blocks TB_SLC_0 and TB_SLC_1 in the flash memory chips 310, 320 constitute a The super block 354, and the first temporary storage blocks TB_MLC_0, TB_MLC_1 of the flash memory chips 310, 320 constitute a super block 356... and so on. When data needs to be written to the flash memory module 120, each time it needs to be written to each data page in the super block, that is, four In a data page of a block, for example, assuming that the size of one data page in a block is 16 KB, the flash memory controller 110 needs to write 64 KB of data to one of the super blocks 356 at a time. The data page also sequentially writes the 64 KB data to a data page of the first temporary storage block TB_MLC_0 in the flash memory chip 310, and a data of the first temporary storage block TB_MLC_1 in the flash memory chip 310. A page of the first temporary storage block TB_MLC_0 in the page, the flash memory chip 320, and a data page of the first temporary storage block TB_MLC_1 in the flash memory chip 320. In other embodiments, the flash memory controller 110 needs to write 128 KB of data to two data pages of a super block 356 at a time, that is, the 128 KB of data is written into the flash memory chip 310. Two data pages of the temporary block TB_MLC_0, two data pages of the first temporary storage block TB_MLC_1 in the flash memory chip 310, and two data pages of the first temporary storage block TB_MLC_0 in the flash memory chip 320 And two data pages of the first temporary storage block TB_MLC_1 in the flash memory chip 320.

In this embodiment, when data needs to be written to the flash memory module 120, the flash memory controller 110 selects one of the first temporary storage blocks TB_MLC_0~TB_MLC_K for storage, and flashes due to flashing. The amount of data written by the memory controller 110 for the first temporary storage block TB_MLC_0~TB_MLC_K needs to be greater than a critical value (for example, 64 KB described above). Therefore, in step 204, the flash memory controller 110 judges fast. Whether the access of the flash memory module 120 meets a specific condition, if not, the flow proceeds to step 206; if so, the flow proceeds to step 208. Specifically, the specific condition refers to the sum of the data corresponding to the write command described in step 202 and the data currently stored in the second temporary storage block and not yet moved to the first temporary storage block. Whether to reach the threshold.

In step 206, the flash memory controller 110 writes the data corresponding to the write command described in step 202 into the second temporary storage block. In step 208, the flash memory controller 110 stores the data corresponding to the write command described in step 202, together with the data currently stored in the second temporary storage block. The data that has not been moved to the first temporary storage block is also written into the first temporary storage block, and the first temporary storage block is recorded in the first temporary storage block. Information on a blank data page. Then, the flow returns to step 202.

The flow chart shown in FIG. 2 will be described in detail below by taking an example of FIG. 4. It should be noted that, for convenience of understanding, FIG. 4 is a second temporary storage block TB_SLC_0 and a first temporary storage block TB_MLC_0. As an illustration, those skilled in the art should be able to understand that the above-mentioned temporary storage block can be implemented as a super block shown in FIG. 3B. First, the flash memory controller 110 autonomous device 130 receives a first write command, and assumes that the data corresponding to the first write command is random data (for example, 4 KB) and the data amount is less than the critical value. The flash memory controller 110 writes the data corresponding to the first write command to the first data page P0 of the second temporary storage block TB_SLC_0; then, the flash memory controller 110 autonomous device 130 sequentially Receiving a second write command and a third write command, assuming that the data corresponding to the second and third write commands is also random data (for example, 4 KB), the flash memory controller 110 sequentially The data corresponding to the second and third write commands are written into the data pages P1 and P2 of the second temporary storage block TB_SLC_0. Next, the flash memory controller 110 autonomous device 130 receives a fourth write command, and assumes that the data corresponding to the fourth write command is continuous data, and the data amount of the data is 548 KB greater than the critical value. If the amount of data to be written to the first temporary storage block TB_MLC_0 is greater than the critical value, the flash memory controller 110 firstly sets the data pages P0~P2 of the second temporary storage block TB_SLC_0. The valid data (12 KB in total) is written to the data pages P0 to P34 of the first temporary storage block TB_MLC_0 together with the data (548 KB) corresponding to the fourth write command. In this embodiment, the flash memory controller 110 records the current second temporary storage in a spare area of each of the data pages P0 to P34 in the process of writing the data to the first temporary storage block TB_MLC_0. The information of the first blank data page of the block TB_SLC_0 (ie, the data page P3). In this embodiment, the size of the spare area is usually 64B or 128B, and is generally used to store management information of the file system.

Generally, when the flash memory controller 110 receives the data corresponding to the first, second, and third write commands, the first, second, and third write commands are first The data is temporarily stored in the buffer memory 116, and when the flash memory controller 110 writes the data corresponding to the first, second, and third write commands to the data page P0 of the second temporary storage block TB_SLC_0 After P1 and P2, the corresponding data temporarily stored in the buffer memory 116 is deleted. In this embodiment, after the flash memory controller 110 writes the data corresponding to the first, second, and third write commands to the data pages P0, P1, and P2 of the second temporary storage block TB_SLC_0. The data corresponding to the first, second, and third write commands temporarily stored in the buffer memory 116 are not deleted. When the fourth write command is received, the flash memory controller 110 temporarily stores the data corresponding to the fourth write command in the buffer memory 116, and directly reads the first data from the buffer memory 116. The data corresponding to the fourth write command is collectively written into the data pages P0 to P34 of the first temporary storage block TB_MLC_0, and then the first to fourth temporarily stored in the buffer memory 116 are deleted. Write the data corresponding to the command. In other embodiments, after the flash memory controller 110 writes the data corresponding to the first, second, and third write commands to the data pages P0, P1, and P2 of the second temporary storage block TB_SLC_0. The data corresponding to the first, second, and third write commands temporarily stored in the buffer memory 116 is deleted. When receiving the fourth write command, the flash memory controller 110 temporarily stores the data corresponding to the fourth write command in the buffer memory 116, and from the data page P0 of the second temporary storage block TB_SLC_0. After P1 and P2 read the data to the buffer memory 116, the data corresponding to the first to fourth write commands are read from the buffer memory 116, and are collectively written to the first temporary storage block. TB_MLC_0 data page P0~P34.

It should be noted that, in the foregoing embodiment, the information of the first blank data page of the second temporary storage block TB_SLC_0 recorded in the first temporary storage block TB_MLC_0 is the data page P3, but the present invention does not To be limited thereto, in other embodiments, the first blank of the second temporary storage block TB_SLC_0 is called. The information of the data page may be any content that can be associated with and determined by the data page P3, for example, the serial number of the last data page written by the second temporary storage block TB_SLC_0, and these design changes shall be attached to Within the scope of the invention.

Then, the flash memory controller 110 autonomous device 130 receives a fifth write command and a sixth write command, and assumes that the data corresponding to the fifth and sixth write commands is random data, then flash memory The body controller 110 sequentially writes the data corresponding to the fifth and sixth write commands to the data pages P3 and P4 of the second temporary storage block TB_SLC_0. In this embodiment, it is assumed that the data stored in the data page P4 of the second temporary storage block TB_SLC_0 is used to update the data stored in the data page P1 of the second temporary storage block TB_SLC_0, that is, the second temporary storage area. The data pages P1, P4 of the block TB_SLC_0 and the data page P1 of the first temporary storage block TB_MLC_0 correspond to the same logical address.

In the embodiment of the second to fourth embodiments, the first blank of the second temporary storage block TB_SLC_0 is recorded in the spare area of the data pages P0 to P34 in the first temporary storage block TB_MLC_0 in the data writing process. The purpose of the information on the data page is to avoid the subsequent occurrence of a power failure (POR) or a SPOR condition, and it is impossible to determine the first temporary storage block TB_MLC0 and the second temporary storage block TB_SLC_0. Information is old and new, causing errors. The following embodiments shown in FIGS. 5 and 6 will explain how to correctly determine the first temporary storage area by using the information of the first blank data page of the second temporary storage block TB_SLC_0 recorded by the first temporary storage block TB_MLC_0. The data in the block TB_MLC_0 and the second temporary storage block TB_SLC_0 is new and old.

Referring to FIG. 5, a flowchart of a method of managing a flash memory module 120 in accordance with an embodiment of the present invention. In step 500, the memory device 100 encounters a state after a power failure (POR) or a power failure (SPOR). Therefore, the address mapping table originally stored in the buffer memory 116 has been Lost. In step 502, the flash memory controller 110 reads the content of the spare area of the last data page of the first temporary storage block to determine a data page number of the second temporary storage block. . In step 504, the flash memory controller 110 determines that the data in the second temporary storage block starting from the data page number is the latest data, and the data page number is the old data (invalid data). In step 506, the flash memory controller 110 re-establishes the address mapping table according to the determination result of step 504.

Specifically, following the embodiment shown in FIG. 4, and referring to FIG. 6, when the memory device 100 encounters a power failure (POR) or a sudden power failure (SPOR) condition, The flash memory controller 110 may need to re-establish an address mapping table corresponding to the second temporary storage block TB_SLC_0 and the first temporary storage block TB_MLC_0, respectively. At this time, the flash memory controller 110 directly reads the content to the spare area of the last data page (ie, P34) of the first temporary storage block TB_MLC_0, and obtains a data page number ( That is, P3), in the process of establishing the address mapping table of the second temporary storage block TB_SLC_0, the flash memory controller 110 directly determines the data of the second temporary storage block TB_SLC_0 starting from the data page P3. It is the new data, and the data before the data page P3 is the old data. Therefore, the address mapping table of the second temporary storage block TB_SLC_0 will only record the physical addresses of the data pages P3 and P4 and the corresponding The logical address does not record the address information about the data pages P0~P2.

In addition, regarding the address mapping table of the first temporary storage block TB_MLC_0, the flash memory controller 110 sequentially reads the information of each of the first temporary storage blocks TB_MLC_0 to re-establish the first temporary The physical address of each data page P0~P34 in the block TB_MLC_0 and the corresponding logical address.

In the above embodiments, the status of the reply after the power is restored after the power is turned off or the power is suddenly turned off. The address mapping table of the second temporary storage block TB_SLC_0 newly re-established will only contain the latest information, so if the second temporary storage block TB_SLC_0 has the same address mapping table as the first temporary storage block TB_MLC_0 The logical address, for example, the data page P4 of the second temporary storage block TB_SLC_0 shown in FIG. 6 has the same logical address (LBA_001) as the data page P1 of the first temporary storage block TB_MLC_0, and the content can be directly judged. The data page P4 of the second temporary storage block TB_SLC_0 is the latest data, that is, the data of the data page P4 of the second temporary storage block TB_SLC_0 is used to update the content of the data page P1 of the first temporary storage block TB_MLC_0. In an embodiment, if the flash memory controller 110 receives a read command requesting the read logical address LBA_001, the flash memory controller 110 directly starts from the second temporary storage block TB_SLC_0. The address mapping table obtains the corresponding physical address, and reads the data from the data page P4 of the second temporary storage block TB_SLC_0, and does not need to read the address mapping table of the first temporary storage block TB_MLC_0 Content.

In an embodiment, after the plurality of first temporary storage blocks complete the data writing, the first temporary storage blocks may be subjected to a garbage collection operation to move the valid data to at least one of the first temporary storage blocks. The data blocks (for example, DB_0) can be released after the first temporary storage blocks to continue for data writing.

Briefly summarized in the present invention, in the method for managing a flash memory module of the present invention, two temporary storage blocks (a first temporary storage block and a second temporary storage block) are used to store and write to the flash. The data in the memory module, wherein the first temporary storage block is mainly used for storing data whose data amount is greater than a critical value (for example, 64 KB), and the second temporary storage block is used for storing data amount smaller than the Random data for the critical value. In addition, by recording the information of the last blank data page of the current second temporary storage block in the first temporary storage block, the information can be accurately determined after the power failure after the power failure or the power failure after the sudden power failure. The information in the second temporary storage block and the first temporary storage block is new and old, especially when the first temporary storage block and the second temporary storage block There are cases where the data pages have the same logical address in the memory block to solve the problem of the prior art.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

Claims (10)

A method for managing a flash memory module, wherein the flash memory module comprises a plurality of flash memory chips, each of the flash memory chips comprising a plurality of first temporary memory blocks and a plurality of The second temporary storage block, each of the first temporary storage block and the second temporary storage block includes a plurality of data pages, and the method includes: writing a first data to the plurality of second temporary storage areas a second temporary storage block in the block; when the access of the flash memory module meets a specific condition, moving the first data stored in the second temporary storage block to the plurality of a first temporary storage block in the first temporary storage block, and recording the current second temporary storage in the first temporary storage block when the first data is moved to the first temporary storage block Information on the first blank data page of the block. The method of claim 1, wherein the second temporary storage block is a single-level cell (SLC) block, and the first temporary storage block is a multi-layer storage ( Multiple-Level Cell (MLC) block or Triple-Level Cell (TLC) block. The method of claim 1, wherein the information of the first blank data page of the second temporary storage block is the serial number of the first blank data page of the second temporary storage block, or The last one of the second temporary storage block has the serial number of the data page to which the data is written. The method of claim 1, wherein the first data stored in the second temporary storage block is moved to the first temporary storage block, and recorded in the first temporary storage block. The step of the information about the serial number of the first blank data page in the second temporary storage block includes: moving the first data stored in the second temporary storage block to the first temporary storage block Multiple funds In the material page, the information of the first blank data page of the second temporary storage block is recorded in a spare area of each of the plurality of data pages. The method of claim 4, further comprising: writing a second data into the second temporary storage block; and recovering after power failure occurs during the writing of the second data (power) In the off recovery (POR) state, the information of the first blank data page of the second temporary storage block is read from the spare area of the last data page in which the data is written in the first temporary storage block, and Based on the information, it is determined that the data pages in the second temporary storage block are invalid data pages, and the contents of those data pages have not been moved into the first temporary storage block for establishing a logical entity address mapping table. The method of claim 5, wherein the information of the first blank data page of the second temporary storage block is a data page number, and the second temporary storage block is determined according to the information. The data pages are invalid data pages, and the steps of the data pages have not been moved to the first temporary storage block. The method includes: determining that all the data pages in the second temporary storage block that are located before the data page number are Invalid data page; and determining that the data page number and all subsequent data pages in the second temporary storage block are valid data pages, and the contents of the valid data pages are the latest data in the flash memory module . A flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module includes a plurality of flash memory chips, each flashing The memory chip includes a plurality of first temporary storage blocks and a plurality of second temporary storage blocks, each of the first temporary storage block and the second temporary storage block includes a plurality of data pages, and the flash memory Controller contains There is: a read-only memory for storing a code; and a microprocessor for executing the code to control access to the flash memory module; wherein the microprocessor will be a first Data is written into a second temporary storage block of the plurality of second temporary storage blocks; and when the access of the flash memory module meets a specific condition, the microprocessor is stored in the The first data in the second temporary storage block is moved to a first temporary storage block of the plurality of first temporary storage blocks, and when the first data is moved to the first temporary storage block And storing information of the first blank data page of the second temporary storage block in the first temporary storage block. The flash memory controller of claim 7, wherein the second temporary storage block is a single-level cell (SLC) block, and the first temporary storage block It is a Multiple-Level Cell (MLC) block or a Triple-Level Cell (TLC) block. The flash memory controller of claim 7, wherein the information of the first blank data page of the second temporary storage block is the first blank data page of the second temporary storage block. The serial number or the serial number of the data page to which the last data of the second temporary storage block is written. The flash memory controller of claim 7, wherein the microprocessor moves the first data stored in the second temporary storage block to the plurality of first temporary storage blocks. In the data page, the information of the first blank data page of the second temporary storage block is recorded in a spare area of each of the plurality of data pages.