WO2009104588A1 - Dispositif d'émission de signal, procédé de traitement de conversion de signal, programme de traitement de conversion de signal et circuit d'émission pseudo hdlc - Google Patents

Dispositif d'émission de signal, procédé de traitement de conversion de signal, programme de traitement de conversion de signal et circuit d'émission pseudo hdlc Download PDF

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Publication number
WO2009104588A1
WO2009104588A1 PCT/JP2009/052665 JP2009052665W WO2009104588A1 WO 2009104588 A1 WO2009104588 A1 WO 2009104588A1 JP 2009052665 W JP2009052665 W JP 2009052665W WO 2009104588 A1 WO2009104588 A1 WO 2009104588A1
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Prior art keywords
signal sequence
signal
conversion
pattern
pseudo
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PCT/JP2009/052665
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English (en)
Japanese (ja)
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嘉一郎 齊藤
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日本電気株式会社
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/08—Protocols for interworking; Protocol conversion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H04L69/324—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC

Definitions

  • the present invention converts a discontinuous data signal sequence into a continuous data signal sequence using a pseudo HDLC encapsulation method, sends the data signal sequence to an opposite station via a wireless transmission path, and receives the continuous data signal sequence received from the opposite station.
  • the present invention relates to a signal transmission device, a signal conversion processing method, a signal conversion processing program, and a pseudo HDLC transmission circuit that reproduces and outputs a discontinuous data signal sequence again.
  • LAN signals networks that handle interface signals
  • IEEE 802.3 transmission signal sequences
  • a wireless transmission device that sends LAN signals received in units of frames from a wired transmission path to the opposite station one-to-one via the wireless transmission path, and outputs them again to the wired transmission path at the opposite station.
  • an encapsulation method using a pseudo-HDLC (High-level Data Link Control Procedure) frame as a signal conversion means for converting a discontinuous data signal sequence handled in units of frames into a continuous data signal sequence (
  • the pseudo HDLC encapsulation method is frequently used.
  • the pseudo HDLC frame is defined by RFC (Request FOR Comment) 1662.
  • a process of filling a space between frames (hereinafter referred to as an inter frame) with a predetermined signal sequence (hereinafter referred to as a flag pattern) is performed.
  • a signal sequence having the same pattern as the flag pattern included in the transmission signal sequence is changed to another predetermined signal sequence different from the flag pattern (hereinafter referred to as a pattern conversion process) is performed in units of octets.
  • the signal sequence of 1 octet to be subjected to pattern conversion processing is replaced with a signal sequence of 2 octets (hereinafter referred to as a converted signal sequence).
  • This conversion signal sequence is obtained by re-determining a signal sequence of 1 octet (hereinafter referred to as a control pattern) that has been determined in advance for identifying a signal sequence that has undergone pattern conversion processing, and a signal sequence that has undergone pattern conversion processing.
  • 1-octet signal string hereinafter referred to as an identification pattern
  • Such signal conversion realizes signal reproduction on the receiving side.
  • a signal sequence having the same pattern as the control pattern included in the frame signal is replaced with another predetermined conversion pattern different from the control pattern in units of octets.
  • the signal sequence of 1 octet is also the original control sequence of 1 octet for identifying that it is a signal sequence subjected to pattern conversion processing and the signal sequence subjected to pattern conversion processing again. It can be replaced with a 2-octet signal sequence composed of an identification pattern of 1 octet for storing information for returning to the signal sequence.
  • a signal sequence of 1 octet included in the frame signal and the same signal sequence as the flag pattern and the control pattern is converted into a 2-octet conversion signal sequence. replace.
  • the data length is greatly expanded after the pattern conversion process, resulting in a decrease in throughput and a decrease in transmission efficiency.
  • the pattern conversion process is repeated a plurality of times, resulting in a significant decrease in throughput.
  • the present invention provides a signal transmission device, a signal conversion processing method, a signal conversion processing program, and a pseudo HDLC transmission circuit capable of avoiding a significant increase in data length after pattern conversion processing and causing a decrease in throughput. With the goal.
  • the present invention provides: A signal transmission device that performs conversion processing to convert a discontinuous data signal sequence configured in units of frames into a pseudo HDLC signal sequence that is a continuous data signal sequence using a pseudo HDLC encapsulation method,
  • the signal sequence to be subjected to the conversion process included in the discontinuous data signal sequence has a predetermined conversion pattern including continuous frequency information indicating the number of times the signal sequence to be converted is generated continuously.
  • a pseudo HDLC transmission circuit for converting into a signal sequence is provided.
  • a signal in a signal transmission apparatus that performs transmission processing by converting a discontinuous data signal sequence configured in units of frames into a pseudo HDLC signal sequence that is a continuous data signal sequence using a pseudo HDLC encapsulation method.
  • a conversion processing method The signal sequence to be subjected to the conversion process included in the discontinuous data signal sequence has a predetermined conversion pattern including continuous frequency information indicating the number of times the signal sequence to be converted is generated continuously. Converting to a signal sequence.
  • a signal transmission device configured to perform conversion processing for converting a discontinuous data signal sequence configured in units of frames into a pseudo HDLC signal sequence that is a continuous data signal sequence using a pseudo HDLC encapsulation method is configured.
  • a signal conversion processing program executed on a computer, In the computer, The signal sequence to be subjected to the conversion process included in the discontinuous data signal sequence has a predetermined conversion pattern including continuous frequency information indicating the number of times the signal sequence to be converted is generated continuously. A function to convert to a signal sequence is realized.
  • a pseudo signal transmission apparatus that performs transmission processing by converting a discontinuous data signal sequence configured in units of frames into a pseudo HDLC signal sequence that is a continuous data signal sequence using a pseudo HDLC encapsulation method.
  • An HDLC transmission circuit comprising: The signal sequence to be subjected to the conversion process included in the discontinuous data signal sequence has a predetermined conversion pattern including continuous frequency information indicating the number of times the signal sequence to be converted is generated continuously.
  • a signal conversion circuit for converting into a signal train is provided.
  • the present invention is configured as described above, it can be avoided that the data length is significantly expanded after the pattern conversion process and the throughput is reduced.
  • FIG. 2 is a diagram illustrating an example of a pseudo HDLC signal sequence in the wireless transmission device illustrated in FIG. 1. It is a figure for demonstrating the flag pattern conversion rule in the radio
  • FIG. 3 is a diagram illustrating an example of a pseudo HDLC signal sequence obtained by performing pattern conversion processing on a LAN signal received by the wireless transmission device illustrated in FIG. 1.
  • FIG. 2 is a diagram for comparing the conversion results of the pattern conversion processing in the wireless transmission device shown in FIG. 1 and the pattern conversion processing defined in RFC1662, and (a) shows the conversion result of the pattern conversion processing defined in RFC1662.
  • FIG. 8B is a diagram illustrating a conversion result of the pattern conversion process in the wireless transmission device illustrated in FIG. 1. It is a block diagram which shows the hardware structural example of the radio
  • FIG. 1 is a block diagram showing an example of the configuration of a wireless transmission device to which the signal transmission device of the present invention is applied.
  • the wireless transmission devices 10 a and 10 b are connected to face each other via the wireless transmission path 110.
  • the wireless transmission devices 10a and 10b convert the LAN signal received from the wired transmission path into a pseudo HDLC frame signal, and then send the same to the opposite station via the wireless transmission path 110, and from the pseudo HDLC frame signal at the opposite station.
  • the LAN signal is reproduced and output to the wired transmission path.
  • the wireless transmission device 10a and the wireless transmission device 10b have the same configuration, and the configuration will be described below with reference to only the wireless transmission device 10a.
  • the wireless transmission device 10a includes a LAN signal transmission / reception circuit 12a, a pseudo HDLC transmission circuit 13a, a pseudo HDLC reception circuit 15a, and a wireless transmission / reception circuit 14a.
  • the LAN signal transmission / reception circuit 12a outputs the reception LAN signal 120a received from the wired transmission path 111a to the pseudo HDLC transmission circuit 13a.
  • the LAN signal transmission / reception circuit 12a outputs the transmission LAN signal 155a received from the pseudo HDLC reception circuit 15a to the wired transmission path 111a.
  • the pseudo HDLC transmission circuit 13a includes a signal conversion circuit 30a, a flag pattern detection circuit 31a, a flag counter 32a, a control pattern detection circuit 33a, and a control counter 34a.
  • the pseudo HDLC transmission circuit 13a performs pseudo HDLC encapsulation processing described later on the received LAN signal 120a to generate a pseudo HDLC transmission signal 134a.
  • FIG. 2 is a diagram illustrating an example of a LAN signal string in the wireless transmission devices 10a and 10b illustrated in FIG.
  • FIG. 3 is a diagram illustrating an example of a pseudo HDLC signal sequence in the wireless transmission devices 10a and 10b illustrated in FIG.
  • FIG. 4 is a diagram for explaining a flag pattern conversion rule in the wireless transmission devices 10a and 10b shown in FIG.
  • FIG. 5 is a diagram for explaining control pattern conversion rules in the wireless transmission devices 10a and 10b shown in FIG.
  • the pseudo HDLC encapsulation processing performed by the pseudo HDLC transmission circuit 13a is performed by converting the discontinuous LAN signal sequence including the LAN frame 200a and the inter frames 201a and 202a shown in FIG. 2 into the pseudo HDLC frame 200b and the flag patterns 201b and 202b shown in FIG. Is a process of converting into a continuous pseudo HDLC signal sequence consisting of
  • a signal sequence 200c identical to a continuous flag pattern of n octets (n is an integer of 1 to 15) included in the LAN frame 200a is converted into a 2-octet flag conversion pattern 205c. (Hereinafter referred to as flag pattern conversion process).
  • control pattern conversion process Based on the control pattern conversion rule shown in FIG. 5, a signal sequence 200d identical to a continuous control pattern of m octets (m is an integer of 1 to 15) included in the LAN frame 200a is converted into a 2-octet control conversion pattern 205d. (Hereinafter referred to as control pattern conversion process).
  • the flag conversion pattern 205c shown in FIG. 4 includes a 1-octet control pattern 201c (defined as 0x7D in hexadecimal) for identifying a signal sequence subjected to pattern conversion, and a 1-octet flag identification pattern 202c. Is composed of.
  • the flag identification pattern 202c shown in FIG. 4 includes a 4-bit continuous number information field 203c and a predetermined 4-bit flag pattern identifier 204c (defined as 0xE in hexadecimal).
  • the continuous number information field 203c is a field for storing information on the number n of times that the pattern to be converted is continuous, and the flag pattern identifier 204c indicates that the flag pattern conversion process is being performed.
  • Information (information for returning a signal sequence subjected to flag pattern conversion back to the original signal sequence).
  • the control conversion pattern 205d shown in FIG. 5 includes a 1-octet control pattern 201c and a 1-octet control identification pattern 202d.
  • control identification pattern 202d shown in FIG. 5 includes a 4-bit continuous number information field 203c and a predetermined 4-bit control pattern identifier 204d (defined as 0xD in hexadecimal).
  • the control pattern identifier 204d is information indicating that the control pattern conversion process is being performed (information for returning the signal sequence subjected to the control pattern conversion back to the original signal sequence).
  • the flag pattern detection circuit 31a monitors the received LAN signal 120a in units of octets. When the same signal sequence (0x7E) as n consecutive flag patterns is detected, the flag pattern detection information 130a is output to the flag counter 32a and the signal conversion circuit 30a.
  • the flag counter 32a monitors the flag pattern detection information 130a from the flag pattern detection circuit 31a. Then, by measuring the number n of times that the same signal sequence (0x7E) as the flag pattern is continuously detected, flag conversion number information 131a including the number n as information is generated and output to the signal conversion circuit 30a.
  • the control pattern detection circuit 33a monitors the received LAN signal 120a in units of octets. When the same signal sequence (0x7D) as m consecutive control patterns is detected, the control pattern detection information 132a is output to the control counter 34a and the signal conversion circuit 30a.
  • the control counter 34a monitors the control pattern detection information 132a from the control pattern detection circuit 33a. Then, by measuring the number m of times that the same signal sequence (0x7D) as the control pattern is continuously detected, control conversion number information 133a including the number m as information is generated and output to the signal conversion circuit 30a.
  • the signal conversion circuit 30a performs a flag pattern conversion process on the received LAN signal 120a based on the flag pattern detection information 130a and the flag conversion count information 131a. Further, the signal conversion circuit 30a performs a control pattern conversion process on the received LAN signal 120a based on the control pattern detection information 132a and the control conversion frequency information 133a. Further, the signal conversion circuit 30a performs a flag pattern insertion process. Then, the pseudo HDLC transmission signal 134a is generated, and the generated pseudo HDLC transmission signal 134a is output to the wireless transmission / reception circuit 14a.
  • the signal conversion circuit 30a When the flag pattern detection information 130a is detected, the signal conversion circuit 30a indicates that the signal sequence (0x7E) identical to the flag pattern has been detected n times continuously in the continuous number information field 203c of the flag identification pattern 202c.
  • the conversion number information 131a is multiplexed. Thereby, the flag pattern conversion process for generating the flag conversion pattern 205c is performed.
  • the signal conversion circuit 30a detects that the signal sequence (0x7D) that is the same as the control pattern is detected m times continuously in the continuous number information field 203c of the control identification pattern 202d.
  • the control conversion frequency information 133a shown is multiplexed. Thereby, a control pattern conversion process for generating the control conversion pattern 205d is performed.
  • the pseudo HDLC reception circuit 15a includes a synchronization circuit 50a, a flag conversion signal detection circuit 51a, a control conversion signal detection circuit 52a, and a signal reproduction circuit 53a.
  • the pseudo HDLC reception circuit 15a receives the pseudo HDLC reception signal 140a and executes signal reproduction processing from the pseudo HDLC signal sequence as shown in FIG. 3 to the LAN signal sequence as shown in FIG.
  • the synchronization circuit 50a detects the flag patterns 201b and 202b shown in FIG. 3 from the pseudo HDLC reception signal 140a received from the wireless transmission / reception circuit 14a, and performs frame synchronization of the pseudo HDLC signal. Also, the synchronization circuit 50a removes the flag patterns 201b and 202b and reproduces the inter frame. Then, the pseudo HDLC frame signal 150a is generated, and the generated pseudo HDLC frame signal 150a is output to the flag conversion signal detection circuit 51a, the control conversion signal detection circuit 52a, and the signal reproduction circuit 53a.
  • the flag conversion signal detection circuit 51a monitors the pseudo HDLC frame signal 150a from the synchronization circuit 50a. Then, the flag conversion pattern 205c is detected based on the control pattern 201c (see FIG. 4) and the flag pattern identifier 204c included in the pseudo HDLC frame signal 150a.
  • the flag conversion signal detection circuit 51a When the flag conversion pattern 205c is detected, the flag conversion signal detection circuit 51a generates the flag conversion pattern detection signal 151a, extracts the continuous number information n stored in the continuous number information field 203c, and extracts the flag reproduction number information 152a. Is generated. Then, the generated flag conversion pattern detection signal 151a and flag reproduction count information 152a are output to the signal reproduction circuit 53a.
  • the control conversion signal detection circuit 52a monitors the pseudo HDLC frame signal 150a. Then, the control conversion pattern 205d is detected based on the control pattern 201c (see FIG. 5) and the control pattern identifier 204d included in the pseudo HDLC frame signal 150a.
  • control conversion signal detection circuit 52a When the control conversion pattern 205d is detected, the control conversion signal detection circuit 52a generates the control conversion pattern detection signal 153a, extracts the continuous number information m stored in the continuous number information field 203c, and extracts the control reproduction number information 154a. Is generated. Then, the generated control conversion pattern detection signal 153a and control reproduction count information 154a are output to the signal reproduction circuit 53a.
  • the signal reproduction circuit 53a performs a process opposite to the flag pattern conversion process on the pseudo HDLC frame signal 150a based on the flag conversion pattern detection signal 151a and the flag reproduction count information 152a. Further, the signal reproduction circuit 53a performs a process reverse to the control pattern conversion process based on the control conversion pattern detection signal 153a and the control reproduction number-of-times information 154a. Further, the signal reproduction circuit 53a reproduces the inter frame by deleting the flag pattern, generates a transmission LAN signal 155a, and outputs it to the LAN signal transmission / reception circuit 12a.
  • the signal reproduction circuit 53a When the flag conversion pattern detection signal 151a is detected, the signal reproduction circuit 53a repeatedly generates the same signal sequence (0x7E) as the flag pattern by the number n of times indicated in the flag reproduction number information 152a, and performs a flag pattern conversion process. The reverse process is applied.
  • the signal reproduction circuit 53a When the control conversion pattern detection signal 153a is detected, the signal reproduction circuit 53a repeatedly generates the same signal sequence (0x7D) as the control pattern by the number m of times indicated in the control reproduction number information 154a, and performs control pattern conversion processing. The reverse process is applied.
  • the wireless transmission / reception circuit 14a shown in FIG. 1 multiplexes the pseudo HDLC transmission signal 134a received from the pseudo HDLC transmission circuit 13a into a wireless frame and outputs the multiplexed signal to the wireless transmission path 110. Further, the wireless transmission / reception circuit 14a extracts the pseudo HDLC reception signal 140a from the wireless signal received from the wireless transmission path 110 and outputs the pseudo HDLC reception signal 140a to the pseudo HDLC reception circuit 15a.
  • the wireless transmission device 10b also corresponds to the components of the wireless transmission device 10a, and includes a LAN signal transmission / reception circuit 12b, a pseudo HDLC transmission circuit 13b, a pseudo HDLC reception circuit 15b, and a wireless transmission / reception circuit. 14b.
  • the pseudo HDLC transmission circuit 13b shown in FIG. 1 includes a signal conversion circuit 30b, a flag pattern detection circuit 31b, a flag counter 32b, a control pattern detection circuit 33b, and a control counter 34b.
  • the pseudo HDLC reception circuit 15b shown in FIG. 1 includes a synchronization circuit 50b, a flag conversion signal detection circuit 51b, a control conversion signal detection circuit 52b, and a signal reproduction circuit 53b.
  • FIG. 8 is a block diagram illustrating a hardware configuration example of the wireless transmission device 10a illustrated in FIG.
  • the wireless transmission device 10a can be realized by the same hardware configuration as a general computer device.
  • the wireless transmission device 10b shown in FIG. 1 can also be realized by the same hardware configuration as a general computer device.
  • the wireless transmission device 10a illustrated in FIG. 8 is connected to a CPU (Central Processing Unit) 401, a main storage unit 402, a communication unit 403 that transmits and receives data via a network, and an external device to transmit and receive data.
  • a CPU Central Processing Unit
  • main storage unit 402 main storage unit 402
  • communication unit 403 that transmits and receives data via a network
  • an external device to transmit and receive data.
  • An input / output interface unit 404, an auxiliary storage unit 405, and a system bus 406 for connecting the above-described components of the apparatus to each other are provided.
  • the main storage unit 402 is a main memory such as a RAM (Random Access Memory), for example, and is used as a data work area or a temporary data save area.
  • a RAM Random Access Memory
  • the auxiliary storage unit 405 is a hard disk device including a nonvolatile memory such as a ROM (Read Only Memory), a magnetic disk, and a semiconductor memory.
  • a nonvolatile memory such as a ROM (Read Only Memory), a magnetic disk, and a semiconductor memory.
  • the wireless transmission device 10a of the present embodiment includes circuit components that are hardware components such as LSI (Large Scale Integration) in which programs for executing the functions of the pseudo HDLC transmission circuit 13a and the pseudo HDLC reception circuit 15a are incorporated. By implementing it, the operation is realized in hardware.
  • LSI Large Scale Integration
  • a program (signal conversion processing program) for providing each function by the pseudo HDLC transmission circuit 13a and the pseudo HDLC reception circuit 15a is stored in the auxiliary storage unit 405, and the program is loaded into the main storage unit 402 and executed by the CPU 401. By doing so, it can also be realized in software.
  • FIG. 6 is a diagram for explaining pattern conversion processing in the wireless transmission devices 10a and 10b shown in FIG. 1.
  • FIG. 6A shows a LAN signal received by the wireless transmission device 10a shown in FIG. 1 in units of frames.
  • FIG. 5B is a diagram illustrating an example, and FIG. 5B is a diagram illustrating an example of a pseudo HDLC signal sequence obtained by performing pattern conversion processing on the LAN signal received by the wireless transmission device 10a illustrated in FIG.
  • the wireless transmission device 10a receives the LAN signal 303a shown in FIG. 6A from the wired transmission path 111a and connects to the wireless transmission device 10b via the wireless transmission path 110. A case of outputting to the wired transmission path 111b will be described.
  • the LAN signal 303a is composed of inter frames 301a and 302a and a frame 300a existing between the inter frames 301a and 302a.
  • the frame 300a includes signal sequences Da3 to Da5 having the same pattern as the flag pattern (0x7E), and a signal sequence Da7 having the same pattern as the control pattern (0x7D).
  • the signal sequence Da1 to Da9 is included.
  • the LAN signal transmission / reception circuit 12a of the wireless transmission device 10a receives the LAN signal 303a received from the wired transmission path 111a to each of the signal conversion circuit 30a, the flag pattern detection circuit 31a, and the control pattern detection circuit 33a of the pseudo HDLC transmission circuit 13a. Output as a LAN signal 120a.
  • the flag pattern detection circuit 31a monitors the frame 300a of the LAN signal 303a received via the reception LAN signal 120a, and detects a signal sequence having the same pattern as the flag pattern (0x7E) from the frame 300a.
  • the flag pattern detection circuit 31a When the flag pattern detection circuit 31a detects the signal sequences Da3 to Da5 having the same pattern as the flag pattern (0x7E), the flag pattern detection circuit 31a generates flag pattern detection information 130a indicating that the signal sequences Da3 to Da5 are subject to flag pattern conversion. To do. Then, the flag pattern detection circuit 31a outputs the generated flag pattern detection information 130a to the signal conversion circuit 30a and the flag counter 32a.
  • the flag counter 32a that has received the flag pattern detection information 130a measures that the number of consecutive signal sequences to be subjected to flag pattern conversion is 3, and uses flag conversion number information 131a including the number of times as information. Generate and output to the signal conversion circuit 30a.
  • control pattern detection circuit 33a monitors the frame 300a of the LAN signal 303a received via the reception LAN signal 120a, and detects a signal sequence having the same pattern as the control pattern (0x7D) from the frame 300a. .
  • control pattern detection circuit 33a When the control pattern detection circuit 33a detects a signal sequence Da7 having the same pattern as the control pattern (0x7D), the control pattern detection circuit 33a generates control pattern detection information 132a indicating that the signal sequence Da7 is a target of control pattern conversion. Then, the control pattern detection circuit 33a outputs the generated control pattern detection information 132a to the signal conversion circuit 30a and the control counter 34a.
  • the control counter 34a that has received the control pattern detection information 132a measures that the number of consecutive signal sequences to be subjected to control pattern conversion is 1, and uses control conversion count information 133a including the count as information. Generate and output to the signal conversion circuit 30a.
  • the signal conversion circuit 30a Based on the flag pattern detection information 130a and the flag conversion count information 131a, the signal conversion circuit 30a indicates three times, which is the number of times that the signal sequence to be subjected to flag pattern conversion indicated by the flag conversion count information 131a is continuous. The value is set in the continuous count information field 203c (see FIG. 4). This is performed according to the flag pattern conversion rule shown in FIG.
  • the signal conversion circuit 30a has a signal string Db3 having a control pattern 201c (see FIG. 4) of hexadecimal 0x7D and a signal string having a flag identification pattern 202c of hexadecimal 0x3E. Db4 is generated.
  • the signal conversion circuit 30a is based on the control pattern detection information 132a and the control conversion frequency information 133a, and is one time that is the number of times that the signal sequence to be subjected to the control pattern conversion indicated by the control conversion frequency information 133a is continuous. Is set in the continuous count information field 203c (see FIG. 5). This is performed according to the control pattern conversion rule shown in FIG.
  • the signal conversion circuit 30a has a signal string Db6 having a control pattern 201c (see FIG. 5) of hexadecimal 0x7D and a signal string having a control identification pattern 202d of hexadecimal 0x1D. Db7 is generated.
  • the signal conversion circuit 30a converts the signal sequences Da1, Da2, Da6, Da8, and Da9 shown in FIG. 6A that are not subjected to flag pattern conversion processing and control pattern conversion processing into signal sequences shown in FIG. 6B, respectively. Insert into Db1, Db2, Db5, Db8, Db9.
  • the signal conversion circuit 30a combines the signal sequences Db3 and Db4 generated by performing the flag pattern conversion process with the signal sequences Db6 and Db7 generated by performing the control pattern conversion process, and uses the signal sequences Db1 to Db9.
  • the constructed pseudo HDLC frame 300b is generated.
  • the signal conversion circuit 30a converts the interframes 301a and 302a in the LAN signal 303a received via the reception LAN signal 120a into the 0x7E flag patterns 301b and 302b in hexadecimal.
  • the pseudo HDLC transmission signal 134a composed of the pseudo HDLC signal sequence 303b shown in FIG. 6B is generated.
  • the signal conversion circuit 30a outputs the generated pseudo HDLC transmission signal 134a to the wireless transmission device 10b via the wireless transmission / reception circuit 14a and the wireless transmission path 110.
  • the wireless transmission device 10b receives the pseudo HDLC transmission signal 134a as the pseudo HDLC reception signal 140b by the wireless transmission / reception circuit 14b, and outputs the pseudo HDLC transmission signal 134b to the pseudo HDLC reception circuit 15b of the wireless transmission device 10b.
  • the synchronization circuit 50b of the pseudo HDLC reception circuit 15b of the wireless transmission device 10b receives the pseudo HDLC reception signal 140b, and detects a 0x7E pattern in hexadecimal from the pseudo HDLC signal sequence 303b of the received pseudo HDLC reception signal 140b. Thus, frame synchronization of the pseudo HDLC signal sequence is achieved.
  • the synchronization circuit 50b discriminates between the flag patterns 301b and 302b and the pseudo HDLC frame 300b, performs the removal processing of the flag patterns 301b and 302b, and generates the pseudo HDLC frame 300b. Then, the synchronization circuit 50b outputs the generated pseudo HDLC frame 300b to the flag conversion signal detection circuit 51b, the control conversion signal detection circuit 52b, and the signal reproduction circuit 53b as a pseudo HDLC frame signal 150b.
  • the flag conversion signal detection circuit 51b monitors the pseudo HDLC frame signal 150b, and detects that the signal sequence Db3 of the received pseudo HDLC frame 300b is a control pattern of 0x7D in hexadecimal.
  • the flag conversion signal detection circuit 51b detects that the lower 4 bits of the signal sequence Db4 following the signal sequence Db3 are hexadecimal values indicating that the flag pattern conversion processing is being performed and is a value of 0xE. It is recognized that the columns Db3 and Db4 are flag conversion patterns.
  • the flag conversion signal detection circuit 51b outputs a flag conversion pattern detection signal 151b indicating that the signal sequences Db3 and Db4 are flag conversion patterns to the signal reproduction circuit 53b.
  • the flag conversion signal detection circuit 51b performs flag reproduction number information indicating that conversion is performed three times based on the value of 0x3 in hexadecimal extracted from the continuous number information field indicated by the upper 4 bits of the signal string Db4. 152b is generated and output to the signal reproduction circuit 53b.
  • the control conversion signal detection circuit 52b monitors the pseudo HDLC frame signal 150a and detects that the signal string Db6 in the received pseudo HDLC frame 300b is a control pattern of 0x7D in hexadecimal.
  • control conversion signal detection circuit 52b detects that the lower 4 bits of the signal sequence Db7 following the signal sequence Db6 are hexadecimal values indicating that control pattern conversion is being performed and is a value of 0xD, and the signal sequence Db6 Recognize that Db7 is a control conversion pattern.
  • control conversion signal detection circuit 52b outputs a control conversion pattern detection signal 153b indicating that the signal sequences Db6 and Db7 are control conversion patterns to the signal reproduction circuit 53b.
  • the flag conversion signal detection circuit 51b performs control reproduction number information indicating that one conversion is performed based on the value of 0x1 in hexadecimal extracted from the continuous number information field indicated by the upper 4 bits of the signal string Db7. 154b is generated and output to the signal reproduction circuit 53b.
  • the signal reproduction circuit 53b generates a signal sequence Da3 to Da5 that is three consecutive times of 0x7E in hexadecimal, based on the flag conversion pattern detection signal 151b and the flag reproduction number information 152b.
  • the signal reproduction circuit 53b generates a signal string Da7 of one pattern of 0x7D in hexadecimal based on the control conversion pattern detection signal 153b and the control reproduction number information 154b.
  • the signal reproduction circuit 53b receives the signal sequences Db1, Db2, Db5, Db8, and Db9 shown in FIG. 6B that are not to be reproduced by the flag pattern conversion process and the control pattern conversion process, respectively, as shown in FIG. 6A. Inserted in the columns Da1, Da2, Da6, Da8, Da9.
  • the signal reproduction circuit 53b matches the signal sequence Da3 to Da5 reproduced based on the flag conversion pattern detection signal 151b with the signal sequence Da7 reproduced based on the control conversion pattern detection signal 153b.
  • the LAN signal 303a composed of the frame 300a composed of the signal sequences Da1 to Da9 and the inter frames 301a and 302a is reproduced, and the transmission LAN signal 155b is generated.
  • the signal reproduction circuit 53b outputs the generated transmission LAN signal 155b to the wired transmission line 111b via the LAN signal transmission / reception circuit 12b.
  • the LAN signal 303a received by the wireless transmission device 10a from the wired transmission path 111a is converted into a pseudo HDLC signal sequence 303b and transmitted to the wireless transmission device 10b via the wireless transmission path 110. Then, it is reproduced again as the LAN signal 303a and output to the wired transmission line 111b.
  • the continuous signal conversion target signal sequences are collectively performed once, and converted into a signal sequence having a conversion pattern including the continuous count information.
  • FIG. 7 is a diagram for comparing the conversion results of the pattern conversion processing in the radio transmission apparatuses 10a and 10b shown in FIG. 1 and the pattern conversion processing defined by RFC1662, and (a) is defined by RFC1662.
  • the signal sequence 400a has 6 octets. Is converted to a signal sequence 401a.
  • the number of times that the signal sequence to be converted is continuous is counted and replaced with the converted signal sequence including the information of the count value.
  • the signal train 400b shown in FIG. 7B which is the same as the signal train 400a shown in FIG. 7A, is converted into a 2-octet signal train 401b.
  • the extension of the signal sequence after pattern conversion can be significantly reduced as compared with the pattern conversion processing defined by RFC1662.
  • the pattern conversion target is a flag pattern defined as 0x7E in hexadecimal and a control pattern defined as 0x7D in hexadecimal.
  • a flag pattern defined as 0x7E in hexadecimal
  • a control pattern defined as 0x7D in hexadecimal.
  • the upper 4 bits of the flag identification pattern 202c or the control identification pattern 202d are set as the continuous count information field 203c and the lower 4 bits are set as the flag pattern identifier 204c or the control pattern identifier 204d.
  • the number of bits allocated to the flag pattern identifier 204c or the control pattern identifier 204d can be arbitrarily changed.
  • the processing in the signal transmission device is recorded on a recording medium readable by the signal transmission device, in addition to the processing realized by the dedicated hardware described above.
  • the program recorded on the recording medium may be read by the signal transmission device and executed.
  • the recording medium that can be read by the signal transmission device indicates a transfer medium such as a floppy disk, a magneto-optical disk, a DVD, and a CD, as well as an HDD built in the signal transmission device.
  • It can be used for a transmission method of a data bus signal used between a wireless transmission device and a wired transmission device that perform signal transmission between different points, between modules in a device, or between devices.

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  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)

Abstract

L'invention porte sur un dispositif d'émission de signal qui effectue un traitement de conversion pour convertir par procédé d'encapsulation pseudo HDLC une séquence de signaux de données discontinue configurée trame par trame en une séquence de signaux pseudo HDLC, qui constitue une séquence de signaux de données continue, et transmet le résultat. Le dispositif d'émission de signal comprend un circuit d'émission pseudo HDLC pour convertir une séquence de signaux inclue dans la séquence de signaux de données discontinue et sur laquelle sera effectué le traitement de conversion, en une séquence de signaux à motif de conversion prédéterminé comprenant les informations de nombre de fois continu qui indiquent le nombre de fois où la séquence de signaux sur laquelle est effectué le traitement de conversion est apparu de façon continue.
PCT/JP2009/052665 2008-02-18 2009-02-17 Dispositif d'émission de signal, procédé de traitement de conversion de signal, programme de traitement de conversion de signal et circuit d'émission pseudo hdlc WO2009104588A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008035884A JP2011119781A (ja) 2008-02-18 2008-02-18 信号伝送装置、及び信号変換処理方法、信号変換処理プログラム及び疑似ｈｄｌｃ送信回路
JP2008-035884 2008-02-18

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WO2009104588A1 true WO2009104588A1 (fr) 2009-08-27

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10200415A (ja) * 1997-01-10 1998-07-31 Ricoh Co Ltd データ圧縮方法及びデータ圧縮／伸長装置
JPH11145940A (ja) * 1997-09-08 1999-05-28 Oki Electric Ind Co Ltd データ送信装置及びデータ受信装置
JPH11163959A (ja) * 1997-11-28 1999-06-18 Ando Electric Co Ltd フレーム変換回路および該フレーム変換回路を用いた回線モニタ装置
WO2001010098A1 (fr) * 1999-08-02 2001-02-08 Fujitsu Limited Dispositif de communication par trames

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10200415A (ja) * 1997-01-10 1998-07-31 Ricoh Co Ltd データ圧縮方法及びデータ圧縮／伸長装置
JPH11145940A (ja) * 1997-09-08 1999-05-28 Oki Electric Ind Co Ltd データ送信装置及びデータ受信装置
JPH11163959A (ja) * 1997-11-28 1999-06-18 Ando Electric Co Ltd フレーム変換回路および該フレーム変換回路を用いた回線モニタ装置
WO2001010098A1 (fr) * 1999-08-02 2001-02-08 Fujitsu Limited Dispositif de communication par trames

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