WO2009102918A1 - Cellule de mémoire enregistrable ayant de multiples états physiques - Google Patents

Cellule de mémoire enregistrable ayant de multiples états physiques Download PDF

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Publication number
WO2009102918A1
WO2009102918A1 PCT/US2009/034004 US2009034004W WO2009102918A1 WO 2009102918 A1 WO2009102918 A1 WO 2009102918A1 US 2009034004 W US2009034004 W US 2009034004W WO 2009102918 A1 WO2009102918 A1 WO 2009102918A1
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Prior art keywords
layer
memory
memory device
memory cells
states
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PCT/US2009/034004
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English (en)
Inventor
Geoffrey Wen-Tai Shuy
Hsin-Chen Lai
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Hong Kong Applied Science & Technology Research Institute Co. Ltd
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Publication of WO2009102918A1 publication Critical patent/WO2009102918A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/02—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/009—Write using potential difference applied between cell electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used

Definitions

  • This invention relates to recordable electrical memory cells that have multiple physical states.
  • NVM devices are widely used for storing information, such as program storage for Micro-Controller Units (MCU) and Multi-Media Content data Storage.
  • MCU Micro-Controller Unit
  • Multi-Media Content data Storage Typically, an NVM device includes an array of addressable memory cells, where word lines and bit lines define the address of each cell.
  • NVM devices include at least three major categories: namely "Process Memory Device,” “Circuitry Memory Device,” and “Material Memory Device,” as described briefly below.
  • Process Memory Devices can be used as a program storage device for MCU.
  • a Process Memory Device is a mask-programming ROM.
  • Mask-programming ROM may have low production costs, but it may need a dedicated mask for each program under its specific implementation. Thus, in some cases, mask-programming ROM needs to be programmed in a wafer fabrication process with a Minimum-Order-Quality (MOQ) requirement.
  • MOQ Minimum-Order-Quality
  • Circuitry Memory Devices can be used for program storage (such as one-time programmable memory (OTP) and/or data storage (such as Flash memory).
  • OTP one-time programmable memory
  • Flash memory Flash memory
  • Flash memory device aims at rewritable (not irreversibly recordable) recording.
  • Each memory cell of the flash memory device includes a floating gate metal oxide semiconductor (MOS) transistor, in which the electrically isolated floating gate is used to store charges at its inscription state.
  • MOS floating gate metal oxide semiconductor
  • Common flash memory chips range widely in capacity from several hundred kilobytes to several gigabytes. Although flash memory chips exhibit many desirable characteristics including user-friendliness, they may require complicated wafer processing to produce the intricate two-transistor memory device. This leads to its fabrication technology being about 1 to 2 generations behind the state-of-the-art CMOS process. It is desirable to achieve memory size larger than CMOS.
  • some flash memories have been designed to encode more than two values per cell according to the amount of charge stored in the floating gate. Yet such memories may still need to overcome the problem of poor data retention.
  • Material Memory Devices can also be used for providing electrically rewritable or irreversibly recordable recording.
  • a Material Memory Device is a phase change memory, which aims to provide electrically rewritable (not irreversibly recordable) recording and can switch material between generally amorphous and generally crystalline states.
  • phase change memory was first used back in the 1960s, it remains difficult to make commercially viable products based on phase change memory.
  • Reasons may include (1) high current density required in inscription, (2) low inscription contrast ratio for meaningful multiple-state-recording, and/or (3) challenge of Moore's law extremity. Phase change memory currently does not provide irreversibly recordable memory capability.
  • Some general aspects of the invention relate to memory devices, for example, material memory devices that are irreversibly recordable.
  • REME recordable electrical memory
  • This REME can be used, for example, in one-time programmable (recordable) binary storage devices.
  • the REME can be designed to have an inscription voltage threshold (e.g., between 1.5 to 6 volts) and possess distinctive physical characteristics between states before and after inscription.
  • the resistance of REME can be designed to fall from "almost as insulator” steeply down to "almost as conductor” after fully inscription.
  • a second example of irreversibly recordable material memory device implements sub-division process techniques for generating memory cells of multiple inscription states, as disclosed in U.S. Patent Application Serial No. 11/855,537, titled “Recordable Electrical Memory,” by Geoffrey Wen-Tain Shuy, the disclosure of which is incorporated herein by reference.
  • U.S. Patent Application Serial No. 11/855,537 titled “Recordable Electrical Memory,” by Geoffrey Wen-Tain Shuy, the disclosure of which is incorporated herein by reference.
  • a third example of irreversibly recordable material memory device is capable of having multiple inscription states without necessarily creating physical subdivisions within a single cell.
  • This type of memory cells makes use of materials that may have one or more of following characteristics: (1) the resistance contrast ratio of the virgin (un-inscribed) state to the fully inscribed state can be extended to greater than 9 orders of magnitude; and (2) by injecting proper energy (& power) input during inscription, the resistance of the inscribed state between un-inscribed and fully inscribed states can be derived to various levels as desired.
  • & power proper energy
  • a large number of intermediate states can be formed between the un-inscribed state and the fully inscribed state using suitable inscription techniques, for example, by injecting a pulse train (e.g., in the form of voltage and/or current) of a prescribed number of discrete "chunk" of energy into a single memory cell.
  • a pulse train e.g., in the form of voltage and/or current
  • the data storage capacity of such memory devices can be greatly increased, without having to reduce the dimension of the memory cell or complicate the fabrication process.
  • the memory device includes a recordable thin material layer, and a plurality of memory cells each formed using a corresponding different portion of the recordable thin material layer.
  • each memory cell Upon application of an electrical write signal selected from a plurality of predetermined write signals, each memory cell is configured to alter the corresponding portion of the layer from a first physical state to a physical state selected from a plurality of substantially distinct physical states.
  • the first physical state is associated with a substantially diode-like current- voltage characteristic.
  • Each of the plurality of substantially distinct physical states has a resistor-like current-voltage characteristic.
  • Implementation of the memory device may include one or more of the following features.
  • the corresponding portion of the layer in each one of the plurality of substantially distinct physical states may have a substantially different electrical state.
  • the corresponding portion of the layer in each one of the plurality of substantially distinct physical states may have a substantially different resistance.
  • the memory cell may have a Schottky barrier formed at an interface between the layer of material and a metal electrode or a metal layer, and said interface forming a substantially ohmic junction after application of at least some of the predetermined write signals.
  • the memory device may further include electrodes for transmitting the electrical write signal.
  • At least one of the memory cells may include a layer that combines with a portion of the electrodes upon application of the electrical write signal.
  • the memory device may further include a first layer and a second layer that combine upon application of the write signal.
  • At least one of the plurality of predetermined write signals may include a pulse (e.g., a voltage pulse or a current pulse).
  • a pulse e.g., a voltage pulse or a current pulse.
  • At least one of the plurality of predetermined write signals may include a sequence of pulses.
  • the memory device may further include electrodes for sending the write signals, and the electrodes do not interact with the layer of material upon application of the write signal to the memory cells.
  • FIGS. IA to 1C show a perspective view, a side view, and a top view, respectively, of a portion of a recordable electrical memory device.
  • FIG. 2 shows I-V curves of a binary memory cell before and after inscription.
  • FIG. 3 shows I-V curves of a memory cell that has multiple physical states.
  • FIG. 4 shows a write circuit model for inscribing a memory cell.
  • FIG. 5 shows six I-V curves of an exemplary memory cell inscribed by six different levels of inscription energies of the same duration.
  • FIG. 6 shows five I-V curves of a memory cell inscribed by five different inscription energies of various durations.
  • FIG. 7 shows the result of data retention test on exemplary memory cells in virgin state.
  • FIG. 8 shows the result of data retention test on exemplary cells in an inscribed state.
  • FIG. 9 includes Table 1 showing exemplary resistance values of memory cells after inscription with two inscription energies of different characteristics.
  • FIG. 10 includes Table 2 showing exemplary resistance values of memory cells after inscription with three inscription energies of different characteristics.
  • FIG. 11 includes Table 3 showing exemplary resistance values of memory cells after inscription with another three inscription energies of different characteristics
  • Recordable thin film material may irreversibly change its physical states upon application of drive signals. Therefore, such a thin film material can be used for manufacturing memory cells for storage devices, where each physical state of a cell can represent stored information.
  • the small dimension of thin film memory cells typically ⁇ 50 nm x 50 nm per cell
  • large-capacity memory devices e.g., >10GB
  • electrical thin film memory device which includes memory cells that each store one bit of information, is described in U.S. Patent Application Serial No. 11/503,671 by Geoffrey Wen-Tai Shuy, the disclosure of which is incorporated herein by reference.
  • the recordable layer in a memory cell has distinctly different material properties before and after energy application.
  • a memory cell 120 in a memory device 100 can be marked (inscribed) using a drive signal that induces electrical current through the cell via a selected pair of a word line 140 and a bit line 130 that defines the address of the memory cell 120.
  • the applied electrical energy then drives the memory cell to a different physical state from its virgin state.
  • a memory cell exhibits a diode-like I-V characteristic in its virgin state, while having a resistor-like I-V characteristic in the inscribed state, shown by curves 202 and 204 respectively.
  • the memory cell can represent a data bit of "0" before and "1" after inscription.
  • the recorded data i.e., either "0” or "1”
  • the memory cell 120 may be used in memory device to store retrievable binary information, e.g., with "0” corresponding to its virgin state and "1" corresponding to its inscribed state.
  • more than two physical states in a memory cell are used for storing data, without necessarily having distinct physical subdivisions within the cell.
  • write signals with different numbers (or other characteristics such as duration, amplitude, and timing) of chunks of inscription energy (or power) may change the material properties into corresponding different physical levels and therefore create multiple physical states in a single cell.
  • Each of the multiple physical states has distinct material properties, thus the memory cell may be used to record multiple (i.e., more than two) data bits.
  • Drive (write) signals for changing material properties can take various forms, for example, specified or characterized according to a voltage (or current ) as a function of time for the duration of the drive signal. That is, each drive signal is characterized by a voltage (or current) waveform that is applied to the memory cell.
  • a drive signal may be a single voltage (or current) pulse characterized in its voltage (or current) level and time duration.
  • a drive signal may also be a sequence of voltage (or current) pulses characterized in the nature, the magnitude, the timing and the arrangements of its individual components.
  • the electrical current introduced by the drive signal generates energy (e.g., thermal energy) that changes the material properties in the recordable layer, for example, by causing a chemical reaction in the cell, or causing different materials to intermix.
  • energy e.g., thermal energy
  • Examples of material properties that may change upon the drive signal include resistivity permittivity, capacity, dielectric constant, and junction characteristics such as a Schottky barrier or an ohmic junction within the recordable layer.
  • a memory device includes a layer of material and a set of memory cells each formed using a corresponding different portion of the layer. Each memory cell can be inscribed to multiple physical states (e.g., by changing the material property of the corresponding portion of the layer) upon application of various electrical write signals.
  • a potential barrier forms at an interface of the layer of material and a metal electrode or a metal layer. Thus, a memory cell in its virgin state behaves substantially like a diode.
  • the recordable layer includes at least one of a semiconductor material or a dielectric material.
  • a voltage (or current) pulse with sufficient power level and/or duration may eliminate the potential barrier and change the cell to a first inscribed state of being resistor-like, i.e., having a substantially linear current- voltage relationship.
  • a voltage (or current) pulse with a higher power level may break the potential barrier, change the Ohmic-like area, and drive the cell to a second inscribed state, also being resistor-like, but having a new resistivity level substantially different from the first inscribed state. Therefore, the memory cell in this case has at least three physical states: a diode-like state, a first inscribed state having a substantially constant resistance value, and a second inscribed state having a substantially constant resistance value which is different from the first inscribed state.
  • FIG. 3 shows the I-V curves of a memory cell that has six physical states, including a virgin state ("0"), represented by curve 302, and five inscribed states ("1,” “2,” “3,” “4,” and “5"), represented by curves 304, 306, 308, 310 and 312 respectively.
  • the material in the recordable layer has a diode-like current-voltage relationship in its virgin state, and can be changed by write signals (e.g., signals with various numbers of chunks of write energies) to have essentially resistor-like current- voltage relationships with five different resistance levels.
  • write signals may include a single voltage (or current) pulse or multiple pulses with suitable combinations of voltage (or current) level, duration, and sequences. .
  • applying a pulse of high voltage (or current) level to the cell may result in a larger resistance compared with a low voltage (or current) pulse (e.g., as the results shown in FIGs. 9, 10, and 11), while in some other examples, high- voltage pulses may actually result in a smaller memory cell resistance ((e.g., as the results shown in FIGs. 5 and 6).
  • applying a pulse sequence may result in a larger, or sometimes smaller, resistance than merely applying one of the individual pulses within the sequence.
  • a number of test instances of the memory device are first fabricated.
  • a possibly large set of candidate drive signals are defined, for example, by varying signal characteristics such as pulse amplitude, pulse duration, pulse number, and duty cycle.
  • several predefined drive signals are used for inscribing the cells of test devices in a test or calibration phase to determine a set of specified drive signals that correlate to distinct inscription states.
  • the inscription results obtained from these predefined drive signals in the test or calibration phase can be documented in a comprehensive database, from which one may select a write signal that has been shown to create the desired physical state for the target cell.
  • the database may also include additional information describing characteristics of recordable material (e.g., type(s) of semiconductor or dielectric material(s), the doping level of the semiconductor material, and the type(s) of metal used for the electrode) that may, to some extent, affect the outcome of a write signal.
  • a definite set of driving signals are known to the external device interfacing to the memory device. For example, if the memory devices share common characteristics, the driving signals can be "universal.”
  • thin film memory devices may differ in the selection of the materials and/or the geometric configuration of memory cells in the device, and a write signal that marks a specific inscribed state (such as "2") in one memory device may not necessarily be applicable to another.
  • each memory device carries a customized write table that describes the group of write signals that can properly inscribe its memory cells.
  • the write table contains information regarding the characteristics of each write signal as well as the corresponding physical state created by each signal.
  • the computer or other electronic devices generally starts the writing process by allocating a data bit to each one of the memory cells based on existing algorithm. Next, it sends commands that search the entire write table to find the appropriate write signals for each cell and subsequently applies the identified write signals.
  • each cell in the memory device is configured to represent one of the Estates, including a "0” (referring to an empty write signal) and "1," “2,” “3,”.... "N-I” that corresponds to N-I number of write signals respectively.
  • retrieving the data i.e., identifying the physical state of each memory cell
  • retrieve the data is accomplished by employing read circuitry that can detect material properties (such as electrical resistance and/or resistivity) of the target cells.
  • material properties such as electrical resistance and/or resistivity
  • memory cells in each one of the multiples states have different electrical properties, e.g., electrical resistance.
  • the physical state of a memory cell is detected essentially by measuring the resistivity (or electrical resistance) of the cell.
  • an energy source 404 e.g., a voltage source, in a write circuit 400 is used to supply write signals for inscribing a memory cell 402.
  • write signals include voltage (or current) pulses, such as a single square wave 406 having a voltage level of Vo and a time duration of to, a single square wave 408 having a voltage level of Vi and a duration of t ls a dual square wave 410 consisting of both 406 and 408, and other write signals that may contain either single or multiple pulses.
  • Write signals capable of inscribing the memory cell to one of the physical states are recorded in a write strategy table, for example, Table 4.
  • the memory cell can be inscribed from its virgin state ("0") to one of the multiple inscribed states ("1,” “2,” “3,” “4,” and “5"), and each state has a distinct ohmic-like voltage-current relationship that is established by the corresponding write pulse/pulses.
  • Write pulses in this table symbolized as (V, t), are characterized in their voltage levels (V) and durations (t).
  • a single write pulse drives a memory cell from its original diode-like state “0" to inscribed state “1” that results in a resistance value of Ri
  • a different write pulse drives the memory cell to inscribed state "2" having a different resistance value ofR 2
  • a write sequence is applied to the memory cell, e.g. a first write pulse (Vo, to) followed by a delay t 12 and subsequently a second pulse (V 1 , ti)
  • the cell will be changed to inscribed state "3", with a new resistance value OfR 3 .
  • the memory cell can be insccribed into either one of the inscribed states "4" and "5", having resistance values R 4 and R5, respectively, by applying the corresponding sequence of write pulses listed in Table 1. Therefore, upon the application of the proper write signals, the memory cell can be selectively inscribed to one of its five available inscribed states.
  • the materials and thickness of the recordable layer 110 can be selected based on information from a pre-established database.
  • the database can be established by measuring the material properties (including electrical properties) of various thin layers or combinations of thin layers of various materials.
  • the database can include information e.g., about the resistance per unit area, and diode-like characteristics, of (1) a single layer of material at different thicknesses, and (2) various combinations of materials of varying thicknesses, before and after application of some write signals.
  • the materials and thickness of the layers are selected to achieve a desired contrast in resistance between virgin state and inscribed states. Examples of suitable materials are described in U.S. Patent Application Serial No. 11/503,671 by Geoffrey Wen-Tai Shuy et al, filed on Aug 14, 2006.
  • memory cells were fabricated using the following process.
  • the base pressures of the main chamber and the process chamber were maintained below 10 "7 mbar.
  • the operation pressure in the process chamber was set to be in the range of 10 "3 to 10 "2 mbar during film deposition.
  • the thicknesses of the layers were controlled by the sputtering power and sputtering time.
  • the thickness of each of the thin layers was measured and estimated based on the sputtering yield of the material, the sputtering time (e.g., from 7 to 28 seconds), and the sputtering power density (e.g., 4 to 8 W/cm 2 ) used for the layers.
  • the recordable layer was made of p-type silicon and has a thickness of about 10 nm.
  • the metal (electrode) layers were made of aluminum; each has a thickness of about 750 nm.
  • the size of memory cell between the two metal layers is 1.2 ⁇ m x 1.2 ⁇ m.
  • the recordable electrical memory cell has diode-like current- voltage characteristics in virgin state and can be modified to multiple distinctive inscribed states upon applying specified write signals. Each inscribed state has resistor-like current-voltage characteristics.
  • Three cells are inscribed by three different inscription energies at the same pulse duration (210 ⁇ s) with three different voltage pulse amplitudes (3.8V, 4.2V, and 5.5V).
  • Three distinctive inscribed states with tunable resistance contrast ratio (factors of 4-30) for any two adjacent inscribed states are created.
  • the resistances of the three inscribed states are 180 ⁇ , 1300 ⁇ , and 5400 ⁇ , as shown in Table 2 of FIG. 10.
  • Three cells are inscribed by three different inscription energies at the same pulse duration (5 ⁇ sec) with three different voltage pulse amplitude (5.7V, 6.0V, and 6.2V).
  • Three distinctive inscribed states with tunable resistance contrast ratio (factor of 5-47) for any two adjacent inscribed states are created.
  • the resistances for the three inscribed states are 10 ⁇ , 83 ⁇ , and 470 ⁇ , as shown in Table 3 of FIG. 11.
  • One cell is inscribed by six chunks of inscription energy (and power) at specific pulse duration (5 ⁇ sec) with six different voltage pulse amplitudes (3.4 V, 3.5 V, 3.6 V, 3.7 V, 3.8 V, and 4.0V).
  • the memory cell can be modified to six distinctive inscribed states; I-V curves of every physical state are calibrated and shown in Fig. 5.
  • the resistance for each inscribed state is 11.1 ⁇ , 8.3 ⁇ , 7.7 ⁇ , 6.1 ⁇ , 5.3 ⁇ , and 4.4 ⁇ .
  • the memory cell in virgin state and inscribed states easily maintains itself at a substantially constant resistance level, regardless of variations in the storage environment.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un dispositif de mémoire comprenant une mince couche matérielle enregistrable et une pluralité de cellules de mémoire formées chacune à l’aide d’une partie différente correspondante de la mince couche matérielle enregistrable. Lors de l'application d'un signal d'écriture électrique sélectionné parmi une pluralité de signaux d'écriture prédéterminés, chaque cellule de mémoire est configurée pour modifier la partie correspondante de la couche d'un premier état physique à un état physique sélectionné parmi une pluralité d'états physiques sensiblement distincts. Le premier état physique est associé à une caractéristique courant-tension sensiblement analogue à une diode. Chacun parmi la pluralité d'états physiques sensiblement distincts présente une caractéristique courant-tension analogue à une résistance.
PCT/US2009/034004 2008-02-13 2009-02-13 Cellule de mémoire enregistrable ayant de multiples états physiques WO2009102918A1 (fr)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9472281B1 (en) 2015-06-30 2016-10-18 HGST Netherlands B.V. Non-volatile memory with adjustable cell bit shape
US9728255B2 (en) 2015-10-13 2017-08-08 Western Digital Technologies, Inc. Planar variable resistance memory

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050058010A1 (en) * 2000-07-07 2005-03-17 Thin Film Electronics Asa Addressing of memory matrix
US20070015348A1 (en) * 2005-07-18 2007-01-18 Sharp Laboratories Of America, Inc. Crosspoint resistor memory device with back-to-back Schottky diodes

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050058010A1 (en) * 2000-07-07 2005-03-17 Thin Film Electronics Asa Addressing of memory matrix
US20070015348A1 (en) * 2005-07-18 2007-01-18 Sharp Laboratories Of America, Inc. Crosspoint resistor memory device with back-to-back Schottky diodes

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"Nanoscience and nanotechnology in Europe", NANOTECHNOLOTY, vol. 7, no. ISS.2, June 1996 (1996-06-01), pages 59 - 105, Retrieved from the Internet <URL:http://www.iop.org/EJ/abstract/0957-4484/7/2/001> [retrieved on 20090402] *
TOLLES.: "Nanoscience and nanotechnology in Europe", NANOTECHNOLOTY, vol. 7, no. ISS.5, June 1996 (1996-06-01), pages 59 - 105, Retrieved from the Internet <URL:http://nanotech.iu4.bmstu.ru/archive/ran/Nanoscience%20and%20nanotechnology%20in%20Europe.pdf> [retrieved on 20090402] *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9472281B1 (en) 2015-06-30 2016-10-18 HGST Netherlands B.V. Non-volatile memory with adjustable cell bit shape
US10229737B2 (en) 2015-06-30 2019-03-12 HGST Netherlands B.V. Non-volatile memory with adjustable cell bit shape
US9728255B2 (en) 2015-10-13 2017-08-08 Western Digital Technologies, Inc. Planar variable resistance memory
US10163504B2 (en) 2015-10-13 2018-12-25 Western Digital Technologies, Inc. Planar variable resistance memory

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