WO2009089321A4 - Digital feequency generator - Google Patents
Digital feequency generator Download PDFInfo
- Publication number
- WO2009089321A4 WO2009089321A4 PCT/US2009/030398 US2009030398W WO2009089321A4 WO 2009089321 A4 WO2009089321 A4 WO 2009089321A4 US 2009030398 W US2009030398 W US 2009030398W WO 2009089321 A4 WO2009089321 A4 WO 2009089321A4
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- circuit
- sample
- state
- input
- output
- Prior art date
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/03—Astable circuits
- H03K3/0315—Ring oscillators
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/004—Counters counting in a non-natural counting order, e.g. random counters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
- H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
- H03K23/502—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits with a base or a radix other than a power of two
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L1/00—Stabilisation of generator output against variations of physical values, e.g. power supply
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L1/00—Stabilisation of generator output against variations of physical values, e.g. power supply
- H03L1/02—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only
- H03L1/022—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature
- H03L1/027—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature by using frequency conversion means which is variable with temperature, e.g. mixer, frequency divider, pulse add/substract logic circuit
Abstract
A feed-forward control loop circuit, almost-binary counter and ring oscillator, comprising: an oscillation source; a reference frequency source having a second frequency independently generated from the oscillation source; a measurement circuit responsive to the reference source and the oscillation source; a first circuit accepting an input frequency and creating an output frequency dependent on another input; and a second circuit operating on an output of the measurement circuit and receiving a frequency input. The feed-forward control loop produces an output from the first circuit, the reference source and the frequency input being sufficient to determine the output of the feed-forward control loop.
Claims
AMENDED CLAIMS received by the International Bureau on 30 November 2009 (30.11.2009)
1 , A feed-forward control loop circuit, comprising: an oscillation source having a first frequency; a reference frequency source having a second frequency independently generated from the oscillation source, wherein a timing reference is based on the reference frequency source; a measurement circuit responsive to the reference source and the oscillation source, the measurement unit assessing the first frequency relative to the second frequency; a first circuit accepting an input frequency and creating an output frequency dependent on another input, wherein the input frequency is determined by the oscillation source; and a second circuit operating on an output of the measurement circuit and receiving a frequency input, the second circuit controlling a second input of the first circuit, such that a feedforward control loop produces an output from the first circuit, the reference source and the frequency input being sufficient to determine the output of the feed-forward contfol loop,
2. A ςounting circuit producing a sequence of states in response to a clock input, such that a number of states of the counting circuit between any two states of the sequence of states are calculated, comprising: an interconnected set of cany D-type flip-flops configured to perform (i) samph'ng of an input of the interconnected set of carry D-type flip-flops, (ii) synchronous detection of a change on the input interconnected set of carry D-type flip-flops, said detection responsive to a difference between the input of the interconnected set of cany D-type flip-flops and the input of the.interconnected set of cany D-type flip-flops as sampled, and (iii) providing said detection to an output of the interconnected set of carry D-type flip-flops; an interconnected set of at least two state D-type flip-flops configured to perform, responsive to a controlling input of the interconnected set of at least two state D-type flip-flops, (i) change state or (ii) not change state; connections between the interconnected set of carry D-type flip-flops and the interconnected set of at least two state D-type flip-flops, said connections connecting the output of. the interconnected set of carry D-type flip-flops to the controlling input of the interconnected, set of at least two state D-type flip-flops, such that the change in the input of the interconnected set! of carry D-type flip-flops changes an output of the interconnected set of at least twq state D- type flip-flops.
3. The circuit of claim 2, wherein the change on the input of the interconnected set of carry D-type flip-flops is from a "one" state to a "zero" state, such that a change to a corresponding one of the interconnected set of at least two state D-type flip-flops is detected, responsive to synchronously detecting a negative edge.
4. A counting circuit producing a sequence of states in response to a clock input such that a number of states of the counting circuit between any two states of the sequence of states are ^calculated, comprising: an interconnected set of at least two state D-type flip-flops and ripple-through carry logic, including an enable signal output allowing additional significant bits to change responsive to a local state D-type flip-flop, and including an enable signal input that indicates all lower significant bits are in a state allowing a carry output; an interconnected set of carry D-type flip-flops between the enable signal output of the lower significant bits and the enable signal input of the more significant bits, such that at least one clock cycle delay occurs in propagation of carry from less significant bits to more significant bits.
5. . The circuit of claim 4, wherein the local state D-type flip-flop and the lower significant bits have a "one" state to generate carry output,
6. The circuit of claim 5, further comprising: a set of latches sampling values of the interconnected set of at least two state D-type flip- flops and sampling values of interconnected set of carry D-type flip-flops, responsive tp an external signal; and combinatorial logic that generates a number indicative of the number of cycles of between a present state of the counting circuit and a sampled state of the counting circuit.
7. The circuit of claim 6, wherein the computation of the circuit is forced to be modulo two to the power of a finite number of elements of the circuit,
8.,; . A circuit, comprising: a ring oscillator; a pulse circuit generating an output pulse at a rate greater than a rate of oscillation of elements in the ring oscillator; a first sampling circuit generating a first sample of the ring oscillator, responsive to an extemaal event; a second sampling circuit sampling the external event into a state variable clocked by the output pulse; a third sampling circuit, responsive to a sampled event in the state variable, sampling state of elements of the ring oscillator to generate a second sample of the ting oscillator.
9. A circuit, comprising: a ring oscillator consisting at least two interconnected elements* the ring configured to oscillate and generate output pulses at a rate representative of a time delay of at least two .elements of the ring; a first sampling circuit creating an oscillator phase sample by sampling state of elements of the ring oscillator, responsive to an external event; a high speed counter; a second sampling circuit creating a creating a counter sample by sampling state of the ^igh speed counter, responsive to a sample in a state variable clocked by pulses from the ring oscillator and representing the external event;
$ circuitry receiving as inputs a current value of the oscillator phase sample and a current value of the counter sample, at least one historical record of the oscillator phase sample, and at least one historical record of the counter sample, said circuitry determining a difference in count in successive values of the counter sample and a fractional difference in oscillator phase from successive values of the oscillator phase sample, such that a measurement of time interval is gerfoimed at a time resolution smaller than a time interval of the high speed counter,
10. The circuit of claim 8, further comprising: a high speed counter; and a fourth sampling circuit sampling a state of the high speed counter, responsive to a sample in the state variable clocked by pulses from the ring oscillator and representing^ staticized external event, thereby creating a counter sample of a counter state of the high speed counter; circuitry receiving as input current values of the first sample of the ring oscillator, the second sample of the ring oscillator, at least one historical record of the first sample of the ring oscillator, and at least one historical record of the second sample of the ring oscillator, the circuitry determining a difference in count in successive values of the counter samples and a fractional difference in oscillator phase from successive values of the first sample and the second jsample, such that a measurement of time interval is performed at a time resolution smaller than a time interval of the high speed counter.
11. The circuit of claim 7, further comprising: a ring oscillator; a sampling circuit creating an oscillator phase sample by sampling a state of elements of the ring oscillator, responsive to an external event, circuitry operating on at least two successive samples of the oscillator phase sample and the output , of the counting circuit, the circuitry creating a measurement of time interval at a time resolution smaller than a time interval of a high speed counter.
12. The circuit of claim 7, further comprising a ring oscillator; a pulse circuit generating an output pulse at a mte greater than a rate of oscillation of elements in the ring oscillator; a first sampling circuit generating a first sample of the ring oscillator, responsive to an external event; a second sampling circuit sampling the external event into a state variable clocked by the output puls;e; a third sampling circuit, responsive to a sampled event in the state variable, sampling state of elements of the ring oscillator to generate a second sample of the ring oscillator and circuitry receiving as input a current value of a first sample of the ring oscillator, a current value of a second sample of the ring oscillator, a current value of output of the modulo two computation of the combinatorial logic, at least one historical record of the first sample, at least one historical record of the second sample, and at least one historical record of output of the modulo two computation of the combinatorial logic, the circuitry operating to determine a difference in count in successive values of a high speed counter, a fractional difference in oscillator phase from the successive values of the first sample and the second sample, such that a measurement of time interval is performed at a time resolution smaller than, a time interval of the high speed counter,
13. . The circuit of claim 12, further comprising: a feed-forward control loop circuit, comprising: an oscillation source having a first frequency; a reference frequency source having a second frequency independently generated from the oscillation source, wherein a timing reference is based on the reference frequency source; a measurement circuit responsive to the reference source and the oscillation source, the measurement unit assessing the first frequency relative to the second , frequency; a first circuit accepting an input frequency and creating an output frequency dependent on another input, wherein the input frequency is determined by the oscillation source; and a second, circuit operating on an output of the measurement circuit and receiving a frequency input, the second circuit controlling a second input of the first circuit, such that a feed-forward control loop produces an output from the first circuit, the reference source and the frequency input being sufficient to determine the output of the feed-forward control loop, wherein the circuit generates a fixed and predictable output frequency.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US1981108P | 2008-01-08 | 2008-01-08 | |
| US61/019,811 | 2008-01-08 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| WO2009089321A2 WO2009089321A2 (en) | 2009-07-16 |
| WO2009089321A3 WO2009089321A3 (en) | 2009-12-03 |
| WO2009089321A4 true WO2009089321A4 (en) | 2010-02-25 |
Family
ID=40853755
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2009/030398 WO2009089321A2 (en) | 2008-01-08 | 2009-01-08 | Digital feequency generator |
Country Status (1)
| Country | Link |
|---|---|
| WO (1) | WO2009089321A2 (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6111442A (en) * | 1998-03-09 | 2000-08-29 | International Business Machines Corporation | Phase-locked loop circuit with dynamic backup |
| JP3888792B2 (en) * | 1998-12-25 | 2007-03-07 | 富士通株式会社 | Clock generation circuit |
| JP3533351B2 (en) * | 1999-12-28 | 2004-05-31 | 日本無線株式会社 | Feed forward amplifier and control circuit thereof |
| JP2006324750A (en) * | 2005-05-17 | 2006-11-30 | Nec Electronics Corp | Clock generating circuit |
-
2009
- 2009-01-08 WO PCT/US2009/030398 patent/WO2009089321A2/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| WO2009089321A2 (en) | 2009-07-16 |
| WO2009089321A3 (en) | 2009-12-03 |
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