WO2009086080A2 - Procédé et appareil de traitement d'un signal de communication - Google Patents

Procédé et appareil de traitement d'un signal de communication Download PDF

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Publication number
WO2009086080A2
WO2009086080A2 PCT/US2008/087644 US2008087644W WO2009086080A2 WO 2009086080 A2 WO2009086080 A2 WO 2009086080A2 US 2008087644 W US2008087644 W US 2008087644W WO 2009086080 A2 WO2009086080 A2 WO 2009086080A2
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WO
WIPO (PCT)
Prior art keywords
communication signal
cap
determined
bias point
access terminal
Prior art date
Application number
PCT/US2008/087644
Other languages
English (en)
Other versions
WO2009086080A3 (fr
Inventor
James Young Hurt
Preethi Chandrasekhar
Roland Reinhard Rick
Original Assignee
Qualcomm Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/962,655 external-priority patent/US8073076B2/en
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Priority to KR1020107016007A priority Critical patent/KR101134722B1/ko
Priority to JP2010539867A priority patent/JP5378405B2/ja
Priority to CN200880122286.3A priority patent/CN101904128B/zh
Publication of WO2009086080A2 publication Critical patent/WO2009086080A2/fr
Publication of WO2009086080A3 publication Critical patent/WO2009086080A3/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0202—Channel estimation
    • H04L25/0224—Channel estimation using sounding signals
    • H04L25/0228—Channel estimation using sounding signals with direct estimation from sounding signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H04B1/7097—Interference-related aspects
    • H04B1/711—Interference-related aspects the interference being multi-path interference
    • H04B1/7115—Constructive combining of multi-path signals, i.e. RAKE receivers

Definitions

  • the present invention generally relates to communication signals, and more specifically to a method and apparatus for processing a communication signal.
  • an access terminal for processing a communication signal includes a receiver configured to determine a bias point for the communication signal based on a quality measurement of the communication signal, the quality measurement having a carrier-to-interference (C/I) estimate associated therewith.
  • the receiver is further configured to determine a C/I cap for the communication signal using the C/I estimate, the C/I cap being configured to cap a signal to interference-plus-noise ratio (SINR) of the communication signal.
  • SINR signal to interference-plus-noise ratio
  • the receiver is configured to process the communication signal using the determined bias point and the determined C/I cap.
  • a method for processing a communication signal includes determining a bias point for the communication signal based on a quality measurement of the communication signal, the quality measurement having a carrier-to-interference (C/I) estimate associated therewith.
  • the method further includes determining a C/I cap for the communication signal using the C/I estimate, the C/I cap for capping a signal to interference-plus-noise ratio (SINR) of the communication signal.
  • SINR signal to interference-plus-noise ratio
  • the method includes processing the communication signal using the determined bias point and the determined C/I cap.
  • an apparatus for processing a communication signal is provided.
  • the apparatus includes means for determining a bias point for the communication signal based on a quality measurement of the communication signal, the quality measurement having a carrier-to-interference (C/I) estimate associated therewith.
  • the apparatus further includes means for determining a C/I cap for the communication signal using the C/I estimate, the C/I cap being configured to cap a signal to interference-plus-noise ratio (SINR) of the communication signal.
  • SINR signal to interference-plus-noise ratio
  • the apparatus includes means for processing the communication signal using the determined bias point and the determined C/I cap.
  • the processing system includes a module configured to determine a bias point for the communication signal based on a quality measurement of the communication signal, the quality measurement having a carrier-to- interference (C/I) estimate associated therewith.
  • the module is further configured to determine a C/I cap for the communication signal using the C/I estimate, the C/I cap being configured to cap a signal to interference-plus-noise ratio (SINR) of the communication signal.
  • SINR signal to interference-plus-noise ratio
  • the module is configured to process the communication signal using the determined bias point and the determined C/I cap.
  • the instructions include code for determining a bias point for the communication signal based on a quality measurement of the communication signal, the quality measurement having a carrier-to-interference (C/I) estimate associated therewith.
  • the instructions further include code for determining a C/I cap for the communication signal using the C/I estimate, the C/I cap for capping a signal to interference-plus-noise ratio (SINR) of the communication signal.
  • the instructions include code for processing the communication signal using the determined bias point and the determined C/I cap.
  • FIG. 1 is a diagram illustrating an example of a wireless communication system in which processing of a communication signal can be used.
  • FIG. 2 is a conceptual block diagram illustrating an example of one of the access terminals of FIG. 1.
  • FIG. 3 is a conceptual block diagram illustrating an exemplary receiver system, with a RAKE receiver, for performing variable scaling and C/I saturation.
  • FIG. 4 is a conceptual block diagram illustrating an exemplary receiver system, with an equalizer filter, for performing variable scaling and C/I saturation.
  • FIG. 5 is a flowchart illustrating an exemplary operation of processing of a communication signal.
  • FIG. 6 is a conceptual block diagram illustrating an example of the functionality of a device for processing of a communication signal.
  • FIG. 1 is a diagram illustrating an example of a wireless communication system in which processing of a communication signal can be used.
  • Wireless communication system 100 includes an access network 102 which can communicate with multiple access terminals 104i to 104 N .
  • Access terminals 104i to 104 N can also communicate with each other via access network 102.
  • a communication link from the access network to one of access terminals 104i to 104 N is typically referred to as a forward link, and a communication link from one of access terminals 104i to 104 N to access network 102 is typically referred to as a reverse link.
  • Access terminals 104i to 104 N can represent a mobile phone, a computer, a laptop computer, a telephone, a personal digital assistant (PDA), an audio player, a game console, a camera, a camcorder, an audio device, a video device, a multimedia device, a component(s) of any of the foregoing (such as a printed circuit board(s), an integrated circuit(s), and/or a circuit component(s)), or any other device capable of supporting wireless communication.
  • access terminals 104i to 104 N can be stationary or mobile, and can include digital devices, analog devices or a combination of both.
  • Communication system 100 can correspond with an Ultra- Wideband (UWB) system, which is a radio technology for Wireless Personal Area Networks (WPAN).
  • Communication system 100 may use one of many other communications protocols.
  • communication system 100 may support Evolution-Data Optimized (EV-DO) and/or Ultra Mobile Broadband (UMB).
  • EV-DO and UMB are air interface standards promulgated by the 3rd Generation Partnership Project 2 (3GPP2) as part of the CDMA2000 family of standards and employ multiple access techniques such as Code Division Multiple Access (CDMA) to provide broadband Internet access to mobile subscribers.
  • 3GPP2 3rd Generation Partnership Project 2
  • CDMA Code Division Multiple Access
  • communication system 100 may support Long Term Evolution (LTE), which is a project within the 3GPP2 to improve the Universal Mobile Telecommunications System (UMTS) mobile phone standard based primarily on a Wideband CDMA (W-CDMA) air interface.
  • LTE Long Term Evolution
  • UMTS Universal Mobile Telecommunications System
  • W-CDMA Wideband CDMA
  • Communication system 100 may also support the WiMAX standard associated with the WiMAX forum.
  • These are merely exemplary protocols, and communication system 100 is not limited to these examples.
  • the actual communications protocol(s) employed by communication system 100 will depend on the specific application and the overall design constraints imposed on the system. The various techniques presented throughout this disclosure are equally applicable to any combination of heterogeneous or homogeneous communication protocols.
  • FIG. 2 is a conceptual block diagram illustrating an example of one of the access terminals of FIG. 1.
  • Access terminal 104 includes a processing system 202 which is capable of communication with a receiver 206 and transmitter 208 through a bus 204 or other structures or devices. It should be understood that communication means other than busses can be utilized with the disclosed configurations.
  • Processing system 202 can generate audio, video, multimedia, and/or other types of data to be provided to transmitter 208 for communication. In addition, audio, video, multimedia, and/or other types of data can be received at receiver 206, and processed by processing system 202.
  • Processing system 202 may include a general purpose processor and volatile or non- volatile memory for storing data and instructions for software programs.
  • the software programs may be stored in memory 210, may be used by processing system 202 to control and manage access to the various networks, as well as provide other communication and processing functions.
  • the software programs may also provide an interface to processing system 202 for various user interface devices, such as a display 212 and a keypad 214.
  • Processing system 202 may also include a digital signal processor (DSP) with an embedded software layer to offload various signal processing functions, such as convolutional encoding, modulation and spread-spectrum processing.
  • DSP digital signal processor
  • the DSP may also perform encoder functions to support telephony applications.
  • access terminal 104 is typically responsible for estimating the forward link pilot channel's carrier to interference ratio (C/I), and for transforming that measurement into a feedback channel sent to access network 102.
  • the feedback channel is typically in the form of a data rate control (DRC) channel.
  • DRC data rate control
  • the DRC channel is then subsequently demodulated at access network 102 and fed into a scheduler.
  • access network 102 transmits to access terminal 104, access network 102 transmits the forward link waveform with the packet type desired by access terminal 104, as indicated by the DRC channel sent by access terminal 104.
  • DRC 13 typically includes 3136 modulation symbols, and 4 interlaces for a hybrid automatic repeat request (H-ARQ) scheme. Further, for EV-DO revision A, DRC 13 corresponds to packets with the largest number of modulation symbols, and with 4 interlaces.
  • H-ARQ hybrid automatic repeat request
  • an access terminal may use a fixed scaling at each point of its processing, where the fixed scaling encompasses the entire dynamic range with acceptable quantization noise as desired by a system designer.
  • a backend RAM (not shown) for such an access terminal can thus be sized at M S XN HARQ XS BW XM C X2, where Ms represents the number of modulated symbols to store, NHARQ represents the number of interlaces, SB W represents the bit width per phase of the symbol, and Mc represents the number of simultaneous carriers (e.g., 1 in EV-DO revision A).
  • Ms represents the number of modulated symbols to store
  • NHARQ represents the number of interlaces
  • SB W represents the bit width per phase of the symbol
  • Mc represents the number of simultaneous carriers (e.g., 1 in EV-DO revision A).
  • the expected signal to interference-plus-noise ratio (SINR) needed to support the wide variety of packet formats typically spans a wide range (e.g., from -1 IdB to > 19.5 dB).
  • SINR signal to interference-plus-noise ratio
  • FIG. 3 is a conceptual block diagram illustrating an exemplary receiver system with a RAKE receiver, for performing variable scaling and C/I saturation.
  • Receiver system 300 includes a RAKE receiver 302, variable scale selection and C/I saturation (VSS C/I) module 304.
  • Receiver system 300 may further include a multiplier 306.
  • RAKE receiver 302 can receive an input signal and output a demodulated signal.
  • the demodulated signal can be multiplied with output from VSS C/I module 306, thereby scaling the demodulated signal.
  • Output from multiplier 306 can be a demodulated signal corresponding to the floating point value of the input signal.
  • receiver 206 of FIG. 2 can be seen to correspond with RAKE receiver 302, or with receiver system 300.
  • VSS C/I module 304 and multiplier 306 can be included in receiver 206, or can be implemented in another part of access terminal 102, such as processing system 202.
  • Receiver system 300 may process a properly modulated and filtered forward link waveform, to recover the original stream of information bits. For example, receiver system 300 can begin its processing with a stream of offset two's complement receiver samples and can produce decoded bits to processing system 202, as necessary. As noted above, when access terminal 104 receives a packet from the access network 102, access terminal 104 knows apriori the packet format that it will receive.
  • receiver system 300 does not use fixed scaling to process the input signal.
  • receiver system 300 may be preferably configured to use less bits (e.g., 8-10 bits per phase) than a fixed scaling system (e.g., 16 bits per phase).
  • the memory requirement for receiver system 300 is reduced by resizing the number of bits per phase.
  • the backend RAM can be resized from 16 bits per I and Q phase to 8 to 10 bits per phase in memory 210. It should be noted that the resized bits do not necessarily have to reside in the backend RAM, but can reside in another portion of memory 210. However, for purposes of this example, discussion is provided with reference to a backend RAM.
  • Reducing the size of the backend RAM may typically limit the dynamic range of the demodulated symbol.
  • a fixed scaling system will likely not result in acceptable performance spanning across all candidate packet formats. Therefore, instead of fixed scaling, the demodulated signal can be variably adjusted, to optimize the amount of storage in the backend RAM.
  • variable gain can be applied to the symbols, which are then stored in the backend RAM, by using a DRC dependent scaling system.
  • the final symbol can be biased to a lower point, without introducing excessive quantization noise.
  • the variable bias point can reduce the dynamic range requirement as a function of modulation format, where the modulation format information is provided by the DRC channel.
  • the variable bias point can be selected using VSS C/I module 304 of FIG. 3.
  • the acceptable bias points can be determined for symbols in the backend RAM based on quantization noise.
  • Such determination of acceptable bias points can be performed by simulating the various DRCs and receiver types over a wide SINR range.
  • bias points associated with negligible quantization noise are preferably selected.
  • bias points can be considered in the range from 256 to 1/16 I or /N t , wherein I 0 ZN t represents the measurement of the total signal to total noise ratio as measured at receiving system 300, in steps of decreasing powers of 2.
  • a C/I cap on SINR for the communication signal is determined, to indicate over what range of SINR the bias point is acceptable before performance degrades (e.g., what range of SINR values meet a performance criteria). The determination of a C/I cap will be described in greater detail below.
  • a bias point can be applied to the input signal. With reference to FIG. 3, the bias can be applied to the input signal by multiplying the demodulated signal from RAKE receiver 302 with the output of VSS C/I module 304, using multiplier 306.
  • scaling of the pilot phase estimate can be used. Due to the wide dynamic range that receiver system 300 can support (e.g., C/I can vary from -15dB to 23dB), the pilot phase estimate can be appropriately scaled such that the final scaling on the demodulated symbol lies within an acceptable range for I or /N t .
  • Symbol demodulation may be accomplished by taking the projection of the data symbol on the pilot phase estimate vector provided.
  • a receiver extracts both the inphase and quadrature phase components of the demodulated symbol.
  • the inphase component can be computed using the complex dot product as follows:
  • quadrature phase component can be computed using the complex cross product as follows:
  • Di and D Q are the real and imaginary parts of the data symbol, and I and Q are the real and imaginary parts of the demodulated symbol, respectively.
  • a cap on SINR for the communication signal is determined, to indicate over what range of SINR the bias point is acceptable before performance degrades. This cap can be determined by VSS C/I module 304.
  • Each DRC typically has a wide range of gain values with acceptable performance.
  • certain modulation format types which correspond with certain
  • DRCs are more sensitive to demodulated symbol saturation.
  • the effects of symbol saturation at high SINR can be severe for higher modulation formats.
  • the packet error rate (PER) tends to increase as SINR increases.
  • a per packet C/I cap may be applied to ensure that symbol saturation is kept at a level such that performance of receiver system 300 is not compromised.
  • the C/I cap may be chosen high enough so that if a packet format had a counterpart spanning a fewer number of slots (i.e., if the bits per packet and modulation formats are the same with the number of slots being different), the packet can decode early at sufficiently high SINR.
  • the C/I cap value is used to cap the C/I estimate, which is obtained from the DRC. In other words, once a C/I cap value is determined, the C/I estimate is compared with the C/I cap value. If the C/I estimate is higher than the C/I cap value, the C/I estimate can be reduced to equal the C/I cap value.
  • access terminal 104 can estimate the C/I of the received signal, and variably bias this demodulated symbol based on the C/I estimate.
  • the scaling would be sensitive to variance of the C/I estimate.
  • the C/I cap can be determined based on a second order statistic of the received signal or the demodulated symbol.
  • the resultant signal is at the determined bias along with the effective C/I estimate, which is at the determined C/I cap value if the original C/I estimate is higher than the C/I cap value.
  • the demodulated symbol corresponds with the real floating point value of the input signal, and quantization and saturation effects are seen to be improved with a reduced number of bits per phase.
  • the backend RAM can be resized to any number of bits per phase.
  • backend RAM can be resized to 8 or 10 bits per phase.
  • Simulations performed on an 8, 9 or 10 bit backend RAM can be used to determine quantization noise performance for the backend RAMs of other bit sizes. For saturation effects, performance for the backend RAMs of other bit sizes can be inferred from the simulation results.
  • FIG. 4 is a conceptual block diagram illustrating an exemplary receiver system, with an equalizer filter, for performing variable scaling and C/I saturation.
  • Receiver system 400 includes equalizer filter 402, variable scale selection and C/I saturation (VSS C/I) module 404.
  • Receiver system 400 may further include a multiplier 406.
  • Equalizer filter 402 can receive an input signal and output an equalized signal. The equalized signal can be multiplied with output from VSS C/I module 406, thereby scaling the equalized signal.
  • Output from multiplier 306 can be an equalized signal corresponding to the floating point value of the input signal.
  • receiver 206 of FIG. 2 can be seen to correspond with equalizer filter 402, or with receiver system 400.
  • VSS C/I module 404 and multiplier 406 can be included in receiver 206, or can be implemented in another part of access terminal 102, such as processing system 202.
  • Receiver system 400 can scale an input signal and apply a C/I cap to the input signal. Receiver system 400 can perform such scaling and capping in a manner similar to that described above with reference to FIG. 3. However, instead of demodulating the signal with RAKE receiver 302, receiver system 400 equalizes the input signal using equalizer filter 402.
  • equalizer filter 402 typically operates in the moderate to high SINR region. As such, even with the DRC dependent scaling, saturation effects typically cause the packet error rate (PER) to increase at high SINR.
  • the C/I cap which can depend on the DRC, can be applied to the C/I estimate. Since this may affect performance of receiver system 400, the C/I cap values can be chosen to be much higher than the 1% PER point.
  • FIG. 5 is a flowchart illustrating an exemplary operation of processing of a communication signal.
  • a bias point for the communication signal is determined based on a quality measurement of the communication signal.
  • the quality measurement has a carrier-to-interference (C/I) estimate associated therewith.
  • C/I carrier-to-interference
  • a C/I cap is determined for the communication signal using the C/I estimate.
  • the C/I cap is for capping a signal to interference-plus-noise ratio (SINR) of the communication signal.
  • SINR signal to interference-plus-noise ratio
  • FIG. 6 is a conceptual block diagram illustrating an example of the functionality of a device for processing of a communication signal.
  • Device 600 includes a module 602 for determining a bias point for the communication signal based on a quality measurement of the communication signal. The quality measurement has a carrier-to- interference (C/I) estimate associated therewith.
  • Device 600 further includes a module 604 for determining a C/I cap for the communication signal using the C/I estimate.
  • the C/I cap is configured to cap a signal to interference-plus-noise ratio (SINR) of the communication signal.
  • SINR signal to interference-plus-noise ratio
  • device 600 includes a module 606 for processing the communication signal using the determined bias point and the determined C/I cap.
  • processing system 202 may be implemented using software, hardware, or a combination of both.
  • processing system 202 may be implemented with one or more processors.
  • a processor may be a general- purpose microprocessor, a microcontroller, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic device (PLD), a controller, a state machine, gated logic, discrete hardware components, or any other suitable device that can perform calculations or other manipulations of information.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • PLD programmable logic device
  • controller a state machine, gated logic, discrete hardware components, or any other suitable device that can perform calculations or other manipulations of information.
  • Processing system 202 may also include one or more machine-readable media for storing software.
  • Software shall be construed broadly to mean instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Instructions may include code (e.g., in source code format, binary code format, executable code format, or any other suitable format of code).
  • Machine-readable media may include storage integrated into a processor, such as might be the case with an ASIC.
  • Machine -readable media may also include storage external to a processor, such as a random access memory (RAM), a flash memory, a read only memory (ROM), a programmable read-only memory (PROM), an erasable PROM (EPROM), registers, a hard disk, a removable disk, a CD-ROM, a DVD, or any other suitable storage device.
  • RAM random access memory
  • ROM read only memory
  • PROM erasable PROM
  • registers a hard disk, a removable disk, a CD-ROM, a DVD, or any other suitable storage device.
  • machine-readable media may include a transmission line or a carrier wave that encodes a data signal.
  • a machine-readable medium is a computer-readable medium encoded or stored with instructions and is a computing element, which defines structural and functional interrelationships between the instructions and the rest of the system, which permit the instructions' functionality to be realized. Instructions may be executable, for example, by an access terminal or a processing system. Instructions can be, for example, a computer program including code. A machine-readable medium may comprise one or more media. [0051] Those of skill in the art would appreciate that the various illustrative blocks, modules, elements, components, methods, and algorithms described herein may be implemented as electronic hardware, computer software, or combinations of both.
  • each of the rake receiver, variable scale selection and C/I saturation (VSS C/I) module, multiplier, and equalizer filter may be implemented as electronic hardware, computer software, or combinations of both.
  • VSS C/I variable scale selection and C/I saturation
  • various illustrative blocks, modules, elements, components, methods, and algorithms have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application.
  • various components and blocks may be arranged differently (e.g., arranged in a different order, or partitioned in a different way) all without departing from the scope of the subject technology.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Noise Elimination (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

Un terminal d'accès pour traiter un signal de communication comprend un récepteur. Le récepteur est configuré pour déterminer un point de polarisation pour le signal de communication sur la base d'une mesure de qualité du signal de communication, une estimation de rapport porteuse/interférence (C/I) étant associée à la mesure de qualité. Le récepteur est en outre configuré pour déterminer un plafond C/I pour le signal de communication en utilisant l'estimation C/I, le plafond C/I étant configuré pour plafonner un signal au rapport interférence plus bruit (SINR) du signal de communication. De plus, le récepteur est configuré pour traiter le signal de communication en utilisant le point de polarisation et le plafond C/I déterminé. Un procédé de traitement d'un signal de communication est également proposé.
PCT/US2008/087644 2007-12-21 2008-12-19 Procédé et appareil de traitement d'un signal de communication WO2009086080A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020107016007A KR101134722B1 (ko) 2007-12-21 2008-12-19 측정된 ｃ/ｉ의 변조 포맷에 따른 디지털 수신 신호의 스케일링과 클리핑
JP2010539867A JP5378405B2 (ja) 2007-12-21 2008-12-19 通信信号を処理するための方法および装置
CN200880122286.3A CN101904128B (zh) 2007-12-21 2008-12-19 根据c/i调制格式缩放和限制数字接收信号的方法和装置

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/962,655 2007-12-21
US11/962,655 US8073076B2 (en) 2007-12-21 2007-12-21 Method and apparatus for processing a communication signal
EP08006410A EP2091170B1 (fr) 2007-12-21 2008-03-31 Mise à l'échelle et écrêtage d'un signal reçu digital selon la modulation ou du rapport porteuse/interférence mesuré
EP08006410.8 2008-03-31

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WO2009086080A3 WO2009086080A3 (fr) 2009-09-11

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040076184A1 (en) * 2002-10-22 2004-04-22 Eitan Tene Method to reduce the number of bits per soft bit
US20040081259A1 (en) * 2002-10-24 2004-04-29 Gerhard Ammer Soft sample scaling in a turbo decoder
US20040179583A1 (en) * 2003-03-13 2004-09-16 Gibong Jeong Method and apparatus for decoder input scaling based on interference estimation in CDMA
US20070036246A1 (en) * 2005-08-12 2007-02-15 Broadcom Corporation Methods and systems for soft-bit demapping
GB2434948A (en) * 2006-02-03 2007-08-08 Motorola Inc LLR calculation with quantization of values which are scaled depending on SNR.

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040076184A1 (en) * 2002-10-22 2004-04-22 Eitan Tene Method to reduce the number of bits per soft bit
US20040081259A1 (en) * 2002-10-24 2004-04-29 Gerhard Ammer Soft sample scaling in a turbo decoder
US20040179583A1 (en) * 2003-03-13 2004-09-16 Gibong Jeong Method and apparatus for decoder input scaling based on interference estimation in CDMA
US20070036246A1 (en) * 2005-08-12 2007-02-15 Broadcom Corporation Methods and systems for soft-bit demapping
GB2434948A (en) * 2006-02-03 2007-08-08 Motorola Inc LLR calculation with quantization of values which are scaled depending on SNR.

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