WO2009077340A1 - Viterbi decoder - Google Patents

Viterbi decoder Download PDF

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Publication number
WO2009077340A1
WO2009077340A1 PCT/EP2008/066779 EP2008066779W WO2009077340A1 WO 2009077340 A1 WO2009077340 A1 WO 2009077340A1 EP 2008066779 W EP2008066779 W EP 2008066779W WO 2009077340 A1 WO2009077340 A1 WO 2009077340A1
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WIPO (PCT)
Prior art keywords
operand
bits
bit
sequence
replacing
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PCT/EP2008/066779
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French (fr)
Inventor
Steve Felix
Graham Cunningham
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Icera Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Priority to GB1010462.8A priority Critical patent/GB2467885B/en
Publication of WO2009077340A1 publication Critical patent/WO2009077340A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4161—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4161—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management
    • H03M13/4169—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management using traceback
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms

Definitions

  • the present invention relates to a Viterbi decoder.
  • Viterbi decoding is a decoding technique for decoding convolutional codes which process incoming bits in streams.
  • a feature of such codes is that the encoding of any bit is strongly influenced by the bits that preceded it (that is, the memory of past bits).
  • a convolutional decoder takes into account such memory when trying to estimate the most likely sequence of data that produced a received sequence of code bits.
  • the Viterbi decoding algorithm compares, at each bit interval, the actual received code bits with the code bits that might have been generated for each possible memory state transition.
  • the algorithm consists of a forward pass through a trellis decoder which provides a relatively small number of candidate possible sequences. This is followed by a trace-back stage to calculate the most likely decoded symbol. In this context, each symbol represents only one uncoded bit.
  • Viterbi decoding There are many dedicated hardware solutions for Viterbi decoding. As an alternative, it is known to implement a software solution where a processor executes instructions for accelerating algorithms. The advantage of these is that they represent a small incremental hardware cost, sharing memory and register infrastructure for storing and fetching operands etc. that the processor already utilises.
  • a method of decoding a stream of encoded bits received via a transmission channel to produce decoded bits comprising: storing a first operand comprising a sequence of bits output from a trace- back execution unit; storing a second operand comprising a sequence of history bits generated by a forward trellis iteration in the Viterbi decoder; generating a result operand by using a set of bits of the first operand to select a bit from the second operand, and replacing a bit of the first operand with the selected bit from the second operand, wherein a sequence of decoded bits is produced by carrying out the steps of using and replacing multiple times.
  • Another aspect of the invention provides a method of processing encoded bits received via a transmission channel, the method comprising: executing an instruction in a processor, the instruction defining a first register holding a first operand, a second register holding a second operand and a destination register for holding a result, wherein execution of the instruction comprising: storing in the first register a first operand comprising a sequence of bits output from a trace-back execution unit; storing in the second register a second operand comprising a sequence of history bits generated by a forward trellis iteration in the Viterbi decoder; and generating a bit of a result operand to be held in the destination register by using a set of bits of the first operand to select a bit from the second operand and replacing a bit of the first operand with the selected bit from the second operand.
  • the instruction is executed multiple times. Each time a different history vector is used as input and one more (decoded) bit is shifted into the result operand.
  • a further aspect of the invention provides an execution unit for executing a Viterbi trace-back instruction, the execution unit comprising: a store holding a first operand comprising a sequence of bits output from the execution unit; a second store holding a second operand comprising a sequence of history bits generated by a forward trellis iteration in a Viterbi decoder; a destination store for holding a result operand; selection means for selecting a bit from the second operand using a set of bits from the first operand; and replacement means for replacing a bit of the first operand with the selected bit from the second operand.
  • a still further aspect of the invention provides a Viterbi decoder which uses an execution unit as defined hereinabove, with a forward trellis iteration stage.
  • Figure 1 is a schematic block diagram showing a Viterbi decoder
  • FIG. 2 is a schematic diagram showing a Viterbi trace-back execution unit.
  • a highly simplified schematic diagram of a Viterbi decoder is shown in Figure 1.
  • An incoming stream of received bits is supplied to a forward trellis decode stage 4 which operates on a p-state vector per decoded bit.
  • the forward trellis stage 4 generates each iteration a vector of history bits which are stored to a memory 6.
  • the full sequence of history vectors expresses all of the candidate sequences.
  • the history vectors provide as many candidate references as there are states.
  • the history bits are supplied to a trace-back stage 8 which is described in more detail in the following and which produces a stream of decoded bits.
  • the trace- back stage 8 implements an instruction which is executed by a processor in which the Viterbi decoder is provided.
  • the Viterbi trace-back instruction is a single-cycle register-to-register processor instruction designed to accelerate the trace-back phase of the Viterbi algorithm.
  • the instruction processes 64-bit operands, but it is scalable in that it can process a N-bit history vector in each cycle, taking two N-bit operands and generating a single N-bit result, where n is typically the width of the processor's data path.
  • Figure 2 illustrates the trace-back stage 8 in more detail.
  • a first store 10 holds a first operand SRCO.
  • the second store 12 receives a second operand SRC1 which is a vector of history bits.
  • a third store 14 holds a result operand.
  • the first operand is loaded from the result operand at the end of each cycle of operation of the trace-back stage. Initially, it can be loaded with "don't care" states.
  • the outputs of the second store 12 are supplied to a multiplexer 16 which is controlled by a set of bits from the first operand SRCO, in this case bits 0:5. Based on these bits, the multiplexer 16 selects one of the 64 input bits and supplies it to a shift unit 18.
  • the shift unit 18 shifts the bits of the first operand SRCO left by one bit and places the selected bit at bit position zero to generate a 64 bit result operand.
  • the instruction is executed 64 times to generate a 64-bit set of decoded bits. For example, this could be expressed in software by placing the instruction in a 'for' loop.
  • results are saved every 64 traceback iterations, using software to do this.
  • Outputting the results 64-bits at a time using a normal "store" instruction is highly flexible and efficient since it is only necessary every 64 iterations.
  • bits of the first operand which are used to control the multiplexer 16 are the least significant M bits, where N is 2 M .
  • bits 6 and 7 of the bit sequence in the first store 10 should be used to determine which 64 bits of each 256 bit history vector should be fetched and supplied to the second store 12. In this way, the Viterbi trace-back instruction can be used on 256 state convolutional code data.
  • the described embodiments of the present invention provide a significantly improved Viterbi trace-back instruction which allows an entire N-bit history vector to be processed in a single cycle, i.e. each cycle gives you one new decoded bit. Moreover, the hardware cost of the dedicated logic is very small rendering this a particularly area efficient solution to Viterbi trace-back processing.

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  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Artificial Intelligence (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)

Abstract

A method of decoding a stream of encoded bits received via a transmission channel to produce decoded bits. The method comprises: storing a first operand comprising a sequence of bits output from a trace-back execution unit; storing a second operand comprising a sequence of history bits generated by a forward trellis iteration in the Viterbi decoder; generating a result operand by using a set of bits of the first operand to select a bit from the second operand, and replacing a bit of the first operand with the selected bit from the second operand, wherein a sequence of decoded bits is produced by carrying out the steps of using and replacing multiple times.

Description

VITERBI DECODER
The present invention relates to a Viterbi decoder.
Many communications standards make use of the Viterbi forward error correction (FEC) algorithm for coping with transmission errors which arise when a stream of encoded bits is sent from a transmitter to a receiver via a transmission channel that is capable of introducing errors. This can be particularly the case for wireless communications. Viterbi decoding is a decoding technique for decoding convolutional codes which process incoming bits in streams. A feature of such codes is that the encoding of any bit is strongly influenced by the bits that preceded it (that is, the memory of past bits). As is well known, a convolutional decoder takes into account such memory when trying to estimate the most likely sequence of data that produced a received sequence of code bits. The Viterbi decoding algorithm compares, at each bit interval, the actual received code bits with the code bits that might have been generated for each possible memory state transition. The algorithm consists of a forward pass through a trellis decoder which provides a relatively small number of candidate possible sequences. This is followed by a trace-back stage to calculate the most likely decoded symbol. In this context, each symbol represents only one uncoded bit.
It is known to accelerate the forward pass through the trellis decoder when the Viterbi algorithm is implemented using dedicated hardware or configurable add- compare-select (ACS) units or instructions. In this way it is possible to optimise the forward pass to the point where bits can be handled in a relatively small number of cycles, possibly as few as four cycles for a single 64-state trellis iteration. At this point, the trace-back stage can become the limiting factor in the performance of the Viterbi algorithm.
There are many dedicated hardware solutions for Viterbi decoding. As an alternative, it is known to implement a software solution where a processor executes instructions for accelerating algorithms. The advantage of these is that they represent a small incremental hardware cost, sharing memory and register infrastructure for storing and fetching operands etc. that the processor already utilises.
In addition to instructions which exist for accelerating the forward trellis decoder Viterbi algorithm mentioned above, there are a number of microprocessor executed instructions which aim to accelerate Viterbi trace-back execution. These include special register-to-register shift instructions or use embedded state bits to store history information to allow trace-back. An example is shown in section
2.2.2.9 of the StarCore DSP manual. See http://vww.cs.virginia.edu/~ig9h/photos/vpo- notes/down loads/M NSC140CORE.pdf.
It is an aim of the present invention to provide an improved instruction for a Viterbi trace-back operation.
According to one aspect of the present invention there is provided a method of decoding a stream of encoded bits received via a transmission channel to produce decoded bits, the method comprising: storing a first operand comprising a sequence of bits output from a trace- back execution unit; storing a second operand comprising a sequence of history bits generated by a forward trellis iteration in the Viterbi decoder; generating a result operand by using a set of bits of the first operand to select a bit from the second operand, and replacing a bit of the first operand with the selected bit from the second operand, wherein a sequence of decoded bits is produced by carrying out the steps of using and replacing multiple times.
Another aspect of the invention provides a method of processing encoded bits received via a transmission channel, the method comprising: executing an instruction in a processor, the instruction defining a first register holding a first operand, a second register holding a second operand and a destination register for holding a result, wherein execution of the instruction comprising: storing in the first register a first operand comprising a sequence of bits output from a trace-back execution unit; storing in the second register a second operand comprising a sequence of history bits generated by a forward trellis iteration in the Viterbi decoder; and generating a bit of a result operand to be held in the destination register by using a set of bits of the first operand to select a bit from the second operand and replacing a bit of the first operand with the selected bit from the second operand.
To generate a set of decoded bits, the instruction is executed multiple times. Each time a different history vector is used as input and one more (decoded) bit is shifted into the result operand.
A further aspect of the invention provides an execution unit for executing a Viterbi trace-back instruction, the execution unit comprising: a store holding a first operand comprising a sequence of bits output from the execution unit; a second store holding a second operand comprising a sequence of history bits generated by a forward trellis iteration in a Viterbi decoder; a destination store for holding a result operand; selection means for selecting a bit from the second operand using a set of bits from the first operand; and replacement means for replacing a bit of the first operand with the selected bit from the second operand.
A still further aspect of the invention provides a Viterbi decoder which uses an execution unit as defined hereinabove, with a forward trellis iteration stage.
For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made by way of example to the accompanying drawings, in which:
Figure 1 is a schematic block diagram showing a Viterbi decoder; and
Figure 2 is a schematic diagram showing a Viterbi trace-back execution unit. A highly simplified schematic diagram of a Viterbi decoder is shown in Figure 1. An incoming stream of received bits is supplied to a forward trellis decode stage 4 which operates on a p-state vector per decoded bit. Typically, the vector is a 64 state vector (k=7), where k is the constraint length. The forward trellis stage 4 generates each iteration a vector of history bits which are stored to a memory 6. The full sequence of history vectors expresses all of the candidate sequences. The history vectors provide as many candidate references as there are states.
The history bits are supplied to a trace-back stage 8 which is described in more detail in the following and which produces a stream of decoded bits. The trace- back stage 8 implements an instruction which is executed by a processor in which the Viterbi decoder is provided. The Viterbi trace-back instruction is a single-cycle register-to-register processor instruction designed to accelerate the trace-back phase of the Viterbi algorithm. In the described example, the instruction processes 64-bit operands, but it is scalable in that it can process a N-bit history vector in each cycle, taking two N-bit operands and generating a single N-bit result, where n is typically the width of the processor's data path.
It is designed to accelerate 64-state Viterbi algorithms as these have a 64-state (2k"1) trellis and consequently history vectors precisely 64 bits long. These are commonly used in wireless communications standards, but the design is scalable to a wider range of constraint lengths. Also, as described in the following, a 64 bit instruction can be used to accelerate the back-trace operation of a 256-state (k=9) trellis.
Figure 2 illustrates the trace-back stage 8 in more detail. A first store 10 holds a first operand SRCO. The second store 12 receives a second operand SRC1 which is a vector of history bits. A third store 14 holds a result operand. The first operand is loaded from the result operand at the end of each cycle of operation of the trace-back stage. Initially, it can be loaded with "don't care" states.
The outputs of the second store 12 are supplied to a multiplexer 16 which is controlled by a set of bits from the first operand SRCO, in this case bits 0:5. Based on these bits, the multiplexer 16 selects one of the 64 input bits and supplies it to a shift unit 18. The shift unit 18 shifts the bits of the first operand SRCO left by one bit and places the selected bit at bit position zero to generate a 64 bit result operand. The instruction is executed 64 times to generate a 64-bit set of decoded bits. For example, this could be expressed in software by placing the instruction in a 'for' loop.
The results are saved every 64 traceback iterations, using software to do this. Outputting the results 64-bits at a time using a normal "store" instruction is highly flexible and efficient since it is only necessary every 64 iterations.
The bits of the first operand which are used to control the multiplexer 16 are the least significant M bits, where N is 2M.
The Viterbi trace-back instructions can be used in conjunction with an extra Iog_base2(64)=6 iterations by the forward trellis stage 4 with the input data set to zero to ensure that the largest state metric is the last one. This prevents the need to search back and find the largest previous state metric to start the trace-back from.
For a 256 state convolutional code (of the type used in code division multiple access wireless transmission), bits 6 and 7 of the bit sequence in the first store 10 should be used to determine which 64 bits of each 256 bit history vector should be fetched and supplied to the second store 12. In this way, the Viterbi trace-back instruction can be used on 256 state convolutional code data.
The described embodiments of the present invention provide a significantly improved Viterbi trace-back instruction which allows an entire N-bit history vector to be processed in a single cycle, i.e. each cycle gives you one new decoded bit. Moreover, the hardware cost of the dedicated logic is very small rendering this a particularly area efficient solution to Viterbi trace-back processing.

Claims

CLAIMS:
1. A method of decoding a stream of encoded bits received via a transmission channel to produce decoded bits, the method comprising: storing a first operand comprising a sequence of bits output from a trace- back execution unit; storing a second operand comprising a sequence of history bits generated by a forward trellis iteration in the Viterbi decoder; generating a result operand by using a set of bits of the first operand to select a bit from the second operand, and replacing a bit of the first operand with the selected bit from the second operand, wherein a sequence of decoded bits is produced by carrying out the steps of using and replacing multiple times.
2. A method according to claimi , wherein the step of replacing the bit comprises removing a bit from a first end position in the sequence and inserting said selected bit at a last end position in the sequence.
3. A method according to claim 1 , wherein the number of bits in each sequence of the first and second operand is the same and matches the number of bits in the result operand.
4. A method according to claim 2, wherein the number of bits is 64.
5. A method according to claim 1 , for decoding a stream of encoded bits using a 256 state Viterbi decoder wherein the sequence of history bits is selected from a
256 bit sequence using a second set of bits from the first operand.
6. A method according to claim 1 , wherein the set of bits comprise the least significant M bits where N, the number of bits in the operand, equals 2M.
7. A method according to claim 5, wherein the set of bits are bits 6:7.
8. A method of processing encoded bits received via a transmission channel, the method comprising: executing an instruction in a processor, the instruction defining a first register holding a first operand, a second register holding a second operand and a destination register for holding a result, wherein execution of the instruction comprising: storing in the first register a first operand comprising a sequence of bits output from a trace-back execution unit; storing in the second register a second operand comprising a sequence of history bits generated by a forward trellis iteration in the Viterbi decoder; and generating a bit of a result operand to be held in the destination register by using a set of bits of the first operand to select a bit from the second operand and replacing a bit of the first operand with the selected bit from the second operand.
9. A method according to claim 8, wherein the step of replacing the bits comprises removing a bit from a first end position in the sequence and inserting said selected bit at a last end position in the sequence.
10. A method according to claim 8, comprising the step of selecting from a number of history bits generated by the forward trellis iteration said sequence using a second set of bits from the first operand.
11. An execution unit for executing a Viterbi trace-back instruction, the execution unit comprising: a store holding a first operand comprising a sequence of bits output from the execution unit; a second store holding a second operand comprising a sequence of history bits generated by a forward trellis iteration in a Viterbi decoder; a destination store for holding a result operand; selection means for selecting a bit from the second operand using a set of bits from the first operand; and replacement means for replacing a bit of the first operand with the selected bit from the second operand.
12. A unit according to claim 11 , wherein the selection means comprises a multiplexer connected to the second store and controllable by said set of bits from the first operand.
13. A unit according to claim 11 , wherein the replacement means comprises a shift unit operable to remove a bit from a first end position in the sequence and insert said selected bit at a last end position in the sequence thereby to generate said result operand.
14. A Viterbi decoder comprising an execution unit according to any of claims 11 , 12, or 13 and a forward trellis decode stage.
PCT/EP2008/066779 2007-12-14 2008-12-04 Viterbi decoder WO2009077340A1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0409205A2 (en) * 1989-07-18 1991-01-23 Sony Corporation Viterbi decoder
WO2007021057A1 (en) * 2005-08-19 2007-02-22 Electronics And Telecommunications Research Institute Viterbi decoder and method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0409205A2 (en) * 1989-07-18 1991-01-23 Sony Corporation Viterbi decoder
WO2007021057A1 (en) * 2005-08-19 2007-02-22 Electronics And Telecommunications Research Institute Viterbi decoder and method thereof

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GB0724418D0 (en) 2008-01-30
TW200935760A (en) 2009-08-16
GB2467885A (en) 2010-08-18
GB2467885B (en) 2012-07-11
GB201010462D0 (en) 2010-08-04

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