200935760 六、發明說明： 【發明所屬气技術領域】 發明領域 本發明有關於一維特比解碼器。 5 【先前技術】 發明背景 才多通爲準利用維特比順向錯誤修正(FEC),來處理 〇 #—串流的經編碼位元經由能夠引進錯誤的-傳送頻道， 從-發送器發送至-接收器時產生之傳送錯誤。這特別是 1〇對於無線通訊的情況下。維特比解碼係用以解碼處理在串 流中進來的位元之迴旋碼的一種解碼技術。這種碼的一個 * 肖徵是任何位元的編料由在其之前的位元(亦即，過去位 、 ⑽記憶體)所強烈影響。如糾皆知地，當嘗試估計產生 1 接收串流的碼位元之最有可能的資料串流時，-趣旋解 15碼器考慮此種記憶體。維特比解碼演算法在每個位元間隔 鬌 k匕較實際接收的碼位元與針對每個可能的記憶體狀態變遷 所可能已產生之碼位元。該演算法由經過提供—相對小數 目的候選可能序狀-交織解碼器的—順向顺成。這是 2〇被—追溯級所跟隨，以計算最可能的經解碼符號。在本= ° 中，每個符號表示僅僅一個未經編碼位元。 已知當該維特比演算法係使用專用硬體或可組配的相 加-比較選擇(ACS)單元錢令來實施時，加速通過該交織 解碼器的該順向。這樣可能使經過能在一相對小數目的週 期中處理位元的點之該順向最佳化，也許對一單―料狀熊 200935760 交織叠代-樣少的四個週期。在此點上，該追溯級能變纟 · 該維特比演算法之效能中的限制因素。 對於維特比解碼有許多專用硬體解決方法。如同—替 代例，已知實施一軟體解決方法，其中一處理器執行用於 5加速决算法之指令。這些方法的優點是它們表示—個小增 量的硬體花費，共享記憶體和暫存器基礎結構來儲存和提 取處理器已利用之運算元等。 除了為加速上述提及之該順向交織解碼器維特比演算 法而存在的指令以外，有一些執行幫助加速維特比追溯執 ❹ 1〇 行的指令之微處理器。這些包括特別的暫存器對暫存器移 位指令，或使用嵌入狀態位元，以儲存歷史資訊來允許追 溯。一實例示於StarCore DSP手冊第2.2.2.9節。參見 Mi£lZtoy_w.CS.virginji^lig£liZEto〇s/vp〇n〇tes/tovnl〇ads/ ’ MNSC140CORE.pdf ° ' 15 【發明内容】 發明概要 本發明對於針對-維特比追溯操作提供一經改良指令 〇 是有幫助的。 根據本發明之-面向，提供有一種解碼經由傳送頻道 20所接收之-串流的編碼位元以產生解碼位元之方法，該方 法包含下列步驟： ~ 儲存一第一運算元，兮笛一運管-h人 〇亥第運异疋包含從—追溯執行 單元輸出之一序列的位元； 儲存-第二運算元，該第二運算元包含於維特比解碼 4 200935760 器中一順向交織疊代所產生之一序列的歷史位元； 藉由使用該第一運算元之一組位元來從該第二運算元 選擇出一位元、以及以來自該第二運算元之該經選擇位元 取代該第一運算元之一位元，而產生一結果運算元，其中 5 一序列的經解碼位元係藉由多次實施該等使用和取代步驟 而產出。 本發明之另一面向提供一種處理經由傳送頻道所接收 之經編碼位元之方法，該方法包含下列步驟： 〇 在一處理器中執行一指令，該指令定義持有一第一運 10 算元之一第一暫存器、持有一第二運算元之一第二暫存 器、以及用以持有一結果之一目的地暫存器，其中執行該 指令之步驟包含： 將包含從一追溯執行單元輸出之一序列的位元之一第 一運算元儲存於該第一暫存器中； 15 將包含藉由維特比解碼器中的一順向交織疊代所產生 之一序列的歷史位元之一第二運算元，儲存於該第二暫存 ® 器中；以及 藉由使用該第一運算元之一組位元來從該第二運算元 選擇一位元，以及以來自該第二運算元之該經選擇位元取 20 代該第一運算元之一位元，來產生將要在該目的地暫存器 中持有的一結果運算元之一位元。 為了產生一組經解碼位元，該指令被多次執行。每次 使用一不同的歷史向量作為輸入，且一或多個（經解碼)位元 係獲移位至該結果運算元中。 200935760 ίο 15 20 本發明之—進—步面向提供—種用. b之執行單元，錢行單元包括· 執仃維特比追溯 —存錯器，其持有包含自^ f 位元之—第一運算元； 订車，出之-序列的 —第二存儲器，其持有包含由一 向交織叠代所產生之—序列的 维特比解碼器中-順 用以持有一結果運糞分+ 兀之—第二運算元； 用以使用來自該第—運算Γ目的地存儲器； 算元選擇-位元之選擇裝置.:之—組位元，從該第二運 用以令來自該第二運算 _ 運算元之-位元之取代裝置。δχ經選擇位元取代該第- 本發明之一更進—弗 使用如同上述所定義之 j供—種維特比解碼器，其 級。 仃早兀、以及一順向交織疊代 圖式簡單說明 為了更了解本發明，以 J0 m 冋樣顯示如何被實踐，參照 現將經由附圖的實例獲做出，其中： 第1圖係顯示一維特比解 幻匕解喝器之-示意方塊圖；以及 =圖係顯示-維特比追溯執行單元之一示意圖。 【實施方式】 較佳實施例之詳細說明 、維特比解碼器之—非常簡單化的示意圖在第工圖中 能曰冑入串机的經接收位元係被供應給操作於- P-狀 .。向ϊ每解碼位S之—順向交織解碼級4。典型地，該向量 © 〇 6 200935760 為一64狀態向量㈣），其中k是限制長度。該順向交織級4 在每個且代產生儲存於—記憶體6中的—向量之歷史位 兀。玄全口p序列之歷史向量表示所有的候選序列。該等歷 史向量和:供跟狀態一樣多的候選參考。 等歷史位元被供應給_追湖級8，該追溯級8在下文 更詳細描述且產出_串流之經解碼位元。該追雜8實施由 提供雜特比解碼器的一處理器所執行之一指令。該維特 比追湖指令係設計來加速該維特比演算法的該追溯相位之 -單週期暫存器對暫存器處理器指令。在該描述的實例 1〇中’該指令處理64位元運算元，但其為可縮放的，其中其 能在，個週期中處理一娜位元歷史向量、取得二個N-位 凡運其元、及產生一置一 1ST y^ ,, 早N-位凡結果，其中n典型地是該處 理器的資料路徑之寬度。 田64狀態維特比演算法具有—⑷狀態(門交織和結 15果地歷史向量綠實為64位元長，這是設計來加速⑷狀態維 特比演算法。這些在無線通訊標準中是被普遍地使用，但 該設計可放大至-更廣泛為的限制長度 。而且’如同下文 所描述，一64位元指令可被用來加速-256-狀態㈣)交織 之該追溯操作。 第2圖f詳細地繪示該追溯級8。-第-存儲器10持有 第運算兀SRC0。第二存儲器㈣收一第二運算 ，其係一向量的歷史位元。-第三存儲器14持有一姓 果運算元。該第—運算元係於操作該追溯級之每個週期： 結束時，自該結果運算錢人。最初，其能以「不關、、主 20 200935760 狀態遭載入。 該第二存儲器12之輸出被供應到多工器16，該多工器 係由來自該第一運算元SRC0之一組位元所控制，此例中為 位元0:5。根據這些位元，該多工器16選擇該等糾輸入位元 5中之一者，以及將其供應至—移位單元18。該移位單元18 將該第一運算元SRC0之該等位元向左移位—位元，以及設 置該經選擇位元至位元位置零，以產生_64位元結果運算 元。該指令係遭執行64次，以產生一64_位元組的經解碼位 元。舉例來說’這可在軟體中藉由設置該指令於一if〇r,迴圈 10 來表示。 該等結果於每個64追溯疊代獲儲存，使用軟體來為 之。使用一普通”儲存”指令來在一次時輸出該等結果64_位 元是非常靈活且有效的’蓋因其僅需要每個64疊代。 用來控制該多工器16的該第一運算元之該等位元為最 15 低最低有效Μ位元，其中N為2M。 該等維特比追溯指令能被用來藉由該順向交織級4以該輸 入資料設定為零，來與一額外log_base2(64)=6個疊代連接， 以確認最大狀態度量是最後一個。這樣避免了回頭搜尋以 及找出作為追溯起始之出最大先前狀態度量的需求。 2〇 針對(在碼分多重存取無線傳送中使用的類型之）一256 狀態迴旋碼’該第一存儲器1〇内之該位元序列的位元6和7 應被用來判定每256位元歷史向量之那些個64位元應被提 取及被供應該第二存儲器12。這樣’該維特比追溯指令可 被使用在256狀態迴旋碼資料上。 200935760 本發明之該等描述的實施例提供一相當程度地經改良 維特比追溯指令，其允許一完整N-位元歷史向量將被在一 單一週期内處理；例如每個週期給你一個新的經解碼位 元。此外，專用邏輯之硬體花費非常小，讓此對維特比追 5 溯處理是一特別領域有效解決方法。 【圖式簡單說明3 第1圖係顯示一維特比解碼器之一示意方塊圖；以及 第2圖係顯示一維特比追溯執行單元之一示意圖。 〇 【主要元件符號說明】 4順向交織解碼級 16 多工器 6記憶體 18移位單元 8 追溯級 SCR0 第一運算元 10 第一存儲器 SCR1 第二運算元 12 第二存儲器 DEST 結果運算元 14 第三存儲器200935760 VI. Description of the Invention: [Technical Field of the Invention] Field of the Invention The present invention relates to a one-dimensional ratio decoder. 5 [Prior Art] Background of the Invention Multi-pass is used to utilize Viterbi Forward Error Correction (FEC) to process 〇#-stream encoded bits via a capable transmit channel, from the transmitter to the sender - A transmission error generated by the receiver. This is especially the case for wireless communication. Viterbi decoding is a decoding technique used to decode the convolutional code of a bit that is coming in the stream. One of the codes of this code is that the coding of any bit is strongly influenced by the bits preceding it (i.e., past bits, (10) memory). As is well known, when attempting to estimate the most probable data stream for a code bit that produces a received stream, the 15-spin 15 code considers such memory. The Viterbi decoding algorithm is at each bit interval 鬌 k 匕 compared to the actual received code bits and the code bits that may have been generated for each possible memory state transition. The algorithm is compliant with the forward-sequence of the candidate-sequence-interleaving decoder that provides the relative-counter number. This is followed by the traceback level to calculate the most likely decoded symbols. In this = °, each symbol represents only one uncoded bit. It is known that when the Viterbi algorithm is implemented using a dedicated hardware or an configurable Add-Compare Selection (ACS) unit, the progression through the interleaving decoder is accelerated. This may optimize the forward direction through points that can process the bits in a relatively small number of cycles, perhaps for a single-material bear 200935760 interleaved-like four cycles. At this point, the traceability level can be changed. • The limiting factor in the performance of the Viterbi algorithm. There are many specialized hardware solutions for Viterbi decoding. As in the alternative, it is known to implement a software solution in which a processor executes instructions for a 5 accelerated algorithm. The advantage of these methods is that they represent a small incremental hardware cost, shared memory and scratchpad infrastructure to store and extract the operands that the processor has utilized. In addition to the instructions that exist to speed up the aforementioned forward interleaving decoder Viterbi calculus, there are a number of microprocessors that execute instructions that help speed up Viterbi's traceability. These include special scratchpad-to-storage shift instructions, or use embedded status bits to store historical information to allow traceback. An example is shown in Section 2.2.2.9 of the StarCore DSP Handbook. See also Mi£lZtoy_w.CS.virginji^lig£liZEto〇s/vp〇n〇tes/tovnl〇ads/ ' MNSC140CORE.pdf ° ' 15 SUMMARY OF THE INVENTION The present invention provides an improvement for the tracking operation of the Viterbi The command 〇 is helpful. According to the invention, there is provided a method of decoding a coded bit received via a transport channel 20 to generate a decoded bit, the method comprising the steps of: ~ storing a first operand, a flute The transport---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- An iterative generation of a sequence of historical bits; selecting a bit from the second operand by using a set of bits of the first operand, and selecting the second operand from the second operand The bit replaces one of the first operand bits to produce a result operand, wherein the 5-sequence of decoded bits is produced by performing the use and replace steps multiple times. Another aspect of the present invention provides a method of processing encoded bits received via a transmission channel, the method comprising the steps of: ??? executing an instruction in a processor that defines a first 10 operator a first register, a second register holding a second operand, and a destination register for holding a result, wherein the step of executing the instruction comprises: including Tracing one of the bits of a sequence of execution unit outputs, the first operand is stored in the first register; 15 will contain a history of a sequence generated by a forward interleaved iteration in the Viterbi decoder a second operand of the bit, stored in the second temporary store; and selecting a bit from the second operand by using a set of bits of the first operand, and from the The selected bit of the second operand takes 20 bits of the first operand to generate one bit of a result operand to be held in the destination register. In order to generate a set of decoded bits, the instruction is executed multiple times. Each time a different history vector is used as an input, and one or more (decoded) bits are shifted into the result operand. 200935760 ίο 15 20 The invention is provided for the purpose of providing - the execution unit of b. The execution unit of b, the money line unit includes · the execution of the Viterbi traceability-storage, which holds the self-containing bits. An operational unit; a subscription-sequence-sequence-second memory that holds a Viterbi decoder containing a sequence generated by a one-way interleaved iteration--for holding a result of the scum + 兀a second operand; used to use the memory from the first operation memory; an operator selection-bit selection device: a group bit from the second operation to cause the second operation _ operation Yuan-bit replacement device. χ 取代 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 使用 使用 使用 使用 使用 使用 使用 使用 使用仃 兀 兀 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 以及 兀 兀 兀 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单 简单A Viterbi solution for the illusion of the illusion - a schematic block diagram; and = diagram display - a diagram of the Viterbi traceability execution unit. [Embodiment] A detailed description of the preferred embodiment, a very simplified schematic of the Viterbi decoder, in the drawing, the received bit system that can be inserted into the stringer is supplied to operate in the -P- shape. . The decoding stage 4 is interleaved with each decoding bit S. Typically, the vector © 〇 6 200935760 is a 64 state vector (four)), where k is the limit length. The forward interleaving stage 4 produces a history bit of the vector stored in the memory 6 at each generation. The history vector of the full-length p-sequence represents all candidate sequences. These historical vectors are: as many candidate references as there are states. The historical bits are supplied to the _ lake level 8, which is described in more detail below and yields the decoded bits of the stream. The tracking 8 implements one of the instructions executed by a processor that provides a hetero-specific decoder. The Viterbi Lake Tracking System is designed to accelerate the traceback phase of the Viterbi algorithm - the single cycle register to the scratchpad processor instructions. In the example of the description, the instruction processes a 64-bit operand, but it is scalable, where it can process a one-bit history vector in one cycle, and obtain two N-bits. The element, and the resulting one is set to 1ST y^, the early N-bit result, where n is typically the width of the data path of the processor. The Field 64 state Viterbi algorithm has a -(4) state (gate interleaving and knot 15 fruit history vector green is 64 bits long, which is designed to speed up the (4) state Viterbi algorithm. These are common in wireless communication standards. Used, but the design can be scaled up to - a wider range of limits. And 'as described below, a 64-bit instruction can be used to speed up the -256-state (four)) interleaving operation. Figure 2 f shows the traceability level 8 in detail. - The first memory 10 holds the first operation SRC0. The second memory (4) receives a second operation, which is a history bit of a vector. - The third memory 14 holds a surrogate element. The first operand is used to operate each cycle of the traceback level: At the end, the money is calculated from the result. Initially, it can be loaded with "No Off," the main 20 200935760 state. The output of the second memory 12 is supplied to the multiplexer 16, which is from a group of the first operand SRC0. The element is controlled, in this case bit 0: 5. According to these bits, the multiplexer 16 selects one of the correct input bits 5 and supplies it to the shift unit 18. The bit unit 18 shifts the bits of the first operand SRC0 to the left-bit, and sets the selected bit to the bit position zero to generate a _64-bit result operand. Execute 64 times to generate a 64_byte decoded bit. For example, 'this can be represented in the software by setting the instruction to an if〇r, loop 10. The results are in each 64 traces the iterations for storage, using software for it. Using a normal "storage" instruction to output the results at one time 64_bits is very flexible and efficient 'caps because it only needs 64 iterations per generation. The bits of the first operand used to control the multiplexer 16 are the lowest 15 least significant significant bits, where N 2M. The Viterbi traceback commands can be used to connect with an additional log_base2(64)=6 iterations by the forward interleaving stage 4 with the input data set to zero to confirm that the maximum state metric is final One. This avoids the need to look back and find out the need for the largest previous state metric as the start of the traceback. 2 〇 for a type of 256 state revolution code used in code division multiple access radio transmissions' Bits 6 and 7 of the sequence of bits in memory 1 should be used to determine which of the 64 bits of each 256-bit history vector should be extracted and supplied to the second memory 12. Thus the Viterbi traceability The instructions can be used on 256 state whirling code data. 200935760 The described embodiments of the present invention provide a relatively improved Viterbi traceback instruction that allows a complete N-bit history vector to be in a single cycle. Internal processing; for example, each cycle gives you a new decoded bit. In addition, the hardware cost of dedicated logic is very small, so that this pair of Viterbi tracking is a special field effective solution. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic block diagram showing one of the Viterbi decoders; and Fig. 2 is a schematic diagram showing one of the one-dimensional tracking execution units. 〇 [Main component symbol description] 4 Forward interleaving decoding stage 16 multiplexer 6 memory 18 shift unit 8 traceback stage SCR0 first operand 10 first memory SCR1 second operand 12 second memory DEST result operand 14 third memory