WO2009075318A1 - Storage device and information re-recording method - Google Patents

Storage device and information re-recording method Download PDF

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Publication number
WO2009075318A1
WO2009075318A1 PCT/JP2008/072491 JP2008072491W WO2009075318A1 WO 2009075318 A1 WO2009075318 A1 WO 2009075318A1 JP 2008072491 W JP2008072491 W JP 2008072491W WO 2009075318 A1 WO2009075318 A1 WO 2009075318A1
Authority
WO
WIPO (PCT)
Prior art keywords
information
value
storage device
vgs
verify process
Prior art date
Application number
PCT/JP2008/072491
Other languages
French (fr)
Japanese (ja)
Inventor
Tomohito Tsushima
Tsunenori Shiimoto
Shuichiro Yasuda
Original Assignee
Sony Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corporation filed Critical Sony Corporation
Priority to KR1020107012474A priority Critical patent/KR101679868B1/en
Priority to US12/745,952 priority patent/US8363447B2/en
Priority to EP20080859874 priority patent/EP2230667A4/en
Priority to CN2008801192942A priority patent/CN101889312B/en
Publication of WO2009075318A1 publication Critical patent/WO2009075318A1/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0064Verifying circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009RRAM elements whose operation depends upon chemical change
    • G11C13/0011RRAM elements whose operation depends upon chemical change comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0069Writing or programming circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0069Writing or programming circuits or methods
    • G11C2013/0071Write using write potential applied to access device gate
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0069Writing or programming circuits or methods
    • G11C2013/0092Write characterized by the shape, e.g. form, length, amplitude of the write pulse
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10Resistive cells; Technology aspects
    • G11C2213/11Metal ion trapping, i.e. using memory material including cavities, pores or spaces in form of tunnels or channels wherein metal ions can be trapped but do not react and form an electro-deposit creating filaments or dendrites
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50Resistive cell structure aspects
    • G11C2213/56Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70Resistive array aspects
    • G11C2213/79Array wherein the access device being a transistor

Abstract

Provided is a storage device which can reduce the number of cycles required for a verify process upon a multi-value recording. The initial value of the potential difference VGS between a gate and a source of a switching transistor upon a verify process is varied in accordance with the resistance value level of the multi-value information. When the write side performs a 3-value recording, if “01” is the information, the initial value VGS01 is set to be smaller than VGS = 1.7V corresponding to the target resistance value level “01”, and if “00” is the information, a value is set to be lower than VGS = 2.2 V corresponding to the target resistance value level “00” and higher than the aforementioned VGS01. This can reduce the number of cycles required for the verify process.
PCT/JP2008/072491 2007-12-12 2008-12-11 Storage device and information re-recording method WO2009075318A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020107012474A KR101679868B1 (en) 2007-12-12 2008-12-11 Storage device and information re-recording method
US12/745,952 US8363447B2 (en) 2007-12-12 2008-12-11 Storage device and information recording and verification method
EP20080859874 EP2230667A4 (en) 2007-12-12 2008-12-11 Storage device and information re-recording method
CN2008801192942A CN101889312B (en) 2007-12-12 2008-12-11 Storage device and information re-recording method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-320580 2007-12-12
JP2007320580A JP5151439B2 (en) 2007-12-12 2007-12-12 Storage device and information re-recording method

Publications (1)

Publication Number Publication Date
WO2009075318A1 true WO2009075318A1 (en) 2009-06-18

Family

ID=40755557

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/072491 WO2009075318A1 (en) 2007-12-12 2008-12-11 Storage device and information re-recording method

Country Status (6)

Country Link
US (1) US8363447B2 (en)
EP (1) EP2230667A4 (en)
JP (1) JP5151439B2 (en)
KR (1) KR101679868B1 (en)
CN (1) CN101889312B (en)
WO (1) WO2009075318A1 (en)

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JP4466738B2 (en) 2008-01-09 2010-05-26 ソニー株式会社 Storage element and storage device
JP5397668B2 (en) * 2008-09-02 2014-01-22 ソニー株式会社 Storage element and storage device
CN102822900B (en) * 2010-03-30 2015-09-30 国际商业机器公司 At least one multi-level phase change memory cell is programmed
US8913444B1 (en) 2011-03-01 2014-12-16 Adesto Technologies Corporation Read operations and circuits for memory devices having programmable elements, including programmable resistance elements
CN103345936B (en) * 2011-04-19 2016-08-03 黑龙江大学 Arbitrarily K value and 8 is worth write circuit and the reading circuit of DRAM
CN102290095B (en) * 2011-04-19 2013-10-30 黑龙江大学 Storage unit circuit for any K-valued and 8-valued DRAM (dynamic random access memory)
US8605531B2 (en) * 2011-06-20 2013-12-10 Intel Corporation Fast verify for phase change memory with switch
JP5858350B2 (en) 2011-09-14 2016-02-10 インテル・コーポレーション Apparatus, method and system
KR102166506B1 (en) * 2012-12-26 2020-10-15 소니 세미컨덕터 솔루션즈 가부시키가이샤 Storage apparatus and method for manufacturing same
KR102030326B1 (en) 2013-01-21 2019-10-10 삼성전자 주식회사 Nonvolatile memory device and driving method thereof
JP6251885B2 (en) * 2013-04-26 2017-12-27 パナソニックIpマネジメント株式会社 Resistance variable nonvolatile memory device and writing method thereof
TWI571872B (en) * 2013-06-21 2017-02-21 旺宏電子股份有限公司 Phase change memory, writing method thereof and reading method thereof
US10727404B1 (en) * 2019-01-23 2020-07-28 International Business Machines Corporation Tunable resistive element
CN113517015A (en) * 2021-04-29 2021-10-19 中国科学院上海微系统与信息技术研究所 Method and device for realizing multilevel storage of storage unit

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JP2005235360A (en) 2004-01-20 2005-09-02 Sony Corp Storage device
JP2007018615A (en) * 2005-07-08 2007-01-25 Sony Corp Storage device and semiconductor device

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US6662263B1 (en) * 2000-03-03 2003-12-09 Multi Level Memory Technology Sectorless flash memory architecture
US7073103B2 (en) * 2002-12-05 2006-07-04 Sandisk Corporation Smart verify for multi-state memories
US7286388B1 (en) * 2005-06-23 2007-10-23 Spansion Llc Resistive memory device with improved data retention
US7289351B1 (en) 2005-06-24 2007-10-30 Spansion Llc Method of programming a resistive memory device
DE602006013935D1 (en) 2006-03-31 2010-06-10 St Microelectronics Srl A method of programming a memory device adapted to minimize the coupling of the floating gates and a memory device
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Non-Patent Citations (1)

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Also Published As

Publication number Publication date
JP2009146480A (en) 2009-07-02
CN101889312B (en) 2013-12-11
CN101889312A (en) 2010-11-17
US20100254178A1 (en) 2010-10-07
EP2230667A4 (en) 2011-01-19
EP2230667A1 (en) 2010-09-22
KR20100097676A (en) 2010-09-03
JP5151439B2 (en) 2013-02-27
US8363447B2 (en) 2013-01-29
KR101679868B1 (en) 2016-11-25

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