WO2009069174A1 - 組込装置及び制御方法 - Google Patents

組込装置及び制御方法 Download PDF

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Publication number
WO2009069174A1
WO2009069174A1 PCT/JP2007/001305 JP2007001305W WO2009069174A1 WO 2009069174 A1 WO2009069174 A1 WO 2009069174A1 JP 2007001305 W JP2007001305 W JP 2007001305W WO 2009069174 A1 WO2009069174 A1 WO 2009069174A1
Authority
WO
WIPO (PCT)
Prior art keywords
rom
reconfiguration
circuit
fpga
data
Prior art date
Application number
PCT/JP2007/001305
Other languages
English (en)
French (fr)
Inventor
Masami Mizu
Noboru Morita
Original Assignee
Fujitsu Limited
Ffc Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited, Ffc Limited filed Critical Fujitsu Limited
Priority to PCT/JP2007/001305 priority Critical patent/WO2009069174A1/ja
Publication of WO2009069174A1 publication Critical patent/WO2009069174A1/ja

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1666—Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17764—Structural details of configuration resources for reliability
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Quality & Reliability (AREA)
  • Computing Systems (AREA)
  • Logic Circuits (AREA)

Abstract

　外部からの回路構成データによって所望の論理回路を書き込むことのできるプログラマブル論理回路と回路構成データを保持するＲＯＭ等を２重化した組込装置において、障害回避制御を簡略化することを課題とする。再構成完了監視固定回路３０４は、データＲＯＭ選択信号３０８により、第１ＲＯＭ３０２を選択してＦＰＧＡ３０１に再構成指示信号３０６を出力し、その後一定時間内にＦＰＧＡ３０１から再構成完了信号３０７を受信しない場合には、第２ＲＯＭ３０３を選択してＦＰＧＡ３０１に再構成指示信号３０６を再度出力する。これにより、第１ＲＯＭ３０２において障害が発生した場合に、自動的に第２ＲＯＭ３０３からＦＰＧＡ３０１に再構成用ＲＯＭデータ３１０をロードして内部再構成させることができる。
PCT/JP2007/001305 2007-11-27 2007-11-27 組込装置及び制御方法 WO2009069174A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/001305 WO2009069174A1 (ja) 2007-11-27 2007-11-27 組込装置及び制御方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/001305 WO2009069174A1 (ja) 2007-11-27 2007-11-27 組込装置及び制御方法

Publications (1)

Publication Number Publication Date
WO2009069174A1 true WO2009069174A1 (ja) 2009-06-04

Family

ID=40678092

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/001305 WO2009069174A1 (ja) 2007-11-27 2007-11-27 組込装置及び制御方法

Country Status (1)

Country Link
WO (1) WO2009069174A1 (ja)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0962528A (ja) * 1995-08-23 1997-03-07 Fujitsu Ltd 自己修復装置
JP2006099305A (ja) * 2004-09-29 2006-04-13 Hitachi Ltd プログラマブルｌｓｉのコンフィグレーション制御方法
JP2006157482A (ja) * 2004-11-30 2006-06-15 Fujitsu Ltd プログラマブル・ロジック・デバイス、情報処理装置、プログラマブル・ロジック・デバイスの制御方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0962528A (ja) * 1995-08-23 1997-03-07 Fujitsu Ltd 自己修復装置
JP2006099305A (ja) * 2004-09-29 2006-04-13 Hitachi Ltd プログラマブルｌｓｉのコンフィグレーション制御方法
JP2006157482A (ja) * 2004-11-30 2006-06-15 Fujitsu Ltd プログラマブル・ロジック・デバイス、情報処理装置、プログラマブル・ロジック・デバイスの制御方法

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