WO2009068893A1 - Rastérisation multi-noyau dans un système de rendu par mosaïque - Google Patents

Rastérisation multi-noyau dans un système de rendu par mosaïque Download PDF

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Publication number
WO2009068893A1
WO2009068893A1 PCT/GB2008/003984 GB2008003984W WO2009068893A1 WO 2009068893 A1 WO2009068893 A1 WO 2009068893A1 GB 2008003984 W GB2008003984 W GB 2008003984W WO 2009068893 A1 WO2009068893 A1 WO 2009068893A1
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WO
WIPO (PCT)
Prior art keywords
processing units
graphics processing
image
graphics
rectangular area
Prior art date
Application number
PCT/GB2008/003984
Other languages
English (en)
Inventor
John William Howson
Original Assignee
Imagination Technologies Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imagination Technologies Limited filed Critical Imagination Technologies Limited
Publication of WO2009068893A1 publication Critical patent/WO2009068893A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/005—General purpose rendering architectures

Definitions

  • This invention relates to a three-dimensional computer graphics rendering system and in particular to methods and apparatus which may be used for combining multiple independent graphics processing cores for the purpose of increasing rasterisation performance.
  • Tile based rendering systems are well-known. These subdivide an image into a plurality of rectangular blocks or tiles.
  • Figure 1 illustrates an example of a tile based rendering system.
  • a primitive/command fetch unit 101 retrieves command and (graphics) primitive data from memory and passes this to a geometry processing unit 102. This transforms the primitive and command data into screen space using well-known methods.
  • This data is then supplied to a tiling unit 103 which inserts object data from the screen space geometry into object lists for each of a set of defined rectangular regions or tiles in which screen space is divided.
  • An object list for each tile contains primitives that exist wholly or partially in that tile.
  • An object list exists for every tile on the screen, although some object lists may have no data in them.
  • tile parameter fetch unit 105 which supplies them tile by tile to a hidden surface removal unit (HSR) 106 which removes the primitives of surfaces which will not contribute to the final scene (usually because they are obscured by another surface).
  • HSR unit processes each primitive in the tile to determine which on visible of pixels and passes only data for visible pixels to a testing and shading unit (TSU) 108.
  • TSU testing and shading unit
  • the TSU takes the data from the HSR and uses it to fetch textures and apply shading to each pixel within a visible object using well-known techniques.
  • the TSU then supplies the textured and shaded data to an alpha test/fogging/alpha blending unit 110. This is able to apply degrees of transparency/opacity to the surfaces again using well-known techniques.
  • Alpha blending is performed using an on chip tile buffer 112 thereby eliminating the requirement to access external memory for this operation. It should be noted that the TSU and alpha test/fogging/alpha blend units may be fully programmable in nature.
  • the pixel processing unit 114 performs any necessary backend processing such as packing and anti-alias filtering before writing the resulting data to a rendered scene buffer 116, ready for displayBritish Patent No. GB2343598 (the contents of which are incorporated herein by reference) describes scaling rasterisation performance within a tile based rendering environment by distributing workload across cores by rasterising alternate tiles on alternate cores, for example in a chequer board pattern. Although this approach minimises the effects of uneven distribution of work load across the tiles that make up the scene it doesn't allow for all circumstances.
  • triangles 1 and 2 (200, 210) in tile 0 require a total of 600 clocks of processing
  • the triangles overlapping each of the remaining tiles T3, T4 and T5 (220, 230 and 240) each require 200 clocks of pixel processing.
  • core 1 will execute a total of 800 clocks of pixel processing
  • core 2 will execute a total of 400 clocks of pixel processing, as a result core 2 will remain idle for 400 clocks. This is a significant imbalance in processing load between the two processing cores.
  • Preferred embodiments of the present invention provide a method and apparatus that allow a tile based rendering system to scale rasterisation performance in a linear fashion and that minimises the loading differences across a plurality of cores. This is accomplished by the addition of separate region fetch and distribution units that distribute regions to be processed across multiple cores based on work load within each core.
  • Figure 1 illustrates an example of a prior art tile based rendering system as described above
  • Figure 2 illustrates the load balancing problem that occurs with a fixed assignment of cores to regions as described above.
  • FIG. 3 illustrates a system embodying the invention.
  • the output of the tiling process in a graphics rasterisation system is a set of object lists for non overlapping regions each of which contains references to all geometry that overlaps its respective region. As there is no spatial overlap between each region it is possible to rasterise the regions in any order. Given this it is possible to distribute regions across processing cores for rasterisation in an order that is dictated by loading on the individual processing cores instead of some predetermined spatial arrangement as described in our previous United Kingdom Patent No. GB2343598.
  • Figure 3 illustrates a proposed arrangement embodying the invention.
  • a region fetch unit 300 reads region header data (including object list data) from memory and passes them to a region distribution unit 310 which passes the region data to a processing core within an array of available cores 340 that is least busy for processing.
  • Each core within the array of cores receives a signal or set of signals 330 from the region distribution unit 310 including data about the region to be processed by the processing core.
  • Each processing core produces a return signal 320 that indicates whether or not the core can take a new region for processing, at that time.
  • the system when equipped with two processing cores will operate as follows.
  • the region fetch unit 310 fetches region data for tileO and passes it to the region distribution unit 310.
  • the region distribution unit will distribute data for the regionto the available cores in a round robin fashion, starting with core 0 for tile 0 and core 1 for tile and so on.
  • the region distribution unit will then need to wait for one of the processing cores to be able to accept another region before proceeding to distribute tile 2.
  • core 2 will only have 200 clocks of processing for tile 1 it will become free first so the region distribution unit will pass tile 2 to it for process, and again for tile 3 when tile 2 is complete.
  • the region fetch unit and the region distribution unit allow subsequent renders for the next field frame to be executed in the case where one or more of the processing cores has become idle and there are no more regions to be rasterised in the current scene.

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  • Engineering & Computer Science (AREA)
  • Computer Graphics (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Image Generation (AREA)
  • Image Processing (AREA)

Abstract

L'invention concerne un procédé et un appareil pour rendre une image graphique informatique tridimensionnelle. L'image est subdivisée en une pluralité de zones rectangulaires associées chacune à une partie rectangulaire d'un affichage. Des données d'image graphique concernant des objets à rendre sont produites et attribuées à des listes d'objets respectives parmi des listes d'objets associées à chaque zone rectangulaire respective. Les listes d'objets de chaque zone rectangulaire sont transmises à un moyen de distribution couplé à une pluralité d'unités de traitement graphique. Le moyen de distribution détermine les unités de traitement graphique qui sont en mesure de recevoir des données pour le traitement et transmet les listes d'objets à des unités de traitement particulières parmi les unités de traitement en fonction du résultat de la détermination.
PCT/GB2008/003984 2007-11-30 2008-12-01 Rastérisation multi-noyau dans un système de rendu par mosaïque WO2009068893A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0723537A GB0723537D0 (en) 2007-11-30 2007-11-30 Multi-core rasterisation in a tile based rendering system7743180001
GB0723537.7 2007-11-30

Publications (1)

Publication Number Publication Date
WO2009068893A1 true WO2009068893A1 (fr) 2009-06-04

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PCT/GB2008/003984 WO2009068893A1 (fr) 2007-11-30 2008-12-01 Rastérisation multi-noyau dans un système de rendu par mosaïque

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GB (1) GB0723537D0 (fr)
WO (1) WO2009068893A1 (fr)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011028981A1 (fr) * 2009-09-03 2011-03-10 Advanced Micro Devices, Inc. Unité de traitement avec pluralité de moteurs de contrôleur de nuances
US20130076761A1 (en) * 2011-09-22 2013-03-28 Arm Limited Graphics processing systems
US8587610B2 (en) 2008-12-12 2013-11-19 Microsoft Corporation Rendering source content for display
GB2559042A (en) * 2015-12-21 2018-07-25 Imagination Tech Ltd Allocation of tiles to processing engines in a graphics processing system
CN113139891A (zh) * 2021-04-28 2021-07-20 北京百度网讯科技有限公司 图像处理方法、装置、电子设备和存储介质
CN115210748A (zh) * 2020-02-03 2022-10-18 索尼互动娱乐股份有限公司 渲染时通过区域测试进行几何图形高效多gpu渲染的系统和方法
CN115335866A (zh) * 2020-02-03 2022-11-11 索尼互动娱乐股份有限公司 在渲染时通过几何图形分析进行几何图形的高效多gpu渲染的系统和方法

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
ELLSWORTH D A: "A NEW ALGORITHM FOR INTERACTIVE GRAPHICS ON MULTICOMPUTERS", IEEE COMPUTER GRAPHICS AND APPLICATIONS, IEEE SERVICE CENTER, NEW YORK, NY, US, vol. 14, no. 4, 1 July 1994 (1994-07-01), pages 33 - 40, XP000509478, ISSN: 0272-1716 *
HENRY FUCHS ET AL: "Pixel-Planes 5: A Heterogeneous Multiprocessor Graphics System Using Processor-Enhanced Memories", COMPUTER GRAPHICS, vol. 23, no. 3, 1 July 1989 (1989-07-01), pages 79 - 88, XP007905796 *
KAWAI T ET AL: "Evaluation of Parallel Ray Tracing Algorithm Using Screen Space Subdivision for Image Generation System MAGG", SYSTEMS & COMPUTERS IN JAPAN, WILEY, HOBOKEN, NJ, US, vol. 15, no. 11, 1 January 1994 (1994-01-01), pages 78 - 87, XP002477481, ISSN: 0882-1666 *

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8587610B2 (en) 2008-12-12 2013-11-19 Microsoft Corporation Rendering source content for display
WO2011028981A1 (fr) * 2009-09-03 2011-03-10 Advanced Micro Devices, Inc. Unité de traitement avec pluralité de moteurs de contrôleur de nuances
JP2013504129A (ja) * 2009-09-03 2013-02-04 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 複数のシェーダエンジンを伴う処理ユニット
US9142057B2 (en) 2009-09-03 2015-09-22 Advanced Micro Devices, Inc. Processing unit with a plurality of shader engines
US20130076761A1 (en) * 2011-09-22 2013-03-28 Arm Limited Graphics processing systems
US9122646B2 (en) * 2011-09-22 2015-09-01 Arm Limited Graphics processing systems
US10210651B2 (en) 2015-12-21 2019-02-19 Imagination Technologies Limited Allocation of tiles to processing engines in a graphics processing system
US10055877B2 (en) 2015-12-21 2018-08-21 Imagination Technologies Limited Allocation of tiles to processing engines in a graphics processing system
GB2559042A (en) * 2015-12-21 2018-07-25 Imagination Tech Ltd Allocation of tiles to processing engines in a graphics processing system
GB2559042B (en) * 2015-12-21 2019-06-05 Imagination Tech Ltd Allocation of tiles to processing engines in a graphics processing system
US10475228B2 (en) 2015-12-21 2019-11-12 Imagination Technologies Limited Allocation of tiles to processing engines in a graphics processing system
CN115210748A (zh) * 2020-02-03 2022-10-18 索尼互动娱乐股份有限公司 渲染时通过区域测试进行几何图形高效多gpu渲染的系统和方法
CN115335866A (zh) * 2020-02-03 2022-11-11 索尼互动娱乐股份有限公司 在渲染时通过几何图形分析进行几何图形的高效多gpu渲染的系统和方法
CN115210748B (zh) * 2020-02-03 2023-11-24 索尼互动娱乐股份有限公司 渲染时通过区域测试进行几何图形高效多gpu渲染的系统和方法
CN113139891A (zh) * 2021-04-28 2021-07-20 北京百度网讯科技有限公司 图像处理方法、装置、电子设备和存储介质
CN113139891B (zh) * 2021-04-28 2023-09-26 北京百度网讯科技有限公司 图像处理方法、装置、电子设备和存储介质

Also Published As

Publication number Publication date
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