JP2012178158A - グラフィックスプロセッサの並列アレイアーキテクチャ - Google Patents
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Abstract
【解決手段】グラフィックスプロセッサの並列アレイアーキテクチャは、複数の処理クラスタを含み、各処理クラスタがカバレッジデータから画素データを生成するピクセルシェーダープログラムを実行する少なくとも1個の処理コアを含む、マルチスレッド型コアアレイと、複数の画素のうちの1画素毎にカバレッジデータを生成するラスタライザと、ラスタライザからマルチスレッド型コアアレイ中の処理クラスタのうちの1つにカバレッジデータを配信する画素分配ロジックとを含む。画素分配ロジックは、画像エリアの範囲内の第1画素の位置に少なくとも部分的に依存して第1画素のためのカバレッジデータが配信される処理クラスタのうちの1つを選択する。画素データが処理クラスタから適切なフレームバッファ区画へ直接的に配信される。
【選択図】図6
Description
[0012]以下の詳細な説明は、添付図面と共に、本発明の本質及び利点のより良い理解を与える。
[0019]図1は本発明の実施形態によるコンピュータシステム100のブロック図である。コンピュータシステム100は、中央処理ユニット(CPU)102と、メモリブリッジ105を含むバス経路を介して通信するシステムメモリ104とを含む。メモリブリッジ105は、バス経路106を介して、I/O(入力/出力)ブリッジ107に接続されている。I/Oブリッジ107は、1台以上のユーザ入力装置108(たとえば、キーボード、マウス)からユーザ入力を受信し、バス106及びメモリブリッジ105を介して入力をCPU102へ転送する。可視出力がバス113を介してメモリブリッジ105に連結されたグラフィックスサブシステム112の制御の下で動作する画素ベースの表示装置110(たとえば、従来型のCRT又はLCDベースのモニター)上に提供される。システムディスク114はさらにI/Oブリッジ107に接続されている。スイッチ116は、I/Oブリッジ107と、ネットワークアダプタ118及び種々のアドインカード120、121のような他のコンポーネントとの間で接続を行う。USB又は他のポート接続、CDドライブ、DVDドライブなどを含むその他のコンポーネント(明示的に示されていない)もまたI/Oブリッジ107に接続されてもよい。種々のコンポーネント間でのバス接続は、PCI(ペリフェラル・コンポーネント・インターコネクト)、PCIエクスプレス(PCI−E)、AGP(アクセラレーテッド・グラフィックス・ポート)、ハイパートランスポート、又は、その他の(複数の)バスプロトコルのようなバスプロトコルを使用して実施可能であり、様々な装置間の接続は当分野で公知のような異なるプロトコルを使用してもよい。
[0027]図2は本発明の実施形態による図1のGPU122で実施され得るレンダリングパイプライン200のブロック図である。本実施形態では、レンダリングパイプライン200は、適用可能なバーテックスシェーダープログラム、ジオメトリシェーダープログラム、及び、ピクセルシェーダープログラムが、本明細書で「マルチスレッド型コアアレイ」202と呼ばれる同じ並列処理ハードウェアを使用して実行されるアーキテクチャを使用して実施される。マルチスレッド型コアアレイ202は後述されている。
[0047]一実施形態では、マルチスレッド型コアアレイ202は、様々に組み合わされたバーテックスシェーダープログラム、ジオメトリシェーダープログラム、及び/又は、ピクセルシェーダープログラムの非常に多数のインスタンスの同時実行をサポートする高度な並列アーキテクチャを提供する。図3は本発明の実施形態によるマルチスレッド型コアアレイ202のブロック図である。
[0058]本発明の実施形態によれば、ピクセルシェーダープログラムによって処理されるべき画素は、画像エリア内の画素の位置に基づいて処理クラスタ302(図3)へ向けられる。たとえば、画像エリアはある数のタイルに分割され得る。各タイルは、1つのクラスタに関連付けられたタイルが画像エリアの全体に散在させられるように、処理クラスタ302のうちの1つが関連付けられている(すなわち、1つの処理クラスタに関連付けられているタイルの少なくとも一部は相互に隣接していない)。
[0063]一部の実施形態では、図2に提案されている集中型ROP214ではなく、図3の各ピクセルコントローラ306は、画素を図2のフレームバッファ226へ通信する固有のROPを含む。このような実施形態では、処理クラスタ302からフレームバッファへのカップリングが行われる。
[0072]本発明は特定の実施形態に関して説明されているが、当業者は数多くの変形例が可能であることを認める。したがって、本発明は特定の実施形態に関して説明されているが、本発明が特許請求の範囲に記載された事項の範囲内のすべての変更及び均等物に及ぶように意図されていることが認められる。
Claims (7)
- 複数の処理クラスタを含むマルチスレッド型コアアレイであって、各処理クラスタが、カバレッジデータから画素データを生成するピクセルシェーダープログラムを実行するように動作可能である少なくとも1個の処理コアを含むマルチスレッド型コアアレイと、
複数の画素の1つずつに対しカバレッジデータを生成するように構成されたラスタライザと、
前記ラスタライザから前記マルチスレッド型コアアレイ中の前記処理クラスタのうちの1個の処理クラスタに前記カバレッジデータを配信するように構成された画素分配論理回路と、
を備え、
前記画素分配論理回路が、画像エリア内の第1の画素の場所に少なくとも部分的に基づいて、前記第1の画素のための前記カバレッジデータが配信される、前記処理クラスタのうちの前記1個の処理クラスタを選択し、
各処理コアがバーテックスシェーダープログラム及びジオメトリシェーダープログラムを実行するようにさらに動作可能であり、
各処理コアは、前記三つのシェーダプログラムのうち異なる複数のプログラムを実行する複数のスレッドの同時実行をサポートする、
グラフィックスプロセッサ。 - 前記画像エリアが複数のタイルに分割され、各タイルが前記処理クラスタの一つに割り当てられ、
前記画素分配論理回路が、前記複数のタイルのうちどれが前記第1の画素を含むかに関する判断に基づいて、前記処理クラスタのうちの前記1つを選択する、請求項1に記載のグラフィックスプロセッサ。 - 前記複数のタイルのうちの少なくとも二つが前記処理クラスタの各々に割り当てられ、
各処理クラスタについて、該処理クラスタに割り当てられた前記タイルが相互に隣接していない、請求項2に記載のグラフィックスプロセッサ。 - 前記処理クラスタのうちの各処理クラスタが画素データをフレームバッファの複数の区画のうちの対応する1個の区画に配信するように構成されている、請求項1に記載のグラフィックスプロセッサ。
- 前記処理クラスタのうちの各処理クラスタに連結され、前記処理クラスタから複数の区画を有するフレームバッファへ画素データを配信するように構成されているクロスバーをさらに備える、請求項1に記載のグラフィックスプロセッサ。
- 前記処理クラスタのうちのいずれか1個の処理クラスタによって生成された画素データが前記フレームバッファの区画のうちのいずれか1個の区画へ配信可能であるように、前記クロスバーが構成されている、請求項5に記載のグラフィックスプロセッサ。
- 前記マルチスレッド型コアアレイは、レンダリングアプリケーションが前記三つのシェーダプログラムのいずれかに集中する場合に、該対応するシェーダプログラムに振り向けられる処理サイクルを増大する、請求項1〜6のいずれか一項に記載のグラフィックスプロセッサ。
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KR (1) | KR101027621B1 (ja) |
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TW200745987A (en) | 2007-12-16 |
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