WO2009066997A2 - Contact etch for ams products - Google Patents
Contact etch for ams products Download PDFInfo
- Publication number
- WO2009066997A2 WO2009066997A2 PCT/MY2008/000163 MY2008000163W WO2009066997A2 WO 2009066997 A2 WO2009066997 A2 WO 2009066997A2 MY 2008000163 W MY2008000163 W MY 2008000163W WO 2009066997 A2 WO2009066997 A2 WO 2009066997A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- contact
- profile
- etch
- semi
- rounded
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
Definitions
- This invention relates, in general, to contact etch processes and, more particularly, to semi rounded contact etch process.
- the conduction layers be interconnected through holes in the insulating layers. Holes are usually formed by etching through a dielectric layer that separates one or more layers of components of an integrated circuit If the holes filled with metal connect conductive layers, they are referred to as via holes, and as contact holes if they connect the devices that are formed on the substrate.
- Standard techniques for deposition of the conduction layers include sputtering and evaporation.
- a good contact hole must fulfill the following criteria (a) low unit resistivity (b) good adhesion to silicon and oxide layer (c) good coverage of steps on chip surface (d) immunity to corrosion (e) ductility and compatibility with bonding.
- the disadvantage of the conventional sputtering method is that the step coverage of a film deposited by sputtering is poor, especially when filing contact holes having an aspect ratio of more than one. This problem becomes more prominent in Analog Mixed Signal (AMS) products that utilize Poly Insulator Poly (PIP) capacitor structure, encompassed a Pre-Metal Dielectric (PMD) layer.
- AMS Analog Mixed Signal
- PIP Poly Insulator Poly
- PMD Pre-Metal Dielectric
- the invention is directed towards a method for contact etch process that improves the metal step coverage for contact holes with a high aspect ratio.
- This invention will be focussing mainly on an approach taken to improve first metal layer step coverage inside contact hole.
- FIG. 2 Schematic diagram of PMP with various thickness that needs to be . etched across different structures
- Metal deposition step coverage percentage is defined as metal thickness inside the hole Y, divided by metal thickness outside the hole X, and then multiplied by 100. This can been seen from Figure 1. Proper connection can be achieved with a high step coverage percentage. This is very significant to integrated process that implements metallization scheme without tungsten deposition and tungsten etch back.
- the AMS product utilizes thick PIP structure, about 800nm in total and this PIP structure is located on top of 700nm semirecessed LOCOS. This results in contact holes that needs to be etched in various Pre-Metal Dielectric (PMD) thickness.
- PMD Pre-Metal Dielectric
- Figure 2 shows the schematic diagram of PMP with various thickness that needs to be etched across diferrent structures. The thickness may vary from 500nm of PMD on top of PIP structure to up to 1300nm of PMD on active area located next to PIP structure.
- the aspect ratio across tihis structure is also varied with Contact Critical Dimension (CD) of 800nm.
- the high aspect ratio is expected to be 1.6.
- the aspect ratio can be calculated as illustrated in Figure 3.
- PVD physical vapour deposition
- the molecules or atoms are ejected from a targe material by high energy particle bombardment so that the ejected molecules or atoms can condense on a substrate to create a thin film.
- the drawback of the PVD technique is that holes with high aspect ratio are difficult to be filled. Further to this, higher aspect ratio contact hole etches slower that lower aspect ratio hole. It is to be noted that the highest aspect ratio that can be expected in a 0.8 ⁇ m AMS products is 1.6.
- the approach taken in this invention to solve the above problem is to optimize the contact hole profile prior to metal deposition. Hence, the metal deposition scheme does not have to be altered.
- Semi-rounded contact etching is a new etching technique that combines isotropic etching and anisotropic etching, both utilizing the dry etching technique, which is illustrated in Figure 4.
- PE plasma etcher
- RIE reactive ion etching
- anisotropic etching means etching only in ore direction, perpendicular to the wafer surface.
- the baseline recipe used to produce semi rounded profiles on the top half of the contact holes consists of O 2 and CF 4 gases in the ratio of 1 :9, at 1500mTorr pressure and 200OWaIt RF power.
- This recipe employs totally chemical reaction mechanism without physical reaction to provide ion bombardment such as Argon gas.
- the baseline etching process recipe for straight profile consists of one etch step:
- Step 1 Main etch (ME), controlled by time.
- the baseline recipe used consists of CF 4 , CHF3 ; 02 and Argon gases in the ratio of 6:4:1:60.
- the CF 4 gas is the primary gas etchant, while CHF 3 gas promotes a protective film layers that increase selectivity to the underlying material. Addition of a small amount of oxygen gas 02 is to minimize CD loss i.e. reduction in critical dimension size between pattern and after etching process.
- the Argon gas provides ion bombardment and promotes physical reaction. Therefore this recipe is called as reactive ion etching (RIE), based on chemical and physical etches mechanism. A thirty five percent overetching is performed after the main etch step to ensure complete removal of the oxide film at the thickest PMD layer.
- RIE reactive ion etching
- the baseline etching process recipe for semi-rounded profile consists of two etch steps:
- Step 1 Main etch (ME), controlled by time.
- Step 2 Over etch (OE)
- the ME step is to remove the bulk PMD oxide layer while the OE step is to remove the remaining oxide on areas where the PMD is thicker.
- Final PMD layer consists of three films.
- the bottom film is Undoped Silicate Glass (USG), followed by Boron and Phosphorous Doped Silicate Glass (BPSG) film.
- the top film is Spin-On Glass (SOG) and it is used for planarization.
- SOG Spin-On Glass
- the etch process time is calculated based on the etch rates of the annealed USG and BPSG films.
- a groundwork test was performed to produce isotropic profile using the first baseline recipe.
- the recipe allows the etching process characteristic to be isotropic, where the etching rate is horizontal or lateral direction faster then vertical direction.
- the etch time process was calculated based on etch rates of the annealed BPSG only.
- the expected annealed BPSG to be removed is 300nm with the isotropic profile.
- Fig. 5 shows the Field Emission Scanning Electron Microscopy (FESEM) image of the isotropic etch using this system.
- a subsequent test was performed to produce anisotropic profile using second baseline recipe.
- the recipe allows the etching process characteristic to be anisotropic as a standard Contact profile.
- the etching rate is vertical direction faster then horizontal direction.
- the etch rate time process was calculated based on etch rates of the annealed BSPG and USG films
- the expected annealed BPSG and USG to be removed are 400nm and 200nm respectively.
- Fig. 6 shows FESEM image of complete semi- rounded Contact etch profile using Plasma Etcher and RIE etcher.
- Figure 7 to 11 are cross section images taken of a 0.8/ ⁇ m AMS product wafer, which has been etched and filed with metal deposition. The figures show a comparison of a straight contact profile and a semi-rounded contact profile.
- the metal step coverage inside the semi-rounded contact profile has a better percentage than a straight contact profile.
- the metal coverage percentage and original aspect ratio derived from Figures 7 to 11 is listed below in Table 1. As the aspect ratio increases, metal step coverage percentage decreases when using the straight contact profile. However, an improved metal step coverage percentage can be seen when using the semi-rounded contact profile.
- Figure 13 further shows the relationship between the metal step coverage percentage and the aspect ratio for both types of contact profile.
- Table II shows Contact Resistivity Average value and its standard deviation for four sets of different Contact Chain test structure to compare between semi-rounded Contact profile and straight Contact profile. Better Contact resistivity can be achieved by implementing semi-rounded Contact hole profile although its standard deviation is higher than straight Contact profile for Poly2 and N+ Contact Chain TABLE ⁇ CONTACT RESISTIVITY
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
Abstract
This invention provides a method to improve metal step coverage in contact hole filling by utilizing two step contact etch. The contact etch process provides a semi-rounded profile on the top half of the contact hole and a straight profile at the lower half. The semi-rounded contact etch process is able to reduce the aspect ratio to 1.
Description
CONTACT ETCH FOR AMS PRODUCTS
Field of Invention
This invention relates, in general, to contact etch processes and, more particularly, to semi rounded contact etch process.
Background of Invention
In the manufacture of semiconductor devices, it is often required that the conduction layers be interconnected through holes in the insulating layers. Holes are usually formed by etching through a dielectric layer that separates one or more layers of components of an integrated circuit If the holes filled with metal connect conductive layers, they are referred to as via holes, and as contact holes if they connect the devices that are formed on the substrate.
Controlled manufacture of the shape and dimensions of holes through which connections are made between various components of integrated circuits in semiconductor substrates is well known in the art.
Standard techniques for deposition of the conduction layers include sputtering and evaporation. A good contact hole must fulfill the following criteria (a) low unit resistivity (b) good adhesion to silicon and oxide layer (c) good coverage of steps on chip surface (d) immunity to corrosion (e) ductility and compatibility with bonding.
However, the disadvantage of the conventional sputtering method is that the step coverage of a film deposited by sputtering is poor, especially when filing contact holes having an aspect ratio of more than one. This problem becomes more prominent in Analog Mixed Signal (AMS) products that utilize Poly Insulator Poly (PIP) capacitor structure, encompassed a Pre-Metal Dielectric (PMD) layer.
Contact holes on the active area have the thickest PMD layer, thus making it the most difficult to fill with the metal due to its high aspect ratio.
Therefore there arise a need for a contact etch method that improves the metal step coverage for contact holes with an high aspect ratio for example an aspect ratio of 1.6
Summary of Invention
It is therefore the object of the invention to provide a contact etch process that improves the metal step coverage for contact holes with a high aspect ratio to ensure proper connection path has been developed.
To achieve these object, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a method for contact etch process that improves the metal step coverage for contact holes with a high aspect ratio. This invention will be focussing mainly on an approach taken to improve first metal layer step coverage inside contact hole.
These objects are accomplished by a taper or round profile for the upper half of the PMD layer, while maintaining a straight profile for the bottom half of the PMD for Critical Dimension (CD) control.
Brief Description of Drawings
Figure 1 Illustration of definition of Metal step coverage percentage
Figure 2 Schematic diagram of PMP with various thickness that needs to be . etched across different structures
Figure 3 Method to calculate the aspect ratio
Figure 4 Semi-rounded contact etching profile
Figure 5 Cross section of straight profile
Figure 6 Cross section of a semi-rounded profile Figures 7 to 11 Comparison metal coverage percentage and original aspect ratio
Detailed Description
Metal deposition step coverage percentage is defined as metal thickness inside the hole Y, divided by metal thickness outside the hole X, and then multiplied by 100. This can been seen from Figure 1. Proper connection can be achieved with a high step coverage percentage. This is very significant to integrated process that implements metallization scheme without tungsten deposition and tungsten etch back.
The method and use of the presently preferred embodiments will now be discussed in great detail. However, it should be appreciated that the present invention provides widely applicable inventive concept, which can be embodied in a variety of specific contexts; the specific embodiments discussed are merely illustrative of specific ways to use the invention, and do not delimit the scope of the invention. Therefore, for the purpose of discussion 0.8 μm Analog and Mixed Signal (AMS) product with double poly and double metal layer, will be used as the product to which the semi-rounded contact etch process is applied to.
The AMS product utilizes thick PIP structure, about 800nm in total and this PIP structure is located on top of 700nm semirecessed LOCOS. This results in contact holes that needs to be etched in various Pre-Metal Dielectric (PMD) thickness. Figure 2 shows the schematic diagram of PMP with various thickness that needs to be etched across diferrent structures. The thickness may vary from 500nm of PMD on top of PIP structure to up to 1300nm of PMD on active area located next to PIP structure.
The aspect ratio across tihis structure is also varied with Contact Critical Dimension (CD) of 800nm. The high aspect ratio is expected to be 1.6. The aspect ratio can be calculated as illustrated in Figure 3.
Currently the metal is deposited using physical vapour deposition (PVD) technique, more specifically sputerring. In this method, the molecules or atoms are ejected from a targe material by high energy particle bombardment so that the ejected molecules or atoms can condense on a substrate to create a thin film.
However, the drawback of the PVD technique is that holes with high aspect ratio are difficult to be filled. Further to this, higher aspect ratio contact hole etches slower that lower aspect ratio hole. It is to be noted that the highest aspect ratio that can be expected in a 0.8μm AMS products is 1.6.
Therefore, the approach taken in this invention to solve the above problem is to optimize the contact hole profile prior to metal deposition. Hence, the metal deposition scheme does not have to be altered.
The method presented in this application to optimize the contact hole profile is by means of semi-rounded contact etch process. Semi-rounded contact etching is a new etching technique that combines isotropic etching and anisotropic etching, both utilizing the dry etching technique, which is illustrated in Figure 4.
Dry-etch has been used as opposed to wet-etch as wet etch has disadvantages such as
(a) It is incaple of replicating the mask pattern precisely into the film layer to be etched.
(b) It is operator dependant, which results in the problem of not being able to reproduce uniform etch results between different batches of wafer. (c) It is difficult to automate
Semi-rounded profile reduces the aspect ratio to 1, which results in better metal step coverage inside the hole. Referring to Figure 4, it can been noted that the top half of the contact hole can be easily filled with metal, and the thickness to be etched H is now reduced to Hnew.
Semi-rounded Contact hole etching process is achieved using a plasma etcher (PE) and reactive ion etching (RIE). The etch result of a plasma etcher is typically isotropic. Isotropic etch proceeds in all direction at the same rate. This will lead to undercutting of the photoresist mask, in which it is quite similar to wet chemical etching process.
The RIE system on the other hand etches anisotropically, where anisotropic is defined as movement in only one direction. In this instance anisotropic etching means etching only
in ore direction, perpendicular to the wafer surface. By properly controlling the parameters that are influencing these mechanism (i.e. gases used, power, pressure, magnetic field, temperature), it is possible to achieve a variety of desired directionalities and selectivities of the process.
hi the Examples discussed below, the baseline recipe used to produce semi rounded profiles on the top half of the contact holes consists of O2 and CF4 gases in the ratio of 1 :9, at 1500mTorr pressure and 200OWaIt RF power. This recipe employs totally chemical reaction mechanism without physical reaction to provide ion bombardment such as Argon gas.
The baseline etching process recipe for straight profile consists of one etch step:
Step 1 : Main etch (ME), controlled by time.
For the straight etch profile of the bottom part of the contact hole, the baseline recipe used consists of CF4, CHF3; 02 and Argon gases in the ratio of 6:4:1:60. The CF4 gas is the primary gas etchant, while CHF3 gas promotes a protective film layers that increase selectivity to the underlying material. Addition of a small amount of oxygen gas 02 is to minimize CD loss i.e. reduction in critical dimension size between pattern and after etching process. The Argon gas provides ion bombardment and promotes physical reaction. Therefore this recipe is called as reactive ion etching (RIE), based on chemical and physical etches mechanism. A thirty five percent overetching is performed after the main etch step to ensure complete removal of the oxide film at the thickest PMD layer.
The baseline etching process recipe for semi-rounded profile consists of two etch steps:
Step 1 : Main etch (ME), controlled by time. Step 2: Over etch (OE)
The ME step is to remove the bulk PMD oxide layer while the OE step is to remove the remaining oxide on areas where the PMD is thicker.
Final PMD layer consists of three films. The bottom film is Undoped Silicate Glass (USG), followed by Boron and Phosphorous Doped Silicate Glass (BPSG) film. The top film is Spin-On Glass (SOG) and it is used for planarization. For both baseline recipes (i.e. for semi-rounded profile and for straight profile), the etch process time is calculated based on the etch rates of the annealed USG and BPSG films.
A groundwork test was performed to produce isotropic profile using the first baseline recipe. Using Plasma etch with undercut technique the recipe allows the etching process characteristic to be isotropic, where the etching rate is horizontal or lateral direction faster then vertical direction. The etch time process was calculated based on etch rates of the annealed BPSG only. The expected annealed BPSG to be removed is 300nm with the isotropic profile.
As mentioned earlier, the top half of the Contact profile is semi-rounded and it is produced by Plasma Etching systems. Fig. 5 shows the Field Emission Scanning Electron Microscopy (FESEM) image of the isotropic etch using this system.
A subsequent test was performed to produce anisotropic profile using second baseline recipe. Using RIE system, the recipe allows the etching process characteristic to be anisotropic as a standard Contact profile. The etching rate is vertical direction faster then horizontal direction. The etch rate time process was calculated based on etch rates of the annealed BSPG and USG films The expected annealed BPSG and USG to be removed are 400nm and 200nm respectively. Fig. 6 shows FESEM image of complete semi- rounded Contact etch profile using Plasma Etcher and RIE etcher.
Figure 7 to 11 are cross section images taken of a 0.8/ιm AMS product wafer, which has been etched and filed with metal deposition. The figures show a comparison of a straight contact profile and a semi-rounded contact profile.
It can be deduced from the figures that the metal step coverage inside the semi-rounded contact profile has a better percentage than a straight contact profile. The metal coverage percentage and original aspect ratio derived from Figures 7 to 11 is listed below in Table 1. As the aspect ratio increases, metal step coverage percentage decreases when using
the straight contact profile. However, an improved metal step coverage percentage can be seen when using the semi-rounded contact profile. Figure 13, further shows the relationship between the metal step coverage percentage and the aspect ratio for both types of contact profile.
TABLE I
METAL STEP COVERAGE
Meanwhile Table II shows Contact Resistivity Average value and its standard deviation for four sets of different Contact Chain test structure to compare between semi-rounded Contact profile and straight Contact profile. Better Contact resistivity can be achieved by implementing semi-rounded Contact hole profile although its standard deviation is higher than straight Contact profile for Poly2 and N+ Contact Chain
TABLE π CONTACT RESISTIVITY
Claims
1. An contact hole etching method, comprising: a step of using isotropic etching to produce semi-rounded on the top half; a step of using anisotropic etching to produce straight profile on the lower half
2. A method according to claim 1 , wherein plasma etch technique is used for the semi-rounded profile.
3. A method according to claim 1 , wherein reactive ion etch is used for the straight profile.
4. A method according to claim 1 , wherein metal is deposited in the contact hole by means of physical vapour deposition.
5. A method according to claim 4, wherein the physical vapour deposition memod used in sputtering.
6. A method according claim 1 , wherein the aspect ration is reduced to 1.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| MYPI20072068A MY162269A (en) | 2007-11-22 | 2007-11-22 | Contact etch for ams products |
| MYPI20072068 | 2007-11-22 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO2009066997A2 true WO2009066997A2 (en) | 2009-05-28 |
| WO2009066997A3 WO2009066997A3 (en) | 2009-10-15 |
Family
ID=40668030
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/MY2008/000163 WO2009066997A2 (en) | 2007-11-22 | 2008-11-24 | Contact etch for ams products |
Country Status (2)
| Country | Link |
|---|---|
| MY (1) | MY162269A (en) |
| WO (1) | WO2009066997A2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2287895A1 (en) * | 2009-08-18 | 2011-02-23 | Unisantis Electronics (Japan) Ltd. | Semiconductor device and production method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5940730A (en) * | 1995-12-29 | 1999-08-17 | Hyundai Electronics Industries Co., Ltd. | Method of forming a contact hole of a semiconductor device |
| US6294476B1 (en) * | 1998-03-30 | 2001-09-25 | Vanguard International Semiconductor Corporation | Plasma surface treatment method for forming patterned TEOS based silicon oxide layer with reliable via and interconnection formed therethrough |
| US20020135071A1 (en) * | 2001-01-17 | 2002-09-26 | Sang-Bom Kang | Integrated circuit device contact plugs having a liner layer that exerts compressive stress thereon and methods of manufacturing same |
-
2007
- 2007-11-22 MY MYPI20072068A patent/MY162269A/en unknown
-
2008
- 2008-11-24 WO PCT/MY2008/000163 patent/WO2009066997A2/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5940730A (en) * | 1995-12-29 | 1999-08-17 | Hyundai Electronics Industries Co., Ltd. | Method of forming a contact hole of a semiconductor device |
| US6294476B1 (en) * | 1998-03-30 | 2001-09-25 | Vanguard International Semiconductor Corporation | Plasma surface treatment method for forming patterned TEOS based silicon oxide layer with reliable via and interconnection formed therethrough |
| US20020135071A1 (en) * | 2001-01-17 | 2002-09-26 | Sang-Bom Kang | Integrated circuit device contact plugs having a liner layer that exerts compressive stress thereon and methods of manufacturing same |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2287895A1 (en) * | 2009-08-18 | 2011-02-23 | Unisantis Electronics (Japan) Ltd. | Semiconductor device and production method thereof |
| CN101996942A (en) * | 2009-08-18 | 2011-03-30 | 日本优尼山帝斯电子株式会社 | Semiconductor device and production method thereof |
| US8466512B2 (en) | 2009-08-18 | 2013-06-18 | Unisantis Electronics Singapore Pte Ltd. | Semiconductor device and production method thereof |
| US8563379B2 (en) | 2009-08-18 | 2013-10-22 | Unisantis Electronics Singapore Pte Ltd. | Semiconductor device and production method thereof |
| TWI415196B (en) * | 2009-08-18 | 2013-11-11 | Unisantis Elect Singapore Pte | Semiconductor device and production method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2009066997A3 (en) | 2009-10-15 |
| MY162269A (en) | 2017-05-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4454148B2 (en) | Improved oxide layer etching method | |
| TWI254408B (en) | Method of forming a dielectric film including an air gap and a low-k dielectric layer, and semiconductor structure | |
| EP3625834B1 (en) | Preclean and deposition methodology for superconductor interconnects | |
| JPH0251232A (en) | Manufacture of semiconductor device | |
| JP2913936B2 (en) | Method for manufacturing semiconductor device | |
| Kamto et al. | Cryogenic inductively coupled plasma etching for fabrication of tapered through-silicon vias | |
| US10811269B2 (en) | Method to achieve a sidewall etch | |
| US6540885B1 (en) | Profile control of oxide trench features for dual damascene applications | |
| KR20010030091A (en) | Method of fabricating a semiconductor device | |
| KR0171733B1 (en) | Contact hole forming method of semiconductor device | |
| WO2009066997A2 (en) | Contact etch for ams products | |
| JP2650313B2 (en) | Dry etching method | |
| US20010042919A1 (en) | Semiconductor device and manufacturing method thereof | |
| WO2000039839A2 (en) | High aspect ratio sub-micron contact etch process in an inductively-coupled plasma processing system | |
| JPS5987834A (en) | Forming method of thin-film | |
| TWI778226B (en) | Method to achieve a sidewall etch | |
| US20040014311A1 (en) | Method for manufacturing a semiconductor device | |
| KR100628216B1 (en) | method for forming metal line of semiconductor device | |
| JPH02281622A (en) | Manufacture of semiconductor device | |
| JP2611273B2 (en) | Method for manufacturing semiconductor device | |
| JP2000150482A (en) | Dry etching method | |
| KR20070089498A (en) | Method for forming semiconductor device | |
| JP2000133711A (en) | Semiconductor device and its manufacture | |
| KR100283409B1 (en) | Etching method of semiconductor device | |
| JPS5933849A (en) | Semiconductor device and manufacture thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 08852198 Country of ref document: EP Kind code of ref document: A2 |
|
| NENP | Non-entry into the national phase in: |
Ref country code: DE |
|
| 122 | Ep: pct application non-entry in european phase |
Ref document number: 08852198 Country of ref document: EP Kind code of ref document: A2 |