WO2009052683A1 - Electronic circuit package - Google Patents

Electronic circuit package Download PDF

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Publication number
WO2009052683A1
WO2009052683A1 PCT/CN2007/070954 CN2007070954W WO2009052683A1 WO 2009052683 A1 WO2009052683 A1 WO 2009052683A1 CN 2007070954 W CN2007070954 W CN 2007070954W WO 2009052683 A1 WO2009052683 A1 WO 2009052683A1
Authority
WO
WIPO (PCT)
Prior art keywords
package
ceramic substrate
thin
integrated
circuit
Prior art date
Application number
PCT/CN2007/070954
Other languages
French (fr)
Inventor
Lap-Wai Lydia Leung
Yu-Chih Chen
Chi Kuen Leung
Chang Hwa Chung
Original Assignee
Hong Kong Applied Science And Technology Research Institute Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hong Kong Applied Science And Technology Research Institute Co., Ltd. filed Critical Hong Kong Applied Science And Technology Research Institute Co., Ltd.
Priority to PCT/CN2007/070954 priority Critical patent/WO2009052683A1/en
Publication of WO2009052683A1 publication Critical patent/WO2009052683A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/13—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body combined with thin-film or thick-film passive components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • the current invention relates to an electronic circuit package and in particular to a ceramic substrate for holding both passive and active electronic circuit components
  • United States Patent 6,545,225 discloses a small form-factor electronic circuit package in which passive components, such as capacitois, resistors and inductors, are formed on a substrate of an insulating material using a thin film technique A pianarizing layer of glass is first coated onto the insulating material and then the thin film circuits arc formed on the barrier layer. The partial or full integration of passive components onto the substrate leads to the creation of a module which is very compact.
  • Taiwanese patent publication TW0494560B Jn this package a patterned insulation layer is located on the upper surface of a ceramic substrate and a thin film passive device layer is locating on the patterned insulation layer. A passivation layer is formed on the thin film passive device layer and a chip is located on the passivation layer and electrically connected with the passive device through a multi-level interconnect.
  • the packages disclosed in these two patents have insulating or barrier layers on the supporting substrate to achieve passive components with acceptable performance at RF operating frequencies.
  • the insulating and barrier layers deteriorate the thermal spreading performance of the package and so these packages are not suitable for high power application.
  • an electronic circuit package comprising a ceramic substrate, a thin-film circuit integrated with the ceramic substrate and having at least two passive circuit elements joined by an integrated electrical interconnect, and at least one active power electronic component mounted on the ceramic substrate and electrically connected with the integrated thin-film circuit.
  • the thin-film circuit is integrated with the ceramic substrate by a method selected from a group comprising metal and dielectric deposition, electroplating and etching.
  • the active electronic component is mounted to the ceramic substrate without any dielectric material between the active electronic component and the ceramic substrate.
  • the active electronic component is mounted on the die bond pad with adhesive which could be conductive or non-conductive.
  • the thin-film circuit is integrated with the ceramic substrate.
  • the passive circuit elements are selected from the group consisting of a resistor, a capacitor, an inductor, a through hole, a via and a wrap-around.
  • the thin-film circuit is selected from a group consisting of an LC matching network, a low-pass filter, a band-pass filter, a high-pass filter, a diplexer and a balun.
  • the active electronic component comprises a semiconductor chip device or packaged IC
  • the semiconductor chip device is selected from a group consisting of a RF die, a low-noise amplifier, a power amplifier and a switch.
  • the electronic circuit package comprises a ceramic substrate, a thin-film circuit integrated with the ceramic substrate, thin-film circuit comprising at least two passive circuit elements connected to a bond pad and wherein there is no dielectric layer between the die bond pad and the substrate, and an active electronic component mounted to the die bond pad using a conductive or non conductive adhesive.
  • FIG. 1 is a schematic overview of an electronic circuit package according to the invention
  • Figure 2 is a side schematic view of the package
  • Figure 3 is an enlarged size schematic view of area A of Figure 2.
  • an electronic circuit package 1 comprising a ceramic supporting substrate 2, a plurality of thin-film circuits 3 deposited on the ceramic substrate 2 and a plurality of active electronic devices 4.
  • the thin-film circuits 3 comprise a plurality of passive circuit elements which in combination with the active electronic devices 4 form a functioning electronic circuit.
  • the passive circuit elements of the thin-film circuits 3 may include, but are not limited to, any one of resistors, capacitors, inductors, through-holes, vias and/or edge wrap-arounds. These components are formed on the ceramic by depositing thin films of metal, dielectric or photoresist materials using plasma enhanced chemical vapor deposition (PF-CVD), physical vapor deposition (PVD) such as sputtering, patterning and etching and electroplating processes.
  • PF-CVD plasma enhanced chemical vapor deposition
  • PVD physical vapor deposition
  • the electroplating process is used to control the metal thickness of components whose performance is sensitive to metal thickness, for example, Q-factor of inductors a.nd insertion loss of transmission line.
  • the thin film passive circuit elements are joined to form thin-film electronic circuits by interconnects also integrated with the ceramic substrate 2.
  • the passive components may be of any arbitrary shape, taking account of the voltage, current, frequency characteristics of the electrical signal and the shape and size of the active electronic components they will carry, and are arranged to form passive circuit elements such as LC matching networks, low- pass filters, band-pass filers, high-pass filters, diplexers and the like.
  • Die Bond pads 6 are also formed on the substrate for mounting the active components 4.
  • the die bond pads are formed by electroplating or one of the thin-film techniques described above directly onto the substrate without an intervening dielectric layer between the pad 6 and ceramic substrate 2.
  • the active electronic components 4 of the package may include, bat are not limited to, semiconductor devices and dies such as transistors, low noise amplifiers (LNAs), power amplifiers, switches and the like.
  • the package includes at least one power active device, such as a power amplifier, together with other active devices, for example LNAs and switches.
  • the active devices can be bare dies or packaged integrated circuits (ICs).
  • Each active component is mounted to the ceramic substrate 2 in an area over or directly adjacent to the metal layer 3 formed on the ceramic substrate 2.
  • the active components are attached to the die bond pads 6 via conductive adhesive or via non-conductive adhesive and bonding wires 5. There is no intervening insulating material such as oxide between the active component 4 and the substrate 2.
  • the active components 4 are mounted as closely as possible to the associated passive elements and circuit 3 integrated with this ceramic.
  • a circuit package of the current invention is particularly useful in radio frequency (RF) front end modules.
  • a typical RF front end comprises everything from the antenna to the intermediate frequency (IF) stage of an RF receiver, and may include a low noise amplifier (LNA), one or more mixer stages, a phase lock loop (PLL), automatic gain control (ACJC) and filters, ft includes both active and passive analog components operating at high frequency.
  • the active components can be mounted on a ceramic support substrate and interconnected with thin-film passive components integrated with the ceramic substrate.
  • Such a construction provides a simpler assembly procedure and lower assembly capabilities, for example minimum separation between dies, minimum separation between die and discrete integrated passive devices, without affecting the performance of the module, for example, minimum bond wire length.
  • Integrating thin- film passive components with the ceramic substrate improves routing flexibility and reduces the package form-factor. Because active components can be mounted directly above their associated passive components, bond wire lengths are shorter which reduces parasitics and losses especially operating at high frequency.
  • the various passive components are connected by integrated on-ceramic interconnects with well-matched impedance instead of bonded-wires resulting in better impedance control and thus reduced losses. Because the die bond pads of active components such as power dies are formed directly on the ceramic substrate 2 without any intervening dielectric layer the package has better thermal spread effect than prior art assembly methods which typically have an insulating layer, for example, silicon oxide, BCB, between the die and ceramic/glass/silicon substrate. Testing by the inventors reveals that surface temperature can be reduced by up to 15% by removing the insulating layer.
  • an insulating layer for example, silicon oxide, BCB

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

An electronic circuit package(1) has a thin-film circuit(3) integrated with the ceramic substrate(2). The thin-film circuit(3) includes at least two passive circuit elements joined by an integrated electrical interconnect. At least one active electronic component(4) is mounted on the ceramic substrate(2) without any dielectric material between the active electronic component(4) and the ceramic substrate, and is electrically connected with the integrated thin-film circuit(3).

Description

Electronic Circuit Package
Background to the invention
1 Field of the Invention
The current invention relates to an electronic circuit package and in particular to a ceramic substrate for holding both passive and active electronic circuit components
2 Background Information Modern electronic devices are characterised by small size and large functionalit\
Consumers desire products with more and more functions, but without compromising on si/e and weight Such dev ices are also characterised by wireless interconnectivity for communicating, sharing or downloading information In response, electronic designers are continually striving to make smaller moie efficient electronic circuit packages However, v arious design considerations such as track/interconnect routing, parasitica losses and heating affect the size and form-factor of electronic packages., particularly in radio frequency applications Another aspect that affects size and form-factor is the number of passive circuit component in modern electronic circuitry Modern electronic circuits contain a large number of semiconductor integrated circuit (1C) devices, however it is estimated there between 60-70% of components in modern electronic circuits aie discrete passise components Although modern techniques such as Low Temperature Co- tired Ceramic (Ϊ.TCC) and thin-film are used to reduce the size of passive components separation between active and passive devices is still go\erned by assembly capabilities and many active devices are not closely placed to associated passive components in order to optimise module layout Form-factor is also governed by assembly capabilities and minimum separation between 1C dies
United States Patent 6,545,225 discloses a small form-factor electronic circuit package in which passive components, such as capacitois, resistors and inductors, are formed on a substrate of an insulating material using a thin film technique A pianarizing layer of glass is first coated onto the insulating material and then the thin film circuits arc formed on the barrier layer. The partial or full integration of passive components onto the substrate leads to the creation of a module which is very compact.
Another small form-factor electronic circuit, package is disclosed in Taiwanese patent publication TW0494560B Jn this package a patterned insulation layer is located on the upper surface of a ceramic substrate and a thin film passive device layer is locating on the patterned insulation layer. A passivation layer is formed on the thin film passive device layer and a chip is located on the passivation layer and electrically connected with the passive device through a multi-level interconnect.
The packages disclosed in these two patents have insulating or barrier layers on the supporting substrate to achieve passive components with acceptable performance at RF operating frequencies. However, the insulating and barrier layers deteriorate the thermal spreading performance of the package and so these packages are not suitable for high power application.
Thus there exists a need for an improved electronic circuit package that overcomes or ameliorates at least some of the disadvantages with the prior art or at least provides the public with a useful alternative.
Summary of the Invention
Accordingly there is disclosed herein an electronic circuit package comprising a ceramic substrate, a thin-film circuit integrated with the ceramic substrate and having at least two passive circuit elements joined by an integrated electrical interconnect, and at least one active power electronic component mounted on the ceramic substrate and electrically connected with the integrated thin-film circuit.
Preferably, the thin-film circuit is integrated with the ceramic substrate by a method selected from a group comprising metal and dielectric deposition, electroplating and etching. Preferably, the active electronic component is mounted to the ceramic substrate without any dielectric material between the active electronic component and the ceramic substrate.
Preferably, the active electronic component is mounted on the die bond pad with adhesive which could be conductive or non-conductive.
Preferably, the thin-film circuit is integrated with the ceramic substrate.
Preferably, the passive circuit elements are selected from the group consisting of a resistor, a capacitor, an inductor, a through hole, a via and a wrap-around.
Preferably, the thin-film circuit is selected from a group consisting of an LC matching network, a low-pass filter, a band-pass filter, a high-pass filter, a diplexer and a balun.
Preferably, the active electronic component comprises a semiconductor chip device or packaged IC
Preferably, the semiconductor chip device is selected from a group consisting of a RF die, a low-noise amplifier, a power amplifier and a switch.
Preferably, the electronic circuit package comprises a ceramic substrate, a thin-film circuit integrated with the ceramic substrate, thin-film circuit comprising at least two passive circuit elements connected to a bond pad and wherein there is no dielectric layer between the die bond pad and the substrate, and an active electronic component mounted to the die bond pad using a conductive or non conductive adhesive.
Brief Description of the Drawings
Figure 1 is a schematic overview of an electronic circuit package according to the invention,
Figure 2 is a side schematic view of the package, and Figure 3 is an enlarged size schematic view of area A of Figure 2.
Detailed Description of the Exemplary Embodiments
Referring to the drawings, in an exemplified embodiment of the invention there is an electronic circuit package 1 comprising a ceramic supporting substrate 2, a plurality of thin-film circuits 3 deposited on the ceramic substrate 2 and a plurality of active electronic devices 4. The thin-film circuits 3 comprise a plurality of passive circuit elements which in combination with the active electronic devices 4 form a functioning electronic circuit.
The passive circuit elements of the thin-film circuits 3 may include, but are not limited to, any one of resistors, capacitors, inductors, through-holes, vias and/or edge wrap-arounds. These components are formed on the ceramic by depositing thin films of metal, dielectric or photoresist materials using plasma enhanced chemical vapor deposition (PF-CVD), physical vapor deposition (PVD) such as sputtering, patterning and etching and electroplating processes. The formation of thin film circuit using some of the aforementioned methods has been practiced for over 30 years and is well within the capability of those skilled in the art. The electroplating process is used to control the metal thickness of components whose performance is sensitive to metal thickness, for example, Q-factor of inductors a.nd insertion loss of transmission line. The thin film passive circuit elements are joined to form thin-film electronic circuits by interconnects also integrated with the ceramic substrate 2. The passive components may be of any arbitrary shape, taking account of the voltage, current, frequency characteristics of the electrical signal and the shape and size of the active electronic components they will carry, and are arranged to form passive circuit elements such as LC matching networks, low- pass filters, band-pass filers, high-pass filters, diplexers and the like.
Die Bond pads 6 are also formed on the substrate for mounting the active components 4. The die bond pads are formed by electroplating or one of the thin-film techniques described above directly onto the substrate without an intervening dielectric layer between the pad 6 and ceramic substrate 2.
The active electronic components 4 of the package may include, bat are not limited to, semiconductor devices and dies such as transistors, low noise amplifiers (LNAs), power amplifiers, switches and the like. In the preferred embodiment the package includes at least one power active device, such as a power amplifier, together with other active devices, for example LNAs and switches. The active devices can be bare dies or packaged integrated circuits (ICs). Each active component is mounted to the ceramic substrate 2 in an area over or directly adjacent to the metal layer 3 formed on the ceramic substrate 2. The active components are attached to the die bond pads 6 via conductive adhesive or via non-conductive adhesive and bonding wires 5. There is no intervening insulating material such as oxide between the active component 4 and the substrate 2. The active components 4 are mounted as closely as possible to the associated passive elements and circuit 3 integrated with this ceramic.
A circuit package of the current invention is particularly useful in radio frequency (RF) front end modules. A typical RF front end comprises everything from the antenna to the intermediate frequency (IF) stage of an RF receiver, and may include a low noise amplifier (LNA), one or more mixer stages, a phase lock loop (PLL), automatic gain control (ACJC) and filters, ft includes both active and passive analog components operating at high frequency. The active components can be mounted on a ceramic support substrate and interconnected with thin-film passive components integrated with the ceramic substrate. Such a construction provides a simpler assembly procedure and lower assembly capabilities, for example minimum separation between dies, minimum separation between die and discrete integrated passive devices, without affecting the performance of the module, for example, minimum bond wire length. Integrating thin- film passive components with the ceramic substrate improves routing flexibility and reduces the package form-factor. Because active components can be mounted directly above their associated passive components, bond wire lengths are shorter which reduces parasitics and losses especially operating at high frequency. The various passive components are connected by integrated on-ceramic interconnects with well-matched impedance instead of bonded-wires resulting in better impedance control and thus reduced losses. Because the die bond pads of active components such as power dies are formed directly on the ceramic substrate 2 without any intervening dielectric layer the package has better thermal spread effect than prior art assembly methods which typically have an insulating layer, for example, silicon oxide, BCB, between the die and ceramic/glass/silicon substrate. Testing by the inventors reveals that surface temperature can be reduced by up to 15% by removing the insulating layer.
It should be appreciated that modifications and/or alterations obvious to those skilled in the art are not considered as beyond the scope of the present invention.

Claims

What is claimed is:
1. An electronic circuit package comprising. a ceramic substrate, a thin-film circuit integrated with the ceramic substrate and having at least two passive circuit elements joined by art integrated electrical interconnect and at least one active power electronic component mounted on the ceramic substrate and electrically connected with the integrated thin-film circuit.
2. The package of claim 1 wherein the thin-film circuit is integrated with the ceramic substrate by a method selected from a group comprising metal and dielectric deposition, electroplating and etching.
3. The package of claim 1 wherein the active electronic component is mounted to the ceramic substrate without any dielectric material between the active electronic component and the ceramic substrate.
4. The package of claim 3 wherein active electronic component is mounted on the die bond pad with adhesive which could be conductive or non-conductive.
5. The package of claim 1 wherein the thin-film circuit is integrated with the ceramic substrate.
6. The package of claim 1 wherein the passive circuit elements are selected from the group consisting of a resistor, a capacitor, an inductor, a through hole, a via and a wrap- around.
7. The package of claim I wherein the thin-film circuit is selected from a group consisting of an LC matching network, a low-pass filter, a band-pass filter, a high-pass filter, a dipiexer and a balun.
8. The package of claim 1 wherein the active electronic component comprises a semiconductor chip device or packaged IC.
9 The package of claim 8 wherein the semiconductor chip device is selected from a group consisting of a RF die, a low-noise amplifier, a power amplifier and a switch.
10. An electronic circuit package comprising. a ceramic substrate, a thin-film circuit integrated with the ceramic substrate, thin-film circuit comprising at least two passive circuit elements connected to a bond pad and wherein there is no dielectric layer between the bond pad and the substrate, and an active electronic component mounted to the bond pad using a conductive or non conductive adhesive.
PCT/CN2007/070954 2007-10-25 2007-10-25 Electronic circuit package WO2009052683A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2007/070954 WO2009052683A1 (en) 2007-10-25 2007-10-25 Electronic circuit package

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Application Number Priority Date Filing Date Title
PCT/CN2007/070954 WO2009052683A1 (en) 2007-10-25 2007-10-25 Electronic circuit package

Publications (1)

Publication Number Publication Date
WO2009052683A1 true WO2009052683A1 (en) 2009-04-30

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8475955B2 (en) 2005-03-25 2013-07-02 Front Edge Technology, Inc. Thin film battery with electrical connector connecting battery cells
US8679674B2 (en) 2005-03-25 2014-03-25 Front Edge Technology, Inc. Battery with protective packaging
US8753724B2 (en) 2012-09-26 2014-06-17 Front Edge Technology Inc. Plasma deposition on a partially formed battery through a mesh screen
US8865340B2 (en) 2011-10-20 2014-10-21 Front Edge Technology Inc. Thin film battery packaging formed by localized heating
US8864954B2 (en) 2011-12-23 2014-10-21 Front Edge Technology Inc. Sputtering lithium-containing material with multiple targets
US9077000B2 (en) 2012-03-29 2015-07-07 Front Edge Technology, Inc. Thin film battery and localized heat treatment
US9257695B2 (en) 2012-03-29 2016-02-09 Front Edge Technology, Inc. Localized heat treatment of battery component films
US9356320B2 (en) 2012-10-15 2016-05-31 Front Edge Technology Inc. Lithium battery having low leakage anode
US9887429B2 (en) 2011-12-21 2018-02-06 Front Edge Technology Inc. Laminated lithium battery
US9905895B2 (en) 2012-09-25 2018-02-27 Front Edge Technology, Inc. Pulsed mode apparatus with mismatched battery
US10008739B2 (en) 2015-02-23 2018-06-26 Front Edge Technology, Inc. Solid-state lithium battery with electrolyte

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Publication number Priority date Publication date Assignee Title
US5752182A (en) * 1994-05-09 1998-05-12 Matsushita Electric Industrial Co., Ltd. Hybrid IC
CN1531139A (en) * 2003-03-14 2004-09-22 Lg Active intelligent antenna system and producing method thereof
US20060097344A1 (en) * 2001-09-21 2006-05-11 Casper Michael D Integrated thin film capacitor/inductor/interconnect system and method
US20060133011A1 (en) * 2004-12-21 2006-06-22 Cox G S Capacitive devices, organic dielectric laminates, and printed wiring boards incorporating such devices, and methods of making thereof
WO2006126756A1 (en) * 2005-05-26 2006-11-30 Telephus Inc. Integrated passive device chip and method of manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5752182A (en) * 1994-05-09 1998-05-12 Matsushita Electric Industrial Co., Ltd. Hybrid IC
US20060097344A1 (en) * 2001-09-21 2006-05-11 Casper Michael D Integrated thin film capacitor/inductor/interconnect system and method
CN1531139A (en) * 2003-03-14 2004-09-22 Lg Active intelligent antenna system and producing method thereof
US20060133011A1 (en) * 2004-12-21 2006-06-22 Cox G S Capacitive devices, organic dielectric laminates, and printed wiring boards incorporating such devices, and methods of making thereof
WO2006126756A1 (en) * 2005-05-26 2006-11-30 Telephus Inc. Integrated passive device chip and method of manufacturing the same

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8475955B2 (en) 2005-03-25 2013-07-02 Front Edge Technology, Inc. Thin film battery with electrical connector connecting battery cells
US8679674B2 (en) 2005-03-25 2014-03-25 Front Edge Technology, Inc. Battery with protective packaging
US8865340B2 (en) 2011-10-20 2014-10-21 Front Edge Technology Inc. Thin film battery packaging formed by localized heating
US9887429B2 (en) 2011-12-21 2018-02-06 Front Edge Technology Inc. Laminated lithium battery
US8864954B2 (en) 2011-12-23 2014-10-21 Front Edge Technology Inc. Sputtering lithium-containing material with multiple targets
US9077000B2 (en) 2012-03-29 2015-07-07 Front Edge Technology, Inc. Thin film battery and localized heat treatment
US9257695B2 (en) 2012-03-29 2016-02-09 Front Edge Technology, Inc. Localized heat treatment of battery component films
US9905895B2 (en) 2012-09-25 2018-02-27 Front Edge Technology, Inc. Pulsed mode apparatus with mismatched battery
US8753724B2 (en) 2012-09-26 2014-06-17 Front Edge Technology Inc. Plasma deposition on a partially formed battery through a mesh screen
US9356320B2 (en) 2012-10-15 2016-05-31 Front Edge Technology Inc. Lithium battery having low leakage anode
US10008739B2 (en) 2015-02-23 2018-06-26 Front Edge Technology, Inc. Solid-state lithium battery with electrolyte

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